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authorMagnus Damm <damm@opensource.se>2010-11-17 04:53:25 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-11-19 03:02:50 -0500
commitdeaba190188f1caa2317de4df6c9aaba501f9809 (patch)
treec441ee7bbb373541b74fff47558eed806b03b60c
parent5958d58a0e7699c791b9f4c99d76559a14770138 (diff)
fbdev: sh_mipi_dsi: Require two I/O resources V2
This is V2 of the MIPI-DSI two resources patch. The second I/O resource specifies the base address for the link hardware block. The base address for the link hardware block seems to vary with SoC type. Using two I/O resources to describe the MIPI-DSI hardware allows us to support both newer and older SoCs. Signed-off-by: Magnus Damm <damm@opensource.se> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--drivers/video/sh_mipi_dsi.c55
1 files changed, 39 insertions, 16 deletions
diff --git a/drivers/video/sh_mipi_dsi.c b/drivers/video/sh_mipi_dsi.c
index 8abab6d4264..148ee27cf81 100644
--- a/drivers/video/sh_mipi_dsi.c
+++ b/drivers/video/sh_mipi_dsi.c
@@ -34,19 +34,20 @@
34#define DSIINTE 0x0060 34#define DSIINTE 0x0060
35#define PHYCTRL 0x0070 35#define PHYCTRL 0x0070
36 36
37#define DTCTR 0x8000 37/* relative to linkbase */
38#define VMCTR1 0x8020 38#define DTCTR 0x0000
39#define VMCTR2 0x8024 39#define VMCTR1 0x0020
40#define VMLEN1 0x8028 40#define VMCTR2 0x0024
41#define CMTSRTREQ 0x8070 41#define VMLEN1 0x0028
42#define CMTSRTCTR 0x80d0 42#define CMTSRTREQ 0x0070
43 43#define CMTSRTCTR 0x00d0
44 44
45/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */ 45/* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
46#define MAX_SH_MIPI_DSI 2 46#define MAX_SH_MIPI_DSI 2
47 47
48struct sh_mipi { 48struct sh_mipi {
49 void __iomem *base; 49 void __iomem *base;
50 void __iomem *linkbase;
50 struct clk *dsit_clk; 51 struct clk *dsit_clk;
51 struct clk *dsip_clk; 52 struct clk *dsip_clk;
52}; 53};
@@ -71,10 +72,10 @@ static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
71 int cnt = 100; 72 int cnt = 100;
72 73
73 /* transmit a short packet to LCD panel */ 74 /* transmit a short packet to LCD panel */
74 iowrite32(1 | data, mipi->base + CMTSRTCTR); 75 iowrite32(1 | data, mipi->linkbase + CMTSRTCTR);
75 iowrite32(1, mipi->base + CMTSRTREQ); 76 iowrite32(1, mipi->linkbase + CMTSRTREQ);
76 77
77 while ((ioread32(mipi->base + CMTSRTREQ) & 1) && --cnt) 78 while ((ioread32(mipi->linkbase + CMTSRTREQ) & 1) && --cnt)
78 udelay(1); 79 udelay(1);
79 80
80 return cnt ? 0 : -ETIMEDOUT; 81 return cnt ? 0 : -ETIMEDOUT;
@@ -106,7 +107,7 @@ static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
106 * enable LCDC data tx, transition to LPS after completion of each HS 107 * enable LCDC data tx, transition to LPS after completion of each HS
107 * packet 108 * packet
108 */ 109 */
109 iowrite32(0x00000002 | enable, mipi->base + DTCTR); 110 iowrite32(0x00000002 | enable, mipi->linkbase + DTCTR);
110} 111}
111 112
112static void sh_mipi_shutdown(struct platform_device *pdev) 113static void sh_mipi_shutdown(struct platform_device *pdev)
@@ -291,20 +292,21 @@ static int __init sh_mipi_setup(struct sh_mipi *mipi,
291 * Enable transmission of all packets, 292 * Enable transmission of all packets,
292 * transmit LPS after each HS packet completion 293 * transmit LPS after each HS packet completion
293 */ 294 */
294 iowrite32(0x00000006, base + DTCTR); 295 iowrite32(0x00000006, mipi->linkbase + DTCTR);
295 /* VSYNC width = 2 (<< 17) */ 296 /* VSYNC width = 2 (<< 17) */
296 iowrite32(0x00040000 | (pctype << 12) | datatype, base + VMCTR1); 297 iowrite32(0x00040000 | (pctype << 12) | datatype,
298 mipi->linkbase + VMCTR1);
297 /* 299 /*
298 * Non-burst mode with sync pulses: VSE and HSE are output, 300 * Non-burst mode with sync pulses: VSE and HSE are output,
299 * HSA period allowed, no commands in LP 301 * HSA period allowed, no commands in LP
300 */ 302 */
301 iowrite32(0x00e00000, base + VMCTR2); 303 iowrite32(0x00e00000, mipi->linkbase + VMCTR2);
302 /* 304 /*
303 * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see 305 * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
304 * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default 306 * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
305 * (unused, since VMCTR2[HSABM] = 0) 307 * (unused, since VMCTR2[HSABM] = 0)
306 */ 308 */
307 iowrite32(1 | (linelength << 16), base + VMLEN1); 309 iowrite32(1 | (linelength << 16), mipi->linkbase + VMLEN1);
308 310
309 msleep(5); 311 msleep(5);
310 312
@@ -337,11 +339,12 @@ static int __init sh_mipi_probe(struct platform_device *pdev)
337 struct sh_mipi *mipi; 339 struct sh_mipi *mipi;
338 struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data; 340 struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
339 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 341 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
342 struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
340 unsigned long rate, f_current; 343 unsigned long rate, f_current;
341 int idx = pdev->id, ret; 344 int idx = pdev->id, ret;
342 char dsip_clk[] = "dsi.p_clk"; 345 char dsip_clk[] = "dsi.p_clk";
343 346
344 if (!res || idx >= ARRAY_SIZE(mipi_dsi) || !pdata) 347 if (!res || !res2 || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
345 return -ENODEV; 348 return -ENODEV;
346 349
347 mutex_lock(&array_lock); 350 mutex_lock(&array_lock);
@@ -372,6 +375,18 @@ static int __init sh_mipi_probe(struct platform_device *pdev)
372 goto emap; 375 goto emap;
373 } 376 }
374 377
378 if (!request_mem_region(res2->start, resource_size(res2), pdev->name)) {
379 dev_err(&pdev->dev, "MIPI register region 2 already claimed\n");
380 ret = -EBUSY;
381 goto ereqreg2;
382 }
383
384 mipi->linkbase = ioremap(res2->start, resource_size(res2));
385 if (!mipi->linkbase) {
386 ret = -ENOMEM;
387 goto emap2;
388 }
389
375 mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk"); 390 mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
376 if (IS_ERR(mipi->dsit_clk)) { 391 if (IS_ERR(mipi->dsit_clk)) {
377 ret = PTR_ERR(mipi->dsit_clk); 392 ret = PTR_ERR(mipi->dsit_clk);
@@ -447,6 +462,10 @@ eclkpget:
447esettrate: 462esettrate:
448 clk_put(mipi->dsit_clk); 463 clk_put(mipi->dsit_clk);
449eclktget: 464eclktget:
465 iounmap(mipi->linkbase);
466emap2:
467 release_mem_region(res2->start, resource_size(res2));
468ereqreg2:
450 iounmap(mipi->base); 469 iounmap(mipi->base);
451emap: 470emap:
452 release_mem_region(res->start, resource_size(res)); 471 release_mem_region(res->start, resource_size(res));
@@ -463,6 +482,7 @@ static int __exit sh_mipi_remove(struct platform_device *pdev)
463{ 482{
464 struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data; 483 struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
465 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 484 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
485 struct resource *res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
466 struct sh_mipi *mipi = platform_get_drvdata(pdev); 486 struct sh_mipi *mipi = platform_get_drvdata(pdev);
467 int i, ret; 487 int i, ret;
468 488
@@ -491,6 +511,9 @@ static int __exit sh_mipi_remove(struct platform_device *pdev)
491 clk_disable(mipi->dsit_clk); 511 clk_disable(mipi->dsit_clk);
492 clk_put(mipi->dsit_clk); 512 clk_put(mipi->dsit_clk);
493 clk_put(mipi->dsip_clk); 513 clk_put(mipi->dsip_clk);
514 iounmap(mipi->linkbase);
515 if (res2)
516 release_mem_region(res2->start, resource_size(res2));
494 iounmap(mipi->base); 517 iounmap(mipi->base);
495 if (res) 518 if (res)
496 release_mem_region(res->start, resource_size(res)); 519 release_mem_region(res->start, resource_size(res));