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authorLinus Torvalds <torvalds@linux-foundation.org>2011-05-03 21:52:09 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-05-03 21:52:09 -0400
commitd2af6768f6128a682e7490d04e2f3d660bd6fb76 (patch)
tree6f25a84cd251a605b103111d1bd615bfb13b9ae2
parentcce2c56e7666199916525907dc817209dd58287c (diff)
parent8aeb96f80232e9a701b5c4715504f4c9173978bd (diff)
Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon/kms: fix gart setup on fusion parts (v2) drm: Send pending vblank events before disabling vblank. drm/radeon: fix regression on atom cards with hardcoded EDID record. drm/radeon/kms: add some new pci ids
-rw-r--r--drivers/gpu/drm/drm_irq.c23
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c17
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h5
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c5
-rw-r--r--drivers/gpu/drm/radeon/radeon_kms.c3
-rw-r--r--include/drm/drm_pciids.h5
-rw-r--r--include/drm/radeon_drm.h1
7 files changed, 49 insertions, 10 deletions
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index 741457bd1c4..a1f12cb043d 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -932,11 +932,34 @@ EXPORT_SYMBOL(drm_vblank_put);
932 932
933void drm_vblank_off(struct drm_device *dev, int crtc) 933void drm_vblank_off(struct drm_device *dev, int crtc)
934{ 934{
935 struct drm_pending_vblank_event *e, *t;
936 struct timeval now;
935 unsigned long irqflags; 937 unsigned long irqflags;
938 unsigned int seq;
936 939
937 spin_lock_irqsave(&dev->vbl_lock, irqflags); 940 spin_lock_irqsave(&dev->vbl_lock, irqflags);
938 vblank_disable_and_save(dev, crtc); 941 vblank_disable_and_save(dev, crtc);
939 DRM_WAKEUP(&dev->vbl_queue[crtc]); 942 DRM_WAKEUP(&dev->vbl_queue[crtc]);
943
944 /* Send any queued vblank events, lest the natives grow disquiet */
945 seq = drm_vblank_count_and_time(dev, crtc, &now);
946 list_for_each_entry_safe(e, t, &dev->vblank_event_list, base.link) {
947 if (e->pipe != crtc)
948 continue;
949 DRM_DEBUG("Sending premature vblank event on disable: \
950 wanted %d, current %d\n",
951 e->event.sequence, seq);
952
953 e->event.sequence = seq;
954 e->event.tv_sec = now.tv_sec;
955 e->event.tv_usec = now.tv_usec;
956 drm_vblank_put(dev, e->pipe);
957 list_move_tail(&e->base.link, &e->base.file_priv->event_list);
958 wake_up_interruptible(&e->base.file_priv->event_wait);
959 trace_drm_vblank_event_delivered(e->base.pid, e->pipe,
960 e->event.sequence);
961 }
962
940 spin_unlock_irqrestore(&dev->vbl_lock, irqflags); 963 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
941} 964}
942EXPORT_SYMBOL(drm_vblank_off); 965EXPORT_SYMBOL(drm_vblank_off);
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e9bc135d918..c20eac3379e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -862,9 +862,15 @@ int evergreen_pcie_gart_enable(struct radeon_device *rdev)
862 SYSTEM_ACCESS_MODE_NOT_IN_SYS | 862 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
863 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | 863 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
864 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); 864 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
865 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); 865 if (rdev->flags & RADEON_IS_IGP) {
866 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); 866 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
867 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); 867 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
868 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
869 } else {
870 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
871 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
872 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
873 }
868 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); 874 WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
869 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); 875 WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
870 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); 876 WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
@@ -2923,11 +2929,6 @@ static int evergreen_startup(struct radeon_device *rdev)
2923 rdev->asic->copy = NULL; 2929 rdev->asic->copy = NULL;
2924 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 2930 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2925 } 2931 }
2926 /* XXX: ontario has problems blitting to gart at the moment */
2927 if (rdev->family == CHIP_PALM) {
2928 rdev->asic->copy = NULL;
2929 radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2930 }
2931 2932
2932 /* allocate wb buffer */ 2933 /* allocate wb buffer */
2933 r = radeon_wb_init(rdev); 2934 r = radeon_wb_init(rdev);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index 9aaa3f0c937..94533849927 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -221,6 +221,11 @@
221#define MC_VM_MD_L1_TLB0_CNTL 0x2654 221#define MC_VM_MD_L1_TLB0_CNTL 0x2654
222#define MC_VM_MD_L1_TLB1_CNTL 0x2658 222#define MC_VM_MD_L1_TLB1_CNTL 0x2658
223#define MC_VM_MD_L1_TLB2_CNTL 0x265C 223#define MC_VM_MD_L1_TLB2_CNTL 0x265C
224
225#define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
226#define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
227#define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
228
224#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 229#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
225#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 230#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
226#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 231#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index f5d12fb103f..f116516bfef 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -1599,9 +1599,10 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1599 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0], 1599 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1600 fake_edid_record->ucFakeEDIDLength); 1600 fake_edid_record->ucFakeEDIDLength);
1601 1601
1602 if (drm_edid_is_valid(edid)) 1602 if (drm_edid_is_valid(edid)) {
1603 rdev->mode_info.bios_hardcoded_edid = edid; 1603 rdev->mode_info.bios_hardcoded_edid = edid;
1604 else 1604 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1605 } else
1605 kfree(edid); 1606 kfree(edid);
1606 } 1607 }
1607 } 1608 }
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 871df0376b1..bd58af65858 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -234,6 +234,9 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
234 return -EINVAL; 234 return -EINVAL;
235 } 235 }
236 break; 236 break;
237 case RADEON_INFO_FUSION_GART_WORKING:
238 value = 1;
239 break;
237 default: 240 default:
238 DRM_DEBUG_KMS("Invalid request %d\n", info->request); 241 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
239 return -EINVAL; 242 return -EINVAL;
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 816e30cbd96..f04b2a3b0f4 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -155,6 +155,7 @@
155 {0x1002, 0x6719, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ 155 {0x1002, 0x6719, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
156 {0x1002, 0x671c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ 156 {0x1002, 0x671c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
157 {0x1002, 0x671d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \ 157 {0x1002, 0x671d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
158 {0x1002, 0x671f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CAYMAN|RADEON_NEW_MEMMAP}, \
158 {0x1002, 0x6720, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 159 {0x1002, 0x6720, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
159 {0x1002, 0x6721, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 160 {0x1002, 0x6721, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
160 {0x1002, 0x6722, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \ 161 {0x1002, 0x6722, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
@@ -167,6 +168,7 @@
167 {0x1002, 0x6729, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \ 168 {0x1002, 0x6729, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
168 {0x1002, 0x6738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \ 169 {0x1002, 0x6738, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
169 {0x1002, 0x6739, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \ 170 {0x1002, 0x6739, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
171 {0x1002, 0x673e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BARTS|RADEON_NEW_MEMMAP}, \
170 {0x1002, 0x6740, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 172 {0x1002, 0x6740, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
171 {0x1002, 0x6741, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 173 {0x1002, 0x6741, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
172 {0x1002, 0x6742, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 174 {0x1002, 0x6742, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TURKS|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
@@ -199,6 +201,7 @@
199 {0x1002, 0x688D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ 201 {0x1002, 0x688D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
200 {0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ 202 {0x1002, 0x6898, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
201 {0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ 203 {0x1002, 0x6899, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
204 {0x1002, 0x689b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
202 {0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \ 205 {0x1002, 0x689c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
203 {0x1002, 0x689d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \ 206 {0x1002, 0x689d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HEMLOCK|RADEON_NEW_MEMMAP}, \
204 {0x1002, 0x689e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \ 207 {0x1002, 0x689e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYPRESS|RADEON_NEW_MEMMAP}, \
@@ -209,7 +212,9 @@
209 {0x1002, 0x68b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 212 {0x1002, 0x68b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
210 {0x1002, 0x68b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ 213 {0x1002, 0x68b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
211 {0x1002, 0x68b9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ 214 {0x1002, 0x68b9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
215 {0x1002, 0x68ba, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
212 {0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \ 216 {0x1002, 0x68be, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
217 {0x1002, 0x68bf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_JUNIPER|RADEON_NEW_MEMMAP}, \
213 {0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 218 {0x1002, 0x68c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
214 {0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 219 {0x1002, 0x68c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
215 {0x1002, 0x68c7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \ 220 {0x1002, 0x68c7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_REDWOOD|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
index 7aa5dddb209..787f7b6fd62 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -910,6 +910,7 @@ struct drm_radeon_cs {
910#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */ 910#define RADEON_INFO_CLOCK_CRYSTAL_FREQ 0x09 /* clock crystal frequency */
911#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */ 911#define RADEON_INFO_NUM_BACKENDS 0x0a /* DB/backends for r600+ - need for OQ */
912#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */ 912#define RADEON_INFO_NUM_TILE_PIPES 0x0b /* tile pipes for r600+ */
913#define RADEON_INFO_FUSION_GART_WORKING 0x0c /* fusion writes to GTT were broken before this */
913 914
914struct drm_radeon_info { 915struct drm_radeon_info {
915 uint32_t request; 916 uint32_t request;