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authorMichael Chan <mchan@broadcom.com>2007-01-08 22:57:20 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2007-01-09 03:30:06 -0500
commitc1d2a1965a00693bddaddf75d57488a0d8e891af (patch)
tree5658caed34980b6edb302b3fc0103a5d61e7dbb4
parentd6aa4acebafe3acb0aade7704ec5b2f03742ea14 (diff)
[TG3]: Add PHY workaround for 5755M.
Some PHY trim values need to be fine-tuned on 5755M to be IEEE-compliant. Update version to 3.72. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/tg3.c17
-rw-r--r--drivers/net/tg3.h4
2 files changed, 16 insertions, 5 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 4056ba1ff3c..f4bf62c2a7a 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -68,8 +68,8 @@
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": " 70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.71" 71#define DRV_MODULE_VERSION "3.72"
72#define DRV_MODULE_RELDATE "December 15, 2006" 72#define DRV_MODULE_RELDATE "January 8, 2007"
73 73
74#define TG3_DEF_MAC_MODE 0 74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0 75#define TG3_DEF_RX_MODE 0
@@ -1015,7 +1015,12 @@ out:
1015 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) { 1015 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1016 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00); 1016 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1017 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a); 1017 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1018 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); 1018 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1019 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1020 tg3_writephy(tp, MII_TG3_TEST1,
1021 MII_TG3_TEST1_TRIM_EN | 0x4);
1022 } else
1023 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1019 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 1024 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1020 } 1025 }
1021 /* Set Extended packet length bit (bit 14) on all chips that */ 1026 /* Set Extended packet length bit (bit 14) on all chips that */
@@ -10803,9 +10808,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10803 10808
10804 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 10809 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10805 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || 10810 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10806 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) 10811 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10807 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG; 10812 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10808 else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) 10813 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10814 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10815 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10809 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 10816 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10810 } 10817 }
10811 10818
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index cf78a7e5997..80f59ac7ec5 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1658,6 +1658,9 @@
1658#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */ 1658#define MII_TG3_EPHY_TEST 0x1f /* 5906 PHY register */
1659#define MII_TG3_EPHY_SHADOW_EN 0x80 1659#define MII_TG3_EPHY_SHADOW_EN 0x80
1660 1660
1661#define MII_TG3_TEST1 0x1e
1662#define MII_TG3_TEST1_TRIM_EN 0x0010
1663
1661/* There are two ways to manage the TX descriptors on the tigon3. 1664/* There are two ways to manage the TX descriptors on the tigon3.
1662 * Either the descriptors are in host DMA'able memory, or they 1665 * Either the descriptors are in host DMA'able memory, or they
1663 * exist only in the cards on-chip SRAM. All 16 send bds are under 1666 * exist only in the cards on-chip SRAM. All 16 send bds are under
@@ -2256,6 +2259,7 @@ struct tg3 {
2256#define TG3_FLG2_1SHOT_MSI 0x10000000 2259#define TG3_FLG2_1SHOT_MSI 0x10000000
2257#define TG3_FLG2_PHY_JITTER_BUG 0x20000000 2260#define TG3_FLG2_PHY_JITTER_BUG 0x20000000
2258#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000 2261#define TG3_FLG2_NO_FWARE_REPORTED 0x40000000
2262#define TG3_FLG2_PHY_ADJUST_TRIM 0x80000000
2259 2263
2260 u32 split_mode_max_reqs; 2264 u32 split_mode_max_reqs;
2261#define SPLIT_MODE_5704_MAX_REQ 3 2265#define SPLIT_MODE_5704_MAX_REQ 3