diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-02-24 14:02:13 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2009-03-13 00:24:10 -0400 |
| commit | befb73c2322923766df7e36b51f407dbdc047eab (patch) | |
| tree | de14b3d98afba01aab45b4cfa531b14c34905f82 | |
| parent | 995e37cafb90f104395e015a9836cc459df1fc39 (diff) | |
drm/radeon: prep for r6xx/r7xx support
- add r6xx/r7xx regs and macros
- add r6xx/r7xx chip families
- fix register access for regs with offsets >= 0x10000
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_cp.c | 14 | ||||
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_drv.h | 504 | ||||
| -rw-r--r-- | include/drm/radeon_drm.h | 5 |
3 files changed, 521 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c index 8338353e505..e42b6a2a7e8 100644 --- a/drivers/gpu/drm/radeon/radeon_cp.c +++ b/drivers/gpu/drm/radeon/radeon_cp.c | |||
| @@ -89,6 +89,20 @@ u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index) | |||
| 89 | return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index); | 89 | return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index); |
| 90 | } | 90 | } |
| 91 | 91 | ||
| 92 | u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr) | ||
| 93 | { | ||
| 94 | u32 ret; | ||
| 95 | |||
| 96 | if (addr < 0x10000) | ||
| 97 | ret = DRM_READ32(dev_priv->mmio, addr); | ||
| 98 | else { | ||
| 99 | DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr); | ||
| 100 | ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA); | ||
| 101 | } | ||
| 102 | |||
| 103 | return ret; | ||
| 104 | } | ||
| 105 | |||
| 92 | static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) | 106 | static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr) |
| 93 | { | 107 | { |
| 94 | u32 ret; | 108 | u32 ret; |
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h index aa078cbe38f..9326c73976c 100644 --- a/drivers/gpu/drm/radeon/radeon_drv.h +++ b/drivers/gpu/drm/radeon/radeon_drv.h | |||
| @@ -134,6 +134,16 @@ enum radeon_family { | |||
| 134 | CHIP_RV560, | 134 | CHIP_RV560, |
| 135 | CHIP_RV570, | 135 | CHIP_RV570, |
| 136 | CHIP_R580, | 136 | CHIP_R580, |
| 137 | CHIP_R600, | ||
| 138 | CHIP_RV610, | ||
| 139 | CHIP_RV630, | ||
| 140 | CHIP_RV620, | ||
| 141 | CHIP_RV635, | ||
| 142 | CHIP_RV670, | ||
| 143 | CHIP_RS780, | ||
| 144 | CHIP_RV770, | ||
| 145 | CHIP_RV730, | ||
| 146 | CHIP_RV710, | ||
| 137 | CHIP_LAST, | 147 | CHIP_LAST, |
| 138 | }; | 148 | }; |
| 139 | 149 | ||
| @@ -317,6 +327,26 @@ typedef struct drm_radeon_private { | |||
| 317 | int num_gb_pipes; | 327 | int num_gb_pipes; |
| 318 | int track_flush; | 328 | int track_flush; |
| 319 | drm_local_map_t *mmio; | 329 | drm_local_map_t *mmio; |
| 330 | |||
| 331 | /* r6xx/r7xx pipe/shader config */ | ||
| 332 | int r600_max_pipes; | ||
| 333 | int r600_max_tile_pipes; | ||
| 334 | int r600_max_simds; | ||
| 335 | int r600_max_backends; | ||
| 336 | int r600_max_gprs; | ||
| 337 | int r600_max_threads; | ||
| 338 | int r600_max_stack_entries; | ||
| 339 | int r600_max_hw_contexts; | ||
| 340 | int r600_max_gs_threads; | ||
| 341 | int r600_sx_max_export_size; | ||
| 342 | int r600_sx_max_export_pos_size; | ||
| 343 | int r600_sx_max_export_smx_size; | ||
| 344 | int r600_sq_num_cf_insts; | ||
| 345 | int r700_sx_num_of_sets; | ||
| 346 | int r700_sc_prim_fifo_size; | ||
| 347 | int r700_sc_hiz_tile_fifo_size; | ||
| 348 | int r700_sc_earlyz_tile_fifo_fize; | ||
| 349 | |||
| 320 | } drm_radeon_private_t; | 350 | } drm_radeon_private_t; |
| 321 | 351 | ||
| 322 | typedef struct drm_radeon_buf_priv { | 352 | typedef struct drm_radeon_buf_priv { |
| @@ -366,6 +396,7 @@ extern int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_fi | |||
| 366 | extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); | 396 | extern int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv); |
| 367 | extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); | 397 | extern int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); |
| 368 | extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); | 398 | extern u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv); |
| 399 | extern u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr); | ||
| 369 | 400 | ||
| 370 | extern void radeon_freelist_reset(struct drm_device * dev); | 401 | extern void radeon_freelist_reset(struct drm_device * dev); |
| 371 | extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); | 402 | extern struct drm_buf *radeon_freelist_get(struct drm_device * dev); |
| @@ -436,6 +467,8 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev, | |||
| 436 | /* Register definitions, register access macros and drmAddMap constants | 467 | /* Register definitions, register access macros and drmAddMap constants |
| 437 | * for Radeon kernel driver. | 468 | * for Radeon kernel driver. |
| 438 | */ | 469 | */ |
| 470 | #define RADEON_MM_INDEX 0x0000 | ||
| 471 | #define RADEON_MM_DATA 0x0004 | ||
| 439 | 472 | ||
| 440 | #define RADEON_AGP_COMMAND 0x0f60 | 473 | #define RADEON_AGP_COMMAND 0x0f60 |
| 441 | #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ | 474 | #define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */ |
| @@ -645,6 +678,19 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); | |||
| 645 | 678 | ||
| 646 | #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) | 679 | #define GET_SCRATCH(dev_priv, x) radeon_get_scratch(dev_priv, x) |
| 647 | 680 | ||
| 681 | #define R600_SCRATCH_REG0 0x8500 | ||
| 682 | #define R600_SCRATCH_REG1 0x8504 | ||
| 683 | #define R600_SCRATCH_REG2 0x8508 | ||
| 684 | #define R600_SCRATCH_REG3 0x850c | ||
| 685 | #define R600_SCRATCH_REG4 0x8510 | ||
| 686 | #define R600_SCRATCH_REG5 0x8514 | ||
| 687 | #define R600_SCRATCH_REG6 0x8518 | ||
| 688 | #define R600_SCRATCH_REG7 0x851c | ||
| 689 | #define R600_SCRATCH_UMSK 0x8540 | ||
| 690 | #define R600_SCRATCH_ADDR 0x8544 | ||
| 691 | |||
| 692 | #define R600_SCRATCHOFF(x) (R600_SCRATCH_REG_OFFSET + 4*(x)) | ||
| 693 | |||
| 648 | #define RADEON_GEN_INT_CNTL 0x0040 | 694 | #define RADEON_GEN_INT_CNTL 0x0040 |
| 649 | # define RADEON_CRTC_VBLANK_MASK (1 << 0) | 695 | # define RADEON_CRTC_VBLANK_MASK (1 << 0) |
| 650 | # define RADEON_CRTC2_VBLANK_MASK (1 << 9) | 696 | # define RADEON_CRTC2_VBLANK_MASK (1 << 9) |
| @@ -924,6 +970,7 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); | |||
| 924 | #define RADEON_CP_RB_CNTL 0x0704 | 970 | #define RADEON_CP_RB_CNTL 0x0704 |
| 925 | # define RADEON_BUF_SWAP_32BIT (2 << 16) | 971 | # define RADEON_BUF_SWAP_32BIT (2 << 16) |
| 926 | # define RADEON_RB_NO_UPDATE (1 << 27) | 972 | # define RADEON_RB_NO_UPDATE (1 << 27) |
| 973 | # define RADEON_RB_RPTR_WR_ENA (1 << 31) | ||
| 927 | #define RADEON_CP_RB_RPTR_ADDR 0x070c | 974 | #define RADEON_CP_RB_RPTR_ADDR 0x070c |
| 928 | #define RADEON_CP_RB_RPTR 0x0710 | 975 | #define RADEON_CP_RB_RPTR 0x0710 |
| 929 | #define RADEON_CP_RB_WPTR 0x0714 | 976 | #define RADEON_CP_RB_WPTR 0x0714 |
| @@ -985,6 +1032,14 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); | |||
| 985 | # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 | 1032 | # define RADEON_CNTL_BITBLT_MULTI 0x00009B00 |
| 986 | # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 | 1033 | # define RADEON_CNTL_SET_SCISSORS 0xC0001E00 |
| 987 | 1034 | ||
| 1035 | # define R600_IT_INDIRECT_BUFFER 0x00003200 | ||
| 1036 | # define R600_IT_ME_INITIALIZE 0x00004400 | ||
| 1037 | # define R600_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) | ||
| 1038 | # define R600_IT_EVENT_WRITE 0x00004600 | ||
| 1039 | # define R600_IT_SET_CONFIG_REG 0x00006800 | ||
| 1040 | # define R600_SET_CONFIG_REG_OFFSET 0x00008000 | ||
| 1041 | # define R600_SET_CONFIG_REG_END 0x0000ac00 | ||
| 1042 | |||
| 988 | #define RADEON_CP_PACKET_MASK 0xC0000000 | 1043 | #define RADEON_CP_PACKET_MASK 0xC0000000 |
| 989 | #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 | 1044 | #define RADEON_CP_PACKET_COUNT_MASK 0x3fff0000 |
| 990 | #define RADEON_CP_PACKET0_REG_MASK 0x000007ff | 1045 | #define RADEON_CP_PACKET0_REG_MASK 0x000007ff |
| @@ -1183,6 +1238,422 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); | |||
| 1183 | #define R500_D1_VBLANK_INTERRUPT (1 << 4) | 1238 | #define R500_D1_VBLANK_INTERRUPT (1 << 4) |
| 1184 | #define R500_D2_VBLANK_INTERRUPT (1 << 5) | 1239 | #define R500_D2_VBLANK_INTERRUPT (1 << 5) |
| 1185 | 1240 | ||
| 1241 | /* R6xx/R7xx registers */ | ||
| 1242 | #define R600_MC_VM_FB_LOCATION 0x2180 | ||
| 1243 | #define R600_MC_VM_AGP_TOP 0x2184 | ||
| 1244 | #define R600_MC_VM_AGP_BOT 0x2188 | ||
| 1245 | #define R600_MC_VM_AGP_BASE 0x218c | ||
| 1246 | #define R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 | ||
| 1247 | #define R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 | ||
| 1248 | #define R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 | ||
| 1249 | |||
| 1250 | #define R700_MC_VM_FB_LOCATION 0x2024 | ||
| 1251 | #define R700_MC_VM_AGP_TOP 0x2028 | ||
| 1252 | #define R700_MC_VM_AGP_BOT 0x202c | ||
| 1253 | #define R700_MC_VM_AGP_BASE 0x2030 | ||
| 1254 | #define R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 | ||
| 1255 | #define R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 | ||
| 1256 | #define R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203c | ||
| 1257 | |||
| 1258 | #define R600_MCD_RD_A_CNTL 0x219c | ||
| 1259 | #define R600_MCD_RD_B_CNTL 0x21a0 | ||
| 1260 | |||
| 1261 | #define R600_MCD_WR_A_CNTL 0x21a4 | ||
| 1262 | #define R600_MCD_WR_B_CNTL 0x21a8 | ||
| 1263 | |||
| 1264 | #define R600_MCD_RD_SYS_CNTL 0x2200 | ||
| 1265 | #define R600_MCD_WR_SYS_CNTL 0x2214 | ||
| 1266 | |||
| 1267 | #define R600_MCD_RD_GFX_CNTL 0x21fc | ||
| 1268 | #define R600_MCD_RD_HDP_CNTL 0x2204 | ||
| 1269 | #define R600_MCD_RD_PDMA_CNTL 0x2208 | ||
| 1270 | #define R600_MCD_RD_SEM_CNTL 0x220c | ||
| 1271 | #define R600_MCD_WR_GFX_CNTL 0x2210 | ||
| 1272 | #define R600_MCD_WR_HDP_CNTL 0x2218 | ||
| 1273 | #define R600_MCD_WR_PDMA_CNTL 0x221c | ||
| 1274 | #define R600_MCD_WR_SEM_CNTL 0x2220 | ||
| 1275 | |||
| 1276 | # define R600_MCD_L1_TLB (1 << 0) | ||
| 1277 | # define R600_MCD_L1_FRAG_PROC (1 << 1) | ||
| 1278 | # define R600_MCD_L1_STRICT_ORDERING (1 << 2) | ||
| 1279 | |||
| 1280 | # define R600_MCD_SYSTEM_ACCESS_MODE_MASK (3 << 6) | ||
| 1281 | # define R600_MCD_SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) | ||
| 1282 | # define R600_MCD_SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) | ||
| 1283 | # define R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) | ||
| 1284 | # define R600_MCD_SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) | ||
| 1285 | |||
| 1286 | # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) | ||
| 1287 | # define R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) | ||
| 1288 | |||
| 1289 | # define R600_MCD_SEMAPHORE_MODE (1 << 10) | ||
| 1290 | # define R600_MCD_WAIT_L2_QUERY (1 << 11) | ||
| 1291 | # define R600_MCD_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 12) | ||
| 1292 | # define R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 15) | ||
| 1293 | |||
| 1294 | #define R700_MC_VM_MD_L1_TLB0_CNTL 0x2654 | ||
| 1295 | #define R700_MC_VM_MD_L1_TLB1_CNTL 0x2658 | ||
| 1296 | #define R700_MC_VM_MD_L1_TLB2_CNTL 0x265c | ||
| 1297 | |||
| 1298 | #define R700_MC_VM_MB_L1_TLB0_CNTL 0x2234 | ||
| 1299 | #define R700_MC_VM_MB_L1_TLB1_CNTL 0x2238 | ||
| 1300 | #define R700_MC_VM_MB_L1_TLB2_CNTL 0x223c | ||
| 1301 | #define R700_MC_VM_MB_L1_TLB3_CNTL 0x2240 | ||
| 1302 | |||
| 1303 | # define R700_ENABLE_L1_TLB (1 << 0) | ||
| 1304 | # define R700_ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) | ||
| 1305 | # define R700_SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) | ||
| 1306 | # define R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) | ||
| 1307 | # define R700_EFFECTIVE_L1_TLB_SIZE(x) ((x) << 15) | ||
| 1308 | # define R700_EFFECTIVE_L1_QUEUE_SIZE(x) ((x) << 18) | ||
| 1309 | |||
| 1310 | #define R700_MC_ARB_RAMCFG 0x2760 | ||
| 1311 | # define R700_NOOFBANK_SHIFT 0 | ||
| 1312 | # define R700_NOOFBANK_MASK 0x3 | ||
| 1313 | # define R700_NOOFRANK_SHIFT 2 | ||
| 1314 | # define R700_NOOFRANK_MASK 0x1 | ||
| 1315 | # define R700_NOOFROWS_SHIFT 3 | ||
| 1316 | # define R700_NOOFROWS_MASK 0x7 | ||
| 1317 | # define R700_NOOFCOLS_SHIFT 6 | ||
| 1318 | # define R700_NOOFCOLS_MASK 0x3 | ||
| 1319 | # define R700_CHANSIZE_SHIFT 8 | ||
| 1320 | # define R700_CHANSIZE_MASK 0x1 | ||
| 1321 | # define R700_BURSTLENGTH_SHIFT 9 | ||
| 1322 | # define R700_BURSTLENGTH_MASK 0x1 | ||
| 1323 | #define R600_RAMCFG 0x2408 | ||
| 1324 | # define R600_NOOFBANK_SHIFT 0 | ||
| 1325 | # define R600_NOOFBANK_MASK 0x1 | ||
| 1326 | # define R600_NOOFRANK_SHIFT 1 | ||
| 1327 | # define R600_NOOFRANK_MASK 0x1 | ||
| 1328 | # define R600_NOOFROWS_SHIFT 2 | ||
| 1329 | # define R600_NOOFROWS_MASK 0x7 | ||
| 1330 | # define R600_NOOFCOLS_SHIFT 5 | ||
| 1331 | # define R600_NOOFCOLS_MASK 0x3 | ||
| 1332 | # define R600_CHANSIZE_SHIFT 7 | ||
| 1333 | # define R600_CHANSIZE_MASK 0x1 | ||
| 1334 | # define R600_BURSTLENGTH_SHIFT 8 | ||
| 1335 | # define R600_BURSTLENGTH_MASK 0x1 | ||
| 1336 | |||
| 1337 | #define R600_VM_L2_CNTL 0x1400 | ||
| 1338 | # define R600_VM_L2_CACHE_EN (1 << 0) | ||
| 1339 | # define R600_VM_L2_FRAG_PROC (1 << 1) | ||
| 1340 | # define R600_VM_ENABLE_PTE_CACHE_LRU_W (1 << 9) | ||
| 1341 | # define R600_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 13) | ||
| 1342 | # define R700_VM_L2_CNTL_QUEUE_SIZE(x) ((x) << 14) | ||
| 1343 | |||
| 1344 | #define R600_VM_L2_CNTL2 0x1404 | ||
| 1345 | # define R600_VM_L2_CNTL2_INVALIDATE_ALL_L1_TLBS (1 << 0) | ||
| 1346 | # define R600_VM_L2_CNTL2_INVALIDATE_L2_CACHE (1 << 1) | ||
| 1347 | #define R600_VM_L2_CNTL3 0x1408 | ||
| 1348 | # define R600_VM_L2_CNTL3_BANK_SELECT_0(x) ((x) << 0) | ||
| 1349 | # define R600_VM_L2_CNTL3_BANK_SELECT_1(x) ((x) << 5) | ||
| 1350 | # define R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 10) | ||
| 1351 | # define R700_VM_L2_CNTL3_BANK_SELECT(x) ((x) << 0) | ||
| 1352 | # define R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(x) ((x) << 6) | ||
| 1353 | |||
| 1354 | #define R600_VM_L2_STATUS 0x140c | ||
| 1355 | |||
| 1356 | #define R600_VM_CONTEXT0_CNTL 0x1410 | ||
| 1357 | # define R600_VM_ENABLE_CONTEXT (1 << 0) | ||
| 1358 | # define R600_VM_PAGE_TABLE_DEPTH_FLAT (0 << 1) | ||
| 1359 | |||
| 1360 | #define R600_VM_CONTEXT0_CNTL2 0x1430 | ||
| 1361 | #define R600_VM_CONTEXT0_REQUEST_RESPONSE 0x1470 | ||
| 1362 | #define R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 | ||
| 1363 | #define R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14b0 | ||
| 1364 | #define R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 | ||
| 1365 | #define R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 | ||
| 1366 | #define R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15b4 | ||
| 1367 | |||
| 1368 | #define R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c | ||
| 1369 | #define R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c | ||
| 1370 | #define R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157c | ||
| 1371 | |||
| 1372 | #define R600_HDP_HOST_PATH_CNTL 0x2c00 | ||
| 1373 | |||
| 1374 | #define R600_GRBM_CNTL 0x8000 | ||
| 1375 | # define R600_GRBM_READ_TIMEOUT(x) ((x) << 0) | ||
| 1376 | |||
| 1377 | #define R600_GRBM_STATUS 0x8010 | ||
| 1378 | # define R600_CMDFIFO_AVAIL_MASK 0x1f | ||
| 1379 | # define R700_CMDFIFO_AVAIL_MASK 0xf | ||
| 1380 | # define R600_GUI_ACTIVE (1 << 31) | ||
| 1381 | #define R600_GRBM_STATUS2 0x8014 | ||
| 1382 | #define R600_GRBM_SOFT_RESET 0x8020 | ||
| 1383 | # define R600_SOFT_RESET_CP (1 << 0) | ||
| 1384 | #define R600_WAIT_UNTIL 0x8040 | ||
| 1385 | |||
| 1386 | #define R600_CP_SEM_WAIT_TIMER 0x85bc | ||
| 1387 | #define R600_CP_ME_CNTL 0x86d8 | ||
| 1388 | # define R600_CP_ME_HALT (1 << 28) | ||
| 1389 | #define R600_CP_QUEUE_THRESHOLDS 0x8760 | ||
| 1390 | # define R600_ROQ_IB1_START(x) ((x) << 0) | ||
| 1391 | # define R600_ROQ_IB2_START(x) ((x) << 8) | ||
| 1392 | #define R600_CP_MEQ_THRESHOLDS 0x8764 | ||
| 1393 | # define R700_STQ_SPLIT(x) ((x) << 0) | ||
| 1394 | # define R600_MEQ_END(x) ((x) << 16) | ||
| 1395 | # define R600_ROQ_END(x) ((x) << 24) | ||
| 1396 | #define R600_CP_PERFMON_CNTL 0x87fc | ||
| 1397 | #define R600_CP_RB_BASE 0xc100 | ||
| 1398 | #define R600_CP_RB_CNTL 0xc104 | ||
| 1399 | # define R600_RB_BUFSZ(x) ((x) << 0) | ||
| 1400 | # define R600_RB_BLKSZ(x) ((x) << 8) | ||
| 1401 | # define R600_RB_NO_UPDATE (1 << 27) | ||
| 1402 | # define R600_RB_RPTR_WR_ENA (1 << 31) | ||
| 1403 | #define R600_CP_RB_RPTR_WR 0xc108 | ||
| 1404 | #define R600_CP_RB_RPTR_ADDR 0xc10c | ||
| 1405 | #define R600_CP_RB_RPTR_ADDR_HI 0xc110 | ||
| 1406 | #define R600_CP_RB_WPTR 0xc114 | ||
| 1407 | #define R600_CP_RB_WPTR_ADDR 0xc118 | ||
| 1408 | #define R600_CP_RB_WPTR_ADDR_HI 0xc11c | ||
| 1409 | #define R600_CP_RB_RPTR 0x8700 | ||
| 1410 | #define R600_CP_RB_WPTR_DELAY 0x8704 | ||
| 1411 | #define R600_CP_PFP_UCODE_ADDR 0xc150 | ||
| 1412 | #define R600_CP_PFP_UCODE_DATA 0xc154 | ||
| 1413 | #define R600_CP_ME_RAM_RADDR 0xc158 | ||
| 1414 | #define R600_CP_ME_RAM_WADDR 0xc15c | ||
| 1415 | #define R600_CP_ME_RAM_DATA 0xc160 | ||
| 1416 | #define R600_CP_DEBUG 0xc1fc | ||
| 1417 | |||
| 1418 | #define R600_PA_CL_ENHANCE 0x8a14 | ||
| 1419 | # define R600_CLIP_VTX_REORDER_ENA (1 << 0) | ||
| 1420 | # define R600_NUM_CLIP_SEQ(x) ((x) << 1) | ||
| 1421 | #define R600_PA_SC_LINE_STIPPLE_STATE 0x8b10 | ||
| 1422 | #define R600_PA_SC_MULTI_CHIP_CNTL 0x8b20 | ||
| 1423 | #define R700_PA_SC_FORCE_EOV_MAX_CNTS 0x8b24 | ||
| 1424 | # define R700_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) | ||
| 1425 | # define R700_FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) | ||
| 1426 | #define R600_PA_SC_AA_SAMPLE_LOCS_2S 0x8b40 | ||
| 1427 | #define R600_PA_SC_AA_SAMPLE_LOCS_4S 0x8b44 | ||
| 1428 | #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8b48 | ||
| 1429 | #define R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8b4c | ||
| 1430 | # define R600_S0_X(x) ((x) << 0) | ||
| 1431 | # define R600_S0_Y(x) ((x) << 4) | ||
| 1432 | # define R600_S1_X(x) ((x) << 8) | ||
| 1433 | # define R600_S1_Y(x) ((x) << 12) | ||
| 1434 | # define R600_S2_X(x) ((x) << 16) | ||
| 1435 | # define R600_S2_Y(x) ((x) << 20) | ||
| 1436 | # define R600_S3_X(x) ((x) << 24) | ||
| 1437 | # define R600_S3_Y(x) ((x) << 28) | ||
| 1438 | # define R600_S4_X(x) ((x) << 0) | ||
| 1439 | # define R600_S4_Y(x) ((x) << 4) | ||
| 1440 | # define R600_S5_X(x) ((x) << 8) | ||
| 1441 | # define R600_S5_Y(x) ((x) << 12) | ||
| 1442 | # define R600_S6_X(x) ((x) << 16) | ||
| 1443 | # define R600_S6_Y(x) ((x) << 20) | ||
| 1444 | # define R600_S7_X(x) ((x) << 24) | ||
| 1445 | # define R600_S7_Y(x) ((x) << 28) | ||
| 1446 | #define R600_PA_SC_FIFO_SIZE 0x8bd0 | ||
| 1447 | # define R600_SC_PRIM_FIFO_SIZE(x) ((x) << 0) | ||
| 1448 | # define R600_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 8) | ||
| 1449 | # define R600_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 16) | ||
| 1450 | #define R700_PA_SC_FIFO_SIZE_R7XX 0x8bcc | ||
| 1451 | # define R700_SC_PRIM_FIFO_SIZE(x) ((x) << 0) | ||
| 1452 | # define R700_SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12) | ||
| 1453 | # define R700_SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20) | ||
| 1454 | #define R600_PA_SC_ENHANCE 0x8bf0 | ||
| 1455 | # define R600_FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) | ||
| 1456 | # define R600_FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) | ||
| 1457 | #define R600_PA_SC_CLIPRECT_RULE 0x2820c | ||
| 1458 | #define R700_PA_SC_EDGERULE 0x28230 | ||
| 1459 | #define R600_PA_SC_LINE_STIPPLE 0x28a0c | ||
| 1460 | #define R600_PA_SC_MODE_CNTL 0x28a4c | ||
| 1461 | #define R600_PA_SC_AA_CONFIG 0x28c04 | ||
| 1462 | |||
| 1463 | #define R600_SX_EXPORT_BUFFER_SIZES 0x900c | ||
| 1464 | # define R600_COLOR_BUFFER_SIZE(x) ((x) << 0) | ||
| 1465 | # define R600_POSITION_BUFFER_SIZE(x) ((x) << 8) | ||
| 1466 | # define R600_SMX_BUFFER_SIZE(x) ((x) << 16) | ||
| 1467 | #define R600_SX_DEBUG_1 0x9054 | ||
| 1468 | # define R600_SMX_EVENT_RELEASE (1 << 0) | ||
| 1469 | # define R600_ENABLE_NEW_SMX_ADDRESS (1 << 16) | ||
| 1470 | #define R700_SX_DEBUG_1 0x9058 | ||
| 1471 | # define R700_ENABLE_NEW_SMX_ADDRESS (1 << 16) | ||
| 1472 | #define R600_SX_MISC 0x28350 | ||
| 1473 | |||
| 1474 | #define R600_DB_DEBUG 0x9830 | ||
| 1475 | # define R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE (1 << 31) | ||
| 1476 | #define R600_DB_WATERMARKS 0x9838 | ||
| 1477 | # define R600_DEPTH_FREE(x) ((x) << 0) | ||
| 1478 | # define R600_DEPTH_FLUSH(x) ((x) << 5) | ||
| 1479 | # define R600_DEPTH_PENDING_FREE(x) ((x) << 15) | ||
| 1480 | # define R600_DEPTH_CACHELINE_FREE(x) ((x) << 20) | ||
| 1481 | #define R700_DB_DEBUG3 0x98b0 | ||
| 1482 | # define R700_DB_CLK_OFF_DELAY(x) ((x) << 11) | ||
| 1483 | #define RV700_DB_DEBUG4 0x9b8c | ||
| 1484 | # define RV700_DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6) | ||
| 1485 | |||
| 1486 | #define R600_VGT_CACHE_INVALIDATION 0x88c4 | ||
| 1487 | # define R600_CACHE_INVALIDATION(x) ((x) << 0) | ||
| 1488 | # define R600_VC_ONLY 0 | ||
| 1489 | # define R600_TC_ONLY 1 | ||
| 1490 | # define R600_VC_AND_TC 2 | ||
| 1491 | # define R700_AUTO_INVLD_EN(x) ((x) << 6) | ||
| 1492 | # define R700_NO_AUTO 0 | ||
| 1493 | # define R700_ES_AUTO 1 | ||
| 1494 | # define R700_GS_AUTO 2 | ||
| 1495 | # define R700_ES_AND_GS_AUTO 3 | ||
| 1496 | #define R600_VGT_GS_PER_ES 0x88c8 | ||
| 1497 | #define R600_VGT_ES_PER_GS 0x88cc | ||
| 1498 | #define R600_VGT_GS_PER_VS 0x88e8 | ||
| 1499 | #define R600_VGT_GS_VERTEX_REUSE 0x88d4 | ||
| 1500 | #define R600_VGT_NUM_INSTANCES 0x8974 | ||
| 1501 | #define R600_VGT_STRMOUT_EN 0x28ab0 | ||
| 1502 | #define R600_VGT_EVENT_INITIATOR 0x28a90 | ||
| 1503 | # define R600_CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) | ||
| 1504 | #define R600_VGT_VERTEX_REUSE_BLOCK_CNTL 0x28c58 | ||
| 1505 | # define R600_VTX_REUSE_DEPTH_MASK 0xff | ||
| 1506 | #define R600_VGT_OUT_DEALLOC_CNTL 0x28c5c | ||
| 1507 | # define R600_DEALLOC_DIST_MASK 0x7f | ||
| 1508 | |||
| 1509 | #define R600_CB_COLOR0_BASE 0x28040 | ||
| 1510 | #define R600_CB_COLOR1_BASE 0x28044 | ||
| 1511 | #define R600_CB_COLOR2_BASE 0x28048 | ||
| 1512 | #define R600_CB_COLOR3_BASE 0x2804c | ||
| 1513 | #define R600_CB_COLOR4_BASE 0x28050 | ||
| 1514 | #define R600_CB_COLOR5_BASE 0x28054 | ||
| 1515 | #define R600_CB_COLOR6_BASE 0x28058 | ||
| 1516 | #define R600_CB_COLOR7_BASE 0x2805c | ||
| 1517 | #define R600_CB_COLOR7_FRAG 0x280fc | ||
| 1518 | |||
| 1519 | #define R600_TC_CNTL 0x9608 | ||
| 1520 | # define R600_TC_L2_SIZE(x) ((x) << 5) | ||
| 1521 | # define R600_L2_DISABLE_LATE_HIT (1 << 9) | ||
| 1522 | |||
| 1523 | #define R600_ARB_POP 0x2418 | ||
| 1524 | # define R600_ENABLE_TC128 (1 << 30) | ||
| 1525 | #define R600_ARB_GDEC_RD_CNTL 0x246c | ||
| 1526 | |||
| 1527 | #define R600_TA_CNTL_AUX 0x9508 | ||
| 1528 | # define R600_DISABLE_CUBE_WRAP (1 << 0) | ||
| 1529 | # define R600_DISABLE_CUBE_ANISO (1 << 1) | ||
| 1530 | # define R700_GETLOD_SELECT(x) ((x) << 2) | ||
| 1531 | # define R600_SYNC_GRADIENT (1 << 24) | ||
| 1532 | # define R600_SYNC_WALKER (1 << 25) | ||
| 1533 | # define R600_SYNC_ALIGNER (1 << 26) | ||
| 1534 | # define R600_BILINEAR_PRECISION_6_BIT (0 << 31) | ||
| 1535 | # define R600_BILINEAR_PRECISION_8_BIT (1 << 31) | ||
| 1536 | |||
| 1537 | #define R700_TCP_CNTL 0x9610 | ||
| 1538 | |||
| 1539 | #define R600_SMX_DC_CTL0 0xa020 | ||
| 1540 | # define R700_USE_HASH_FUNCTION (1 << 0) | ||
| 1541 | # define R700_CACHE_DEPTH(x) ((x) << 1) | ||
| 1542 | # define R700_FLUSH_ALL_ON_EVENT (1 << 10) | ||
| 1543 | # define R700_STALL_ON_EVENT (1 << 11) | ||
| 1544 | #define R700_SMX_EVENT_CTL 0xa02c | ||
| 1545 | # define R700_ES_FLUSH_CTL(x) ((x) << 0) | ||
| 1546 | # define R700_GS_FLUSH_CTL(x) ((x) << 3) | ||
| 1547 | # define R700_ACK_FLUSH_CTL(x) ((x) << 6) | ||
| 1548 | # define R700_SYNC_FLUSH_CTL (1 << 8) | ||
| 1549 | |||
| 1550 | #define R600_SQ_CONFIG 0x8c00 | ||
| 1551 | # define R600_VC_ENABLE (1 << 0) | ||
| 1552 | # define R600_EXPORT_SRC_C (1 << 1) | ||
| 1553 | # define R600_DX9_CONSTS (1 << 2) | ||
| 1554 | # define R600_ALU_INST_PREFER_VECTOR (1 << 3) | ||
| 1555 | # define R600_DX10_CLAMP (1 << 4) | ||
| 1556 | # define R600_CLAUSE_SEQ_PRIO(x) ((x) << 8) | ||
| 1557 | # define R600_PS_PRIO(x) ((x) << 24) | ||
| 1558 | # define R600_VS_PRIO(x) ((x) << 26) | ||
| 1559 | # define R600_GS_PRIO(x) ((x) << 28) | ||
| 1560 | # define R600_ES_PRIO(x) ((x) << 30) | ||
| 1561 | #define R600_SQ_GPR_RESOURCE_MGMT_1 0x8c04 | ||
| 1562 | # define R600_NUM_PS_GPRS(x) ((x) << 0) | ||
| 1563 | # define R600_NUM_VS_GPRS(x) ((x) << 16) | ||
| 1564 | # define R700_DYN_GPR_ENABLE (1 << 27) | ||
| 1565 | # define R600_NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) | ||
| 1566 | #define R600_SQ_GPR_RESOURCE_MGMT_2 0x8c08 | ||
| 1567 | # define R600_NUM_GS_GPRS(x) ((x) << 0) | ||
| 1568 | # define R600_NUM_ES_GPRS(x) ((x) << 16) | ||
| 1569 | #define R600_SQ_THREAD_RESOURCE_MGMT 0x8c0c | ||
| 1570 | # define R600_NUM_PS_THREADS(x) ((x) << 0) | ||
| 1571 | # define R600_NUM_VS_THREADS(x) ((x) << 8) | ||
| 1572 | # define R600_NUM_GS_THREADS(x) ((x) << 16) | ||
| 1573 | # define R600_NUM_ES_THREADS(x) ((x) << 24) | ||
| 1574 | #define R600_SQ_STACK_RESOURCE_MGMT_1 0x8c10 | ||
| 1575 | # define R600_NUM_PS_STACK_ENTRIES(x) ((x) << 0) | ||
| 1576 | # define R600_NUM_VS_STACK_ENTRIES(x) ((x) << 16) | ||
| 1577 | #define R600_SQ_STACK_RESOURCE_MGMT_2 0x8c14 | ||
| 1578 | # define R600_NUM_GS_STACK_ENTRIES(x) ((x) << 0) | ||
| 1579 | # define R600_NUM_ES_STACK_ENTRIES(x) ((x) << 16) | ||
| 1580 | #define R600_SQ_MS_FIFO_SIZES 0x8cf0 | ||
| 1581 | # define R600_CACHE_FIFO_SIZE(x) ((x) << 0) | ||
| 1582 | # define R600_FETCH_FIFO_HIWATER(x) ((x) << 8) | ||
| 1583 | # define R600_DONE_FIFO_HIWATER(x) ((x) << 16) | ||
| 1584 | # define R600_ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) | ||
| 1585 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8db0 | ||
| 1586 | # define R700_SIMDA_RING0(x) ((x) << 0) | ||
| 1587 | # define R700_SIMDA_RING1(x) ((x) << 8) | ||
| 1588 | # define R700_SIMDB_RING0(x) ((x) << 16) | ||
| 1589 | # define R700_SIMDB_RING1(x) ((x) << 24) | ||
| 1590 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8db4 | ||
| 1591 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8db8 | ||
| 1592 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8dbc | ||
| 1593 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8dc0 | ||
| 1594 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8dc4 | ||
| 1595 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8dc8 | ||
| 1596 | #define R700_SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8dcc | ||
| 1597 | |||
| 1598 | #define R600_SPI_PS_IN_CONTROL_0 0x286cc | ||
| 1599 | # define R600_NUM_INTERP(x) ((x) << 0) | ||
| 1600 | # define R600_POSITION_ENA (1 << 8) | ||
| 1601 | # define R600_POSITION_CENTROID (1 << 9) | ||
| 1602 | # define R600_POSITION_ADDR(x) ((x) << 10) | ||
| 1603 | # define R600_PARAM_GEN(x) ((x) << 15) | ||
| 1604 | # define R600_PARAM_GEN_ADDR(x) ((x) << 19) | ||
| 1605 | # define R600_BARYC_SAMPLE_CNTL(x) ((x) << 26) | ||
| 1606 | # define R600_PERSP_GRADIENT_ENA (1 << 28) | ||
| 1607 | # define R600_LINEAR_GRADIENT_ENA (1 << 29) | ||
| 1608 | # define R600_POSITION_SAMPLE (1 << 30) | ||
| 1609 | # define R600_BARYC_AT_SAMPLE_ENA (1 << 31) | ||
| 1610 | #define R600_SPI_PS_IN_CONTROL_1 0x286d0 | ||
| 1611 | # define R600_GEN_INDEX_PIX (1 << 0) | ||
| 1612 | # define R600_GEN_INDEX_PIX_ADDR(x) ((x) << 1) | ||
| 1613 | # define R600_FRONT_FACE_ENA (1 << 8) | ||
| 1614 | # define R600_FRONT_FACE_CHAN(x) ((x) << 9) | ||
| 1615 | # define R600_FRONT_FACE_ALL_BITS (1 << 11) | ||
| 1616 | # define R600_FRONT_FACE_ADDR(x) ((x) << 12) | ||
| 1617 | # define R600_FOG_ADDR(x) ((x) << 17) | ||
| 1618 | # define R600_FIXED_PT_POSITION_ENA (1 << 24) | ||
| 1619 | # define R600_FIXED_PT_POSITION_ADDR(x) ((x) << 25) | ||
| 1620 | # define R700_POSITION_ULC (1 << 30) | ||
| 1621 | #define R600_SPI_INPUT_Z 0x286d8 | ||
| 1622 | |||
| 1623 | #define R600_SPI_CONFIG_CNTL 0x9100 | ||
| 1624 | # define R600_GPR_WRITE_PRIORITY(x) ((x) << 0) | ||
| 1625 | # define R600_DISABLE_INTERP_1 (1 << 5) | ||
| 1626 | #define R600_SPI_CONFIG_CNTL_1 0x913c | ||
| 1627 | # define R600_VTX_DONE_DELAY(x) ((x) << 0) | ||
| 1628 | # define R600_INTERP_ONE_PRIM_PER_ROW (1 << 4) | ||
| 1629 | |||
| 1630 | #define R600_GB_TILING_CONFIG 0x98f0 | ||
| 1631 | # define R600_PIPE_TILING(x) ((x) << 1) | ||
| 1632 | # define R600_BANK_TILING(x) ((x) << 4) | ||
| 1633 | # define R600_GROUP_SIZE(x) ((x) << 6) | ||
| 1634 | # define R600_ROW_TILING(x) ((x) << 8) | ||
| 1635 | # define R600_BANK_SWAPS(x) ((x) << 11) | ||
| 1636 | # define R600_SAMPLE_SPLIT(x) ((x) << 14) | ||
| 1637 | # define R600_BACKEND_MAP(x) ((x) << 16) | ||
| 1638 | #define R600_DCP_TILING_CONFIG 0x6ca0 | ||
| 1639 | #define R600_HDP_TILING_CONFIG 0x2f3c | ||
| 1640 | |||
| 1641 | #define R600_CC_RB_BACKEND_DISABLE 0x98f4 | ||
| 1642 | #define R700_CC_SYS_RB_BACKEND_DISABLE 0x3f88 | ||
| 1643 | # define R600_BACKEND_DISABLE(x) ((x) << 16) | ||
| 1644 | |||
| 1645 | #define R600_CC_GC_SHADER_PIPE_CONFIG 0x8950 | ||
| 1646 | #define R600_GC_USER_SHADER_PIPE_CONFIG 0x8954 | ||
| 1647 | # define R600_INACTIVE_QD_PIPES(x) ((x) << 8) | ||
| 1648 | # define R600_INACTIVE_QD_PIPES_MASK (0xff << 8) | ||
| 1649 | # define R600_INACTIVE_SIMDS(x) ((x) << 16) | ||
| 1650 | # define R600_INACTIVE_SIMDS_MASK (0xff << 16) | ||
| 1651 | |||
| 1652 | #define R700_CGTS_SYS_TCC_DISABLE 0x3f90 | ||
| 1653 | #define R700_CGTS_USER_SYS_TCC_DISABLE 0x3f94 | ||
| 1654 | #define R700_CGTS_TCC_DISABLE 0x9148 | ||
| 1655 | #define R700_CGTS_USER_TCC_DISABLE 0x914c | ||
| 1656 | |||
| 1186 | /* Constants */ | 1657 | /* Constants */ |
| 1187 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ | 1658 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
| 1188 | 1659 | ||
| @@ -1192,6 +1663,11 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); | |||
| 1192 | #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 | 1663 | #define RADEON_LAST_SWI_REG RADEON_SCRATCH_REG3 |
| 1193 | #define RADEON_LAST_DISPATCH 1 | 1664 | #define RADEON_LAST_DISPATCH 1 |
| 1194 | 1665 | ||
| 1666 | #define R600_LAST_FRAME_REG R600_SCRATCH_REG0 | ||
| 1667 | #define R600_LAST_DISPATCH_REG R600_SCRATCH_REG1 | ||
| 1668 | #define R600_LAST_CLEAR_REG R600_SCRATCH_REG2 | ||
| 1669 | #define R600_LAST_SWI_REG R600_SCRATCH_REG3 | ||
| 1670 | |||
| 1195 | #define RADEON_MAX_VB_AGE 0x7fffffff | 1671 | #define RADEON_MAX_VB_AGE 0x7fffffff |
| 1196 | #define RADEON_MAX_VB_VERTS (0xffff) | 1672 | #define RADEON_MAX_VB_VERTS (0xffff) |
| 1197 | 1673 | ||
| @@ -1200,7 +1676,15 @@ extern u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index); | |||
| 1200 | #define RADEON_PCIGART_TABLE_SIZE (32*1024) | 1676 | #define RADEON_PCIGART_TABLE_SIZE (32*1024) |
| 1201 | 1677 | ||
| 1202 | #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) | 1678 | #define RADEON_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) |
| 1203 | #define RADEON_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) ) | 1679 | #define RADEON_WRITE(reg, val) \ |
| 1680 | do { \ | ||
| 1681 | if (reg < 0x10000) { \ | ||
| 1682 | DRM_WRITE32(dev_priv->mmio, (reg), (val)); \ | ||
| 1683 | } else { \ | ||
| 1684 | DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, (reg)); \ | ||
| 1685 | DRM_WRITE32(dev_priv->mmio, RADEON_MM_DATA, (val)); \ | ||
| 1686 | } \ | ||
| 1687 | } while (0) | ||
| 1204 | #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) | 1688 | #define RADEON_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) ) |
| 1205 | #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) | 1689 | #define RADEON_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) ) |
| 1206 | 1690 | ||
| @@ -1370,6 +1854,24 @@ do { \ | |||
| 1370 | OUT_RING( age ); \ | 1854 | OUT_RING( age ); \ |
| 1371 | } while (0) | 1855 | } while (0) |
| 1372 | 1856 | ||
| 1857 | #define R600_DISPATCH_AGE(age) do { \ | ||
| 1858 | OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ | ||
| 1859 | OUT_RING((R600_LAST_DISPATCH_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ | ||
| 1860 | OUT_RING(age); \ | ||
| 1861 | } while (0) | ||
| 1862 | |||
| 1863 | #define R600_FRAME_AGE(age) do { \ | ||
| 1864 | OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ | ||
| 1865 | OUT_RING((R600_LAST_FRAME_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ | ||
| 1866 | OUT_RING(age); \ | ||
| 1867 | } while (0) | ||
| 1868 | |||
| 1869 | #define R600_CLEAR_AGE(age) do { \ | ||
| 1870 | OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1)); \ | ||
| 1871 | OUT_RING((R600_LAST_CLEAR_REG - R600_SET_CONFIG_REG_OFFSET) >> 2); \ | ||
| 1872 | OUT_RING(age); \ | ||
| 1873 | } while (0) | ||
| 1874 | |||
| 1373 | /* ================================================================ | 1875 | /* ================================================================ |
| 1374 | * Ring control | 1876 | * Ring control |
| 1375 | */ | 1877 | */ |
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h index 73ff51f1231..937a275cbb9 100644 --- a/include/drm/radeon_drm.h +++ b/include/drm/radeon_drm.h | |||
| @@ -304,6 +304,8 @@ typedef union { | |||
| 304 | 304 | ||
| 305 | #define RADEON_SCRATCH_REG_OFFSET 32 | 305 | #define RADEON_SCRATCH_REG_OFFSET 32 |
| 306 | 306 | ||
| 307 | #define R600_SCRATCH_REG_OFFSET 256 | ||
| 308 | |||
| 307 | #define RADEON_NR_SAREA_CLIPRECTS 12 | 309 | #define RADEON_NR_SAREA_CLIPRECTS 12 |
| 308 | 310 | ||
| 309 | /* There are 2 heaps (local/GART). Each region within a heap is a | 311 | /* There are 2 heaps (local/GART). Each region within a heap is a |
| @@ -526,7 +528,8 @@ typedef struct drm_radeon_init { | |||
| 526 | RADEON_INIT_CP = 0x01, | 528 | RADEON_INIT_CP = 0x01, |
| 527 | RADEON_CLEANUP_CP = 0x02, | 529 | RADEON_CLEANUP_CP = 0x02, |
| 528 | RADEON_INIT_R200_CP = 0x03, | 530 | RADEON_INIT_R200_CP = 0x03, |
| 529 | RADEON_INIT_R300_CP = 0x04 | 531 | RADEON_INIT_R300_CP = 0x04, |
| 532 | RADEON_INIT_R600_CP = 0x05 | ||
| 530 | } func; | 533 | } func; |
| 531 | unsigned long sarea_priv_offset; | 534 | unsigned long sarea_priv_offset; |
| 532 | int is_pci; | 535 | int is_pci; |