diff options
author | Sujith <Sujith.Manoharan@atheros.com> | 2009-03-30 05:58:22 -0400 |
---|---|---|
committer | John W. Linville <linville@tuxdriver.com> | 2009-04-22 16:54:29 -0400 |
commit | bdbdf46daa6dccb472f56559854477faddc44de9 (patch) | |
tree | 24e6968f86689aab0e4db417e4d4f7205ad2911e | |
parent | 8782b41d13c8e5f9a201477d3c15edf9fe7c372c (diff) |
ath9k: Remove a few unused flags
This patch removes unused HW capability flags and
HW operation variables, and a chainmask flag that
we don't use anywhere.
Signed-off-by: Sujith <Sujith.Manoharan@atheros.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r-- | drivers/net/wireless/ath9k/ath9k.h | 25 | ||||
-rw-r--r-- | drivers/net/wireless/ath9k/hw.c | 21 | ||||
-rw-r--r-- | drivers/net/wireless/ath9k/hw.h | 52 | ||||
-rw-r--r-- | drivers/net/wireless/ath9k/main.c | 2 | ||||
-rw-r--r-- | drivers/net/wireless/ath9k/rc.h | 1 |
5 files changed, 30 insertions, 71 deletions
diff --git a/drivers/net/wireless/ath9k/ath9k.h b/drivers/net/wireless/ath9k/ath9k.h index 7b1b40aaf09..1dfc3816a2d 100644 --- a/drivers/net/wireless/ath9k/ath9k.h +++ b/drivers/net/wireless/ath9k/ath9k.h | |||
@@ -525,19 +525,18 @@ struct ath_rfkill { | |||
525 | #define SC_OP_BEACONS BIT(1) | 525 | #define SC_OP_BEACONS BIT(1) |
526 | #define SC_OP_RXAGGR BIT(2) | 526 | #define SC_OP_RXAGGR BIT(2) |
527 | #define SC_OP_TXAGGR BIT(3) | 527 | #define SC_OP_TXAGGR BIT(3) |
528 | #define SC_OP_CHAINMASK_UPDATE BIT(4) | 528 | #define SC_OP_FULL_RESET BIT(4) |
529 | #define SC_OP_FULL_RESET BIT(5) | 529 | #define SC_OP_PREAMBLE_SHORT BIT(5) |
530 | #define SC_OP_PREAMBLE_SHORT BIT(6) | 530 | #define SC_OP_PROTECT_ENABLE BIT(6) |
531 | #define SC_OP_PROTECT_ENABLE BIT(7) | 531 | #define SC_OP_RXFLUSH BIT(7) |
532 | #define SC_OP_RXFLUSH BIT(8) | 532 | #define SC_OP_LED_ASSOCIATED BIT(8) |
533 | #define SC_OP_LED_ASSOCIATED BIT(9) | 533 | #define SC_OP_RFKILL_REGISTERED BIT(9) |
534 | #define SC_OP_RFKILL_REGISTERED BIT(10) | 534 | #define SC_OP_RFKILL_SW_BLOCKED BIT(10) |
535 | #define SC_OP_RFKILL_SW_BLOCKED BIT(11) | 535 | #define SC_OP_RFKILL_HW_BLOCKED BIT(11) |
536 | #define SC_OP_RFKILL_HW_BLOCKED BIT(12) | 536 | #define SC_OP_WAIT_FOR_BEACON BIT(12) |
537 | #define SC_OP_WAIT_FOR_BEACON BIT(13) | 537 | #define SC_OP_LED_ON BIT(13) |
538 | #define SC_OP_LED_ON BIT(14) | 538 | #define SC_OP_SCANNING BIT(14) |
539 | #define SC_OP_SCANNING BIT(15) | 539 | #define SC_OP_TSF_RESET BIT(15) |
540 | #define SC_OP_TSF_RESET BIT(16) | ||
541 | 540 | ||
542 | struct ath_bus_ops { | 541 | struct ath_bus_ops { |
543 | void (*read_cachesize)(struct ath_softc *sc, int *csz); | 542 | void (*read_cachesize)(struct ath_softc *sc, int *csz); |
diff --git a/drivers/net/wireless/ath9k/hw.c b/drivers/net/wireless/ath9k/hw.c index b15eaf8417f..13d8c2a4efa 100644 --- a/drivers/net/wireless/ath9k/hw.c +++ b/drivers/net/wireless/ath9k/hw.c | |||
@@ -363,10 +363,7 @@ static void ath9k_hw_set_defaults(struct ath_hw *ah) | |||
363 | ah->config.ack_6mb = 0x0; | 363 | ah->config.ack_6mb = 0x0; |
364 | ah->config.cwm_ignore_extcca = 0; | 364 | ah->config.cwm_ignore_extcca = 0; |
365 | ah->config.pcie_powersave_enable = 0; | 365 | ah->config.pcie_powersave_enable = 0; |
366 | ah->config.pcie_l1skp_enable = 0; | ||
367 | ah->config.pcie_clock_req = 0; | 366 | ah->config.pcie_clock_req = 0; |
368 | ah->config.pcie_power_reset = 0x100; | ||
369 | ah->config.pcie_restore = 0; | ||
370 | ah->config.pcie_waen = 0; | 367 | ah->config.pcie_waen = 0; |
371 | ah->config.analog_shiftreg = 1; | 368 | ah->config.analog_shiftreg = 1; |
372 | ah->config.ht_enable = 1; | 369 | ah->config.ht_enable = 1; |
@@ -375,13 +372,6 @@ static void ath9k_hw_set_defaults(struct ath_hw *ah) | |||
375 | ah->config.cck_trig_high = 200; | 372 | ah->config.cck_trig_high = 200; |
376 | ah->config.cck_trig_low = 100; | 373 | ah->config.cck_trig_low = 100; |
377 | ah->config.enable_ani = 1; | 374 | ah->config.enable_ani = 1; |
378 | ah->config.noise_immunity_level = 4; | ||
379 | ah->config.ofdm_weaksignal_det = 1; | ||
380 | ah->config.cck_weaksignal_thr = 0; | ||
381 | ah->config.spur_immunity_level = 2; | ||
382 | ah->config.firstep_level = 0; | ||
383 | ah->config.rssi_thr_high = 40; | ||
384 | ah->config.rssi_thr_low = 7; | ||
385 | ah->config.diversity_control = 0; | 375 | ah->config.diversity_control = 0; |
386 | ah->config.antenna_switch_swap = 0; | 376 | ah->config.antenna_switch_swap = 0; |
387 | 377 | ||
@@ -3343,8 +3333,6 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) | |||
3343 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; | 3333 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP; |
3344 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; | 3334 | pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM; |
3345 | 3335 | ||
3346 | pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD; | ||
3347 | |||
3348 | if (ah->config.ht_enable) | 3336 | if (ah->config.ht_enable) |
3349 | pCap->hw_caps |= ATH9K_HW_CAP_HT; | 3337 | pCap->hw_caps |= ATH9K_HW_CAP_HT; |
3350 | else | 3338 | else |
@@ -3368,7 +3356,6 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) | |||
3368 | pCap->keycache_size = AR_KEYTABLE_SIZE; | 3356 | pCap->keycache_size = AR_KEYTABLE_SIZE; |
3369 | 3357 | ||
3370 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; | 3358 | pCap->hw_caps |= ATH9K_HW_CAP_FASTCC; |
3371 | pCap->num_mr_retries = 4; | ||
3372 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; | 3359 | pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD; |
3373 | 3360 | ||
3374 | if (AR_SREV_9285_10_OR_LATER(ah)) | 3361 | if (AR_SREV_9285_10_OR_LATER(ah)) |
@@ -3378,14 +3365,6 @@ bool ath9k_hw_fill_cap_info(struct ath_hw *ah) | |||
3378 | else | 3365 | else |
3379 | pCap->num_gpio_pins = AR_NUM_GPIO; | 3366 | pCap->num_gpio_pins = AR_NUM_GPIO; |
3380 | 3367 | ||
3381 | if (AR_SREV_9280_10_OR_LATER(ah)) { | ||
3382 | pCap->hw_caps |= ATH9K_HW_CAP_WOW; | ||
3383 | pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; | ||
3384 | } else { | ||
3385 | pCap->hw_caps &= ~ATH9K_HW_CAP_WOW; | ||
3386 | pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT; | ||
3387 | } | ||
3388 | |||
3389 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { | 3368 | if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) { |
3390 | pCap->hw_caps |= ATH9K_HW_CAP_CST; | 3369 | pCap->hw_caps |= ATH9K_HW_CAP_CST; |
3391 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; | 3370 | pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX; |
diff --git a/drivers/net/wireless/ath9k/hw.h b/drivers/net/wireless/ath9k/hw.h index 0b594e0ee26..5ba6a4b6035 100644 --- a/drivers/net/wireless/ath9k/hw.h +++ b/drivers/net/wireless/ath9k/hw.h | |||
@@ -124,29 +124,24 @@ enum wireless_mode { | |||
124 | }; | 124 | }; |
125 | 125 | ||
126 | enum ath9k_hw_caps { | 126 | enum ath9k_hw_caps { |
127 | ATH9K_HW_CAP_CHAN_SPREAD = BIT(0), | 127 | ATH9K_HW_CAP_MIC_AESCCM = BIT(0), |
128 | ATH9K_HW_CAP_MIC_AESCCM = BIT(1), | 128 | ATH9K_HW_CAP_MIC_CKIP = BIT(1), |
129 | ATH9K_HW_CAP_MIC_CKIP = BIT(2), | 129 | ATH9K_HW_CAP_MIC_TKIP = BIT(2), |
130 | ATH9K_HW_CAP_MIC_TKIP = BIT(3), | 130 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3), |
131 | ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4), | 131 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(4), |
132 | ATH9K_HW_CAP_CIPHER_CKIP = BIT(5), | 132 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(5), |
133 | ATH9K_HW_CAP_CIPHER_TKIP = BIT(6), | 133 | ATH9K_HW_CAP_VEOL = BIT(6), |
134 | ATH9K_HW_CAP_VEOL = BIT(7), | 134 | ATH9K_HW_CAP_BSSIDMASK = BIT(7), |
135 | ATH9K_HW_CAP_BSSIDMASK = BIT(8), | 135 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8), |
136 | ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9), | 136 | ATH9K_HW_CAP_HT = BIT(9), |
137 | ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10), | 137 | ATH9K_HW_CAP_GTT = BIT(10), |
138 | ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11), | 138 | ATH9K_HW_CAP_FASTCC = BIT(11), |
139 | ATH9K_HW_CAP_HT = BIT(12), | 139 | ATH9K_HW_CAP_RFSILENT = BIT(12), |
140 | ATH9K_HW_CAP_GTT = BIT(13), | 140 | ATH9K_HW_CAP_CST = BIT(13), |
141 | ATH9K_HW_CAP_FASTCC = BIT(14), | 141 | ATH9K_HW_CAP_ENHANCEDPM = BIT(14), |
142 | ATH9K_HW_CAP_RFSILENT = BIT(15), | 142 | ATH9K_HW_CAP_AUTOSLEEP = BIT(15), |
143 | ATH9K_HW_CAP_WOW = BIT(16), | 143 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16), |
144 | ATH9K_HW_CAP_CST = BIT(17), | 144 | ATH9K_HW_CAP_BT_COEX = BIT(17) |
145 | ATH9K_HW_CAP_ENHANCEDPM = BIT(18), | ||
146 | ATH9K_HW_CAP_AUTOSLEEP = BIT(19), | ||
147 | ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20), | ||
148 | ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21), | ||
149 | ATH9K_HW_CAP_BT_COEX = BIT(22) | ||
150 | }; | 145 | }; |
151 | 146 | ||
152 | enum ath9k_capability_type { | 147 | enum ath9k_capability_type { |
@@ -166,7 +161,6 @@ struct ath9k_hw_capabilities { | |||
166 | u16 keycache_size; | 161 | u16 keycache_size; |
167 | u16 low_5ghz_chan, high_5ghz_chan; | 162 | u16 low_5ghz_chan, high_5ghz_chan; |
168 | u16 low_2ghz_chan, high_2ghz_chan; | 163 | u16 low_2ghz_chan, high_2ghz_chan; |
169 | u16 num_mr_retries; | ||
170 | u16 rts_aggr_limit; | 164 | u16 rts_aggr_limit; |
171 | u8 tx_chainmask; | 165 | u8 tx_chainmask; |
172 | u8 rx_chainmask; | 166 | u8 rx_chainmask; |
@@ -184,11 +178,8 @@ struct ath9k_ops_config { | |||
184 | int ack_6mb; | 178 | int ack_6mb; |
185 | int cwm_ignore_extcca; | 179 | int cwm_ignore_extcca; |
186 | u8 pcie_powersave_enable; | 180 | u8 pcie_powersave_enable; |
187 | u8 pcie_l1skp_enable; | ||
188 | u8 pcie_clock_req; | 181 | u8 pcie_clock_req; |
189 | u32 pcie_waen; | 182 | u32 pcie_waen; |
190 | int pcie_power_reset; | ||
191 | u8 pcie_restore; | ||
192 | u8 analog_shiftreg; | 183 | u8 analog_shiftreg; |
193 | u8 ht_enable; | 184 | u8 ht_enable; |
194 | u32 ofdm_trig_low; | 185 | u32 ofdm_trig_low; |
@@ -196,13 +187,6 @@ struct ath9k_ops_config { | |||
196 | u32 cck_trig_high; | 187 | u32 cck_trig_high; |
197 | u32 cck_trig_low; | 188 | u32 cck_trig_low; |
198 | u32 enable_ani; | 189 | u32 enable_ani; |
199 | u8 noise_immunity_level; | ||
200 | u32 ofdm_weaksignal_det; | ||
201 | u32 cck_weaksignal_thr; | ||
202 | u8 spur_immunity_level; | ||
203 | u8 firstep_level; | ||
204 | int8_t rssi_thr_high; | ||
205 | int8_t rssi_thr_low; | ||
206 | u16 diversity_control; | 190 | u16 diversity_control; |
207 | u16 antenna_switch_swap; | 191 | u16 antenna_switch_swap; |
208 | int serialize_regmode; | 192 | int serialize_regmode; |
diff --git a/drivers/net/wireless/ath9k/main.c b/drivers/net/wireless/ath9k/main.c index 97cf83fa855..74fe777b54e 100644 --- a/drivers/net/wireless/ath9k/main.c +++ b/drivers/net/wireless/ath9k/main.c | |||
@@ -287,7 +287,6 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw, | |||
287 | } | 287 | } |
288 | spin_unlock_bh(&sc->sc_resetlock); | 288 | spin_unlock_bh(&sc->sc_resetlock); |
289 | 289 | ||
290 | sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE; | ||
291 | sc->sc_flags &= ~SC_OP_FULL_RESET; | 290 | sc->sc_flags &= ~SC_OP_FULL_RESET; |
292 | 291 | ||
293 | if (ath_startrecv(sc) != 0) { | 292 | if (ath_startrecv(sc) != 0) { |
@@ -416,7 +415,6 @@ set_timer: | |||
416 | */ | 415 | */ |
417 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) | 416 | void ath_update_chainmask(struct ath_softc *sc, int is_ht) |
418 | { | 417 | { |
419 | sc->sc_flags |= SC_OP_CHAINMASK_UPDATE; | ||
420 | if (is_ht || | 418 | if (is_ht || |
421 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { | 419 | (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) { |
422 | sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask; | 420 | sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask; |
diff --git a/drivers/net/wireless/ath9k/rc.h b/drivers/net/wireless/ath9k/rc.h index 199a3ce57d6..ec72dd29da0 100644 --- a/drivers/net/wireless/ath9k/rc.h +++ b/drivers/net/wireless/ath9k/rc.h | |||
@@ -24,7 +24,6 @@ struct ath_softc; | |||
24 | #define ATH_RATE_MAX 30 | 24 | #define ATH_RATE_MAX 30 |
25 | #define RATE_TABLE_SIZE 64 | 25 | #define RATE_TABLE_SIZE 64 |
26 | #define MAX_TX_RATE_PHY 48 | 26 | #define MAX_TX_RATE_PHY 48 |
27 | #define WLAN_CTRL_FRAME_SIZE (2+2+6+4) | ||
28 | 27 | ||
29 | /* VALID_ALL - valid for 20/40/Legacy, | 28 | /* VALID_ALL - valid for 20/40/Legacy, |
30 | * VALID - Legacy only, | 29 | * VALID - Legacy only, |