diff options
author | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:07 -0400 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2007-10-11 18:46:07 -0400 |
commit | baf22c1e7aedf264e264b15d2595e5e76564bd4e (patch) | |
tree | 6983687e9e1a7442247d418207bfb36254167214 | |
parent | 21c854dcbd7698bf723676a552968040e2813490 (diff) |
[MIPS] Split up war.h
It was getting a little big, ugly and a primary source for merge conflicts.
Also the old method was a bit too forgiving in that the workaround did
default to off, so now there is an explicit #error forcing platform
maintainers to think if they should enable a workaround for a particular
platform.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
24 files changed, 625 insertions, 97 deletions
diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h new file mode 100644 index 00000000000..dd57d03d68b --- /dev/null +++ b/include/asm-mips/mach-au1x00/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_AU1X00_WAR_H | ||
9 | #define __ASM_MIPS_MACH_AU1X00_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */ | ||
diff --git a/include/asm-mips/mach-bcm47xx/war.h b/include/asm-mips/mach-bcm47xx/war.h new file mode 100644 index 00000000000..4a2b7986b58 --- /dev/null +++ b/include/asm-mips/mach-bcm47xx/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H | ||
9 | #define __ASM_MIPS_MACH_BCM947XX_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */ | ||
diff --git a/include/asm-mips/mach-cobalt/war.h b/include/asm-mips/mach-cobalt/war.h new file mode 100644 index 00000000000..97884fd18ac --- /dev/null +++ b/include/asm-mips/mach-cobalt/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_COBALT_WAR_H | ||
9 | #define __ASM_MIPS_MACH_COBALT_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_COBALT_WAR_H */ | ||
diff --git a/include/asm-mips/mach-dec/war.h b/include/asm-mips/mach-dec/war.h new file mode 100644 index 00000000000..ca5e2ef909a --- /dev/null +++ b/include/asm-mips/mach-dec/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_DEC_WAR_H | ||
9 | #define __ASM_MIPS_MACH_DEC_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_DEC_WAR_H */ | ||
diff --git a/include/asm-mips/mach-emma2rh/war.h b/include/asm-mips/mach-emma2rh/war.h new file mode 100644 index 00000000000..b660a4c30e6 --- /dev/null +++ b/include/asm-mips/mach-emma2rh/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H | ||
9 | #define __ASM_MIPS_MACH_EMMA2RH_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */ | ||
diff --git a/include/asm-mips/mach-excite/war.h b/include/asm-mips/mach-excite/war.h new file mode 100644 index 00000000000..1f82180c159 --- /dev/null +++ b/include/asm-mips/mach-excite/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_EXCITE_WAR_H | ||
9 | #define __ASM_MIPS_MACH_EXCITE_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 1 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */ | ||
diff --git a/include/asm-mips/mach-ip22/war.h b/include/asm-mips/mach-ip22/war.h new file mode 100644 index 00000000000..a44fa9656a8 --- /dev/null +++ b/include/asm-mips/mach-ip22/war.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_IP22_WAR_H | ||
9 | #define __ASM_MIPS_MACH_IP22_WAR_H | ||
10 | |||
11 | /* | ||
12 | * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. | ||
13 | */ | ||
14 | |||
15 | #define R4600_V1_INDEX_ICACHEOP_WAR 1 | ||
16 | #define R4600_V1_HIT_CACHEOP_WAR 1 | ||
17 | #define R4600_V2_HIT_CACHEOP_WAR 1 | ||
18 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
19 | #define BCM1250_M3_WAR 0 | ||
20 | #define SIBYTE_1956_WAR 0 | ||
21 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
22 | #define MIPS_CACHE_SYNC_WAR 0 | ||
23 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
24 | #define RM9000_CDEX_SMP_WAR 0 | ||
25 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
26 | #define R10000_LLSC_WAR 0 | ||
27 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
28 | |||
29 | #endif /* __ASM_MIPS_MACH_IP22_WAR_H */ | ||
diff --git a/include/asm-mips/mach-ip27/war.h b/include/asm-mips/mach-ip27/war.h new file mode 100644 index 00000000000..e2ddcc9b1ff --- /dev/null +++ b/include/asm-mips/mach-ip27/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_IP27_WAR_H | ||
9 | #define __ASM_MIPS_MACH_IP27_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 1 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_IP27_WAR_H */ | ||
diff --git a/include/asm-mips/mach-ip32/war.h b/include/asm-mips/mach-ip32/war.h new file mode 100644 index 00000000000..d194056dcd7 --- /dev/null +++ b/include/asm-mips/mach-ip32/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_IP32_WAR_H | ||
9 | #define __ASM_MIPS_MACH_IP32_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_IP32_WAR_H */ | ||
diff --git a/include/asm-mips/mach-jazz/war.h b/include/asm-mips/mach-jazz/war.h new file mode 100644 index 00000000000..6158ee861bf --- /dev/null +++ b/include/asm-mips/mach-jazz/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_JAZZ_WAR_H | ||
9 | #define __ASM_MIPS_MACH_JAZZ_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */ | ||
diff --git a/include/asm-mips/mach-jmr3927/war.h b/include/asm-mips/mach-jmr3927/war.h new file mode 100644 index 00000000000..1ff55fb3fbc --- /dev/null +++ b/include/asm-mips/mach-jmr3927/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_JMR3927_WAR_H | ||
9 | #define __ASM_MIPS_MACH_JMR3927_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_JMR3927_WAR_H */ | ||
diff --git a/include/asm-mips/mach-lasat/war.h b/include/asm-mips/mach-lasat/war.h new file mode 100644 index 00000000000..bb1e0325c9b --- /dev/null +++ b/include/asm-mips/mach-lasat/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_LASAT_WAR_H | ||
9 | #define __ASM_MIPS_MACH_LASAT_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_LASAT_WAR_H */ | ||
diff --git a/include/asm-mips/mach-lemote/war.h b/include/asm-mips/mach-lemote/war.h new file mode 100644 index 00000000000..05f89e0f2a1 --- /dev/null +++ b/include/asm-mips/mach-lemote/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H | ||
9 | #define __ASM_MIPS_MACH_LEMOTE_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ | ||
diff --git a/include/asm-mips/mach-mips/war.h b/include/asm-mips/mach-mips/war.h new file mode 100644 index 00000000000..7c6931d5f45 --- /dev/null +++ b/include/asm-mips/mach-mips/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_MIPS_WAR_H | ||
9 | #define __ASM_MIPS_MACH_MIPS_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 1 | ||
18 | #define MIPS_CACHE_SYNC_WAR 1 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ | ||
diff --git a/include/asm-mips/mach-mipssim/war.h b/include/asm-mips/mach-mipssim/war.h new file mode 100644 index 00000000000..c8a74a3515e --- /dev/null +++ b/include/asm-mips/mach-mipssim/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H | ||
9 | #define __ASM_MIPS_MACH_MIPSSIM_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */ | ||
diff --git a/include/asm-mips/mach-pnx8550/war.h b/include/asm-mips/mach-pnx8550/war.h new file mode 100644 index 00000000000..d0458dd082f --- /dev/null +++ b/include/asm-mips/mach-pnx8550/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_PNX8550_WAR_H | ||
9 | #define __ASM_MIPS_MACH_PNX8550_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */ | ||
diff --git a/include/asm-mips/mach-qemu/war.h b/include/asm-mips/mach-qemu/war.h new file mode 100644 index 00000000000..0eaf0c548a4 --- /dev/null +++ b/include/asm-mips/mach-qemu/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_QEMU_WAR_H | ||
9 | #define __ASM_MIPS_MACH_QEMU_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_QEMU_WAR_H */ | ||
diff --git a/include/asm-mips/mach-rm/war.h b/include/asm-mips/mach-rm/war.h new file mode 100644 index 00000000000..948d3129a11 --- /dev/null +++ b/include/asm-mips/mach-rm/war.h | |||
@@ -0,0 +1,29 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_RM_WAR_H | ||
9 | #define __ASM_MIPS_MACH_RM_WAR_H | ||
10 | |||
11 | /* | ||
12 | * The RM200C seems to have been shipped only with V2.0 R4600s | ||
13 | */ | ||
14 | |||
15 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
16 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
17 | #define R4600_V2_HIT_CACHEOP_WAR 1 | ||
18 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
19 | #define BCM1250_M3_WAR 0 | ||
20 | #define SIBYTE_1956_WAR 0 | ||
21 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
22 | #define MIPS_CACHE_SYNC_WAR 0 | ||
23 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
24 | #define RM9000_CDEX_SMP_WAR 0 | ||
25 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
26 | #define R10000_LLSC_WAR 0 | ||
27 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
28 | |||
29 | #endif /* __ASM_MIPS_MACH_RM_WAR_H */ | ||
diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h new file mode 100644 index 00000000000..7950ef4f032 --- /dev/null +++ b/include/asm-mips/mach-sibyte/war.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H | ||
9 | #define __ASM_MIPS_MACH_SIBYTE_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | |||
16 | #if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ | ||
17 | defined(CONFIG_SB1_PASS_2_WORKAROUNDS) | ||
18 | |||
19 | #define BCM1250_M3_WAR 1 | ||
20 | #define SIBYTE_1956_WAR 1 | ||
21 | |||
22 | #else | ||
23 | |||
24 | #define BCM1250_M3_WAR 0 | ||
25 | #define SIBYTE_1956_WAR 0 | ||
26 | |||
27 | #endif | ||
28 | |||
29 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
30 | #define MIPS_CACHE_SYNC_WAR 0 | ||
31 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
32 | #define RM9000_CDEX_SMP_WAR 0 | ||
33 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
34 | #define R10000_LLSC_WAR 0 | ||
35 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
36 | |||
37 | #endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */ | ||
diff --git a/include/asm-mips/mach-tx49xx/war.h b/include/asm-mips/mach-tx49xx/war.h new file mode 100644 index 00000000000..39b5d1177c5 --- /dev/null +++ b/include/asm-mips/mach-tx49xx/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_TX49XX_WAR_H | ||
9 | #define __ASM_MIPS_MACH_TX49XX_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 1 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */ | ||
diff --git a/include/asm-mips/mach-vr41xx/war.h b/include/asm-mips/mach-vr41xx/war.h new file mode 100644 index 00000000000..56a38926412 --- /dev/null +++ b/include/asm-mips/mach-vr41xx/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_VR41XX_WAR_H | ||
9 | #define __ASM_MIPS_MACH_VR41XX_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */ | ||
diff --git a/include/asm-mips/mach-wrppmc/war.h b/include/asm-mips/mach-wrppmc/war.h new file mode 100644 index 00000000000..ac48629bb1c --- /dev/null +++ b/include/asm-mips/mach-wrppmc/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H | ||
9 | #define __ASM_MIPS_MACH_WRPPMC_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 0 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */ | ||
diff --git a/include/asm-mips/mach-yosemite/war.h b/include/asm-mips/mach-yosemite/war.h new file mode 100644 index 00000000000..e5c6d53efc8 --- /dev/null +++ b/include/asm-mips/mach-yosemite/war.h | |||
@@ -0,0 +1,25 @@ | |||
1 | /* | ||
2 | * This file is subject to the terms and conditions of the GNU General Public | ||
3 | * License. See the file "COPYING" in the main directory of this archive | ||
4 | * for more details. | ||
5 | * | ||
6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> | ||
7 | */ | ||
8 | #ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H | ||
9 | #define __ASM_MIPS_MACH_YOSEMITE_WAR_H | ||
10 | |||
11 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
12 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
13 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
14 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
15 | #define BCM1250_M3_WAR 0 | ||
16 | #define SIBYTE_1956_WAR 0 | ||
17 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
18 | #define MIPS_CACHE_SYNC_WAR 0 | ||
19 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
20 | #define RM9000_CDEX_SMP_WAR 1 | ||
21 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
22 | #define R10000_LLSC_WAR 0 | ||
23 | #define MIPS34K_MISSED_ITLB_WAR 0 | ||
24 | |||
25 | #endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */ | ||
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h index c0715d0a6b2..d2808edfd4e 100644 --- a/include/asm-mips/war.h +++ b/include/asm-mips/war.h | |||
@@ -3,20 +3,22 @@ | |||
3 | * License. See the file "COPYING" in the main directory of this archive | 3 | * License. See the file "COPYING" in the main directory of this archive |
4 | * for more details. | 4 | * for more details. |
5 | * | 5 | * |
6 | * Copyright (C) 2002, 2004 by Ralf Baechle | 6 | * Copyright (C) 2002, 2004, 2007 by Ralf Baechle |
7 | */ | 7 | */ |
8 | #ifndef _ASM_WAR_H | 8 | #ifndef _ASM_WAR_H |
9 | #define _ASM_WAR_H | 9 | #define _ASM_WAR_H |
10 | 10 | ||
11 | #include <war.h> | ||
11 | 12 | ||
12 | /* | 13 | /* |
13 | * Another R4600 erratum. Due to the lack of errata information the exact | 14 | * Another R4600 erratum. Due to the lack of errata information the exact |
14 | * technical details aren't known. I've experimentally found that disabling | 15 | * technical details aren't known. I've experimentally found that disabling |
15 | * interrupts during indexed I-cache flushes seems to be sufficient to deal | 16 | * interrupts during indexed I-cache flushes seems to be sufficient to deal |
16 | * with the issue. | 17 | * with the issue. |
17 | * | ||
18 | * #define R4600_V1_INDEX_ICACHEOP_WAR 1 | ||
19 | */ | 18 | */ |
19 | #ifndef R4600_V1_INDEX_ICACHEOP_WAR | ||
20 | #error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform | ||
21 | #endif | ||
20 | 22 | ||
21 | /* | 23 | /* |
22 | * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: | 24 | * Pleasures of the R4600 V1.x. Cite from the IDT R4600 V1.7 errata: |
@@ -43,9 +45,10 @@ | |||
43 | * nop | 45 | * nop |
44 | * nop | 46 | * nop |
45 | * cache Hit_Writeback_Invalidate_D | 47 | * cache Hit_Writeback_Invalidate_D |
46 | * | ||
47 | * #define R4600_V1_HIT_CACHEOP_WAR 1 | ||
48 | */ | 48 | */ |
49 | #ifndef R4600_V1_HIT_CACHEOP_WAR | ||
50 | #error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform | ||
51 | #endif | ||
49 | 52 | ||
50 | 53 | ||
51 | /* | 54 | /* |
@@ -58,32 +61,11 @@ | |||
58 | * by a load instruction to an uncached address to empty the response buffer." | 61 | * by a load instruction to an uncached address to empty the response buffer." |
59 | * (Revision 2.0 device errata from IDT available on http://www.idt.com/ | 62 | * (Revision 2.0 device errata from IDT available on http://www.idt.com/ |
60 | * in .pdf format.) | 63 | * in .pdf format.) |
61 | * | ||
62 | * #define R4600_V2_HIT_CACHEOP_WAR 1 | ||
63 | */ | ||
64 | |||
65 | /* | ||
66 | * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors. | ||
67 | */ | ||
68 | #ifdef CONFIG_SGI_IP22 | ||
69 | |||
70 | #define R4600_V1_INDEX_ICACHEOP_WAR 1 | ||
71 | #define R4600_V1_HIT_CACHEOP_WAR 1 | ||
72 | #define R4600_V2_HIT_CACHEOP_WAR 1 | ||
73 | |||
74 | #endif | ||
75 | |||
76 | /* | ||
77 | * But the RM200C seems to have been shipped only with V2.0 R4600s | ||
78 | */ | 64 | */ |
79 | #ifdef CONFIG_SNI_RM | 65 | #ifndef R4600_V2_HIT_CACHEOP_WAR |
80 | 66 | #error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform | |
81 | #define R4600_V2_HIT_CACHEOP_WAR 1 | ||
82 | |||
83 | #endif | 67 | #endif |
84 | 68 | ||
85 | #ifdef CONFIG_CPU_R5432 | ||
86 | |||
87 | /* | 69 | /* |
88 | * When an interrupt happens on a CP0 register read instruction, CPU may | 70 | * When an interrupt happens on a CP0 register read instruction, CPU may |
89 | * lock up or read corrupted values of CP0 registers after it enters | 71 | * lock up or read corrupted values of CP0 registers after it enters |
@@ -93,13 +75,10 @@ | |||
93 | * first thing in the exception handler, which breaks one of the | 75 | * first thing in the exception handler, which breaks one of the |
94 | * pre-conditions for this problem. | 76 | * pre-conditions for this problem. |
95 | */ | 77 | */ |
96 | #define R5432_CP0_INTERRUPT_WAR 1 | 78 | #ifndef R5432_CP0_INTERRUPT_WAR |
97 | 79 | #error Check setting of R5432_CP0_INTERRUPT_WAR for your platform | |
98 | #endif | 80 | #endif |
99 | 81 | ||
100 | #if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \ | ||
101 | defined(CONFIG_SB1_PASS_2_WORKAROUNDS) | ||
102 | |||
103 | /* | 82 | /* |
104 | * Workaround for the Sibyte M3 errata the text of which can be found at | 83 | * Workaround for the Sibyte M3 errata the text of which can be found at |
105 | * | 84 | * |
@@ -110,13 +89,15 @@ | |||
110 | * will just return and take the exception again if the information was | 89 | * will just return and take the exception again if the information was |
111 | * found to be inconsistent. | 90 | * found to be inconsistent. |
112 | */ | 91 | */ |
113 | #define BCM1250_M3_WAR 1 | 92 | #ifndef BCM1250_M3_WAR |
93 | #error Check setting of BCM1250_M3_WAR for your platform | ||
94 | #endif | ||
114 | 95 | ||
115 | /* | 96 | /* |
116 | * This is a DUART workaround related to glitches around register accesses | 97 | * This is a DUART workaround related to glitches around register accesses |
117 | */ | 98 | */ |
118 | #define SIBYTE_1956_WAR 1 | 99 | #ifndef SIBYTE_1956_WAR |
119 | 100 | #error Check setting of SIBYTE_1956_WAR for your platform | |
120 | #endif | 101 | #endif |
121 | 102 | ||
122 | /* | 103 | /* |
@@ -131,9 +112,8 @@ | |||
131 | * Affects: | 112 | * Affects: |
132 | * MIPS 4K RTL revision <3.0, PRID revision <4 | 113 | * MIPS 4K RTL revision <3.0, PRID revision <4 |
133 | */ | 114 | */ |
134 | #if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ | 115 | #ifndef MIPS4K_ICACHE_REFILL_WAR |
135 | defined(CONFIG_MIPS_SEAD) | 116 | #error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform |
136 | #define MIPS4K_ICACHE_REFILL_WAR 1 | ||
137 | #endif | 117 | #endif |
138 | 118 | ||
139 | /* | 119 | /* |
@@ -151,9 +131,8 @@ | |||
151 | * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 | 131 | * MIPS 5Kc,5Kf RTL revision <2.3, PRID revision <8 |
152 | * MIPS 20Kc RTL revision <4.0, PRID revision <? | 132 | * MIPS 20Kc RTL revision <4.0, PRID revision <? |
153 | */ | 133 | */ |
154 | #if defined(CONFIG_MIPS_MALTA) || defined(CONFIG_MIPS_ATLAS) || \ | 134 | #ifndef MIPS_CACHE_SYNC_WAR |
155 | defined(CONFIG_MIPS_SEAD) | 135 | #error Check setting of MIPS_CACHE_SYNC_WAR for your platform |
156 | #define MIPS_CACHE_SYNC_WAR 1 | ||
157 | #endif | 136 | #endif |
158 | 137 | ||
159 | /* | 138 | /* |
@@ -163,16 +142,16 @@ | |||
163 | * | 142 | * |
164 | * Workaround: do two phase flushing for Index_Invalidate_I | 143 | * Workaround: do two phase flushing for Index_Invalidate_I |
165 | */ | 144 | */ |
166 | #ifdef CONFIG_CPU_TX49XX | 145 | #ifndef TX49XX_ICACHE_INDEX_INV_WAR |
167 | #define TX49XX_ICACHE_INDEX_INV_WAR 1 | 146 | #error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform |
168 | #endif | 147 | #endif |
169 | 148 | ||
170 | /* | 149 | /* |
171 | * On the RM9000 there is a problem which makes the CreateDirtyExclusive | 150 | * On the RM9000 there is a problem which makes the CreateDirtyExclusive |
172 | * eache operation unusable on SMP systems. | 151 | * eache operation unusable on SMP systems. |
173 | */ | 152 | */ |
174 | #if defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE) | 153 | #ifndef RM9000_CDEX_SMP_WAR |
175 | #define RM9000_CDEX_SMP_WAR 1 | 154 | #error Check setting of RM9000_CDEX_SMP_WAR for your platform |
176 | #endif | 155 | #endif |
177 | 156 | ||
178 | /* | 157 | /* |
@@ -181,69 +160,23 @@ | |||
181 | * I-cache line worth of instructions being fetched may case spurious | 160 | * I-cache line worth of instructions being fetched may case spurious |
182 | * exceptions. | 161 | * exceptions. |
183 | */ | 162 | */ |
184 | #if defined(CONFIG_BASLER_EXCITE) || defined(CONFIG_MIPS_ATLAS) || \ | 163 | #ifndef ICACHE_REFILLS_WORKAROUND_WAR |
185 | defined(CONFIG_MIPS_MALTA) || defined(CONFIG_PMC_YOSEMITE) || \ | 164 | #error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform |
186 | defined(CONFIG_SGI_IP32) || defined(CONFIG_WR_PPMC) | ||
187 | #define ICACHE_REFILLS_WORKAROUND_WAR 1 | ||
188 | #endif | 165 | #endif |
189 | 166 | ||
190 | /* | 167 | /* |
191 | * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that | 168 | * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that |
192 | * may cause ll / sc and lld / scd sequences to execute non-atomically. | 169 | * may cause ll / sc and lld / scd sequences to execute non-atomically. |
193 | */ | 170 | */ |
194 | #ifdef CONFIG_SGI_IP27 | 171 | #ifndef R10000_LLSC_WAR |
195 | #define R10000_LLSC_WAR 1 | 172 | #error Check setting of R10000_LLSC_WAR for your platform |
196 | #endif | 173 | #endif |
197 | 174 | ||
198 | /* | 175 | /* |
199 | * 34K core erratum: "Problems Executing the TLBR Instruction" | 176 | * 34K core erratum: "Problems Executing the TLBR Instruction" |
200 | */ | 177 | */ |
201 | #if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \ | ||
202 | defined(CONFIG_PMC_MSP7120_FPGA) | ||
203 | #define MIPS34K_MISSED_ITLB_WAR 1 | ||
204 | #endif | ||
205 | |||
206 | /* | ||
207 | * Workarounds default to off | ||
208 | */ | ||
209 | #ifndef ICACHE_REFILLS_WORKAROUND_WAR | ||
210 | #define ICACHE_REFILLS_WORKAROUND_WAR 0 | ||
211 | #endif | ||
212 | #ifndef R4600_V1_INDEX_ICACHEOP_WAR | ||
213 | #define R4600_V1_INDEX_ICACHEOP_WAR 0 | ||
214 | #endif | ||
215 | #ifndef R4600_V1_HIT_CACHEOP_WAR | ||
216 | #define R4600_V1_HIT_CACHEOP_WAR 0 | ||
217 | #endif | ||
218 | #ifndef R4600_V2_HIT_CACHEOP_WAR | ||
219 | #define R4600_V2_HIT_CACHEOP_WAR 0 | ||
220 | #endif | ||
221 | #ifndef R5432_CP0_INTERRUPT_WAR | ||
222 | #define R5432_CP0_INTERRUPT_WAR 0 | ||
223 | #endif | ||
224 | #ifndef BCM1250_M3_WAR | ||
225 | #define BCM1250_M3_WAR 0 | ||
226 | #endif | ||
227 | #ifndef SIBYTE_1956_WAR | ||
228 | #define SIBYTE_1956_WAR 0 | ||
229 | #endif | ||
230 | #ifndef MIPS4K_ICACHE_REFILL_WAR | ||
231 | #define MIPS4K_ICACHE_REFILL_WAR 0 | ||
232 | #endif | ||
233 | #ifndef MIPS_CACHE_SYNC_WAR | ||
234 | #define MIPS_CACHE_SYNC_WAR 0 | ||
235 | #endif | ||
236 | #ifndef TX49XX_ICACHE_INDEX_INV_WAR | ||
237 | #define TX49XX_ICACHE_INDEX_INV_WAR 0 | ||
238 | #endif | ||
239 | #ifndef RM9000_CDEX_SMP_WAR | ||
240 | #define RM9000_CDEX_SMP_WAR 0 | ||
241 | #endif | ||
242 | #ifndef R10000_LLSC_WAR | ||
243 | #define R10000_LLSC_WAR 0 | ||
244 | #endif | ||
245 | #ifndef MIPS34K_MISSED_ITLB_WAR | 178 | #ifndef MIPS34K_MISSED_ITLB_WAR |
246 | #define MIPS34K_MISSED_ITLB_WAR 0 | 179 | #error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform |
247 | #endif | 180 | #endif |
248 | 181 | ||
249 | #endif /* _ASM_WAR_H */ | 182 | #endif /* _ASM_WAR_H */ |