diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2011-07-20 06:20:50 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-10-03 14:40:42 -0400 |
commit | b7d4d461ad51ad98992a1b4d0b46f86ccabd1ee0 (patch) | |
tree | 6905f65d03a5e00e094447ff539802b80f8836d1 | |
parent | 52734d26ffca727da0e687963333ae88056ad84b (diff) |
tg3: Fix io failures after chip reset
commit 9e975cc291d80d5e4562d6bed15ec171e896d69b upstream.
Commit f2096f94b514d88593355995d5dd276961e88af1, entitled
"tg3: Add 5720 H2BMC support", needed to add code to preserve some bits
set by firmware. Unfortunately the new code causes throughput to stop
after a chip reset because it enables state machines before they are
ready. This patch undoes the problematic code. The bits will be
restored later in the init sequence.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r-- | drivers/net/tg3.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index a1f9f9eef37..ef0dab45188 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -7267,16 +7267,11 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
7267 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | 7267 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); |
7268 | } | 7268 | } |
7269 | 7269 | ||
7270 | if (tg3_flag(tp, ENABLE_APE)) | ||
7271 | tp->mac_mode = MAC_MODE_APE_TX_EN | | ||
7272 | MAC_MODE_APE_RX_EN | | ||
7273 | MAC_MODE_TDE_ENABLE; | ||
7274 | |||
7275 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | 7270 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
7276 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | 7271 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
7277 | val = tp->mac_mode; | 7272 | val = tp->mac_mode; |
7278 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { | 7273 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
7279 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | 7274 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
7280 | val = tp->mac_mode; | 7275 | val = tp->mac_mode; |
7281 | } else | 7276 | } else |
7282 | val = 0; | 7277 | val = 0; |
@@ -8408,12 +8403,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
8408 | udelay(10); | 8403 | udelay(10); |
8409 | } | 8404 | } |
8410 | 8405 | ||
8411 | if (tg3_flag(tp, ENABLE_APE)) | ||
8412 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | ||
8413 | else | ||
8414 | tp->mac_mode = 0; | ||
8415 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | 8406 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
8416 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; | 8407 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
8408 | MAC_MODE_FHDE_ENABLE; | ||
8409 | if (tg3_flag(tp, ENABLE_APE)) | ||
8410 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | ||
8417 | if (!tg3_flag(tp, 5705_PLUS) && | 8411 | if (!tg3_flag(tp, 5705_PLUS) && |
8418 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && | 8412 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
8419 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | 8413 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |