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authorSascha Hauer <s.hauer@pengutronix.de>2009-02-18 05:55:33 -0500
committerSascha Hauer <s.hauer@pengutronix.de>2009-03-13 05:34:32 -0400
commit9eb2eb8c40ffd30da322648c4415bae0288eb167 (patch)
treeb2402fd33314e4a78d11d8429c86ffe15cac8d4c
parent9a51157bab06ab54d6ee442e34fe9574ff14c8c3 (diff)
MX31 clkdev support
This patch adds clkdev support for i.MX31. This is done in a similar way done previously for i.MX27 Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Diffstat
-rw-r--r--arch/arm/mach-mx3/clock.c932
-rw-r--r--arch/arm/mach-mx3/crm_regs.h153
-rw-r--r--arch/arm/plat-mxc/Kconfig1
-rw-r--r--drivers/dma/ipu/ipu_idmac.c2
-rw-r--r--drivers/video/mx3fb.c2
5 files changed, 206 insertions, 884 deletions
diff --git a/arch/arm/mach-mx3/clock.c b/arch/arm/mach-mx3/clock.c
index 9ab5f8b2bc3..ca46f4801c3 100644
--- a/arch/arm/mach-mx3/clock.c
+++ b/arch/arm/mach-mx3/clock.c
@@ -23,10 +23,13 @@
23#include <linux/clk.h> 23#include <linux/clk.h>
24#include <linux/err.h> 24#include <linux/err.h>
25#include <linux/io.h> 25#include <linux/io.h>
26
27#include <asm/clkdev.h>
28#include <asm/div64.h>
29
26#include <mach/clock.h> 30#include <mach/clock.h>
27#include <mach/hardware.h> 31#include <mach/hardware.h>
28#include <mach/common.h> 32#include <mach/common.h>
29#include <asm/div64.h>
30 33
31#include "crm_regs.h" 34#include "crm_regs.h"
32 35
@@ -65,17 +68,17 @@ static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
65} 68}
66 69
67static struct clk mcu_pll_clk; 70static struct clk mcu_pll_clk;
68static struct clk mcu_main_clk;
69static struct clk usb_pll_clk;
70static struct clk serial_pll_clk; 71static struct clk serial_pll_clk;
71static struct clk ipg_clk; 72static struct clk ipg_clk;
72static struct clk ckih_clk; 73static struct clk ckih_clk;
73static struct clk ahb_clk;
74 74
75static int _clk_enable(struct clk *clk) 75static int cgr_enable(struct clk *clk)
76{ 76{
77 u32 reg; 77 u32 reg;
78 78
79 if (!clk->enable_reg)
80 return 0;
81
79 reg = __raw_readl(clk->enable_reg); 82 reg = __raw_readl(clk->enable_reg);
80 reg |= 3 << clk->enable_shift; 83 reg |= 3 << clk->enable_shift;
81 __raw_writel(reg, clk->enable_reg); 84 __raw_writel(reg, clk->enable_reg);
@@ -83,111 +86,69 @@ static int _clk_enable(struct clk *clk)
83 return 0; 86 return 0;
84} 87}
85 88
86static void _clk_disable(struct clk *clk) 89static void cgr_disable(struct clk *clk)
87{ 90{
88 u32 reg; 91 u32 reg;
89 92
93 if (!clk->enable_reg)
94 return;
95
90 reg = __raw_readl(clk->enable_reg); 96 reg = __raw_readl(clk->enable_reg);
91 reg &= ~(3 << clk->enable_shift); 97 reg &= ~(3 << clk->enable_shift);
98
99 /* special case for EMI clock */
100 if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
101 reg |= (1 << clk->enable_shift);
102
92 __raw_writel(reg, clk->enable_reg); 103 __raw_writel(reg, clk->enable_reg);
93} 104}
94 105
95static void _clk_emi_disable(struct clk *clk) 106static unsigned long pll_ref_get_rate(void)
96{ 107{
97 u32 reg; 108 unsigned long ccmr;
109 unsigned int prcs;
98 110
99 reg = __raw_readl(clk->enable_reg); 111 ccmr = __raw_readl(MXC_CCM_CCMR);
100 reg &= ~(3 << clk->enable_shift); 112 prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
101 reg |= (1 << clk->enable_shift); 113 if (prcs == 0x1)
102 __raw_writel(reg, clk->enable_reg); 114 return CKIL_CLK_FREQ * 1024;
115 else
116 return clk_get_rate(&ckih_clk);
103} 117}
104 118
105static int _clk_pll_set_rate(struct clk *clk, unsigned long rate) 119static unsigned long usb_pll_get_rate(struct clk *clk)
106{ 120{
107 u32 reg; 121 unsigned long reg;
108 signed long pd = 1; /* Pre-divider */
109 signed long mfi; /* Multiplication Factor (Integer part) */
110 signed long mfn; /* Multiplication Factor (Integer part) */
111 signed long mfd; /* Multiplication Factor (Denominator Part) */
112 signed long tmp;
113 u32 ref_freq = clk_get_rate(clk->parent);
114 122
115 while (((ref_freq / pd) * 10) > rate) 123 reg = __raw_readl(MXC_CCM_UPCTL);
116 pd++;
117 124
118 if ((ref_freq / pd) < PRE_DIV_MIN_FREQ) 125 return mxc_decode_pll(reg, pll_ref_get_rate());
119 return -EINVAL; 126}
120 127
121 /* the ref_freq/2 in the following is to round up */ 128static unsigned long serial_pll_get_rate(struct clk *clk)
122 mfi = (((rate / 2) * pd) + (ref_freq / 2)) / ref_freq; 129{
123 if (mfi < 5 || mfi > 15) 130 unsigned long reg;
124 return -EINVAL;
125 131
126 /* pick a mfd value that will work 132 reg = __raw_readl(MXC_CCM_SRPCTL);
127 * then solve for mfn */
128 mfd = ref_freq / 50000;
129
130 /*
131 * pll_freq * pd * mfd
132 * mfn = -------------------- - (mfi * mfd)
133 * 2 * ref_freq
134 */
135 /* the tmp/2 is for rounding */
136 tmp = ref_freq / 10000;
137 mfn =
138 ((((((rate / 2) + (tmp / 2)) / tmp) * pd) * mfd) / 10000) -
139 (mfi * mfd);
140
141 mfn = mfn & 0x3ff;
142 pd--;
143 mfd--;
144
145 /* Change the Pll value */
146 reg = (mfi << MXC_CCM_PCTL_MFI_OFFSET) |
147 (mfn << MXC_CCM_PCTL_MFN_OFFSET) |
148 (mfd << MXC_CCM_PCTL_MFD_OFFSET) | (pd << MXC_CCM_PCTL_PD_OFFSET);
149
150 if (clk == &mcu_pll_clk)
151 __raw_writel(reg, MXC_CCM_MPCTL);
152 else if (clk == &usb_pll_clk)
153 __raw_writel(reg, MXC_CCM_UPCTL);
154 else if (clk == &serial_pll_clk)
155 __raw_writel(reg, MXC_CCM_SRPCTL);
156 133
157 return 0; 134 return mxc_decode_pll(reg, pll_ref_get_rate());
158} 135}
159 136
160static unsigned long _clk_pll_get_rate(struct clk *clk) 137static unsigned long mcu_pll_get_rate(struct clk *clk)
161{ 138{
162 unsigned long reg, ccmr; 139 unsigned long reg, ccmr;
163 unsigned int prcs, ref_clk;
164 140
165 ccmr = __raw_readl(MXC_CCM_CCMR); 141 ccmr = __raw_readl(MXC_CCM_CCMR);
166 prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
167 if (prcs == 0x1)
168 ref_clk = CKIL_CLK_FREQ * 1024;
169 else
170 ref_clk = clk_get_rate(&ckih_clk);
171
172 if (clk == &mcu_pll_clk) {
173 if ((ccmr & MXC_CCM_CCMR_MPE) == 0)
174 return ref_clk;
175 if ((ccmr & MXC_CCM_CCMR_MDS) != 0)
176 return ref_clk;
177 reg = __raw_readl(MXC_CCM_MPCTL);
178 } else if (clk == &usb_pll_clk)
179 reg = __raw_readl(MXC_CCM_UPCTL);
180 else if (clk == &serial_pll_clk)
181 reg = __raw_readl(MXC_CCM_SRPCTL);
182 else {
183 BUG();
184 return 0;
185 }
186 142
187 return mxc_decode_pll(reg, ref_clk); 143 if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
144 return clk_get_rate(&ckih_clk);
145
146 reg = __raw_readl(MXC_CCM_MPCTL);
147
148 return mxc_decode_pll(reg, pll_ref_get_rate());
188} 149}
189 150
190static int _clk_usb_pll_enable(struct clk *clk) 151static int usb_pll_enable(struct clk *clk)
191{ 152{
192 u32 reg; 153 u32 reg;
193 154
@@ -201,7 +162,7 @@ static int _clk_usb_pll_enable(struct clk *clk)
201 return 0; 162 return 0;
202} 163}
203 164
204static void _clk_usb_pll_disable(struct clk *clk) 165static void usb_pll_disable(struct clk *clk)
205{ 166{
206 u32 reg; 167 u32 reg;
207 168
@@ -210,7 +171,7 @@ static void _clk_usb_pll_disable(struct clk *clk)
210 __raw_writel(reg, MXC_CCM_CCMR); 171 __raw_writel(reg, MXC_CCM_CCMR);
211} 172}
212 173
213static int _clk_serial_pll_enable(struct clk *clk) 174static int serial_pll_enable(struct clk *clk)
214{ 175{
215 u32 reg; 176 u32 reg;
216 177
@@ -224,7 +185,7 @@ static int _clk_serial_pll_enable(struct clk *clk)
224 return 0; 185 return 0;
225} 186}
226 187
227static void _clk_serial_pll_disable(struct clk *clk) 188static void serial_pll_disable(struct clk *clk)
228{ 189{
229 u32 reg; 190 u32 reg;
230 191
@@ -237,7 +198,7 @@ static void _clk_serial_pll_disable(struct clk *clk)
237#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off) 198#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
238#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off) 199#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
239 200
240static unsigned long _clk_mcu_main_get_rate(struct clk *clk) 201static unsigned long mcu_main_get_rate(struct clk *clk)
241{ 202{
242 u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0); 203 u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
243 204
@@ -247,7 +208,7 @@ static unsigned long _clk_mcu_main_get_rate(struct clk *clk)
247 return clk_get_rate(&mcu_pll_clk); 208 return clk_get_rate(&mcu_pll_clk);
248} 209}
249 210
250static unsigned long _clk_hclk_get_rate(struct clk *clk) 211static unsigned long ahb_get_rate(struct clk *clk)
251{ 212{
252 unsigned long max_pdf; 213 unsigned long max_pdf;
253 214
@@ -256,7 +217,7 @@ static unsigned long _clk_hclk_get_rate(struct clk *clk)
256 return clk_get_rate(clk->parent) / (max_pdf + 1); 217 return clk_get_rate(clk->parent) / (max_pdf + 1);
257} 218}
258 219
259static unsigned long _clk_ipg_get_rate(struct clk *clk) 220static unsigned long ipg_get_rate(struct clk *clk)
260{ 221{
261 unsigned long ipg_pdf; 222 unsigned long ipg_pdf;
262 223
@@ -265,7 +226,7 @@ static unsigned long _clk_ipg_get_rate(struct clk *clk)
265 return clk_get_rate(clk->parent) / (ipg_pdf + 1); 226 return clk_get_rate(clk->parent) / (ipg_pdf + 1);
266} 227}
267 228
268static unsigned long _clk_nfc_get_rate(struct clk *clk) 229static unsigned long nfc_get_rate(struct clk *clk)
269{ 230{
270 unsigned long nfc_pdf; 231 unsigned long nfc_pdf;
271 232
@@ -274,7 +235,7 @@ static unsigned long _clk_nfc_get_rate(struct clk *clk)
274 return clk_get_rate(clk->parent) / (nfc_pdf + 1); 235 return clk_get_rate(clk->parent) / (nfc_pdf + 1);
275} 236}
276 237
277static unsigned long _clk_hsp_get_rate(struct clk *clk) 238static unsigned long hsp_get_rate(struct clk *clk)
278{ 239{
279 unsigned long hsp_pdf; 240 unsigned long hsp_pdf;
280 241
@@ -283,7 +244,7 @@ static unsigned long _clk_hsp_get_rate(struct clk *clk)
283 return clk_get_rate(clk->parent) / (hsp_pdf + 1); 244 return clk_get_rate(clk->parent) / (hsp_pdf + 1);
284} 245}
285 246
286static unsigned long _clk_usb_get_rate(struct clk *clk) 247static unsigned long usb_get_rate(struct clk *clk)
287{ 248{
288 unsigned long usb_pdf, usb_prepdf; 249 unsigned long usb_pdf, usb_prepdf;
289 250
@@ -294,7 +255,7 @@ static unsigned long _clk_usb_get_rate(struct clk *clk)
294 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1); 255 return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
295} 256}
296 257
297static unsigned long _clk_csi_get_rate(struct clk *clk) 258static unsigned long csi_get_rate(struct clk *clk)
298{ 259{
299 u32 reg, pre, post; 260 u32 reg, pre, post;
300 261
@@ -308,7 +269,7 @@ static unsigned long _clk_csi_get_rate(struct clk *clk)
308 return clk_get_rate(clk->parent) / (pre * post); 269 return clk_get_rate(clk->parent) / (pre * post);
309} 270}
310 271
311static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate) 272static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
312{ 273{
313 u32 pre, post, parent = clk_get_rate(clk->parent); 274 u32 pre, post, parent = clk_get_rate(clk->parent);
314 u32 div = parent / rate; 275 u32 div = parent / rate;
@@ -321,7 +282,7 @@ static unsigned long _clk_csi_round_rate(struct clk *clk, unsigned long rate)
321 return parent / (pre * post); 282 return parent / (pre * post);
322} 283}
323 284
324static int _clk_csi_set_rate(struct clk *clk, unsigned long rate) 285static int csi_set_rate(struct clk *clk, unsigned long rate)
325{ 286{
326 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); 287 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
327 288
@@ -342,16 +303,7 @@ static int _clk_csi_set_rate(struct clk *clk, unsigned long rate)
342 return 0; 303 return 0;
343} 304}
344 305
345static unsigned long _clk_per_get_rate(struct clk *clk) 306static unsigned long ssi1_get_rate(struct clk *clk)
346{
347 unsigned long per_pdf;
348
349 per_pdf = PDR0(MXC_CCM_PDR0_PER_PODF_MASK,
350 MXC_CCM_PDR0_PER_PODF_OFFSET);
351 return clk_get_rate(clk->parent) / (per_pdf + 1);
352}
353
354static unsigned long _clk_ssi1_get_rate(struct clk *clk)
355{ 307{
356 unsigned long ssi1_pdf, ssi1_prepdf; 308 unsigned long ssi1_pdf, ssi1_prepdf;
357 309
@@ -362,7 +314,7 @@ static unsigned long _clk_ssi1_get_rate(struct clk *clk)
362 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1); 314 return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
363} 315}
364 316
365static unsigned long _clk_ssi2_get_rate(struct clk *clk) 317static unsigned long ssi2_get_rate(struct clk *clk)
366{ 318{
367 unsigned long ssi2_pdf, ssi2_prepdf; 319 unsigned long ssi2_pdf, ssi2_prepdf;
368 320
@@ -373,7 +325,7 @@ static unsigned long _clk_ssi2_get_rate(struct clk *clk)
373 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1); 325 return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
374} 326}
375 327
376static unsigned long _clk_firi_get_rate(struct clk *clk) 328static unsigned long firi_get_rate(struct clk *clk)
377{ 329{
378 unsigned long firi_pdf, firi_prepdf; 330 unsigned long firi_pdf, firi_prepdf;
379 331
@@ -384,7 +336,7 @@ static unsigned long _clk_firi_get_rate(struct clk *clk)
384 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1); 336 return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
385} 337}
386 338
387static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate) 339static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
388{ 340{
389 u32 pre, post; 341 u32 pre, post;
390 u32 parent = clk_get_rate(clk->parent); 342 u32 parent = clk_get_rate(clk->parent);
@@ -399,7 +351,7 @@ static unsigned long _clk_firi_round_rate(struct clk *clk, unsigned long rate)
399 351
400} 352}
401 353
402static int _clk_firi_set_rate(struct clk *clk, unsigned long rate) 354static int firi_set_rate(struct clk *clk, unsigned long rate)
403{ 355{
404 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent); 356 u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
405 357
@@ -420,12 +372,12 @@ static int _clk_firi_set_rate(struct clk *clk, unsigned long rate)
420 return 0; 372 return 0;
421} 373}
422 374
423static unsigned long _clk_mbx_get_rate(struct clk *clk) 375static unsigned long mbx_get_rate(struct clk *clk)
424{ 376{
425 return clk_get_rate(clk->parent) / 2; 377 return clk_get_rate(clk->parent) / 2;
426} 378}
427 379
428static unsigned long _clk_mstick1_get_rate(struct clk *clk) 380static unsigned long mstick1_get_rate(struct clk *clk)
429{ 381{
430 unsigned long msti_pdf; 382 unsigned long msti_pdf;
431 383
@@ -434,7 +386,7 @@ static unsigned long _clk_mstick1_get_rate(struct clk *clk)
434 return clk_get_rate(clk->parent) / (msti_pdf + 1); 386 return clk_get_rate(clk->parent) / (msti_pdf + 1);
435} 387}
436 388
437static unsigned long _clk_mstick2_get_rate(struct clk *clk) 389static unsigned long mstick2_get_rate(struct clk *clk)
438{ 390{
439 unsigned long msti_pdf; 391 unsigned long msti_pdf;
440 392
@@ -451,663 +403,185 @@ static unsigned long clk_ckih_get_rate(struct clk *clk)
451} 403}
452 404
453static struct clk ckih_clk = { 405static struct clk ckih_clk = {
454 .name = "ckih",
455 .get_rate = clk_ckih_get_rate, 406 .get_rate = clk_ckih_get_rate,
456}; 407};
457 408
458static unsigned long clk_ckil_get_rate(struct clk *clk)
459{
460 return CKIL_CLK_FREQ;
461}
462
463static struct clk ckil_clk = {
464 .name = "ckil",
465 .get_rate = clk_ckil_get_rate,
466};
467
468static struct clk mcu_pll_clk = { 409static struct clk mcu_pll_clk = {
469 .name = "mcu_pll",
470 .parent = &ckih_clk, 410 .parent = &ckih_clk,
471 .set_rate = _clk_pll_set_rate, 411 .get_rate = mcu_pll_get_rate,
472 .get_rate = _clk_pll_get_rate,
473}; 412};
474 413
475static struct clk mcu_main_clk = { 414static struct clk mcu_main_clk = {
476 .name = "mcu_main_clk",
477 .parent = &mcu_pll_clk, 415 .parent = &mcu_pll_clk,
478 .get_rate = _clk_mcu_main_get_rate, 416 .get_rate = mcu_main_get_rate,
479}; 417};
480 418
481static struct clk serial_pll_clk = { 419static struct clk serial_pll_clk = {
482 .name = "serial_pll",
483 .parent = &ckih_clk, 420 .parent = &ckih_clk,
484 .set_rate = _clk_pll_set_rate, 421 .get_rate = serial_pll_get_rate,
485 .get_rate = _clk_pll_get_rate, 422 .enable = serial_pll_enable,
486 .enable = _clk_serial_pll_enable, 423 .disable = serial_pll_disable,
487 .disable = _clk_serial_pll_disable,
488}; 424};
489 425
490static struct clk usb_pll_clk = { 426static struct clk usb_pll_clk = {
491 .name = "usb_pll",
492 .parent = &ckih_clk, 427 .parent = &ckih_clk,
493 .set_rate = _clk_pll_set_rate, 428 .get_rate = usb_pll_get_rate,
494 .get_rate = _clk_pll_get_rate, 429 .enable = usb_pll_enable,
495 .enable = _clk_usb_pll_enable, 430 .disable = usb_pll_disable,
496 .disable = _clk_usb_pll_disable,
497}; 431};
498 432
499static struct clk ahb_clk = { 433static struct clk ahb_clk = {
500 .name = "ahb_clk",
501 .parent = &mcu_main_clk, 434 .parent = &mcu_main_clk,
502 .get_rate = _clk_hclk_get_rate, 435 .get_rate = ahb_get_rate,
503}; 436};
504 437
505static struct clk per_clk = { 438#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
506 .name = "per_clk", 439 static struct clk name = { \
507 .parent = &usb_pll_clk, 440 .id = i, \
508 .get_rate = _clk_per_get_rate, 441 .enable_reg = er, \
509}; 442 .enable_shift = es, \
510 443 .get_rate = gr, \
511static struct clk perclk_clk = { 444 .enable = cgr_enable, \
512 .name = "perclk_clk", 445 .disable = cgr_disable, \
513 .parent = &ipg_clk, 446 .secondary = s, \
514}; 447 .parent = p, \
515 448 }
516static struct clk cspi_clk[] = {
517 {
518 .name = "cspi_clk",
519 .id = 0,
520 .parent = &ipg_clk,
521 .enable = _clk_enable,
522 .enable_reg = MXC_CCM_CGR2,
523 .enable_shift = MXC_CCM_CGR2_CSPI1_OFFSET,
524 .disable = _clk_disable,},
525 {
526 .name = "cspi_clk",
527 .id = 1,
528 .parent = &ipg_clk,
529 .enable = _clk_enable,
530 .enable_reg = MXC_CCM_CGR2,
531 .enable_shift = MXC_CCM_CGR2_CSPI2_OFFSET,
532 .disable = _clk_disable,},
533 {
534 .name = "cspi_clk",
535 .id = 2,
536 .parent = &ipg_clk,
537 .enable = _clk_enable,
538 .enable_reg = MXC_CCM_CGR0,
539 .enable_shift = MXC_CCM_CGR0_CSPI3_OFFSET,
540 .disable = _clk_disable,},
541};
542
543static struct clk ipg_clk = {
544 .name = "ipg_clk",
545 .parent = &ahb_clk,
546 .get_rate = _clk_ipg_get_rate,
547};
548
549static struct clk emi_clk = {
550 .name = "emi_clk",
551 .parent = &ahb_clk,
552 .enable = _clk_enable,
553 .enable_reg = MXC_CCM_CGR2,
554 .enable_shift = MXC_CCM_CGR2_EMI_OFFSET,
555 .disable = _clk_emi_disable,
556};
557
558static struct clk gpt_clk = {
559 .name = "gpt_clk",
560 .parent = &perclk_clk,
561 .enable = _clk_enable,
562 .enable_reg = MXC_CCM_CGR0,
563 .enable_shift = MXC_CCM_CGR0_GPT_OFFSET,
564 .disable = _clk_disable,
565};
566
567static struct clk pwm_clk = {
568 .name = "pwm_clk",
569 .parent = &perclk_clk,
570 .enable = _clk_enable,
571 .enable_reg = MXC_CCM_CGR0,
572 .enable_shift = MXC_CCM_CGR1_PWM_OFFSET,
573 .disable = _clk_disable,
574};
575
576static struct clk epit_clk[] = {
577 {
578 .name = "epit_clk",
579 .id = 0,
580 .parent = &perclk_clk,
581 .enable = _clk_enable,
582 .enable_reg = MXC_CCM_CGR0,
583 .enable_shift = MXC_CCM_CGR0_EPIT1_OFFSET,
584 .disable = _clk_disable,},
585 {
586 .name = "epit_clk",
587 .id = 1,
588 .parent = &perclk_clk,
589 .enable = _clk_enable,
590 .enable_reg = MXC_CCM_CGR0,
591 .enable_shift = MXC_CCM_CGR0_EPIT2_OFFSET,
592 .disable = _clk_disable,},
593};
594
595static struct clk nfc_clk = {
596 .name = "nfc",
597 .parent = &ahb_clk,
598 .get_rate = _clk_nfc_get_rate,
599};
600
601static struct clk scc_clk = {
602 .name = "scc_clk",
603 .parent = &ipg_clk,
604};
605
606static struct clk ipu_clk = {
607 .name = "ipu_clk",
608 .parent = &mcu_main_clk,
609 .get_rate = _clk_hsp_get_rate,
610 .enable = _clk_enable,
611 .enable_reg = MXC_CCM_CGR1,
612 .enable_shift = MXC_CCM_CGR1_IPU_OFFSET,
613 .disable = _clk_disable,
614};
615
616static struct clk kpp_clk = {
617 .name = "kpp_clk",
618 .parent = &ipg_clk,
619 .enable = _clk_enable,
620 .enable_reg = MXC_CCM_CGR1,
621 .enable_shift = MXC_CCM_CGR1_KPP_OFFSET,
622 .disable = _clk_disable,
623};
624
625static struct clk wdog_clk = {
626 .name = "wdog_clk",
627 .parent = &ipg_clk,
628 .enable = _clk_enable,
629 .enable_reg = MXC_CCM_CGR1,
630 .enable_shift = MXC_CCM_CGR1_WDOG_OFFSET,
631 .disable = _clk_disable,
632};
633static struct clk rtc_clk = {
634 .name = "rtc_clk",
635 .parent = &ipg_clk,
636 .enable = _clk_enable,
637 .enable_reg = MXC_CCM_CGR1,
638 .enable_shift = MXC_CCM_CGR1_RTC_OFFSET,
639 .disable = _clk_disable,
640};
641
642static struct clk usb_clk[] = {
643 {
644 .name = "usb_clk",
645 .parent = &usb_pll_clk,
646 .get_rate = _clk_usb_get_rate,},
647 {
648 .name = "usb_ahb_clk",
649 .parent = &ahb_clk,
650 .enable = _clk_enable,
651 .enable_reg = MXC_CCM_CGR1,
652 .enable_shift = MXC_CCM_CGR1_USBOTG_OFFSET,
653 .disable = _clk_disable,},
654};
655
656static struct clk csi_clk = {
657 .name = "csi_clk",
658 .parent = &serial_pll_clk,
659 .get_rate = _clk_csi_get_rate,
660 .round_rate = _clk_csi_round_rate,
661 .set_rate = _clk_csi_set_rate,
662 .enable = _clk_enable,
663 .enable_reg = MXC_CCM_CGR1,
664 .enable_shift = MXC_CCM_CGR1_CSI_OFFSET,
665 .disable = _clk_disable,
666};
667
668static struct clk uart_clk[] = {
669 {
670 .name = "uart",
671 .id = 0,
672 .parent = &perclk_clk,
673 .enable = _clk_enable,
674 .enable_reg = MXC_CCM_CGR0,
675 .enable_shift = MXC_CCM_CGR0_UART1_OFFSET,
676 .disable = _clk_disable,},
677 {
678 .name = "uart",
679 .id = 1,
680 .parent = &perclk_clk,
681 .enable = _clk_enable,
682 .enable_reg = MXC_CCM_CGR0,
683 .enable_shift = MXC_CCM_CGR0_UART2_OFFSET,
684 .disable = _clk_disable,},
685 {
686 .name = "uart",
687 .id = 2,
688 .parent = &perclk_clk,
689 .enable = _clk_enable,
690 .enable_reg = MXC_CCM_CGR1,
691 .enable_shift = MXC_CCM_CGR1_UART3_OFFSET,
692 .disable = _clk_disable,},
693 {
694 .name = "uart",
695 .id = 3,
696 .parent = &perclk_clk,
697 .enable = _clk_enable,
698 .enable_reg = MXC_CCM_CGR1,
699 .enable_shift = MXC_CCM_CGR1_UART4_OFFSET,
700 .disable = _clk_disable,},
701 {
702 .name = "uart",
703 .id = 4,
704 .parent = &perclk_clk,
705 .enable = _clk_enable,
706 .enable_reg = MXC_CCM_CGR1,
707 .enable_shift = MXC_CCM_CGR1_UART5_OFFSET,
708 .disable = _clk_disable,},
709};
710
711static struct clk i2c_clk[] = {
712 {
713 .name = "i2c_clk",
714 .id = 0,
715 .parent = &perclk_clk,
716 .enable = _clk_enable,
717 .enable_reg = MXC_CCM_CGR0,
718 .enable_shift = MXC_CCM_CGR0_I2C1_OFFSET,
719 .disable = _clk_disable,},
720 {
721 .name = "i2c_clk",
722 .id = 1,
723 .parent = &perclk_clk,
724 .enable = _clk_enable,
725 .enable_reg = MXC_CCM_CGR0,
726 .enable_shift = MXC_CCM_CGR0_I2C2_OFFSET,
727 .disable = _clk_disable,},
728 {
729 .name = "i2c_clk",
730 .id = 2,
731 .parent = &perclk_clk,
732 .enable = _clk_enable,
733 .enable_reg = MXC_CCM_CGR0,
734 .enable_shift = MXC_CCM_CGR0_I2C3_OFFSET,
735 .disable = _clk_disable,},
736};
737
738static struct clk owire_clk = {
739 .name = "owire",
740 .parent = &perclk_clk,
741 .enable_reg = MXC_CCM_CGR1,
742 .enable_shift = MXC_CCM_CGR1_OWIRE_OFFSET,
743 .enable = _clk_enable,
744 .disable = _clk_disable,
745};
746
747static struct clk sdhc_clk[] = {
748 {
749 .name = "sdhc_clk",
750 .id = 0,
751 .parent = &perclk_clk,
752 .enable = _clk_enable,
753 .enable_reg = MXC_CCM_CGR0,
754 .enable_shift = MXC_CCM_CGR0_SD_MMC1_OFFSET,
755 .disable = _clk_disable,},
756 {
757 .name = "sdhc_clk",
758 .id = 1,
759 .parent = &perclk_clk,
760 .enable = _clk_enable,
761 .enable_reg = MXC_CCM_CGR0,
762 .enable_shift = MXC_CCM_CGR0_SD_MMC2_OFFSET,
763 .disable = _clk_disable,},
764};
765
766static struct clk ssi_clk[] = {
767 {
768 .name = "ssi_clk",
769 .parent = &serial_pll_clk,
770 .get_rate = _clk_ssi1_get_rate,
771 .enable = _clk_enable,
772 .enable_reg = MXC_CCM_CGR0,
773 .enable_shift = MXC_CCM_CGR0_SSI1_OFFSET,
774 .disable = _clk_disable,},
775 {
776 .name = "ssi_clk",
777 .id = 1,
778 .parent = &serial_pll_clk,
779 .get_rate = _clk_ssi2_get_rate,
780 .enable = _clk_enable,
781 .enable_reg = MXC_CCM_CGR2,
782 .enable_shift = MXC_CCM_CGR2_SSI2_OFFSET,
783 .disable = _clk_disable,},
784};
785
786static struct clk firi_clk = {
787 .name = "firi_clk",
788 .parent = &usb_pll_clk,
789 .round_rate = _clk_firi_round_rate,
790 .set_rate = _clk_firi_set_rate,
791 .get_rate = _clk_firi_get_rate,
792 .enable = _clk_enable,
793 .enable_reg = MXC_CCM_CGR2,
794 .enable_shift = MXC_CCM_CGR2_FIRI_OFFSET,
795 .disable = _clk_disable,
796};
797
798static struct clk ata_clk = {
799 .name = "ata_clk",
800 .parent = &ipg_clk,
801 .enable = _clk_enable,
802 .enable_reg = MXC_CCM_CGR0,
803 .enable_shift = MXC_CCM_CGR0_ATA_OFFSET,
804 .disable = _clk_disable,
805};
806
807static struct clk mbx_clk = {
808 .name = "mbx_clk",
809 .parent = &ahb_clk,
810 .enable = _clk_enable,
811 .enable_reg = MXC_CCM_CGR2,
812 .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
813 .get_rate = _clk_mbx_get_rate,
814};
815
816static struct clk vpu_clk = {
817 .name = "vpu_clk",
818 .parent = &ahb_clk,
819 .enable = _clk_enable,
820 .enable_reg = MXC_CCM_CGR2,
821 .enable_shift = MXC_CCM_CGR2_GACC_OFFSET,
822 .get_rate = _clk_mbx_get_rate,
823};
824
825static struct clk rtic_clk = {
826 .name = "rtic_clk",
827 .parent = &ahb_clk,
828 .enable = _clk_enable,
829 .enable_reg = MXC_CCM_CGR2,
830 .enable_shift = MXC_CCM_CGR2_RTIC_OFFSET,
831 .disable = _clk_disable,
832};
833
834static struct clk rng_clk = {
835 .name = "rng_clk",
836 .parent = &ipg_clk,
837 .enable = _clk_enable,
838 .enable_reg = MXC_CCM_CGR0,
839 .enable_shift = MXC_CCM_CGR0_RNG_OFFSET,
840 .disable = _clk_disable,
841};
842
843static struct clk sdma_clk[] = {
844 {
845 .name = "sdma_ahb_clk",
846 .parent = &ahb_clk,
847 .enable = _clk_enable,
848 .enable_reg = MXC_CCM_CGR0,
849 .enable_shift = MXC_CCM_CGR0_SDMA_OFFSET,
850 .disable = _clk_disable,},
851 {
852 .name = "sdma_ipg_clk",
853 .parent = &ipg_clk,}
854};
855
856static struct clk mpeg4_clk = {
857 .name = "mpeg4_clk",
858 .parent = &ahb_clk,
859 .enable = _clk_enable,
860 .enable_reg = MXC_CCM_CGR1,
861 .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
862 .disable = _clk_disable,
863};
864
865static struct clk vl2cc_clk = {
866 .name = "vl2cc_clk",
867 .parent = &ahb_clk,
868 .enable = _clk_enable,
869 .enable_reg = MXC_CCM_CGR1,
870 .enable_shift = MXC_CCM_CGR1_HANTRO_OFFSET,
871 .disable = _clk_disable,
872};
873
874static struct clk mstick_clk[] = {
875 {
876 .name = "mstick_clk",
877 .id = 0,
878 .parent = &usb_pll_clk,
879 .get_rate = _clk_mstick1_get_rate,
880 .enable = _clk_enable,
881 .enable_reg = MXC_CCM_CGR1,
882 .enable_shift = MXC_CCM_CGR1_MEMSTICK1_OFFSET,
883 .disable = _clk_disable,},
884 {
885 .name = "mstick_clk",
886 .id = 1,
887 .parent = &usb_pll_clk,
888 .get_rate = _clk_mstick2_get_rate,
889 .enable = _clk_enable,
890 .enable_reg = MXC_CCM_CGR1,
891 .enable_shift = MXC_CCM_CGR1_MEMSTICK2_OFFSET,
892 .disable = _clk_disable,},
893};
894
895static struct clk iim_clk = {
896 .name = "iim_clk",
897 .parent = &ipg_clk,
898 .enable = _clk_enable,
899 .enable_reg = MXC_CCM_CGR0,
900 .enable_shift = MXC_CCM_CGR0_IIM_OFFSET,
901 .disable = _clk_disable,
902};
903
904static unsigned long _clk_cko1_round_rate(struct clk *clk, unsigned long rate)
905{
906 u32 div, parent = clk_get_rate(clk->parent);
907
908 div = parent / rate;
909 if (parent % rate)
910 div++;
911
912 if (div > 8)
913 div = 16;
914 else if (div > 4)
915 div = 8;
916 else if (div > 2)
917 div = 4;
918
919 return parent / div;
920}
921
922static int _clk_cko1_set_rate(struct clk *clk, unsigned long rate)
923{
924 u32 reg, div, parent = clk_get_rate(clk->parent);
925
926 div = parent / rate;
927
928 if (div == 16)
929 div = 4;
930 else if (div == 8)
931 div = 3;
932 else if (div == 4)
933 div = 2;
934 else if (div == 2)
935 div = 1;
936 else if (div == 1)
937 div = 0;
938 else
939 return -EINVAL;
940
941 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOUTDIV_MASK;
942 reg |= div << MXC_CCM_COSR_CLKOUTDIV_OFFSET;
943 __raw_writel(reg, MXC_CCM_COSR);
944
945 return 0;
946}
947
948static unsigned long _clk_cko1_get_rate(struct clk *clk)
949{
950 u32 div;
951
952 div = __raw_readl(MXC_CCM_COSR) & MXC_CCM_COSR_CLKOUTDIV_MASK >>
953 MXC_CCM_COSR_CLKOUTDIV_OFFSET;
954
955 return clk_get_rate(clk->parent) / (1 << div);
956}
957
958static int _clk_cko1_set_parent(struct clk *clk, struct clk *parent)
959{
960 u32 reg;
961
962 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOSEL_MASK;
963
964 if (parent == &mcu_main_clk)
965 reg |= 0 << MXC_CCM_COSR_CLKOSEL_OFFSET;
966 else if (parent == &ipg_clk)
967 reg |= 1 << MXC_CCM_COSR_CLKOSEL_OFFSET;
968 else if (parent == &usb_pll_clk)
969 reg |= 2 << MXC_CCM_COSR_CLKOSEL_OFFSET;
970 else if (parent == mcu_main_clk.parent)
971 reg |= 3 << MXC_CCM_COSR_CLKOSEL_OFFSET;
972 else if (parent == &ahb_clk)
973 reg |= 5 << MXC_CCM_COSR_CLKOSEL_OFFSET;
974 else if (parent == &serial_pll_clk)
975 reg |= 7 << MXC_CCM_COSR_CLKOSEL_OFFSET;
976 else if (parent == &ckih_clk)
977 reg |= 8 << MXC_CCM_COSR_CLKOSEL_OFFSET;
978 else if (parent == &emi_clk)
979 reg |= 9 << MXC_CCM_COSR_CLKOSEL_OFFSET;
980 else if (parent == &ipu_clk)
981 reg |= 0xA << MXC_CCM_COSR_CLKOSEL_OFFSET;
982 else if (parent == &nfc_clk)
983 reg |= 0xB << MXC_CCM_COSR_CLKOSEL_OFFSET;
984 else if (parent == &uart_clk[0])
985 reg |= 0xC << MXC_CCM_COSR_CLKOSEL_OFFSET;
986 else
987 return -EINVAL;
988
989 __raw_writel(reg, MXC_CCM_COSR);
990
991 return 0;
992}
993
994static int _clk_cko1_enable(struct clk *clk)
995{
996 u32 reg;
997
998 reg = __raw_readl(MXC_CCM_COSR) | MXC_CCM_COSR_CLKOEN;
999 __raw_writel(reg, MXC_CCM_COSR);
1000
1001 return 0;
1002}
1003
1004static void _clk_cko1_disable(struct clk *clk)
1005{
1006 u32 reg;
1007
1008 reg = __raw_readl(MXC_CCM_COSR) & ~MXC_CCM_COSR_CLKOEN;
1009 __raw_writel(reg, MXC_CCM_COSR);
1010}
1011 449
1012static struct clk cko1_clk = { 450#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
1013 .name = "cko1_clk", 451 static struct clk name = { \
1014 .get_rate = _clk_cko1_get_rate, 452 .id = i, \
1015 .set_rate = _clk_cko1_set_rate, 453 .enable_reg = er, \
1016 .round_rate = _clk_cko1_round_rate, 454 .enable_shift = es, \
1017 .set_parent = _clk_cko1_set_parent, 455 .get_rate = getsetround##_get_rate, \
1018 .enable = _clk_cko1_enable, 456 .set_rate = getsetround##_set_rate, \
1019 .disable = _clk_cko1_disable, 457 .round_rate = getsetround##_round_rate, \
1020}; 458 .enable = cgr_enable, \
459 .disable = cgr_disable, \
460 .secondary = s, \
461 .parent = p, \
462 }
1021 463
1022static struct clk *mxc_clks[] = { 464DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
1023 &ckih_clk, 465
1024 &ckil_clk, 466DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
1025 &mcu_pll_clk, 467DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
1026 &usb_pll_clk, 468DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
1027 &serial_pll_clk, 469DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
1028 &mcu_main_clk, 470DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
1029 &ahb_clk, 471DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
1030 &per_clk, 472DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
1031 &perclk_clk, 473DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, &sdma_clk1, &ahb_clk);
1032 &cko1_clk, 474DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
1033 &emi_clk, 475DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
1034 &cspi_clk[0], 476DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
1035 &cspi_clk[1], 477DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
1036 &cspi_clk[2], 478DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
1037 &ipg_clk, 479DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
1038 &gpt_clk, 480DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
1039 &pwm_clk, 481DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
1040 &wdog_clk, 482
1041 &rtc_clk, 483DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
1042 &epit_clk[0], 484DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
1043 &epit_clk[1], 485DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
1044 &nfc_clk, 486DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &ahb_clk);
1045 &ipu_clk, 487DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ipg_clk);
1046 &kpp_clk, 488DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
1047 &usb_clk[0], 489DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
1048 &usb_clk[1], 490DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
1049 &csi_clk, 491DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
1050 &uart_clk[0], 492DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
1051 &uart_clk[1], 493DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
1052 &uart_clk[2], 494DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
1053 &uart_clk[3], 495DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
1054 &uart_clk[4], 496DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
1055 &i2c_clk[0], 497
1056 &i2c_clk[1], 498DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk);
1057 &i2c_clk[2], 499DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk);
1058 &owire_clk, 500DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk);
1059 &sdhc_clk[0], 501DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk);
1060 &sdhc_clk[1], 502DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk);
1061 &ssi_clk[0], 503DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
1062 &ssi_clk[1], 504DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
1063 &firi_clk, 505
1064 &ata_clk, 506DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk);
1065 &rtic_clk, 507DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk);
1066 &rng_clk, 508DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
1067 &sdma_clk[0], 509DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
1068 &sdma_clk[1], 510DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
1069 &mstick_clk[0], 511
1070 &mstick_clk[1], 512#define _REGISTER_CLOCK(d, n, c) \
1071 &scc_clk, 513 { \
1072 &iim_clk, 514 .dev_id = d, \
515 .con_id = n, \
516 .clk = &c, \
517 },
518
519static struct clk_lookup lookups[] __initdata = {
520 _REGISTER_CLOCK(NULL, "emi", emi_clk)
521 _REGISTER_CLOCK(NULL, "cspi", cspi1_clk)
522 _REGISTER_CLOCK(NULL, "cspi", cspi2_clk)
523 _REGISTER_CLOCK(NULL, "cspi", cspi3_clk)
524 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
525 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
526 _REGISTER_CLOCK(NULL, "wdog", wdog_clk)
527 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
528 _REGISTER_CLOCK(NULL, "epit", epit1_clk)
529 _REGISTER_CLOCK(NULL, "epit", epit2_clk)
530 _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
531 _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
532 _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
533 _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
534 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
535 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
536 _REGISTER_CLOCK("mx3-camera.0", "csi", csi_clk)
537 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
538 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
539 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
540 _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
541 _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
542 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
543 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
544 _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
545 _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
546 _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
547 _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
548 _REGISTER_CLOCK(NULL, "ssi", ssi1_clk)
549 _REGISTER_CLOCK(NULL, "ssi", ssi2_clk)
550 _REGISTER_CLOCK(NULL, "firi", firi_clk)
551 _REGISTER_CLOCK(NULL, "ata", ata_clk)
552 _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
553 _REGISTER_CLOCK(NULL, "rng", rng_clk)
554 _REGISTER_CLOCK(NULL, "sdma_ahb", sdma_clk1)
555 _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
556 _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
557 _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
558 _REGISTER_CLOCK(NULL, "scc", scc_clk)
559 _REGISTER_CLOCK(NULL, "iim", iim_clk)
560 _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
561 _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
1073}; 562};
1074 563
1075int __init mx31_clocks_init(unsigned long fref) 564int __init mx31_clocks_init(unsigned long fref)
1076{ 565{
1077 u32 reg; 566 u32 reg;
1078 struct clk **clkp; 567 int i;
1079 568
1080 mxc_set_cpu_type(MXC_CPU_MX31); 569 mxc_set_cpu_type(MXC_CPU_MX31);
1081 570
1082 ckih_rate = fref; 571 ckih_rate = fref;
1083 572
1084 for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++) 573 for (i = 0; i < ARRAY_SIZE(lookups); i++)
1085 clk_register(*clkp); 574 clkdev_add(&lookups[i]);
1086
1087 if (cpu_is_mx31()) {
1088 clk_register(&mpeg4_clk);
1089 clk_register(&mbx_clk);
1090 } else {
1091 clk_register(&vpu_clk);
1092 clk_register(&vl2cc_clk);
1093 }
1094 575
1095 /* Turn off all possible clocks */ 576 /* Turn off all possible clocks */
1096 __raw_writel(MXC_CCM_CGR0_GPT_MASK, MXC_CCM_CGR0); 577 __raw_writel((3 << 4), MXC_CCM_CGR0);
1097 __raw_writel(0, MXC_CCM_CGR1); 578 __raw_writel(0, MXC_CCM_CGR1);
1098 579 __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
1099 __raw_writel(MXC_CCM_CGR2_EMI_MASK |
1100 MXC_CCM_CGR2_IPMUX1_MASK |
1101 MXC_CCM_CGR2_IPMUX2_MASK |
1102 MXC_CCM_CGR2_MXCCLKENSEL_MASK | /* for MX32 */
1103 MXC_CCM_CGR2_CHIKCAMPEN_MASK | /* for MX32 */
1104 MXC_CCM_CGR2_OVRVPUBUSY_MASK | /* for MX32 */
1105 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for 580 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
1106 MX32, but still required to be set */ 581 MX32, but still required to be set */
1107 MXC_CCM_CGR2); 582 MXC_CCM_CGR2);
1108 583
1109 clk_disable(&cko1_clk); 584 usb_pll_disable(&usb_pll_clk);
1110 clk_disable(&usb_pll_clk);
1111 585
1112 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk)); 586 pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
1113 587
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-mx3/crm_regs.h
index 4a0e0ede23b..adfa3627ad8 100644
--- a/arch/arm/mach-mx3/crm_regs.h
+++ b/arch/arm/mach-mx3/crm_regs.h
@@ -91,47 +91,6 @@
91#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0 91#define MXC_CCM_PDR0_MCU_PODF_OFFSET 0
92#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7 92#define MXC_CCM_PDR0_MCU_PODF_MASK 0x7
93 93
94#define MXC_CCM_PDR0_HSP_DIV_1 (0x0 << 11)
95#define MXC_CCM_PDR0_HSP_DIV_2 (0x1 << 11)
96#define MXC_CCM_PDR0_HSP_DIV_3 (0x2 << 11)
97#define MXC_CCM_PDR0_HSP_DIV_4 (0x3 << 11)
98#define MXC_CCM_PDR0_HSP_DIV_5 (0x4 << 11)
99#define MXC_CCM_PDR0_HSP_DIV_6 (0x5 << 11)
100#define MXC_CCM_PDR0_HSP_DIV_7 (0x6 << 11)
101#define MXC_CCM_PDR0_HSP_DIV_8 (0x7 << 11)
102
103#define MXC_CCM_PDR0_IPG_DIV_1 (0x0 << 6)
104#define MXC_CCM_PDR0_IPG_DIV_2 (0x1 << 6)
105#define MXC_CCM_PDR0_IPG_DIV_3 (0x2 << 6)
106#define MXC_CCM_PDR0_IPG_DIV_4 (0x3 << 6)
107
108#define MXC_CCM_PDR0_MAX_DIV_1 (0x0 << 3)
109#define MXC_CCM_PDR0_MAX_DIV_2 (0x1 << 3)
110#define MXC_CCM_PDR0_MAX_DIV_3 (0x2 << 3)
111#define MXC_CCM_PDR0_MAX_DIV_4 (0x3 << 3)
112#define MXC_CCM_PDR0_MAX_DIV_5 (0x4 << 3)
113#define MXC_CCM_PDR0_MAX_DIV_6 (0x5 << 3)
114#define MXC_CCM_PDR0_MAX_DIV_7 (0x6 << 3)
115#define MXC_CCM_PDR0_MAX_DIV_8 (0x7 << 3)
116
117#define MXC_CCM_PDR0_NFC_DIV_1 (0x0 << 8)
118#define MXC_CCM_PDR0_NFC_DIV_2 (0x1 << 8)
119#define MXC_CCM_PDR0_NFC_DIV_3 (0x2 << 8)
120#define MXC_CCM_PDR0_NFC_DIV_4 (0x3 << 8)
121#define MXC_CCM_PDR0_NFC_DIV_5 (0x4 << 8)
122#define MXC_CCM_PDR0_NFC_DIV_6 (0x5 << 8)
123#define MXC_CCM_PDR0_NFC_DIV_7 (0x6 << 8)
124#define MXC_CCM_PDR0_NFC_DIV_8 (0x7 << 8)
125
126#define MXC_CCM_PDR0_MCU_DIV_1 0x0
127#define MXC_CCM_PDR0_MCU_DIV_2 0x1
128#define MXC_CCM_PDR0_MCU_DIV_3 0x2
129#define MXC_CCM_PDR0_MCU_DIV_4 0x3
130#define MXC_CCM_PDR0_MCU_DIV_5 0x4
131#define MXC_CCM_PDR0_MCU_DIV_6 0x5
132#define MXC_CCM_PDR0_MCU_DIV_7 0x6
133#define MXC_CCM_PDR0_MCU_DIV_8 0x7
134
135#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30 94#define MXC_CCM_PDR1_USB_PRDF_OFFSET 30
136#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30) 95#define MXC_CCM_PDR1_USB_PRDF_MASK (0x3 << 30)
137#define MXC_CCM_PDR1_USB_PODF_OFFSET 27 96#define MXC_CCM_PDR1_USB_PODF_OFFSET 27
@@ -152,118 +111,6 @@
152/* Bit definitions for RCSR */ 111/* Bit definitions for RCSR */
153#define MXC_CCM_RCSR_NF16B 0x80000000 112#define MXC_CCM_RCSR_NF16B 0x80000000
154 113
155/* Bit definitions for both MCU, USB and SR PLL control registers */
156#define MXC_CCM_PCTL_BRM 0x80000000
157#define MXC_CCM_PCTL_PD_OFFSET 26
158#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
159#define MXC_CCM_PCTL_MFD_OFFSET 16
160#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
161#define MXC_CCM_PCTL_MFI_OFFSET 10
162#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
163#define MXC_CCM_PCTL_MFN_OFFSET 0
164#define MXC_CCM_PCTL_MFN_MASK 0x3FF
165
166#define MXC_CCM_CGR0_SD_MMC1_OFFSET 0
167#define MXC_CCM_CGR0_SD_MMC1_MASK (0x3 << 0)
168#define MXC_CCM_CGR0_SD_MMC2_OFFSET 2
169#define MXC_CCM_CGR0_SD_MMC2_MASK (0x3 << 2)
170#define MXC_CCM_CGR0_GPT_OFFSET 4
171#define MXC_CCM_CGR0_GPT_MASK (0x3 << 4)
172#define MXC_CCM_CGR0_EPIT1_OFFSET 6
173#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 6)
174#define MXC_CCM_CGR0_EPIT2_OFFSET 8
175#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 8)
176#define MXC_CCM_CGR0_IIM_OFFSET 10
177#define MXC_CCM_CGR0_IIM_MASK (0x3 << 10)
178#define MXC_CCM_CGR0_ATA_OFFSET 12
179#define MXC_CCM_CGR0_ATA_MASK (0x3 << 12)
180#define MXC_CCM_CGR0_SDMA_OFFSET 14
181#define MXC_CCM_CGR0_SDMA_MASK (0x3 << 14)
182#define MXC_CCM_CGR0_CSPI3_OFFSET 16
183#define MXC_CCM_CGR0_CSPI3_MASK (0x3 << 16)
184#define MXC_CCM_CGR0_RNG_OFFSET 18
185#define MXC_CCM_CGR0_RNG_MASK (0x3 << 18)
186#define MXC_CCM_CGR0_UART1_OFFSET 20
187#define MXC_CCM_CGR0_UART1_MASK (0x3 << 20)
188#define MXC_CCM_CGR0_UART2_OFFSET 22
189#define MXC_CCM_CGR0_UART2_MASK (0x3 << 22)
190#define MXC_CCM_CGR0_SSI1_OFFSET 24
191#define MXC_CCM_CGR0_SSI1_MASK (0x3 << 24)
192#define MXC_CCM_CGR0_I2C1_OFFSET 26
193#define MXC_CCM_CGR0_I2C1_MASK (0x3 << 26)
194#define MXC_CCM_CGR0_I2C2_OFFSET 28
195#define MXC_CCM_CGR0_I2C2_MASK (0x3 << 28)
196#define MXC_CCM_CGR0_I2C3_OFFSET 30
197#define MXC_CCM_CGR0_I2C3_MASK (0x3 << 30)
198
199#define MXC_CCM_CGR1_HANTRO_OFFSET 0
200#define MXC_CCM_CGR1_HANTRO_MASK (0x3 << 0)
201#define MXC_CCM_CGR1_MEMSTICK1_OFFSET 2
202#define MXC_CCM_CGR1_MEMSTICK1_MASK (0x3 << 2)
203#define MXC_CCM_CGR1_MEMSTICK2_OFFSET 4
204#define MXC_CCM_CGR1_MEMSTICK2_MASK (0x3 << 4)
205#define MXC_CCM_CGR1_CSI_OFFSET 6
206#define MXC_CCM_CGR1_CSI_MASK (0x3 << 6)
207#define MXC_CCM_CGR1_RTC_OFFSET 8
208#define MXC_CCM_CGR1_RTC_MASK (0x3 << 8)
209#define MXC_CCM_CGR1_WDOG_OFFSET 10
210#define MXC_CCM_CGR1_WDOG_MASK (0x3 << 10)
211#define MXC_CCM_CGR1_PWM_OFFSET 12
212#define MXC_CCM_CGR1_PWM_MASK (0x3 << 12)
213#define MXC_CCM_CGR1_SIM_OFFSET 14
214#define MXC_CCM_CGR1_SIM_MASK (0x3 << 14)
215#define MXC_CCM_CGR1_ECT_OFFSET 16
216#define MXC_CCM_CGR1_ECT_MASK (0x3 << 16)
217#define MXC_CCM_CGR1_USBOTG_OFFSET 18
218#define MXC_CCM_CGR1_USBOTG_MASK (0x3 << 18)
219#define MXC_CCM_CGR1_KPP_OFFSET 20
220#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
221#define MXC_CCM_CGR1_IPU_OFFSET 22
222#define MXC_CCM_CGR1_IPU_MASK (0x3 << 22)
223#define MXC_CCM_CGR1_UART3_OFFSET 24
224#define MXC_CCM_CGR1_UART3_MASK (0x3 << 24)
225#define MXC_CCM_CGR1_UART4_OFFSET 26
226#define MXC_CCM_CGR1_UART4_MASK (0x3 << 26)
227#define MXC_CCM_CGR1_UART5_OFFSET 28
228#define MXC_CCM_CGR1_UART5_MASK (0x3 << 28)
229#define MXC_CCM_CGR1_OWIRE_OFFSET 30
230#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 30)
231
232#define MXC_CCM_CGR2_SSI2_OFFSET 0
233#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 0)
234#define MXC_CCM_CGR2_CSPI1_OFFSET 2
235#define MXC_CCM_CGR2_CSPI1_MASK (0x3 << 2)
236#define MXC_CCM_CGR2_CSPI2_OFFSET 4
237#define MXC_CCM_CGR2_CSPI2_MASK (0x3 << 4)
238#define MXC_CCM_CGR2_GACC_OFFSET 6
239#define MXC_CCM_CGR2_GACC_MASK (0x3 << 6)
240#define MXC_CCM_CGR2_EMI_OFFSET 8
241#define MXC_CCM_CGR2_EMI_MASK (0x3 << 8)
242#define MXC_CCM_CGR2_RTIC_OFFSET 10
243#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 10)
244#define MXC_CCM_CGR2_FIRI_OFFSET 12
245#define MXC_CCM_CGR2_FIRI_MASK (0x3 << 12)
246#define MXC_CCM_CGR2_IPMUX1_OFFSET 14
247#define MXC_CCM_CGR2_IPMUX1_MASK (0x3 << 14)
248#define MXC_CCM_CGR2_IPMUX2_OFFSET 16
249#define MXC_CCM_CGR2_IPMUX2_MASK (0x3 << 16)
250
251/* These new CGR2 bits are added in MX32 */
252#define MXC_CCM_CGR2_APMSYSCLKSEL_OFFSET 18
253#define MXC_CCM_CGR2_APMSYSCLKSEL_MASK (0x3 << 18)
254#define MXC_CCM_CGR2_APMSSICLKSEL_OFFSET 20
255#define MXC_CCM_CGR2_APMSSICLKSEL_MASK (0x3 << 20)
256#define MXC_CCM_CGR2_APMPERCLKSEL_OFFSET 22
257#define MXC_CCM_CGR2_APMPERCLKSEL_MASK (0x3 << 22)
258#define MXC_CCM_CGR2_MXCCLKENSEL_OFFSET 24
259#define MXC_CCM_CGR2_MXCCLKENSEL_MASK (0x1 << 24)
260#define MXC_CCM_CGR2_CHIKCAMPEN_OFFSET 25
261#define MXC_CCM_CGR2_CHIKCAMPEN_MASK (0x1 << 25)
262#define MXC_CCM_CGR2_OVRVPUBUSY_OFFSET 26
263#define MXC_CCM_CGR2_OVRVPUBUSY_MASK (0x1 << 26)
264#define MXC_CCM_CGR2_APMENA_OFFSET 30
265#define MXC_CCM_CGR2_AOMENA_MASK (0x1 << 30)
266
267/* 114/*
268 * LTR0 register offsets 115 * LTR0 register offsets
269 */ 116 */
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index ed5ab8ed7cf..17d0e9906d5 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -22,6 +22,7 @@ config ARCH_MX2
22config ARCH_MX3 22config ARCH_MX3
23 bool "MX3-based" 23 bool "MX3-based"
24 select CPU_V6 24 select CPU_V6
25 select COMMON_CLKDEV
25 help 26 help
26 This enables support for systems based on the Freescale i.MX3 family 27 This enables support for systems based on the Freescale i.MX3 family
27 28
diff --git a/drivers/dma/ipu/ipu_idmac.c b/drivers/dma/ipu/ipu_idmac.c
index ae50a9d1a4e..da781d10789 100644
--- a/drivers/dma/ipu/ipu_idmac.c
+++ b/drivers/dma/ipu/ipu_idmac.c
@@ -1649,7 +1649,7 @@ static int ipu_probe(struct platform_device *pdev)
1649 } 1649 }
1650 1650
1651 /* Get IPU clock */ 1651 /* Get IPU clock */
1652 ipu_data.ipu_clk = clk_get(&pdev->dev, "ipu_clk"); 1652 ipu_data.ipu_clk = clk_get(&pdev->dev, NULL);
1653 if (IS_ERR(ipu_data.ipu_clk)) { 1653 if (IS_ERR(ipu_data.ipu_clk)) {
1654 ret = PTR_ERR(ipu_data.ipu_clk); 1654 ret = PTR_ERR(ipu_data.ipu_clk);
1655 goto err_clk_get; 1655 goto err_clk_get;
diff --git a/drivers/video/mx3fb.c b/drivers/video/mx3fb.c
index 8a75d05f433..0c27961e47f 100644
--- a/drivers/video/mx3fb.c
+++ b/drivers/video/mx3fb.c
@@ -493,7 +493,7 @@ static int sdc_init_panel(struct mx3fb_data *mx3fb, enum ipu_panel panel,
493 */ 493 */
494 dev_dbg(mx3fb->dev, "pixel clk = %d\n", pixel_clk); 494 dev_dbg(mx3fb->dev, "pixel clk = %d\n", pixel_clk);
495 495
496 ipu_clk = clk_get(mx3fb->dev, "ipu_clk"); 496 ipu_clk = clk_get(mx3fb->dev, NULL);
497 div = clk_get_rate(ipu_clk) * 16 / pixel_clk; 497 div = clk_get_rate(ipu_clk) * 16 / pixel_clk;
498 clk_put(ipu_clk); 498 clk_put(ipu_clk);
499 499
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 13:40:58 -0500