diff options
author | Magnus Damm <damm@opensource.se> | 2010-02-07 21:47:44 -0500 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2010-02-07 21:47:44 -0500 |
commit | 9e9622d1a064705181bea0600ea9eacd95adab7f (patch) | |
tree | 8334f134bc6cfe95d9be2e512e455d4bd976f36b | |
parent | 6339204ecc2aa2067a99595522de0403f0854bb8 (diff) |
serial: sh-sci: remove SCIF code in sci_rxd_in()
Since sci_rxd_in() is used by SCI only, clean up
the header file by killing off code dealing with
SCIF ports and their register definitions.
Also introduce a default sci_rxd_in() function
which can be shared by all SCIF-only processors.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r-- | drivers/serial/sh-sci.h | 220 |
1 files changed, 1 insertions, 219 deletions
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h index 0efcded59ae..f7d2589926d 100644 --- a/drivers/serial/sh-sci.h +++ b/drivers/serial/sh-sci.h | |||
@@ -518,34 +518,6 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
518 | { | 518 | { |
519 | if (port->mapbase == 0xfffffe80) | 519 | if (port->mapbase == 0xfffffe80) |
520 | return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | 520 | return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ |
521 | if (port->mapbase == 0xa4000150) | ||
522 | return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | ||
523 | if (port->mapbase == 0xa4000140) | ||
524 | return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | ||
525 | return 1; | ||
526 | } | ||
527 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) | ||
528 | static inline int sci_rxd_in(struct uart_port *port) | ||
529 | { | ||
530 | if (port->mapbase == SCIF0) | ||
531 | return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | ||
532 | if (port->mapbase == SCIF2) | ||
533 | return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | ||
534 | return 1; | ||
535 | } | ||
536 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) | ||
537 | static inline int sci_rxd_in(struct uart_port *port) | ||
538 | { | ||
539 | return sci_in(port,SCxSR)&0x0010 ? 1 : 0; | ||
540 | } | ||
541 | #elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ | ||
542 | defined(CONFIG_CPU_SUBTYPE_SH7721) | ||
543 | static inline int sci_rxd_in(struct uart_port *port) | ||
544 | { | ||
545 | if (port->mapbase == 0xa4430000) | ||
546 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | ||
547 | else if (port->mapbase == 0xa4438000) | ||
548 | return sci_in(port, SCxSR) & 0x0003 ? 1 : 0; | ||
549 | return 1; | 521 | return 1; |
550 | } | 522 | } |
551 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ | 523 | #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
@@ -558,207 +530,17 @@ static inline int sci_rxd_in(struct uart_port *port) | |||
558 | { | 530 | { |
559 | if (port->mapbase == 0xffe00000) | 531 | if (port->mapbase == 0xffe00000) |
560 | return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | 532 | return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ |
561 | if (port->mapbase == 0xffe80000) | ||
562 | return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | ||
563 | return 1; | ||
564 | } | ||
565 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) | ||
566 | static inline int sci_rxd_in(struct uart_port *port) | ||
567 | { | ||
568 | if (port->mapbase == 0xffe80000) | ||
569 | return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | ||
570 | return 1; | 533 | return 1; |
571 | } | 534 | } |
572 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) | ||
573 | static inline int sci_rxd_in(struct uart_port *port) | ||
574 | { | ||
575 | if (port->mapbase == 0xfe4b0000) | ||
576 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; | ||
577 | if (port->mapbase == 0xfe4c0000) | ||
578 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; | ||
579 | if (port->mapbase == 0xfe4d0000) | ||
580 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; | ||
581 | } | ||
582 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) | ||
583 | static inline int sci_rxd_in(struct uart_port *port) | ||
584 | { | ||
585 | if (port->mapbase == 0xfe600000) | ||
586 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
587 | if (port->mapbase == 0xfe610000) | ||
588 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
589 | if (port->mapbase == 0xfe620000) | ||
590 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
591 | return 1; | ||
592 | } | ||
593 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) | ||
594 | static inline int sci_rxd_in(struct uart_port *port) | ||
595 | { | ||
596 | if (port->mapbase == 0xffe00000) | ||
597 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
598 | if (port->mapbase == 0xffe10000) | ||
599 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
600 | if (port->mapbase == 0xffe20000) | ||
601 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
602 | if (port->mapbase == 0xffe30000) | ||
603 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
604 | return 1; | ||
605 | } | ||
606 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) | ||
607 | static inline int sci_rxd_in(struct uart_port *port) | ||
608 | { | ||
609 | if (port->mapbase == 0xffe00000) | ||
610 | return __raw_readb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | ||
611 | return 1; | ||
612 | } | ||
613 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) | ||
614 | static inline int sci_rxd_in(struct uart_port *port) | ||
615 | { | ||
616 | if (port->mapbase == 0xffe00000) | ||
617 | return __raw_readb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ | ||
618 | if (port->mapbase == 0xffe10000) | ||
619 | return __raw_readb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ | ||
620 | if (port->mapbase == 0xffe20000) | ||
621 | return __raw_readb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ | ||
622 | |||
623 | return 1; | ||
624 | } | ||
625 | #elif defined(CONFIG_CPU_SUBTYPE_SH7723) | ||
626 | static inline int sci_rxd_in(struct uart_port *port) | ||
627 | { | ||
628 | if (port->mapbase == 0xffe00000) | ||
629 | return __raw_readb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ | ||
630 | if (port->mapbase == 0xffe10000) | ||
631 | return __raw_readb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ | ||
632 | if (port->mapbase == 0xffe20000) | ||
633 | return __raw_readb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ | ||
634 | if (port->mapbase == 0xa4e30000) | ||
635 | return __raw_readb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ | ||
636 | if (port->mapbase == 0xa4e40000) | ||
637 | return __raw_readb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ | ||
638 | if (port->mapbase == 0xa4e50000) | ||
639 | return __raw_readb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ | ||
640 | return 1; | ||
641 | } | ||
642 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) | ||
643 | # define SCFSR 0x0010 | ||
644 | # define SCASSR 0x0014 | ||
645 | static inline int sci_rxd_in(struct uart_port *port) | ||
646 | { | ||
647 | if (port->type == PORT_SCIF) | ||
648 | return __raw_readw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; | ||
649 | if (port->type == PORT_SCIFA) | ||
650 | return __raw_readw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; | ||
651 | return 1; | ||
652 | } | ||
653 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) | ||
654 | static inline int sci_rxd_in(struct uart_port *port) | ||
655 | { | ||
656 | return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */ | ||
657 | } | ||
658 | #elif defined(__H8300H__) || defined(__H8300S__) | 535 | #elif defined(__H8300H__) || defined(__H8300S__) |
659 | static inline int sci_rxd_in(struct uart_port *port) | 536 | static inline int sci_rxd_in(struct uart_port *port) |
660 | { | 537 | { |
661 | int ch = (port->mapbase - SMR0) >> 3; | 538 | int ch = (port->mapbase - SMR0) >> 3; |
662 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; | 539 | return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0; |
663 | } | 540 | } |
664 | #elif defined(CONFIG_CPU_SUBTYPE_SH7763) | 541 | #else /* default case for non-SCI processors */ |
665 | static inline int sci_rxd_in(struct uart_port *port) | ||
666 | { | ||
667 | if (port->mapbase == 0xffe00000) | ||
668 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
669 | if (port->mapbase == 0xffe08000) | ||
670 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
671 | if (port->mapbase == 0xffe10000) | ||
672 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ | ||
673 | |||
674 | return 1; | ||
675 | } | ||
676 | #elif defined(CONFIG_CPU_SUBTYPE_SH7770) | ||
677 | static inline int sci_rxd_in(struct uart_port *port) | ||
678 | { | ||
679 | if (port->mapbase == 0xff923000) | ||
680 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
681 | if (port->mapbase == 0xff924000) | ||
682 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
683 | if (port->mapbase == 0xff925000) | ||
684 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
685 | return 1; | ||
686 | } | ||
687 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) | ||
688 | static inline int sci_rxd_in(struct uart_port *port) | ||
689 | { | ||
690 | if (port->mapbase == 0xffe00000) | ||
691 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
692 | if (port->mapbase == 0xffe10000) | ||
693 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
694 | return 1; | ||
695 | } | ||
696 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ | ||
697 | defined(CONFIG_CPU_SUBTYPE_SH7786) | ||
698 | static inline int sci_rxd_in(struct uart_port *port) | ||
699 | { | ||
700 | if (port->mapbase == 0xffea0000) | ||
701 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
702 | if (port->mapbase == 0xffeb0000) | ||
703 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
704 | if (port->mapbase == 0xffec0000) | ||
705 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
706 | if (port->mapbase == 0xffed0000) | ||
707 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
708 | if (port->mapbase == 0xffee0000) | ||
709 | return __raw_readw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | ||
710 | if (port->mapbase == 0xffef0000) | ||
711 | return __raw_readw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | ||
712 | return 1; | ||
713 | } | ||
714 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ | ||
715 | defined(CONFIG_CPU_SUBTYPE_SH7203) || \ | ||
716 | defined(CONFIG_CPU_SUBTYPE_SH7206) || \ | ||
717 | defined(CONFIG_CPU_SUBTYPE_SH7263) | ||
718 | static inline int sci_rxd_in(struct uart_port *port) | ||
719 | { | ||
720 | if (port->mapbase == 0xfffe8000) | ||
721 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
722 | if (port->mapbase == 0xfffe8800) | ||
723 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
724 | if (port->mapbase == 0xfffe9000) | ||
725 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
726 | if (port->mapbase == 0xfffe9800) | ||
727 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
728 | #if defined(CONFIG_CPU_SUBTYPE_SH7201) | ||
729 | if (port->mapbase == 0xfffeA000) | ||
730 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
731 | if (port->mapbase == 0xfffeA800) | ||
732 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
733 | if (port->mapbase == 0xfffeB000) | ||
734 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
735 | if (port->mapbase == 0xfffeB800) | ||
736 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
737 | #endif | ||
738 | return 1; | ||
739 | } | ||
740 | #elif defined(CONFIG_CPU_SUBTYPE_SH7619) | ||
741 | static inline int sci_rxd_in(struct uart_port *port) | ||
742 | { | ||
743 | if (port->mapbase == 0xf8400000) | ||
744 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
745 | if (port->mapbase == 0xf8410000) | ||
746 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
747 | if (port->mapbase == 0xf8420000) | ||
748 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
749 | return 1; | ||
750 | } | ||
751 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) | ||
752 | static inline int sci_rxd_in(struct uart_port *port) | 542 | static inline int sci_rxd_in(struct uart_port *port) |
753 | { | 543 | { |
754 | if (port->mapbase == 0xffc30000) | ||
755 | return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | ||
756 | if (port->mapbase == 0xffc40000) | ||
757 | return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | ||
758 | if (port->mapbase == 0xffc50000) | ||
759 | return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | ||
760 | if (port->mapbase == 0xffc60000) | ||
761 | return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | ||
762 | return 1; | 544 | return 1; |
763 | } | 545 | } |
764 | #endif | 546 | #endif |