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authorPaul Mundt <lethal@linux-sh.org>2010-01-25 22:58:40 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-01-25 22:58:40 -0500
commit9d56dd3b083a3bec56e9da35ce07baca81030b03 (patch)
treea9df9d514fbc32defc1ca8a6d7c2795f15b8a128
parenta077e91690fb32a1453423b2cf1df3492fd30c3a (diff)
sh: Mass ctrl_in/outX to __raw_read/writeX conversion.
The old ctrl in/out routines are non-portable and unsuitable for cross-platform use. While drivers/sh has already been sanitized, there is still quite a lot of code that is not. This converts the arch/sh/ bits over, which permits us to flag the routines as deprecated whilst still building with -Werror for the architecture code, and to ensure that future users are not added. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/boards/board-magicpanelr2.c74
-rw-r--r--arch/sh/boards/board-polaris.c22
-rw-r--r--arch/sh/boards/board-shmin.c4
-rw-r--r--arch/sh/boards/mach-ap325rxa/setup.c16
-rw-r--r--arch/sh/boards/mach-cayman/irq.c16
-rw-r--r--arch/sh/boards/mach-dreamcast/rtc.c20
-rw-r--r--arch/sh/boards/mach-ecovec24/setup.c20
-rw-r--r--arch/sh/boards/mach-highlander/irq-r7780mp.c2
-rw-r--r--arch/sh/boards/mach-highlander/irq-r7780rp.c2
-rw-r--r--arch/sh/boards/mach-highlander/irq-r7785rp.c16
-rw-r--r--arch/sh/boards/mach-highlander/psw.c4
-rw-r--r--arch/sh/boards/mach-highlander/setup.c14
-rw-r--r--arch/sh/boards/mach-hp6xx/hp6xx_apm.c2
-rw-r--r--arch/sh/boards/mach-hp6xx/pm.c38
-rw-r--r--arch/sh/boards/mach-hp6xx/setup.c12
-rw-r--r--arch/sh/boards/mach-kfr2r09/setup.c14
-rw-r--r--arch/sh/boards/mach-landisk/gio.c12
-rw-r--r--arch/sh/boards/mach-landisk/irq.c6
-rw-r--r--arch/sh/boards/mach-landisk/psw.c4
-rw-r--r--arch/sh/boards/mach-landisk/setup.c4
-rw-r--r--arch/sh/boards/mach-microdev/io.c4
-rw-r--r--arch/sh/boards/mach-microdev/irq.c10
-rw-r--r--arch/sh/boards/mach-migor/setup.c8
-rw-r--r--arch/sh/boards/mach-r2d/irq.c4
-rw-r--r--arch/sh/boards/mach-r2d/setup.c8
-rw-r--r--arch/sh/boards/mach-rsk/devices-rsk7203.c2
-rw-r--r--arch/sh/boards/mach-sdk7780/irq.c4
-rw-r--r--arch/sh/boards/mach-sdk7780/setup.c6
-rw-r--r--arch/sh/boards/mach-se/7206/io.c2
-rw-r--r--arch/sh/boards/mach-se/7206/irq.c40
-rw-r--r--arch/sh/boards/mach-se/7343/irq.c10
-rw-r--r--arch/sh/boards/mach-se/7343/setup.c6
-rw-r--r--arch/sh/boards/mach-se/770x/irq.c14
-rw-r--r--arch/sh/boards/mach-se/7721/irq.c2
-rw-r--r--arch/sh/boards/mach-se/7721/setup.c8
-rw-r--r--arch/sh/boards/mach-se/7722/irq.c10
-rw-r--r--arch/sh/boards/mach-se/7722/setup.c34
-rw-r--r--arch/sh/boards/mach-se/7724/irq.c20
-rw-r--r--arch/sh/boards/mach-se/7724/setup.c26
-rw-r--r--arch/sh/boards/mach-se/7780/irq.c18
-rw-r--r--arch/sh/boards/mach-se/7780/setup.c26
-rw-r--r--arch/sh/boards/mach-sh03/rtc.c50
-rw-r--r--arch/sh/boards/mach-sh7763rdp/irq.c10
-rw-r--r--arch/sh/boards/mach-sh7763rdp/setup.c40
-rw-r--r--arch/sh/boards/mach-snapgear/setup.c2
-rw-r--r--arch/sh/boards/mach-systemh/irq.c12
-rw-r--r--arch/sh/boards/mach-titan/io.c30
-rw-r--r--arch/sh/boards/mach-x3proto/ilsel.c8
-rw-r--r--arch/sh/boards/mach-x3proto/setup.c2
-rw-r--r--arch/sh/cchips/hd6446x/hd64461.c2
-rw-r--r--arch/sh/drivers/dma/dma-pvr2.c10
-rw-r--r--arch/sh/drivers/dma/dma-sh.c26
-rw-r--r--arch/sh/drivers/dma/dmabrg.c22
-rw-r--r--arch/sh/drivers/pci/fixups-rts7751r2d.c4
-rw-r--r--arch/sh/drivers/pci/pci-sh4.h4
-rw-r--r--arch/sh/drivers/pci/pci-sh5.h12
-rw-r--r--arch/sh/drivers/pci/pci-sh7751.c12
-rw-r--r--arch/sh/drivers/superhyway/ops-sh4-202.c8
-rw-r--r--arch/sh/include/asm/dma-sh.h12
-rw-r--r--arch/sh/include/asm/mmu_context.h6
-rw-r--r--arch/sh/include/asm/mmu_context_32.h4
-rw-r--r--arch/sh/include/asm/watchdog.h18
-rw-r--r--arch/sh/include/cpu-sh2/cpu/watchdog.h4
-rw-r--r--arch/sh/include/cpu-sh3/cpu/dac.h12
-rw-r--r--arch/sh/include/mach-common/mach/magicpanelr2.h12
-rw-r--r--arch/sh/kernel/cpu/adc.c12
-rw-r--r--arch/sh/kernel/cpu/init.c10
-rw-r--r--arch/sh/kernel/cpu/irq/intc-sh5.c14
-rw-r--r--arch/sh/kernel/cpu/sh2/clock-sh7619.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7201.c8
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7203.c6
-rw-r--r--arch/sh/kernel/cpu/sh2a/clock-sh7206.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh3.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7705.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7706.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7709.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7710.c8
-rw-r--r--arch/sh/kernel/cpu/sh3/clock-sh7712.c6
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c26
-rw-r--r--arch/sh/kernel/cpu/sh3/setup-sh3.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c10
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4.c8
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c6
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh4-202.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7750.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/setup-sh7760.c2
-rw-r--r--arch/sh/kernel/cpu/sh4/sq.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7763.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7770.c8
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7780.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-shx3.c10
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c26
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7763.c20
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7770.c24
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7780.c24
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7785.c26
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7786.c24
-rw-r--r--arch/sh/kernel/cpu/sh5/clock-sh5.c8
-rw-r--r--arch/sh/kernel/io_trapped.c16
-rw-r--r--arch/sh/kernel/process_32.c2
-rw-r--r--arch/sh/kernel/signal_32.c6
-rw-r--r--arch/sh/kernel/traps.c4
-rw-r--r--arch/sh/mm/cache-debugfs.c4
-rw-r--r--arch/sh/mm/cache-sh2.c12
-rw-r--r--arch/sh/mm/cache-sh2a.c20
-rw-r--r--arch/sh/mm/cache-sh3.c6
-rw-r--r--arch/sh/mm/cache-sh4.c10
-rw-r--r--arch/sh/mm/cache-sh7705.c8
-rw-r--r--arch/sh/mm/pmb.c24
-rw-r--r--arch/sh/mm/tlb-sh3.c6
-rw-r--r--arch/sh/mm/tlb-sh4.c10
-rw-r--r--arch/sh/mm/tlbflush_32.c4
115 files changed, 698 insertions, 698 deletions
diff --git a/arch/sh/boards/board-magicpanelr2.c b/arch/sh/boards/board-magicpanelr2.c
index 99ffc5f1c0d..efba450a051 100644
--- a/arch/sh/boards/board-magicpanelr2.c
+++ b/arch/sh/boards/board-magicpanelr2.c
@@ -23,7 +23,7 @@
23#include <asm/heartbeat.h> 23#include <asm/heartbeat.h>
24#include <cpu/sh7720.h> 24#include <cpu/sh7720.h>
25 25
26#define LAN9115_READY (ctrl_inl(0xA8000084UL) & 0x00000001UL) 26#define LAN9115_READY (__raw_readl(0xA8000084UL) & 0x00000001UL)
27 27
28/* Prefer cmdline over RedBoot */ 28/* Prefer cmdline over RedBoot */
29static const char *probes[] = { "cmdlinepart", "RedBoot", NULL }; 29static const char *probes[] = { "cmdlinepart", "RedBoot", NULL };
@@ -60,33 +60,33 @@ static void __init setup_chip_select(void)
60{ 60{
61 /* CS2: LAN (0x08000000 - 0x0bffffff) */ 61 /* CS2: LAN (0x08000000 - 0x0bffffff) */
62 /* no idle cycles, normal space, 8 bit data bus */ 62 /* no idle cycles, normal space, 8 bit data bus */
63 ctrl_outl(0x36db0400, CS2BCR); 63 __raw_writel(0x36db0400, CS2BCR);
64 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 64 /* (SW:1.5 WR:3 HW:1.5), ext. wait */
65 ctrl_outl(0x000003c0, CS2WCR); 65 __raw_writel(0x000003c0, CS2WCR);
66 66
67 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */ 67 /* CS4: CAN1 (0xb0000000 - 0xb3ffffff) */
68 /* no idle cycles, normal space, 8 bit data bus */ 68 /* no idle cycles, normal space, 8 bit data bus */
69 ctrl_outl(0x00000200, CS4BCR); 69 __raw_writel(0x00000200, CS4BCR);
70 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 70 /* (SW:1.5 WR:3 HW:1.5), ext. wait */
71 ctrl_outl(0x00100981, CS4WCR); 71 __raw_writel(0x00100981, CS4WCR);
72 72
73 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */ 73 /* CS5a: CAN2 (0xb4000000 - 0xb5ffffff) */
74 /* no idle cycles, normal space, 8 bit data bus */ 74 /* no idle cycles, normal space, 8 bit data bus */
75 ctrl_outl(0x00000200, CS5ABCR); 75 __raw_writel(0x00000200, CS5ABCR);
76 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 76 /* (SW:1.5 WR:3 HW:1.5), ext. wait */
77 ctrl_outl(0x00100981, CS5AWCR); 77 __raw_writel(0x00100981, CS5AWCR);
78 78
79 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */ 79 /* CS5b: CAN3 (0xb6000000 - 0xb7ffffff) */
80 /* no idle cycles, normal space, 8 bit data bus */ 80 /* no idle cycles, normal space, 8 bit data bus */
81 ctrl_outl(0x00000200, CS5BBCR); 81 __raw_writel(0x00000200, CS5BBCR);
82 /* (SW:1.5 WR:3 HW:1.5), ext. wait */ 82 /* (SW:1.5 WR:3 HW:1.5), ext. wait */
83 ctrl_outl(0x00100981, CS5BWCR); 83 __raw_writel(0x00100981, CS5BWCR);
84 84
85 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */ 85 /* CS6a: Rotary (0xb8000000 - 0xb9ffffff) */
86 /* no idle cycles, normal space, 8 bit data bus */ 86 /* no idle cycles, normal space, 8 bit data bus */
87 ctrl_outl(0x00000200, CS6ABCR); 87 __raw_writel(0x00000200, CS6ABCR);
88 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */ 88 /* (SW:1.5 WR:3 HW:1.5), no ext. wait */
89 ctrl_outl(0x001009C1, CS6AWCR); 89 __raw_writel(0x001009C1, CS6AWCR);
90} 90}
91 91
92static void __init setup_port_multiplexing(void) 92static void __init setup_port_multiplexing(void)
@@ -94,71 +94,71 @@ static void __init setup_port_multiplexing(void)
94 /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5); 94 /* A7 GPO(LED8); A6 GPO(LED7); A5 GPO(LED6); A4 GPO(LED5);
95 * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1); 95 * A3 GPO(LED4); A2 GPO(LED3); A1 GPO(LED2); A0 GPO(LED1);
96 */ 96 */
97 ctrl_outw(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */ 97 __raw_writew(0x5555, PORT_PACR); /* 01 01 01 01 01 01 01 01 */
98 98
99 /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1); 99 /* B7 GPO(RST4); B6 GPO(RST3); B5 GPO(RST2); B4 GPO(RST1);
100 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0); 100 * B3 GPO(PB3); B2 GPO(PB2); B1 GPO(PB1); B0 GPO(PB0);
101 */ 101 */
102 ctrl_outw(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */ 102 __raw_writew(0x5555, PORT_PBCR); /* 01 01 01 01 01 01 01 01 */
103 103
104 /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4); 104 /* C7 GPO(PC7); C6 GPO(PC6); C5 GPO(PC5); C4 GPO(PC4);
105 * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0; 105 * C3 LCD_DATA3; C2 LCD_DATA2; C1 LCD_DATA1; C0 LCD_DATA0;
106 */ 106 */
107 ctrl_outw(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */ 107 __raw_writew(0x5500, PORT_PCCR); /* 01 01 01 01 00 00 00 00 */
108 108
109 /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4); 109 /* D7 GPO(PD7); D6 GPO(PD6); D5 GPO(PD5); D4 GPO(PD4);
110 * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0); 110 * D3 GPO(PD3); D2 GPO(PD2); D1 GPO(PD1); D0 GPO(PD0);
111 */ 111 */
112 ctrl_outw(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */ 112 __raw_writew(0x5555, PORT_PDCR); /* 01 01 01 01 01 01 01 01 */
113 113
114 /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP; 114 /* E7 (x); E6 GPI(nu); E5 GPI(nu); E4 LCD_M_DISP;
115 * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM; 115 * E3 LCD_CL1; E2 LCD_CL2; E1 LCD_DON; E0 LCD_FLM;
116 */ 116 */
117 ctrl_outw(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */ 117 __raw_writew(0x3C00, PORT_PECR); /* 00 11 11 00 00 00 00 00 */
118 118
119 /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3; 119 /* F7 (x); F6 DA1(VLCD); F5 DA0(nc); F4 AN3;
120 * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc); 120 * F3 AN2(MID_AD); F2 AN1(EARTH_AD); F1 AN0(TEMP); F0 GPI+(nc);
121 */ 121 */
122 ctrl_outw(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */ 122 __raw_writew(0x0002, PORT_PFCR); /* 00 00 00 00 00 00 00 10 */
123 123
124 /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2); 124 /* G7 (x); G6 IRQ5(TOUCH_BUSY); G5 IRQ4(TOUCH_IRQ); G4 GPI(KEY2);
125 * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9); 125 * G3 GPI(KEY1); G2 GPO(LED11); G1 GPO(LED10); G0 GPO(LED9);
126 */ 126 */
127 ctrl_outw(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */ 127 __raw_writew(0x03D5, PORT_PGCR); /* 00 00 00 11 11 01 01 01 */
128 128
129 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE); 129 /* H7 (x); H6 /RAS(BRAS); H5 /CAS(BCAS); H4 CKE(BCKE);
130 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR; 130 * H3 GPO(EARTH_OFF); H2 GPO(EARTH_TEST); H1 USB2_PWR; H0 USB1_PWR;
131 */ 131 */
132 ctrl_outw(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */ 132 __raw_writew(0x0050, PORT_PHCR); /* 00 00 00 00 01 01 00 00 */
133 133
134 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3; 134 /* J7 (x); J6 AUDCK; J5 ASEBRKAK; J4 AUDATA3;
135 * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC; 135 * J3 AUDATA2; J2 AUDATA1; J1 AUDATA0; J0 AUDSYNC;
136 */ 136 */
137 ctrl_outw(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */ 137 __raw_writew(0x0000, PORT_PJCR); /* 00 00 00 00 00 00 00 00 */
138 138
139 /* K7 (x); K6 (x); K5 (x); K4 (x); 139 /* K7 (x); K6 (x); K5 (x); K4 (x);
140 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY) 140 * K3 PINT7(/PWR2); K2 PINT6(/PWR1); K1 PINT5(nu); K0 PINT4(FLASH_READY)
141 */ 141 */
142 ctrl_outw(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */ 142 __raw_writew(0x00FF, PORT_PKCR); /* 00 00 00 00 11 11 11 11 */
143 143
144 /* L7 TRST; L6 TMS; L5 TDO; L4 TDI; 144 /* L7 TRST; L6 TMS; L5 TDO; L4 TDI;
145 * L3 TCK; L2 (x); L1 (x); L0 (x); 145 * L3 TCK; L2 (x); L1 (x); L0 (x);
146 */ 146 */
147 ctrl_outw(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */ 147 __raw_writew(0x0000, PORT_PLCR); /* 00 00 00 00 00 00 00 00 */
148 148
149 /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED); 149 /* M7 GPO(CURRENT_SINK); M6 GPO(PWR_SWITCH); M5 GPO(LAN_SPEED);
150 * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL); 150 * M4 GPO(LAN_RESET); M3 GPO(BUZZER); M2 GPO(LCD_BL);
151 * M1 CS5B(CAN3_CS); M0 GPI+(nc); 151 * M1 CS5B(CAN3_CS); M0 GPI+(nc);
152 */ 152 */
153 ctrl_outw(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */ 153 __raw_writew(0x5552, PORT_PMCR); /* 01 01 01 01 01 01 00 10 */
154 154
155 /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit, 155 /* CURRENT_SINK=off, PWR_SWITCH=off, LAN_SPEED=100MBit,
156 * LAN_RESET=off, BUZZER=off, LCD_BL=off 156 * LAN_RESET=off, BUZZER=off, LCD_BL=off
157 */ 157 */
158#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2 158#if CONFIG_SH_MAGIC_PANEL_R2_VERSION == 2
159 ctrl_outb(0x30, PORT_PMDR); 159 __raw_writeb(0x30, PORT_PMDR);
160#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3 160#elif CONFIG_SH_MAGIC_PANEL_R2_VERSION == 3
161 ctrl_outb(0xF0, PORT_PMDR); 161 __raw_writeb(0xF0, PORT_PMDR);
162#else 162#else
163#error Unknown revision of PLATFORM_MP_R2 163#error Unknown revision of PLATFORM_MP_R2
164#endif 164#endif
@@ -167,8 +167,8 @@ static void __init setup_port_multiplexing(void)
167 * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ); 167 * P4 GPO(nu); P3 IRQ3(LAN_IRQ); P2 IRQ2(CAN3_IRQ);
168 * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ) 168 * P1 IRQ1(CAN2_IRQ); P0 IRQ0(CAN1_IRQ)
169 */ 169 */
170 ctrl_outw(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */ 170 __raw_writew(0x0100, PORT_PPCR); /* 00 00 00 01 00 00 00 00 */
171 ctrl_outb(0x10, PORT_PPDR); 171 __raw_writeb(0x10, PORT_PPDR);
172 172
173 /* R7 A25; R6 A24; R5 A23; R4 A22; 173 /* R7 A25; R6 A24; R5 A23; R4 A22;
174 * R3 A21; R2 A20; R1 A19; R0 A0; 174 * R3 A21; R2 A20; R1 A19; R0 A0;
@@ -185,22 +185,22 @@ static void __init setup_port_multiplexing(void)
185 /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2); 185 /* S7 (x); S6 (x); S5 (x); S4 GPO(EEPROM_CS2);
186 * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK; 186 * S3 GPO(EEPROM_CS1); S2 SIOF0_TXD; S1 SIOF0_RXD; S0 SIOF0_SCK;
187 */ 187 */
188 ctrl_outw(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */ 188 __raw_writew(0x0140, PORT_PSCR); /* 00 00 00 01 01 00 00 00 */
189 189
190 /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS; 190 /* T7 (x); T6 (x); T5 (x); T4 COM1_CTS;
191 * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG) 191 * T3 COM1_RTS; T2 COM1_TXD; T1 COM1_RXD; T0 GPO(WDOG)
192 */ 192 */
193 ctrl_outw(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */ 193 __raw_writew(0x0001, PORT_PTCR); /* 00 00 00 00 00 00 00 01 */
194 194
195 /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT); 195 /* U7 (x); U6 (x); U5 (x); U4 GPI+(/AC_FAULT);
196 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK; 196 * U3 GPO(TOUCH_CS); U2 TOUCH_TXD; U1 TOUCH_RXD; U0 TOUCH_SCK;
197 */ 197 */
198 ctrl_outw(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */ 198 __raw_writew(0x0240, PORT_PUCR); /* 00 00 00 10 01 00 00 00 */
199 199
200 /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2); 200 /* V7 (x); V6 (x); V5 (x); V4 GPO(MID2);
201 * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT); 201 * V3 GPO(MID1); V2 CARD_TxD; V1 CARD_RxD; V0 GPI+(/BAT_FAULT);
202 */ 202 */
203 ctrl_outw(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */ 203 __raw_writew(0x0142, PORT_PVCR); /* 00 00 00 01 01 00 00 10 */
204} 204}
205 205
206static void __init mpr2_setup(char **cmdline_p) 206static void __init mpr2_setup(char **cmdline_p)
@@ -209,24 +209,24 @@ static void __init mpr2_setup(char **cmdline_p)
209 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2, 209 * /PCC_CD1, /PCC_CD2, PCC_BVD1, PCC_BVD2,
210 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND 210 * /IOIS16, IRQ4, IRQ5, USB1d_SUSPEND
211 */ 211 */
212 ctrl_outw(0xAABC, PORT_PSELA); 212 __raw_writew(0xAABC, PORT_PSELA);
213 /* set Pin Select Register B: 213 /* set Pin Select Register B:
214 * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC, 214 * /SCIF0_RTS, /SCIF0_CTS, LCD_VCPWC,
215 * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved 215 * LCD_VEPWC, IIC_SDA, IIC_SCL, Reserved
216 */ 216 */
217 ctrl_outw(0x3C00, PORT_PSELB); 217 __raw_writew(0x3C00, PORT_PSELB);
218 /* set Pin Select Register C: 218 /* set Pin Select Register C:
219 * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved 219 * SIOF1_SCK, SIOF1_RxD, SCIF1_RxD, SCIF1_TxD, Reserved
220 */ 220 */
221 ctrl_outw(0x0000, PORT_PSELC); 221 __raw_writew(0x0000, PORT_PSELC);
222 /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, 222 /* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK,
223 * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved 223 * Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved
224 */ 224 */
225 ctrl_outw(0x0000, PORT_PSELD); 225 __raw_writew(0x0000, PORT_PSELD);
226 /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */ 226 /* set USB TxRx Control: Reserved, DRV, Reserved, USB_TRANS, USB_SEL */
227 ctrl_outw(0x0101, PORT_UTRCTL); 227 __raw_writew(0x0101, PORT_UTRCTL);
228 /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */ 228 /* set USB Clock Control: USSCS, USSTB, Reserved (HighByte always A5) */
229 ctrl_outw(0xA5C0, PORT_UCLKCR_W); 229 __raw_writew(0xA5C0, PORT_UCLKCR_W);
230 230
231 setup_chip_select(); 231 setup_chip_select();
232 232
diff --git a/arch/sh/boards/board-polaris.c b/arch/sh/boards/board-polaris.c
index 5bc126900ce..594866356c2 100644
--- a/arch/sh/boards/board-polaris.c
+++ b/arch/sh/boards/board-polaris.c
@@ -89,15 +89,15 @@ static int __init polaris_initialise(void)
89 printk(KERN_INFO "Configuring Polaris external bus\n"); 89 printk(KERN_INFO "Configuring Polaris external bus\n");
90 90
91 /* Configure area 5 with 2 wait states */ 91 /* Configure area 5 with 2 wait states */
92 wcr = ctrl_inw(WCR2); 92 wcr = __raw_readw(WCR2);
93 wcr &= (~AREA5_WAIT_CTRL); 93 wcr &= (~AREA5_WAIT_CTRL);
94 wcr |= (WAIT_STATES_10 << 10); 94 wcr |= (WAIT_STATES_10 << 10);
95 ctrl_outw(wcr, WCR2); 95 __raw_writew(wcr, WCR2);
96 96
97 /* Configure area 5 for 32-bit access */ 97 /* Configure area 5 for 32-bit access */
98 bcr_mask = ctrl_inw(BCR2); 98 bcr_mask = __raw_readw(BCR2);
99 bcr_mask |= 1 << 10; 99 bcr_mask |= 1 << 10;
100 ctrl_outw(bcr_mask, BCR2); 100 __raw_writew(bcr_mask, BCR2);
101 101
102 return platform_add_devices(polaris_devices, 102 return platform_add_devices(polaris_devices,
103 ARRAY_SIZE(polaris_devices)); 103 ARRAY_SIZE(polaris_devices));
@@ -128,13 +128,13 @@ static struct ipr_desc ipr_irq_desc = {
128static void __init init_polaris_irq(void) 128static void __init init_polaris_irq(void)
129{ 129{
130 /* Disable all interrupts */ 130 /* Disable all interrupts */
131 ctrl_outw(0, BCR_ILCRA); 131 __raw_writew(0, BCR_ILCRA);
132 ctrl_outw(0, BCR_ILCRB); 132 __raw_writew(0, BCR_ILCRB);
133 ctrl_outw(0, BCR_ILCRC); 133 __raw_writew(0, BCR_ILCRC);
134 ctrl_outw(0, BCR_ILCRD); 134 __raw_writew(0, BCR_ILCRD);
135 ctrl_outw(0, BCR_ILCRE); 135 __raw_writew(0, BCR_ILCRE);
136 ctrl_outw(0, BCR_ILCRF); 136 __raw_writew(0, BCR_ILCRF);
137 ctrl_outw(0, BCR_ILCRG); 137 __raw_writew(0, BCR_ILCRG);
138 138
139 register_ipr_controller(&ipr_irq_desc); 139 register_ipr_controller(&ipr_irq_desc);
140} 140}
diff --git a/arch/sh/boards/board-shmin.c b/arch/sh/boards/board-shmin.c
index b1dcbbc8918..325bed53b87 100644
--- a/arch/sh/boards/board-shmin.c
+++ b/arch/sh/boards/board-shmin.c
@@ -17,8 +17,8 @@
17 17
18static void __init init_shmin_irq(void) 18static void __init init_shmin_irq(void)
19{ 19{
20 ctrl_outw(0x2a00, PFC_PHCR); // IRQ0-3=IRQ 20 __raw_writew(0x2a00, PFC_PHCR); // IRQ0-3=IRQ
21 ctrl_outw(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active. 21 __raw_writew(0x0aaa, INTC_ICR1); // IRQ0-3=IRQ-mode,Low-active.
22 plat_irq_setup_pins(IRQ_MODE_IRQ); 22 plat_irq_setup_pins(IRQ_MODE_IRQ);
23} 23}
24 24
diff --git a/arch/sh/boards/mach-ap325rxa/setup.c b/arch/sh/boards/mach-ap325rxa/setup.c
index 1f5fa5c44f6..27277cbdb63 100644
--- a/arch/sh/boards/mach-ap325rxa/setup.c
+++ b/arch/sh/boards/mach-ap325rxa/setup.c
@@ -159,21 +159,21 @@ static void ap320_wvga_power_on(void *board_data)
159 msleep(100); 159 msleep(100);
160 160
161 /* ASD AP-320/325 LCD ON */ 161 /* ASD AP-320/325 LCD ON */
162 ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG); 162 __raw_writew(FPGA_LCDREG_VAL, FPGA_LCDREG);
163 163
164 /* backlight */ 164 /* backlight */
165 gpio_set_value(GPIO_PTS3, 0); 165 gpio_set_value(GPIO_PTS3, 0);
166 ctrl_outw(0x100, FPGA_BKLREG); 166 __raw_writew(0x100, FPGA_BKLREG);
167} 167}
168 168
169static void ap320_wvga_power_off(void *board_data) 169static void ap320_wvga_power_off(void *board_data)
170{ 170{
171 /* backlight */ 171 /* backlight */
172 ctrl_outw(0, FPGA_BKLREG); 172 __raw_writew(0, FPGA_BKLREG);
173 gpio_set_value(GPIO_PTS3, 1); 173 gpio_set_value(GPIO_PTS3, 1);
174 174
175 /* ASD AP-320/325 LCD OFF */ 175 /* ASD AP-320/325 LCD OFF */
176 ctrl_outw(0, FPGA_LCDREG); 176 __raw_writew(0, FPGA_LCDREG);
177} 177}
178 178
179static struct sh_mobile_lcdc_info lcdc_info = { 179static struct sh_mobile_lcdc_info lcdc_info = {
@@ -595,7 +595,7 @@ static int __init ap325rxa_devices_setup(void)
595 gpio_request(GPIO_PTZ4, NULL); 595 gpio_request(GPIO_PTZ4, NULL);
596 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */ 596 gpio_direction_output(GPIO_PTZ4, 0); /* SADDR */
597 597
598 ctrl_outw(ctrl_inw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB); 598 __raw_writew(__raw_readw(PORT_MSELCRB) & ~0x0001, PORT_MSELCRB);
599 599
600 /* FLCTL */ 600 /* FLCTL */
601 gpio_request(GPIO_FN_FCE, NULL); 601 gpio_request(GPIO_FN_FCE, NULL);
@@ -613,9 +613,9 @@ static int __init ap325rxa_devices_setup(void)
613 gpio_request(GPIO_FN_FWE, NULL); 613 gpio_request(GPIO_FN_FWE, NULL);
614 gpio_request(GPIO_FN_FRB, NULL); 614 gpio_request(GPIO_FN_FRB, NULL);
615 615
616 ctrl_outw(0, PORT_HIZCRC); 616 __raw_writew(0, PORT_HIZCRC);
617 ctrl_outw(0xFFFF, PORT_DRVCRA); 617 __raw_writew(0xFFFF, PORT_DRVCRA);
618 ctrl_outw(0xFFFF, PORT_DRVCRB); 618 __raw_writew(0xFFFF, PORT_DRVCRB);
619 619
620 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20); 620 platform_resource_setup_memory(&ceu_device, "ceu", 4 << 20);
621 621
diff --git a/arch/sh/boards/mach-cayman/irq.c b/arch/sh/boards/mach-cayman/irq.c
index 33f77085631..1394b078db3 100644
--- a/arch/sh/boards/mach-cayman/irq.c
+++ b/arch/sh/boards/mach-cayman/irq.c
@@ -66,9 +66,9 @@ static void enable_cayman_irq(unsigned int irq)
66 reg = EPLD_MASK_BASE + ((irq / 8) << 2); 66 reg = EPLD_MASK_BASE + ((irq / 8) << 2);
67 bit = 1<<(irq % 8); 67 bit = 1<<(irq % 8);
68 local_irq_save(flags); 68 local_irq_save(flags);
69 mask = ctrl_inl(reg); 69 mask = __raw_readl(reg);
70 mask |= bit; 70 mask |= bit;
71 ctrl_outl(mask, reg); 71 __raw_writel(mask, reg);
72 local_irq_restore(flags); 72 local_irq_restore(flags);
73} 73}
74 74
@@ -83,9 +83,9 @@ void disable_cayman_irq(unsigned int irq)
83 reg = EPLD_MASK_BASE + ((irq / 8) << 2); 83 reg = EPLD_MASK_BASE + ((irq / 8) << 2);
84 bit = 1<<(irq % 8); 84 bit = 1<<(irq % 8);
85 local_irq_save(flags); 85 local_irq_save(flags);
86 mask = ctrl_inl(reg); 86 mask = __raw_readl(reg);
87 mask &= ~bit; 87 mask &= ~bit;
88 ctrl_outl(mask, reg); 88 __raw_writel(mask, reg);
89 local_irq_restore(flags); 89 local_irq_restore(flags);
90} 90}
91 91
@@ -109,8 +109,8 @@ int cayman_irq_demux(int evt)
109 unsigned long status; 109 unsigned long status;
110 int i; 110 int i;
111 111
112 status = ctrl_inl(EPLD_STATUS_BASE) & 112 status = __raw_readl(EPLD_STATUS_BASE) &
113 ctrl_inl(EPLD_MASK_BASE) & 0xff; 113 __raw_readl(EPLD_MASK_BASE) & 0xff;
114 if (status == 0) { 114 if (status == 0) {
115 irq = -1; 115 irq = -1;
116 } else { 116 } else {
@@ -126,8 +126,8 @@ int cayman_irq_demux(int evt)
126 unsigned long status; 126 unsigned long status;
127 int i; 127 int i;
128 128
129 status = ctrl_inl(EPLD_STATUS_BASE + 3 * sizeof(u32)) & 129 status = __raw_readl(EPLD_STATUS_BASE + 3 * sizeof(u32)) &
130 ctrl_inl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff; 130 __raw_readl(EPLD_MASK_BASE + 3 * sizeof(u32)) & 0xff;
131 if (status == 0) { 131 if (status == 0) {
132 irq = -1; 132 irq = -1;
133 } else { 133 } else {
diff --git a/arch/sh/boards/mach-dreamcast/rtc.c b/arch/sh/boards/mach-dreamcast/rtc.c
index a7433685798..061d65714fc 100644
--- a/arch/sh/boards/mach-dreamcast/rtc.c
+++ b/arch/sh/boards/mach-dreamcast/rtc.c
@@ -35,11 +35,11 @@ static void aica_rtc_gettimeofday(struct timespec *ts)
35 unsigned long val1, val2; 35 unsigned long val1, val2;
36 36
37 do { 37 do {
38 val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | 38 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
39 (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); 39 (__raw_readl(AICA_RTC_SECS_L) & 0xffff);
40 40
41 val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | 41 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
42 (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); 42 (__raw_readl(AICA_RTC_SECS_L) & 0xffff);
43 } while (val1 != val2); 43 } while (val1 != val2);
44 44
45 ts->tv_sec = val1 - TWENTY_YEARS; 45 ts->tv_sec = val1 - TWENTY_YEARS;
@@ -60,14 +60,14 @@ static int aica_rtc_settimeofday(const time_t secs)
60 unsigned long adj = secs + TWENTY_YEARS; 60 unsigned long adj = secs + TWENTY_YEARS;
61 61
62 do { 62 do {
63 ctrl_outl((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H); 63 __raw_writel((adj & 0xffff0000) >> 16, AICA_RTC_SECS_H);
64 ctrl_outl((adj & 0xffff), AICA_RTC_SECS_L); 64 __raw_writel((adj & 0xffff), AICA_RTC_SECS_L);
65 65
66 val1 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | 66 val1 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
67 (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); 67 (__raw_readl(AICA_RTC_SECS_L) & 0xffff);
68 68
69 val2 = ((ctrl_inl(AICA_RTC_SECS_H) & 0xffff) << 16) | 69 val2 = ((__raw_readl(AICA_RTC_SECS_H) & 0xffff) << 16) |
70 (ctrl_inl(AICA_RTC_SECS_L) & 0xffff); 70 (__raw_readl(AICA_RTC_SECS_L) & 0xffff);
71 } while (val1 != val2); 71 } while (val1 != val2);
72 72
73 return 0; 73 return 0;
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index a49cce16e78..1135c3b848f 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -696,13 +696,13 @@ static struct platform_device camera_devices[] = {
696#define FCLKBCR 0xa415000c 696#define FCLKBCR 0xa415000c
697static void fsimck_init(struct clk *clk) 697static void fsimck_init(struct clk *clk)
698{ 698{
699 u32 status = ctrl_inl(clk->enable_reg); 699 u32 status = __raw_readl(clk->enable_reg);
700 700
701 /* use external clock */ 701 /* use external clock */
702 status &= ~0x000000ff; 702 status &= ~0x000000ff;
703 status |= 0x00000080; 703 status |= 0x00000080;
704 704
705 ctrl_outl(status, clk->enable_reg); 705 __raw_writel(status, clk->enable_reg);
706} 706}
707 707
708static struct clk_ops fsimck_clk_ops = { 708static struct clk_ops fsimck_clk_ops = {
@@ -853,7 +853,7 @@ static int __init arch_setup(void)
853 gpio_direction_output(GPIO_PTG1, 0); 853 gpio_direction_output(GPIO_PTG1, 0);
854 gpio_direction_output(GPIO_PTG2, 0); 854 gpio_direction_output(GPIO_PTG2, 0);
855 gpio_direction_output(GPIO_PTG3, 0); 855 gpio_direction_output(GPIO_PTG3, 0);
856 ctrl_outw((ctrl_inw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA); 856 __raw_writew((__raw_readw(PORT_HIZA) & ~(0x1 << 1)) , PORT_HIZA);
857 857
858 /* enable SH-Eth */ 858 /* enable SH-Eth */
859 gpio_request(GPIO_PTA1, NULL); 859 gpio_request(GPIO_PTA1, NULL);
@@ -873,16 +873,16 @@ static int __init arch_setup(void)
873 gpio_request(GPIO_FN_LNKSTA, NULL); 873 gpio_request(GPIO_FN_LNKSTA, NULL);
874 874
875 /* enable USB */ 875 /* enable USB */
876 ctrl_outw(0x0000, 0xA4D80000); 876 __raw_writew(0x0000, 0xA4D80000);
877 ctrl_outw(0x0000, 0xA4D90000); 877 __raw_writew(0x0000, 0xA4D90000);
878 gpio_request(GPIO_PTB3, NULL); 878 gpio_request(GPIO_PTB3, NULL);
879 gpio_request(GPIO_PTB4, NULL); 879 gpio_request(GPIO_PTB4, NULL);
880 gpio_request(GPIO_PTB5, NULL); 880 gpio_request(GPIO_PTB5, NULL);
881 gpio_direction_input(GPIO_PTB3); 881 gpio_direction_input(GPIO_PTB3);
882 gpio_direction_output(GPIO_PTB4, 0); 882 gpio_direction_output(GPIO_PTB4, 0);
883 gpio_direction_output(GPIO_PTB5, 0); 883 gpio_direction_output(GPIO_PTB5, 0);
884 ctrl_outw(0x0600, 0xa40501d4); 884 __raw_writew(0x0600, 0xa40501d4);
885 ctrl_outw(0x0600, 0xa4050192); 885 __raw_writew(0x0600, 0xa4050192);
886 886
887 if (gpio_get_value(GPIO_PTB3)) { 887 if (gpio_get_value(GPIO_PTB3)) {
888 printk(KERN_INFO "USB1 function is selected\n"); 888 printk(KERN_INFO "USB1 function is selected\n");
@@ -923,7 +923,7 @@ static int __init arch_setup(void)
923 gpio_request(GPIO_FN_LCDVSYN, NULL); 923 gpio_request(GPIO_FN_LCDVSYN, NULL);
924 gpio_request(GPIO_FN_LCDDON, NULL); 924 gpio_request(GPIO_FN_LCDDON, NULL);
925 gpio_request(GPIO_FN_LCDLCLK, NULL); 925 gpio_request(GPIO_FN_LCDLCLK, NULL);
926 ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA); 926 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
927 927
928 gpio_request(GPIO_PTE6, NULL); 928 gpio_request(GPIO_PTE6, NULL);
929 gpio_request(GPIO_PTU1, NULL); 929 gpio_request(GPIO_PTU1, NULL);
@@ -935,7 +935,7 @@ static int __init arch_setup(void)
935 gpio_direction_output(GPIO_PTA2, 0); 935 gpio_direction_output(GPIO_PTA2, 0);
936 936
937 /* I/O buffer drive ability is high */ 937 /* I/O buffer drive ability is high */
938 ctrl_outw((ctrl_inw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA); 938 __raw_writew((__raw_readw(IODRIVEA) & ~0x00c0) | 0x0080 , IODRIVEA);
939 939
940 if (gpio_get_value(GPIO_PTE6)) { 940 if (gpio_get_value(GPIO_PTE6)) {
941 /* DVI */ 941 /* DVI */
@@ -1067,7 +1067,7 @@ static int __init arch_setup(void)
1067 gpio_direction_output(GPIO_PTB7, 0); 1067 gpio_direction_output(GPIO_PTB7, 0);
1068 1068
1069 /* I/O buffer drive ability is high for SDHI1 */ 1069 /* I/O buffer drive ability is high for SDHI1 */
1070 ctrl_outw((ctrl_inw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA); 1070 __raw_writew((__raw_readw(IODRIVEA) & ~0x3000) | 0x2000 , IODRIVEA);
1071#else 1071#else
1072 /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */ 1072 /* enable MSIOF0 on CN11 (needs DS2.4 set to OFF) */
1073 gpio_request(GPIO_FN_MSIOF0_TXD, NULL); 1073 gpio_request(GPIO_FN_MSIOF0_TXD, NULL);
diff --git a/arch/sh/boards/mach-highlander/irq-r7780mp.c b/arch/sh/boards/mach-highlander/irq-r7780mp.c
index 83c28bcd4d2..9893fd3a135 100644
--- a/arch/sh/boards/mach-highlander/irq-r7780mp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7780mp.c
@@ -64,7 +64,7 @@ static DECLARE_INTC_DESC(intc_desc, "r7780mp", vectors,
64 64
65unsigned char * __init highlander_plat_irq_setup(void) 65unsigned char * __init highlander_plat_irq_setup(void)
66{ 66{
67 if ((ctrl_inw(0xa4000700) & 0xf000) == 0x2000) { 67 if ((__raw_readw(0xa4000700) & 0xf000) == 0x2000) {
68 printk(KERN_INFO "Using r7780mp interrupt controller.\n"); 68 printk(KERN_INFO "Using r7780mp interrupt controller.\n");
69 register_intc_controller(&intc_desc); 69 register_intc_controller(&intc_desc);
70 return irl2irq; 70 return irl2irq;
diff --git a/arch/sh/boards/mach-highlander/irq-r7780rp.c b/arch/sh/boards/mach-highlander/irq-r7780rp.c
index b721e86b5af..0805b215145 100644
--- a/arch/sh/boards/mach-highlander/irq-r7780rp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7780rp.c
@@ -57,7 +57,7 @@ static DECLARE_INTC_DESC(intc_desc, "r7780rp", vectors,
57 57
58unsigned char * __init highlander_plat_irq_setup(void) 58unsigned char * __init highlander_plat_irq_setup(void)
59{ 59{
60 if (ctrl_inw(0xa5000600)) { 60 if (__raw_readw(0xa5000600)) {
61 printk(KERN_INFO "Using r7780rp interrupt controller.\n"); 61 printk(KERN_INFO "Using r7780rp interrupt controller.\n");
62 register_intc_controller(&intc_desc); 62 register_intc_controller(&intc_desc);
63 return irl2irq; 63 return irl2irq;
diff --git a/arch/sh/boards/mach-highlander/irq-r7785rp.c b/arch/sh/boards/mach-highlander/irq-r7785rp.c
index 3811b060a39..558b2486277 100644
--- a/arch/sh/boards/mach-highlander/irq-r7785rp.c
+++ b/arch/sh/boards/mach-highlander/irq-r7785rp.c
@@ -66,20 +66,20 @@ static DECLARE_INTC_DESC(intc_desc, "r7785rp", vectors,
66 66
67unsigned char * __init highlander_plat_irq_setup(void) 67unsigned char * __init highlander_plat_irq_setup(void)
68{ 68{
69 if ((ctrl_inw(0xa4000158) & 0xf000) != 0x1000) 69 if ((__raw_readw(0xa4000158) & 0xf000) != 0x1000)
70 return NULL; 70 return NULL;
71 71
72 printk(KERN_INFO "Using r7785rp interrupt controller.\n"); 72 printk(KERN_INFO "Using r7785rp interrupt controller.\n");
73 73
74 ctrl_outw(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */ 74 __raw_writew(0x0000, PA_IRLSSR1); /* FPGA IRLSSR1(CF_CD clear) */
75 75
76 /* Setup the FPGA IRL */ 76 /* Setup the FPGA IRL */
77 ctrl_outw(0x0000, PA_IRLPRA); /* FPGA IRLA */ 77 __raw_writew(0x0000, PA_IRLPRA); /* FPGA IRLA */
78 ctrl_outw(0xe598, PA_IRLPRB); /* FPGA IRLB */ 78 __raw_writew(0xe598, PA_IRLPRB); /* FPGA IRLB */
79 ctrl_outw(0x7060, PA_IRLPRC); /* FPGA IRLC */ 79 __raw_writew(0x7060, PA_IRLPRC); /* FPGA IRLC */
80 ctrl_outw(0x0000, PA_IRLPRD); /* FPGA IRLD */ 80 __raw_writew(0x0000, PA_IRLPRD); /* FPGA IRLD */
81 ctrl_outw(0x4321, PA_IRLPRE); /* FPGA IRLE */ 81 __raw_writew(0x4321, PA_IRLPRE); /* FPGA IRLE */
82 ctrl_outw(0xdcba, PA_IRLPRF); /* FPGA IRLF */ 82 __raw_writew(0xdcba, PA_IRLPRF); /* FPGA IRLF */
83 83
84 register_intc_controller(&intc_desc); 84 register_intc_controller(&intc_desc);
85 return irl2irq; 85 return irl2irq;
diff --git a/arch/sh/boards/mach-highlander/psw.c b/arch/sh/boards/mach-highlander/psw.c
index 37b1a2ee71a..522786318d3 100644
--- a/arch/sh/boards/mach-highlander/psw.c
+++ b/arch/sh/boards/mach-highlander/psw.c
@@ -24,7 +24,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
24 unsigned int l, mask; 24 unsigned int l, mask;
25 int ret = 0; 25 int ret = 0;
26 26
27 l = ctrl_inw(PA_DBSW); 27 l = __raw_readw(PA_DBSW);
28 28
29 /* Nothing to do if there's no state change */ 29 /* Nothing to do if there's no state change */
30 if (psw->state) { 30 if (psw->state) {
@@ -45,7 +45,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
45out: 45out:
46 /* Clear the switch IRQs */ 46 /* Clear the switch IRQs */
47 l |= (0x7 << 12); 47 l |= (0x7 << 12);
48 ctrl_outw(l, PA_DBSW); 48 __raw_writew(l, PA_DBSW);
49 49
50 return IRQ_RETVAL(ret); 50 return IRQ_RETVAL(ret);
51} 51}
diff --git a/arch/sh/boards/mach-highlander/setup.c b/arch/sh/boards/mach-highlander/setup.c
index f663c14d888..affd66747ba 100644
--- a/arch/sh/boards/mach-highlander/setup.c
+++ b/arch/sh/boards/mach-highlander/setup.c
@@ -311,13 +311,13 @@ device_initcall(r7780rp_devices_setup);
311 */ 311 */
312static int ivdr_clk_enable(struct clk *clk) 312static int ivdr_clk_enable(struct clk *clk)
313{ 313{
314 ctrl_outw(ctrl_inw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL); 314 __raw_writew(__raw_readw(PA_IVDRCTL) | (1 << IVDR_CK_ON), PA_IVDRCTL);
315 return 0; 315 return 0;
316} 316}
317 317
318static void ivdr_clk_disable(struct clk *clk) 318static void ivdr_clk_disable(struct clk *clk)
319{ 319{
320 ctrl_outw(ctrl_inw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL); 320 __raw_writew(__raw_readw(PA_IVDRCTL) & ~(1 << IVDR_CK_ON), PA_IVDRCTL);
321} 321}
322 322
323static struct clk_ops ivdr_clk_ops = { 323static struct clk_ops ivdr_clk_ops = {
@@ -337,7 +337,7 @@ static struct clk *r7780rp_clocks[] = {
337static void r7780rp_power_off(void) 337static void r7780rp_power_off(void)
338{ 338{
339 if (mach_is_r7780mp() || mach_is_r7785rp()) 339 if (mach_is_r7780mp() || mach_is_r7785rp())
340 ctrl_outw(0x0001, PA_POFF); 340 __raw_writew(0x0001, PA_POFF);
341} 341}
342 342
343/* 343/*
@@ -345,7 +345,7 @@ static void r7780rp_power_off(void)
345 */ 345 */
346static void __init highlander_setup(char **cmdline_p) 346static void __init highlander_setup(char **cmdline_p)
347{ 347{
348 u16 ver = ctrl_inw(PA_VERREG); 348 u16 ver = __raw_readw(PA_VERREG);
349 int i; 349 int i;
350 350
351 printk(KERN_INFO "Renesas Solutions Highlander %s support.\n", 351 printk(KERN_INFO "Renesas Solutions Highlander %s support.\n",
@@ -370,12 +370,12 @@ static void __init highlander_setup(char **cmdline_p)
370 clk_enable(clk); 370 clk_enable(clk);
371 } 371 }
372 372
373 ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */ 373 __raw_writew(0x0000, PA_OBLED); /* Clear LED. */
374 374
375 if (mach_is_r7780rp()) 375 if (mach_is_r7780rp())
376 ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */ 376 __raw_writew(0x0001, PA_SDPOW); /* SD Power ON */
377 377
378 ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */ 378 __raw_writew(__raw_readw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */
379 379
380 pm_power_off = r7780rp_power_off; 380 pm_power_off = r7780rp_power_off;
381} 381}
diff --git a/arch/sh/boards/mach-hp6xx/hp6xx_apm.c b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
index e85212faf40..b49535c0ddd 100644
--- a/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
+++ b/arch/sh/boards/mach-hp6xx/hp6xx_apm.c
@@ -53,7 +53,7 @@ static void hp6x0_apm_get_power_status(struct apm_power_info *info)
53 info->ac_line_status = (battery > HP680_BATTERY_AC_ON) ? 53 info->ac_line_status = (battery > HP680_BATTERY_AC_ON) ?
54 APM_AC_ONLINE : APM_AC_OFFLINE; 54 APM_AC_ONLINE : APM_AC_OFFLINE;
55 55
56 pgdr = ctrl_inb(PGDR); 56 pgdr = __raw_readb(PGDR);
57 if (pgdr & PGDR_MAIN_BATTERY_OUT) { 57 if (pgdr & PGDR_MAIN_BATTERY_OUT) {
58 info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT; 58 info->battery_status = APM_BATTERY_STATUS_NOT_PRESENT;
59 info->battery_flag = 0x80; 59 info->battery_flag = 0x80;
diff --git a/arch/sh/boards/mach-hp6xx/pm.c b/arch/sh/boards/mach-hp6xx/pm.c
index d936c1af762..4499a3749d4 100644
--- a/arch/sh/boards/mach-hp6xx/pm.c
+++ b/arch/sh/boards/mach-hp6xx/pm.c
@@ -53,17 +53,17 @@ static void pm_enter(void)
53 sh_wdt_write_cnt(0); 53 sh_wdt_write_cnt(0);
54 54
55 /* disable PLL1 */ 55 /* disable PLL1 */
56 frqcr = ctrl_inw(FRQCR); 56 frqcr = __raw_readw(FRQCR);
57 frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY); 57 frqcr &= ~(FRQCR_PLLEN | FRQCR_PSTBY);
58 ctrl_outw(frqcr, FRQCR); 58 __raw_writew(frqcr, FRQCR);
59 59
60 /* enable standby */ 60 /* enable standby */
61 stbcr = ctrl_inb(STBCR); 61 stbcr = __raw_readb(STBCR);
62 ctrl_outb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR); 62 __raw_writeb(stbcr | STBCR_STBY | STBCR_MSTP2, STBCR);
63 63
64 /* set self-refresh */ 64 /* set self-refresh */
65 mcr = ctrl_inw(MCR); 65 mcr = __raw_readw(MCR);
66 ctrl_outw(mcr & ~MCR_RFSH, MCR); 66 __raw_writew(mcr & ~MCR_RFSH, MCR);
67 67
68 /* set interrupt handler */ 68 /* set interrupt handler */
69 asm volatile("stc vbr, %0" : "=r" (vbr_old)); 69 asm volatile("stc vbr, %0" : "=r" (vbr_old));
@@ -73,8 +73,8 @@ static void pm_enter(void)
73 &wakeup_start, &wakeup_end - &wakeup_start); 73 &wakeup_start, &wakeup_end - &wakeup_start);
74 asm volatile("ldc %0, vbr" : : "r" (vbr_new)); 74 asm volatile("ldc %0, vbr" : : "r" (vbr_new));
75 75
76 ctrl_outw(0, RTCNT); 76 __raw_writew(0, RTCNT);
77 ctrl_outw(mcr | MCR_RFSH | MCR_RMODE, MCR); 77 __raw_writew(mcr | MCR_RFSH | MCR_RMODE, MCR);
78 78
79 cpu_sleep(); 79 cpu_sleep();
80 80
@@ -83,14 +83,14 @@ static void pm_enter(void)
83 free_page(vbr_new); 83 free_page(vbr_new);
84 84
85 /* enable PLL1 */ 85 /* enable PLL1 */
86 frqcr = ctrl_inw(FRQCR); 86 frqcr = __raw_readw(FRQCR);
87 frqcr |= FRQCR_PSTBY; 87 frqcr |= FRQCR_PSTBY;
88 ctrl_outw(frqcr, FRQCR); 88 __raw_writew(frqcr, FRQCR);
89 udelay(50); 89 udelay(50);
90 frqcr |= FRQCR_PLLEN; 90 frqcr |= FRQCR_PLLEN;
91 ctrl_outw(frqcr, FRQCR); 91 __raw_writew(frqcr, FRQCR);
92 92
93 ctrl_outb(stbcr, STBCR); 93 __raw_writeb(stbcr, STBCR);
94 94
95 clear_bl_bit(); 95 clear_bl_bit();
96} 96}
@@ -115,21 +115,21 @@ static int hp6x0_pm_enter(suspend_state_t state)
115 outw(hd64461_stbcr, HD64461_STBCR); 115 outw(hd64461_stbcr, HD64461_STBCR);
116#endif 116#endif
117 117
118 ctrl_outb(0x1f, DACR); 118 __raw_writeb(0x1f, DACR);
119 119
120 stbcr = ctrl_inb(STBCR); 120 stbcr = __raw_readb(STBCR);
121 ctrl_outb(0x01, STBCR); 121 __raw_writeb(0x01, STBCR);
122 122
123 stbcr2 = ctrl_inb(STBCR2); 123 stbcr2 = __raw_readb(STBCR2);
124 ctrl_outb(0x7f , STBCR2); 124 __raw_writeb(0x7f , STBCR2);
125 125
126 outw(0xf07f, HD64461_SCPUCR); 126 outw(0xf07f, HD64461_SCPUCR);
127 127
128 pm_enter(); 128 pm_enter();
129 129
130 outw(0, HD64461_SCPUCR); 130 outw(0, HD64461_SCPUCR);
131 ctrl_outb(stbcr, STBCR); 131 __raw_writeb(stbcr, STBCR);
132 ctrl_outb(stbcr2, STBCR2); 132 __raw_writeb(stbcr2, STBCR2);
133 133
134#ifdef CONFIG_HD64461_ENABLER 134#ifdef CONFIG_HD64461_ENABLER
135 hd64461_stbcr = inw(HD64461_STBCR); 135 hd64461_stbcr = inw(HD64461_STBCR);
diff --git a/arch/sh/boards/mach-hp6xx/setup.c b/arch/sh/boards/mach-hp6xx/setup.c
index e6dd5e96321..8c9add5f4cf 100644
--- a/arch/sh/boards/mach-hp6xx/setup.c
+++ b/arch/sh/boards/mach-hp6xx/setup.c
@@ -149,19 +149,19 @@ static void __init hp6xx_setup(char **cmdline_p)
149 149
150 sh_dac_output(0, DAC_SPEAKER_VOLUME); 150 sh_dac_output(0, DAC_SPEAKER_VOLUME);
151 sh_dac_disable(DAC_SPEAKER_VOLUME); 151 sh_dac_disable(DAC_SPEAKER_VOLUME);
152 v8 = ctrl_inb(DACR); 152 v8 = __raw_readb(DACR);
153 v8 &= ~DACR_DAE; 153 v8 &= ~DACR_DAE;
154 ctrl_outb(v8,DACR); 154 __raw_writeb(v8,DACR);
155 155
156 v8 = ctrl_inb(SCPDR); 156 v8 = __raw_readb(SCPDR);
157 v8 |= SCPDR_TS_SCAN_X | SCPDR_TS_SCAN_Y; 157 v8 |= SCPDR_TS_SCAN_X | SCPDR_TS_SCAN_Y;
158 v8 &= ~SCPDR_TS_SCAN_ENABLE; 158 v8 &= ~SCPDR_TS_SCAN_ENABLE;
159 ctrl_outb(v8, SCPDR); 159 __raw_writeb(v8, SCPDR);
160 160
161 v = ctrl_inw(SCPCR); 161 v = __raw_readw(SCPCR);
162 v &= ~SCPCR_TS_MASK; 162 v &= ~SCPCR_TS_MASK;
163 v |= SCPCR_TS_ENABLE; 163 v |= SCPCR_TS_ENABLE;
164 ctrl_outw(v, SCPCR); 164 __raw_writew(v, SCPCR);
165} 165}
166device_initcall(hp6xx_devices_setup); 166device_initcall(hp6xx_devices_setup);
167 167
diff --git a/arch/sh/boards/mach-kfr2r09/setup.c b/arch/sh/boards/mach-kfr2r09/setup.c
index 5d7b5d92475..ca9e82d77d0 100644
--- a/arch/sh/boards/mach-kfr2r09/setup.c
+++ b/arch/sh/boards/mach-kfr2r09/setup.c
@@ -282,7 +282,7 @@ static int camera_power(struct device *dev, int mode)
282 * use 1.8 V for VccQ_VIO 282 * use 1.8 V for VccQ_VIO
283 * use 2.85V for VccQ_SR 283 * use 2.85V for VccQ_SR
284 */ 284 */
285 ctrl_outw((ctrl_inw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB); 285 __raw_writew((__raw_readw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB);
286 286
287 /* reset clear */ 287 /* reset clear */
288 ret = gpio_request(GPIO_PTB4, NULL); 288 ret = gpio_request(GPIO_PTB4, NULL);
@@ -492,13 +492,13 @@ static int kfr2r09_usb0_gadget_setup(void)
492 if (kfr2r09_usb0_gadget_i2c_setup() != 0) 492 if (kfr2r09_usb0_gadget_i2c_setup() != 0)
493 return -ENODEV; /* unable to configure using i2c */ 493 return -ENODEV; /* unable to configure using i2c */
494 494
495 ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); 495 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
496 gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */ 496 gpio_request(GPIO_FN_PDSTATUS, NULL); /* R-standby disables USB clock */
497 gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */ 497 gpio_request(GPIO_PTV6, NULL); /* USBCLK_ON */
498 gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */ 498 gpio_direction_output(GPIO_PTV6, 1); /* USBCLK_ON = H */
499 msleep(20); /* wait 20ms to let the clock settle */ 499 msleep(20); /* wait 20ms to let the clock settle */
500 clk_enable(clk_get(NULL, "usb0")); 500 clk_enable(clk_get(NULL, "usb0"));
501 ctrl_outw(0x0600, 0xa40501d4); 501 __raw_writew(0x0600, 0xa40501d4);
502 502
503 return 0; 503 return 0;
504} 504}
@@ -526,12 +526,12 @@ static int __init kfr2r09_devices_setup(void)
526 gpio_direction_output(GPIO_PTG3, 1); /* HPON_ON = H */ 526 gpio_direction_output(GPIO_PTG3, 1); /* HPON_ON = H */
527 527
528 /* setup NOR flash at CS0 */ 528 /* setup NOR flash at CS0 */
529 ctrl_outl(0x36db0400, BSC_CS0BCR); 529 __raw_writel(0x36db0400, BSC_CS0BCR);
530 ctrl_outl(0x00000500, BSC_CS0WCR); 530 __raw_writel(0x00000500, BSC_CS0WCR);
531 531
532 /* setup NAND flash at CS4 */ 532 /* setup NAND flash at CS4 */
533 ctrl_outl(0x36db0400, BSC_CS4BCR); 533 __raw_writel(0x36db0400, BSC_CS4BCR);
534 ctrl_outl(0x00000500, BSC_CS4WCR); 534 __raw_writel(0x00000500, BSC_CS4WCR);
535 535
536 /* setup KEYSC pins */ 536 /* setup KEYSC pins */
537 gpio_request(GPIO_FN_KEYOUT0, NULL); 537 gpio_request(GPIO_FN_KEYOUT0, NULL);
diff --git a/arch/sh/boards/mach-landisk/gio.c b/arch/sh/boards/mach-landisk/gio.c
index 52801318819..01e6abb769b 100644
--- a/arch/sh/boards/mach-landisk/gio.c
+++ b/arch/sh/boards/mach-landisk/gio.c
@@ -76,39 +76,39 @@ static long gio_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
76 break; 76 break;
77 77
78 case GIODRV_IOCSGIODATA1: /* write byte */ 78 case GIODRV_IOCSGIODATA1: /* write byte */
79 ctrl_outb((unsigned char)(0x0ff & data), addr); 79 __raw_writeb((unsigned char)(0x0ff & data), addr);
80 break; 80 break;
81 81
82 case GIODRV_IOCSGIODATA2: /* write word */ 82 case GIODRV_IOCSGIODATA2: /* write word */
83 if (addr & 0x01) { 83 if (addr & 0x01) {
84 return -EFAULT; 84 return -EFAULT;
85 } 85 }
86 ctrl_outw((unsigned short int)(0x0ffff & data), addr); 86 __raw_writew((unsigned short int)(0x0ffff & data), addr);
87 break; 87 break;
88 88
89 case GIODRV_IOCSGIODATA4: /* write long */ 89 case GIODRV_IOCSGIODATA4: /* write long */
90 if (addr & 0x03) { 90 if (addr & 0x03) {
91 return -EFAULT; 91 return -EFAULT;
92 } 92 }
93 ctrl_outl(data, addr); 93 __raw_writel(data, addr);
94 break; 94 break;
95 95
96 case GIODRV_IOCGGIODATA1: /* read byte */ 96 case GIODRV_IOCGGIODATA1: /* read byte */
97 data = ctrl_inb(addr); 97 data = __raw_readb(addr);
98 break; 98 break;
99 99
100 case GIODRV_IOCGGIODATA2: /* read word */ 100 case GIODRV_IOCGGIODATA2: /* read word */
101 if (addr & 0x01) { 101 if (addr & 0x01) {
102 return -EFAULT; 102 return -EFAULT;
103 } 103 }
104 data = ctrl_inw(addr); 104 data = __raw_readw(addr);
105 break; 105 break;
106 106
107 case GIODRV_IOCGGIODATA4: /* read long */ 107 case GIODRV_IOCGGIODATA4: /* read long */
108 if (addr & 0x03) { 108 if (addr & 0x03) {
109 return -EFAULT; 109 return -EFAULT;
110 } 110 }
111 data = ctrl_inl(addr); 111 data = __raw_readl(addr);
112 break; 112 break;
113 default: 113 default:
114 return -EFAULT; 114 return -EFAULT;
diff --git a/arch/sh/boards/mach-landisk/irq.c b/arch/sh/boards/mach-landisk/irq.c
index 7b284cde1f5..96f38a4187d 100644
--- a/arch/sh/boards/mach-landisk/irq.c
+++ b/arch/sh/boards/mach-landisk/irq.c
@@ -22,14 +22,14 @@ static void disable_landisk_irq(unsigned int irq)
22{ 22{
23 unsigned char mask = 0xff ^ (0x01 << (irq - 5)); 23 unsigned char mask = 0xff ^ (0x01 << (irq - 5));
24 24
25 ctrl_outb(ctrl_inb(PA_IMASK) & mask, PA_IMASK); 25 __raw_writeb(__raw_readb(PA_IMASK) & mask, PA_IMASK);
26} 26}
27 27
28static void enable_landisk_irq(unsigned int irq) 28static void enable_landisk_irq(unsigned int irq)
29{ 29{
30 unsigned char value = (0x01 << (irq - 5)); 30 unsigned char value = (0x01 << (irq - 5));
31 31
32 ctrl_outb(ctrl_inb(PA_IMASK) | value, PA_IMASK); 32 __raw_writeb(__raw_readb(PA_IMASK) | value, PA_IMASK);
33} 33}
34 34
35static struct irq_chip landisk_irq_chip __read_mostly = { 35static struct irq_chip landisk_irq_chip __read_mostly = {
@@ -52,5 +52,5 @@ void __init init_landisk_IRQ(void)
52 handle_level_irq, "level"); 52 handle_level_irq, "level");
53 enable_landisk_irq(i); 53 enable_landisk_irq(i);
54 } 54 }
55 ctrl_outb(0x00, PA_PWRINT_CLR); 55 __raw_writeb(0x00, PA_PWRINT_CLR);
56} 56}
diff --git a/arch/sh/boards/mach-landisk/psw.c b/arch/sh/boards/mach-landisk/psw.c
index e6b0efa098d..bef83522f95 100644
--- a/arch/sh/boards/mach-landisk/psw.c
+++ b/arch/sh/boards/mach-landisk/psw.c
@@ -25,7 +25,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
25 unsigned int sw_value; 25 unsigned int sw_value;
26 int ret = 0; 26 int ret = 0;
27 27
28 sw_value = (0x0ff & (~ctrl_inb(PA_STATUS))); 28 sw_value = (0x0ff & (~__raw_readb(PA_STATUS)));
29 29
30 /* Nothing to do if there's no state change */ 30 /* Nothing to do if there's no state change */
31 if (psw->state) { 31 if (psw->state) {
@@ -42,7 +42,7 @@ static irqreturn_t psw_irq_handler(int irq, void *arg)
42 42
43out: 43out:
44 /* Clear the switch IRQs */ 44 /* Clear the switch IRQs */
45 ctrl_outb(0x00, PA_PWRINT_CLR); 45 __raw_writeb(0x00, PA_PWRINT_CLR);
46 46
47 return IRQ_RETVAL(ret); 47 return IRQ_RETVAL(ret);
48} 48}
diff --git a/arch/sh/boards/mach-landisk/setup.c b/arch/sh/boards/mach-landisk/setup.c
index 2d09d4d34f8..50337acc18c 100644
--- a/arch/sh/boards/mach-landisk/setup.c
+++ b/arch/sh/boards/mach-landisk/setup.c
@@ -25,7 +25,7 @@ void init_landisk_IRQ(void);
25 25
26static void landisk_power_off(void) 26static void landisk_power_off(void)
27{ 27{
28 ctrl_outb(0x01, PA_SHUTDOWN); 28 __raw_writeb(0x01, PA_SHUTDOWN);
29} 29}
30 30
31static struct resource cf_ide_resources[3]; 31static struct resource cf_ide_resources[3];
@@ -88,7 +88,7 @@ __initcall(landisk_devices_setup);
88static void __init landisk_setup(char **cmdline_p) 88static void __init landisk_setup(char **cmdline_p)
89{ 89{
90 /* LED ON */ 90 /* LED ON */
91 ctrl_outb(ctrl_inb(PA_LED) | 0x03, PA_LED); 91 __raw_writeb(__raw_readb(PA_LED) | 0x03, PA_LED);
92 92
93 printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n"); 93 printk(KERN_INFO "I-O DATA DEVICE, INC. \"LANDISK Series\" support.\n");
94 pm_power_off = landisk_power_off; 94 pm_power_off = landisk_power_off;
diff --git a/arch/sh/boards/mach-microdev/io.c b/arch/sh/boards/mach-microdev/io.c
index 52dd748211c..2960c659020 100644
--- a/arch/sh/boards/mach-microdev/io.c
+++ b/arch/sh/boards/mach-microdev/io.c
@@ -141,10 +141,10 @@ static inline void delay(void)
141#if defined(CONFIG_PCI) 141#if defined(CONFIG_PCI)
142 /* System board present, just make a dummy SRAM access. (CS0 will be 142 /* System board present, just make a dummy SRAM access. (CS0 will be
143 mapped to PCI memory, probably good to avoid it.) */ 143 mapped to PCI memory, probably good to avoid it.) */
144 ctrl_inw(0xa6800000); 144 __raw_readw(0xa6800000);
145#else 145#else
146 /* CS0 will be mapped to flash, ROM etc so safe to access it. */ 146 /* CS0 will be mapped to flash, ROM etc so safe to access it. */
147 ctrl_inw(0xa0000000); 147 __raw_readw(0xa0000000);
148#endif 148#endif
149} 149}
150 150
diff --git a/arch/sh/boards/mach-microdev/irq.c b/arch/sh/boards/mach-microdev/irq.c
index b551963579c..a26d16669aa 100644
--- a/arch/sh/boards/mach-microdev/irq.c
+++ b/arch/sh/boards/mach-microdev/irq.c
@@ -88,7 +88,7 @@ static void disable_microdev_irq(unsigned int irq)
88 fpgaIrq = fpgaIrqTable[irq].fpgaIrq; 88 fpgaIrq = fpgaIrqTable[irq].fpgaIrq;
89 89
90 /* disable interrupts on the FPGA INTC register */ 90 /* disable interrupts on the FPGA INTC register */
91 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG); 91 __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTDSB_REG);
92} 92}
93 93
94static void enable_microdev_irq(unsigned int irq) 94static void enable_microdev_irq(unsigned int irq)
@@ -107,13 +107,13 @@ static void enable_microdev_irq(unsigned int irq)
107 priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq); 107 priorityReg = MICRODEV_FPGA_INTPRI_REG(fpgaIrq);
108 108
109 /* set priority for the interrupt */ 109 /* set priority for the interrupt */
110 priorities = ctrl_inl(priorityReg); 110 priorities = __raw_readl(priorityReg);
111 priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq); 111 priorities &= ~MICRODEV_FPGA_INTPRI_MASK(fpgaIrq);
112 priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri); 112 priorities |= MICRODEV_FPGA_INTPRI_LEVEL(fpgaIrq, pri);
113 ctrl_outl(priorities, priorityReg); 113 __raw_writel(priorities, priorityReg);
114 114
115 /* enable interrupts on the FPGA INTC register */ 115 /* enable interrupts on the FPGA INTC register */
116 ctrl_outl(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG); 116 __raw_writel(MICRODEV_FPGA_INTC_MASK(fpgaIrq), MICRODEV_FPGA_INTENB_REG);
117} 117}
118 118
119/* This function sets the desired irq handler to be a MicroDev type */ 119/* This function sets the desired irq handler to be a MicroDev type */
@@ -134,7 +134,7 @@ extern void __init init_microdev_irq(void)
134 int i; 134 int i;
135 135
136 /* disable interrupts on the FPGA INTC register */ 136 /* disable interrupts on the FPGA INTC register */
137 ctrl_outl(~0ul, MICRODEV_FPGA_INTDSB_REG); 137 __raw_writel(~0ul, MICRODEV_FPGA_INTDSB_REG);
138 138
139 for (i = 0; i < NUM_EXTERNAL_IRQS; i++) 139 for (i = 0; i < NUM_EXTERNAL_IRQS; i++)
140 make_microdev_irq(i); 140 make_microdev_irq(i);
diff --git a/arch/sh/boards/mach-migor/setup.c b/arch/sh/boards/mach-migor/setup.c
index 507c77be476..ed2eeeb390a 100644
--- a/arch/sh/boards/mach-migor/setup.c
+++ b/arch/sh/boards/mach-migor/setup.c
@@ -516,8 +516,8 @@ static int __init migor_devices_setup(void)
516 516
517 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */ 517 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
518 gpio_request(GPIO_FN_IRQ0, NULL); 518 gpio_request(GPIO_FN_IRQ0, NULL);
519 ctrl_outl(0x00003400, BSC_CS4BCR); 519 __raw_writel(0x00003400, BSC_CS4BCR);
520 ctrl_outl(0x00110080, BSC_CS4WCR); 520 __raw_writel(0x00110080, BSC_CS4WCR);
521 521
522 /* KEYSC */ 522 /* KEYSC */
523 gpio_request(GPIO_FN_KEYOUT0, NULL); 523 gpio_request(GPIO_FN_KEYOUT0, NULL);
@@ -533,7 +533,7 @@ static int __init migor_devices_setup(void)
533 533
534 /* NAND Flash */ 534 /* NAND Flash */
535 gpio_request(GPIO_FN_CS6A_CE2B, NULL); 535 gpio_request(GPIO_FN_CS6A_CE2B, NULL);
536 ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR); 536 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
537 gpio_request(GPIO_PTA1, NULL); 537 gpio_request(GPIO_PTA1, NULL);
538 gpio_direction_input(GPIO_PTA1); 538 gpio_direction_input(GPIO_PTA1);
539 539
@@ -627,7 +627,7 @@ static int __init migor_devices_setup(void)
627#else 627#else
628 gpio_direction_output(GPIO_PTT0, 1); 628 gpio_direction_output(GPIO_PTT0, 1);
629#endif 629#endif
630 ctrl_outw(ctrl_inw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */ 630 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
631 631
632 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20); 632 platform_resource_setup_memory(&migor_ceu_device, "ceu", 4 << 20);
633 633
diff --git a/arch/sh/boards/mach-r2d/irq.c b/arch/sh/boards/mach-r2d/irq.c
index 78d7b27c80d..574f009c3c3 100644
--- a/arch/sh/boards/mach-r2d/irq.c
+++ b/arch/sh/boards/mach-r2d/irq.c
@@ -129,7 +129,7 @@ void __init init_rts7751r2d_IRQ(void)
129{ 129{
130 struct intc_desc *d; 130 struct intc_desc *d;
131 131
132 switch (ctrl_inw(PA_VERREG) & 0xf0) { 132 switch (__raw_readw(PA_VERREG) & 0xf0) {
133#ifdef CONFIG_RTS7751R2D_PLUS 133#ifdef CONFIG_RTS7751R2D_PLUS
134 case 0x10: 134 case 0x10:
135 printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n"); 135 printk(KERN_INFO "Using R2D-PLUS interrupt controller.\n");
@@ -147,7 +147,7 @@ void __init init_rts7751r2d_IRQ(void)
147#endif 147#endif
148 default: 148 default:
149 printk(KERN_INFO "Unknown R2D interrupt controller 0x%04x\n", 149 printk(KERN_INFO "Unknown R2D interrupt controller 0x%04x\n",
150 ctrl_inw(PA_VERREG)); 150 __raw_readw(PA_VERREG));
151 return; 151 return;
152 } 152 }
153 153
diff --git a/arch/sh/boards/mach-r2d/setup.c b/arch/sh/boards/mach-r2d/setup.c
index a625ecb93e4..b84df6a3a93 100644
--- a/arch/sh/boards/mach-r2d/setup.c
+++ b/arch/sh/boards/mach-r2d/setup.c
@@ -70,7 +70,7 @@ static struct spi_board_info spi_bus[] = {
70static void r2d_chip_select(struct sh_spi_info *spi, int cs, int state) 70static void r2d_chip_select(struct sh_spi_info *spi, int cs, int state)
71{ 71{
72 BUG_ON(cs != 0); /* Single Epson RTC-9701JE attached on CS0 */ 72 BUG_ON(cs != 0); /* Single Epson RTC-9701JE attached on CS0 */
73 ctrl_outw(state == BITBANG_CS_ACTIVE, PA_RTCCE); 73 __raw_writew(state == BITBANG_CS_ACTIVE, PA_RTCCE);
74} 74}
75 75
76static struct sh_spi_info spi_info = { 76static struct sh_spi_info spi_info = {
@@ -262,7 +262,7 @@ __initcall(rts7751r2d_devices_setup);
262 262
263static void rts7751r2d_power_off(void) 263static void rts7751r2d_power_off(void)
264{ 264{
265 ctrl_outw(0x0001, PA_POWOFF); 265 __raw_writew(0x0001, PA_POWOFF);
266} 266}
267 267
268/* 268/*
@@ -271,14 +271,14 @@ static void rts7751r2d_power_off(void)
271static void __init rts7751r2d_setup(char **cmdline_p) 271static void __init rts7751r2d_setup(char **cmdline_p)
272{ 272{
273 void __iomem *sm501_reg; 273 void __iomem *sm501_reg;
274 u16 ver = ctrl_inw(PA_VERREG); 274 u16 ver = __raw_readw(PA_VERREG);
275 275
276 printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n"); 276 printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n");
277 277
278 printk(KERN_INFO "FPGA version:%d (revision:%d)\n", 278 printk(KERN_INFO "FPGA version:%d (revision:%d)\n",
279 (ver >> 4) & 0xf, ver & 0xf); 279 (ver >> 4) & 0xf, ver & 0xf);
280 280
281 ctrl_outw(0x0000, PA_OUTPORT); 281 __raw_writew(0x0000, PA_OUTPORT);
282 pm_power_off = rts7751r2d_power_off; 282 pm_power_off = rts7751r2d_power_off;
283 283
284 /* sm501 dram configuration: 284 /* sm501 dram configuration:
diff --git a/arch/sh/boards/mach-rsk/devices-rsk7203.c b/arch/sh/boards/mach-rsk/devices-rsk7203.c
index c37617e6322..4fa08ba1025 100644
--- a/arch/sh/boards/mach-rsk/devices-rsk7203.c
+++ b/arch/sh/boards/mach-rsk/devices-rsk7203.c
@@ -96,7 +96,7 @@ static int __init rsk7203_devices_setup(void)
96 gpio_request(GPIO_FN_RXD0, NULL); 96 gpio_request(GPIO_FN_RXD0, NULL);
97 97
98 /* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */ 98 /* Setup LAN9118: CS1 in 16-bit Big Endian Mode, IRQ0 at Port B */
99 ctrl_outl(0x36db0400, 0xfffc0008); /* CS1BCR */ 99 __raw_writel(0x36db0400, 0xfffc0008); /* CS1BCR */
100 gpio_request(GPIO_FN_IRQ0_PB, NULL); 100 gpio_request(GPIO_FN_IRQ0_PB, NULL);
101 101
102 return platform_add_devices(rsk7203_devices, 102 return platform_add_devices(rsk7203_devices,
diff --git a/arch/sh/boards/mach-sdk7780/irq.c b/arch/sh/boards/mach-sdk7780/irq.c
index 855558163c5..e5f7564f251 100644
--- a/arch/sh/boards/mach-sdk7780/irq.c
+++ b/arch/sh/boards/mach-sdk7780/irq.c
@@ -37,9 +37,9 @@ void __init init_sdk7780_IRQ(void)
37{ 37{
38 printk(KERN_INFO "Using SDK7780 interrupt controller.\n"); 38 printk(KERN_INFO "Using SDK7780 interrupt controller.\n");
39 39
40 ctrl_outw(0xFFFF, FPGA_IRQ0MR); 40 __raw_writew(0xFFFF, FPGA_IRQ0MR);
41 /* Setup IRL 0-3 */ 41 /* Setup IRL 0-3 */
42 ctrl_outw(0x0003, FPGA_IMSR); 42 __raw_writew(0x0003, FPGA_IMSR);
43 plat_irq_setup_pins(IRQ_MODE_IRL3210); 43 plat_irq_setup_pins(IRQ_MODE_IRL3210);
44 44
45 register_intc_controller(&fpga_intc_desc); 45 register_intc_controller(&fpga_intc_desc);
diff --git a/arch/sh/boards/mach-sdk7780/setup.c b/arch/sh/boards/mach-sdk7780/setup.c
index b887373a259..4da38db4b5f 100644
--- a/arch/sh/boards/mach-sdk7780/setup.c
+++ b/arch/sh/boards/mach-sdk7780/setup.c
@@ -74,8 +74,8 @@ device_initcall(sdk7780_devices_setup);
74 74
75static void __init sdk7780_setup(char **cmdline_p) 75static void __init sdk7780_setup(char **cmdline_p)
76{ 76{
77 u16 ver = ctrl_inw(FPGA_FPVERR); 77 u16 ver = __raw_readw(FPGA_FPVERR);
78 u16 dateStamp = ctrl_inw(FPGA_FPDATER); 78 u16 dateStamp = __raw_readw(FPGA_FPDATER);
79 79
80 printk(KERN_INFO "Renesas Technology Europe SDK7780 support.\n"); 80 printk(KERN_INFO "Renesas Technology Europe SDK7780 support.\n");
81 printk(KERN_INFO "Board version: %d (revision %d), " 81 printk(KERN_INFO "Board version: %d (revision %d), "
@@ -85,7 +85,7 @@ static void __init sdk7780_setup(char **cmdline_p)
85 dateStamp); 85 dateStamp);
86 86
87 /* Setup pin mux'ing for PCIC */ 87 /* Setup pin mux'ing for PCIC */
88 ctrl_outw(0x0000, GPIO_PECR); 88 __raw_writew(0x0000, GPIO_PECR);
89} 89}
90 90
91/* 91/*
diff --git a/arch/sh/boards/mach-se/7206/io.c b/arch/sh/boards/mach-se/7206/io.c
index 180455642a4..adadc77532e 100644
--- a/arch/sh/boards/mach-se/7206/io.c
+++ b/arch/sh/boards/mach-se/7206/io.c
@@ -16,7 +16,7 @@
16 16
17static inline void delay(void) 17static inline void delay(void)
18{ 18{
19 ctrl_inw(0x20000000); /* P2 ROM Area */ 19 __raw_readw(0x20000000); /* P2 ROM Area */
20} 20}
21 21
22/* MS7750 requires special versions of in*, out* routines, since 22/* MS7750 requires special versions of in*, out* routines, since
diff --git a/arch/sh/boards/mach-se/7206/irq.c b/arch/sh/boards/mach-se/7206/irq.c
index aef7f052851..79be4bc5993 100644
--- a/arch/sh/boards/mach-se/7206/irq.c
+++ b/arch/sh/boards/mach-se/7206/irq.c
@@ -32,12 +32,12 @@ static void disable_se7206_irq(unsigned int irq)
32 unsigned short msk0,msk1; 32 unsigned short msk0,msk1;
33 33
34 /* Set the priority in IPR to 0 */ 34 /* Set the priority in IPR to 0 */
35 val = ctrl_inw(INTC_IPR01); 35 val = __raw_readw(INTC_IPR01);
36 val &= mask; 36 val &= mask;
37 ctrl_outw(val, INTC_IPR01); 37 __raw_writew(val, INTC_IPR01);
38 /* FPGA mask set */ 38 /* FPGA mask set */
39 msk0 = ctrl_inw(INTMSK0); 39 msk0 = __raw_readw(INTMSK0);
40 msk1 = ctrl_inw(INTMSK1); 40 msk1 = __raw_readw(INTMSK1);
41 41
42 switch (irq) { 42 switch (irq) {
43 case IRQ0_IRQ: 43 case IRQ0_IRQ:
@@ -51,8 +51,8 @@ static void disable_se7206_irq(unsigned int irq)
51 msk1 |= 0x00ff; 51 msk1 |= 0x00ff;
52 break; 52 break;
53 } 53 }
54 ctrl_outw(msk0, INTMSK0); 54 __raw_writew(msk0, INTMSK0);
55 ctrl_outw(msk1, INTMSK1); 55 __raw_writew(msk1, INTMSK1);
56} 56}
57 57
58static void enable_se7206_irq(unsigned int irq) 58static void enable_se7206_irq(unsigned int irq)
@@ -62,13 +62,13 @@ static void enable_se7206_irq(unsigned int irq)
62 unsigned short msk0,msk1; 62 unsigned short msk0,msk1;
63 63
64 /* Set priority in IPR back to original value */ 64 /* Set priority in IPR back to original value */
65 val = ctrl_inw(INTC_IPR01); 65 val = __raw_readw(INTC_IPR01);
66 val |= value; 66 val |= value;
67 ctrl_outw(val, INTC_IPR01); 67 __raw_writew(val, INTC_IPR01);
68 68
69 /* FPGA mask reset */ 69 /* FPGA mask reset */
70 msk0 = ctrl_inw(INTMSK0); 70 msk0 = __raw_readw(INTMSK0);
71 msk1 = ctrl_inw(INTMSK1); 71 msk1 = __raw_readw(INTMSK1);
72 72
73 switch (irq) { 73 switch (irq) {
74 case IRQ0_IRQ: 74 case IRQ0_IRQ:
@@ -82,8 +82,8 @@ static void enable_se7206_irq(unsigned int irq)
82 msk1 &= ~0x00ff; 82 msk1 &= ~0x00ff;
83 break; 83 break;
84 } 84 }
85 ctrl_outw(msk0, INTMSK0); 85 __raw_writew(msk0, INTMSK0);
86 ctrl_outw(msk1, INTMSK1); 86 __raw_writew(msk1, INTMSK1);
87} 87}
88 88
89static void eoi_se7206_irq(unsigned int irq) 89static void eoi_se7206_irq(unsigned int irq)
@@ -93,8 +93,8 @@ static void eoi_se7206_irq(unsigned int irq)
93 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 93 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
94 enable_se7206_irq(irq); 94 enable_se7206_irq(irq);
95 /* FPGA isr clear */ 95 /* FPGA isr clear */
96 sts0 = ctrl_inw(INTSTS0); 96 sts0 = __raw_readw(INTSTS0);
97 sts1 = ctrl_inw(INTSTS1); 97 sts1 = __raw_readw(INTSTS1);
98 98
99 switch (irq) { 99 switch (irq) {
100 case IRQ0_IRQ: 100 case IRQ0_IRQ:
@@ -108,8 +108,8 @@ static void eoi_se7206_irq(unsigned int irq)
108 sts1 &= ~0x00ff; 108 sts1 &= ~0x00ff;
109 break; 109 break;
110 } 110 }
111 ctrl_outw(sts0, INTSTS0); 111 __raw_writew(sts0, INTSTS0);
112 ctrl_outw(sts1, INTSTS1); 112 __raw_writew(sts1, INTSTS1);
113} 113}
114 114
115static struct irq_chip se7206_irq_chip __read_mostly = { 115static struct irq_chip se7206_irq_chip __read_mostly = {
@@ -136,11 +136,11 @@ void __init init_se7206_IRQ(void)
136 make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */ 136 make_se7206_irq(IRQ0_IRQ); /* SMC91C111 */
137 make_se7206_irq(IRQ1_IRQ); /* ATA */ 137 make_se7206_irq(IRQ1_IRQ); /* ATA */
138 make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */ 138 make_se7206_irq(IRQ3_IRQ); /* SLOT / PCM */
139 ctrl_outw(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */ 139 __raw_writew(inw(INTC_ICR1) | 0x000b ,INTC_ICR1 ) ; /* ICR1 */
140 140
141 /* FPGA System register setup*/ 141 /* FPGA System register setup*/
142 ctrl_outw(0x0000,INTSTS0); /* Clear INTSTS0 */ 142 __raw_writew(0x0000,INTSTS0); /* Clear INTSTS0 */
143 ctrl_outw(0x0000,INTSTS1); /* Clear INTSTS1 */ 143 __raw_writew(0x0000,INTSTS1); /* Clear INTSTS1 */
144 /* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */ 144 /* IRQ0=LAN, IRQ1=ATA, IRQ3=SLT,PCM */
145 ctrl_outw(0x0001,INTSEL); 145 __raw_writew(0x0001,INTSEL);
146} 146}
diff --git a/arch/sh/boards/mach-se/7343/irq.c b/arch/sh/boards/mach-se/7343/irq.c
index c60fd13608d..d4305c26e9f 100644
--- a/arch/sh/boards/mach-se/7343/irq.c
+++ b/arch/sh/boards/mach-se/7343/irq.c
@@ -21,13 +21,13 @@ unsigned int se7343_fpga_irq[SE7343_FPGA_IRQ_NR] = { 0, };
21static void disable_se7343_irq(unsigned int irq) 21static void disable_se7343_irq(unsigned int irq)
22{ 22{
23 unsigned int bit = (unsigned int)get_irq_chip_data(irq); 23 unsigned int bit = (unsigned int)get_irq_chip_data(irq);
24 ctrl_outw(ctrl_inw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK); 24 __raw_writew(__raw_readw(PA_CPLD_IMSK) | 1 << bit, PA_CPLD_IMSK);
25} 25}
26 26
27static void enable_se7343_irq(unsigned int irq) 27static void enable_se7343_irq(unsigned int irq)
28{ 28{
29 unsigned int bit = (unsigned int)get_irq_chip_data(irq); 29 unsigned int bit = (unsigned int)get_irq_chip_data(irq);
30 ctrl_outw(ctrl_inw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK); 30 __raw_writew(__raw_readw(PA_CPLD_IMSK) & ~(1 << bit), PA_CPLD_IMSK);
31} 31}
32 32
33static struct irq_chip se7343_irq_chip __read_mostly = { 33static struct irq_chip se7343_irq_chip __read_mostly = {
@@ -39,7 +39,7 @@ static struct irq_chip se7343_irq_chip __read_mostly = {
39 39
40static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc) 40static void se7343_irq_demux(unsigned int irq, struct irq_desc *desc)
41{ 41{
42 unsigned short intv = ctrl_inw(PA_CPLD_ST); 42 unsigned short intv = __raw_readw(PA_CPLD_ST);
43 unsigned int ext_irq = 0; 43 unsigned int ext_irq = 0;
44 44
45 intv &= (1 << SE7343_FPGA_IRQ_NR) - 1; 45 intv &= (1 << SE7343_FPGA_IRQ_NR) - 1;
@@ -59,8 +59,8 @@ void __init init_7343se_IRQ(void)
59{ 59{
60 int i, irq; 60 int i, irq;
61 61
62 ctrl_outw(0, PA_CPLD_IMSK); /* disable all irqs */ 62 __raw_writew(0, PA_CPLD_IMSK); /* disable all irqs */
63 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ 63 __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
64 64
65 for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) { 65 for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
66 irq = create_irq(); 66 irq = create_irq();
diff --git a/arch/sh/boards/mach-se/7343/setup.c b/arch/sh/boards/mach-se/7343/setup.c
index 3412bb2973a..d2370af56d7 100644
--- a/arch/sh/boards/mach-se/7343/setup.c
+++ b/arch/sh/boards/mach-se/7343/setup.c
@@ -161,10 +161,10 @@ device_initcall(sh7343se_devices_setup);
161 */ 161 */
162static void __init sh7343se_setup(char **cmdline_p) 162static void __init sh7343se_setup(char **cmdline_p)
163{ 163{
164 ctrl_outw(0xf900, FPGA_OUT); /* FPGA */ 164 __raw_writew(0xf900, FPGA_OUT); /* FPGA */
165 165
166 ctrl_outw(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */ 166 __raw_writew(0x0002, PORT_PECR); /* PORT E 1 = IRQ5 */
167 ctrl_outw(0x0020, PORT_PSELD); 167 __raw_writew(0x0020, PORT_PSELD);
168 168
169 printk(KERN_INFO "MS7343CP01 Setup...done\n"); 169 printk(KERN_INFO "MS7343CP01 Setup...done\n");
170} 170}
diff --git a/arch/sh/boards/mach-se/770x/irq.c b/arch/sh/boards/mach-se/770x/irq.c
index ec1fea571b5..1028c17b81b 100644
--- a/arch/sh/boards/mach-se/770x/irq.c
+++ b/arch/sh/boards/mach-se/770x/irq.c
@@ -96,13 +96,13 @@ static struct ipr_desc ipr_irq_desc = {
96void __init init_se_IRQ(void) 96void __init init_se_IRQ(void)
97{ 97{
98 /* Disable all interrupts */ 98 /* Disable all interrupts */
99 ctrl_outw(0, BCR_ILCRA); 99 __raw_writew(0, BCR_ILCRA);
100 ctrl_outw(0, BCR_ILCRB); 100 __raw_writew(0, BCR_ILCRB);
101 ctrl_outw(0, BCR_ILCRC); 101 __raw_writew(0, BCR_ILCRC);
102 ctrl_outw(0, BCR_ILCRD); 102 __raw_writew(0, BCR_ILCRD);
103 ctrl_outw(0, BCR_ILCRE); 103 __raw_writew(0, BCR_ILCRE);
104 ctrl_outw(0, BCR_ILCRF); 104 __raw_writew(0, BCR_ILCRF);
105 ctrl_outw(0, BCR_ILCRG); 105 __raw_writew(0, BCR_ILCRG);
106 106
107 register_ipr_controller(&ipr_irq_desc); 107 register_ipr_controller(&ipr_irq_desc);
108} 108}
diff --git a/arch/sh/boards/mach-se/7721/irq.c b/arch/sh/boards/mach-se/7721/irq.c
index b417acc4dad..d85022ea3f1 100644
--- a/arch/sh/boards/mach-se/7721/irq.c
+++ b/arch/sh/boards/mach-se/7721/irq.c
@@ -38,7 +38,7 @@ static DECLARE_INTC_DESC(intc_desc, "SE7721", vectors,
38void __init init_se7721_IRQ(void) 38void __init init_se7721_IRQ(void)
39{ 39{
40 /* PPCR */ 40 /* PPCR */
41 ctrl_outw(ctrl_inw(0xa4050118) & ~0x00ff, 0xa4050118); 41 __raw_writew(__raw_readw(0xa4050118) & ~0x00ff, 0xa4050118);
42 42
43 register_intc_controller(&intc_desc); 43 register_intc_controller(&intc_desc);
44 intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0); 44 intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0);
diff --git a/arch/sh/boards/mach-se/7721/setup.c b/arch/sh/boards/mach-se/7721/setup.c
index 460da53b496..7416ad7ee53 100644
--- a/arch/sh/boards/mach-se/7721/setup.c
+++ b/arch/sh/boards/mach-se/7721/setup.c
@@ -80,10 +80,10 @@ device_initcall(se7721_devices_setup);
80static void __init se7721_setup(char **cmdline_p) 80static void __init se7721_setup(char **cmdline_p)
81{ 81{
82 /* for USB */ 82 /* for USB */
83 ctrl_outw(0x0000, 0xA405010C); /* PGCR */ 83 __raw_writew(0x0000, 0xA405010C); /* PGCR */
84 ctrl_outw(0x0000, 0xA405010E); /* PHCR */ 84 __raw_writew(0x0000, 0xA405010E); /* PHCR */
85 ctrl_outw(0x00AA, 0xA4050118); /* PPCR */ 85 __raw_writew(0x00AA, 0xA4050118); /* PPCR */
86 ctrl_outw(0x0000, 0xA4050124); /* PSELA */ 86 __raw_writew(0x0000, 0xA4050124); /* PSELA */
87} 87}
88 88
89/* 89/*
diff --git a/arch/sh/boards/mach-se/7722/irq.c b/arch/sh/boards/mach-se/7722/irq.c
index b221b6842b0..61605db04ee 100644
--- a/arch/sh/boards/mach-se/7722/irq.c
+++ b/arch/sh/boards/mach-se/7722/irq.c
@@ -21,13 +21,13 @@ unsigned int se7722_fpga_irq[SE7722_FPGA_IRQ_NR] = { 0, };
21static void disable_se7722_irq(unsigned int irq) 21static void disable_se7722_irq(unsigned int irq)
22{ 22{
23 unsigned int bit = (unsigned int)get_irq_chip_data(irq); 23 unsigned int bit = (unsigned int)get_irq_chip_data(irq);
24 ctrl_outw(ctrl_inw(IRQ01_MASK) | 1 << bit, IRQ01_MASK); 24 __raw_writew(__raw_readw(IRQ01_MASK) | 1 << bit, IRQ01_MASK);
25} 25}
26 26
27static void enable_se7722_irq(unsigned int irq) 27static void enable_se7722_irq(unsigned int irq)
28{ 28{
29 unsigned int bit = (unsigned int)get_irq_chip_data(irq); 29 unsigned int bit = (unsigned int)get_irq_chip_data(irq);
30 ctrl_outw(ctrl_inw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK); 30 __raw_writew(__raw_readw(IRQ01_MASK) & ~(1 << bit), IRQ01_MASK);
31} 31}
32 32
33static struct irq_chip se7722_irq_chip __read_mostly = { 33static struct irq_chip se7722_irq_chip __read_mostly = {
@@ -39,7 +39,7 @@ static struct irq_chip se7722_irq_chip __read_mostly = {
39 39
40static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc) 40static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
41{ 41{
42 unsigned short intv = ctrl_inw(IRQ01_STS); 42 unsigned short intv = __raw_readw(IRQ01_STS);
43 unsigned int ext_irq = 0; 43 unsigned int ext_irq = 0;
44 44
45 intv &= (1 << SE7722_FPGA_IRQ_NR) - 1; 45 intv &= (1 << SE7722_FPGA_IRQ_NR) - 1;
@@ -59,8 +59,8 @@ void __init init_se7722_IRQ(void)
59{ 59{
60 int i, irq; 60 int i, irq;
61 61
62 ctrl_outw(0, IRQ01_MASK); /* disable all irqs */ 62 __raw_writew(0, IRQ01_MASK); /* disable all irqs */
63 ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ 63 __raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
64 64
65 for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) { 65 for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
66 irq = create_irq(); 66 irq = create_irq();
diff --git a/arch/sh/boards/mach-se/7722/setup.c b/arch/sh/boards/mach-se/7722/setup.c
index 93675418171..80a4e571b31 100644
--- a/arch/sh/boards/mach-se/7722/setup.c
+++ b/arch/sh/boards/mach-se/7722/setup.c
@@ -156,32 +156,32 @@ device_initcall(se7722_devices_setup);
156 156
157static void __init se7722_setup(char **cmdline_p) 157static void __init se7722_setup(char **cmdline_p)
158{ 158{
159 ctrl_outw(0x010D, FPGA_OUT); /* FPGA */ 159 __raw_writew(0x010D, FPGA_OUT); /* FPGA */
160 160
161 ctrl_outw(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */ 161 __raw_writew(0x0000, PORT_PECR); /* PORT E 1 = IRQ5 ,E 0 = BS */
162 ctrl_outw(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */ 162 __raw_writew(0x1000, PORT_PJCR); /* PORT J 1 = IRQ1,J 0 =IRQ0 */
163 163
164 /* LCDC I/O */ 164 /* LCDC I/O */
165 ctrl_outw(0x0020, PORT_PSELD); 165 __raw_writew(0x0020, PORT_PSELD);
166 166
167 /* SIOF1*/ 167 /* SIOF1*/
168 ctrl_outw(0x0003, PORT_PSELB); 168 __raw_writew(0x0003, PORT_PSELB);
169 ctrl_outw(0xe000, PORT_PSELC); 169 __raw_writew(0xe000, PORT_PSELC);
170 ctrl_outw(0x0000, PORT_PKCR); 170 __raw_writew(0x0000, PORT_PKCR);
171 171
172 /* LCDC */ 172 /* LCDC */
173 ctrl_outw(0x4020, PORT_PHCR); 173 __raw_writew(0x4020, PORT_PHCR);
174 ctrl_outw(0x0000, PORT_PLCR); 174 __raw_writew(0x0000, PORT_PLCR);
175 ctrl_outw(0x0000, PORT_PMCR); 175 __raw_writew(0x0000, PORT_PMCR);
176 ctrl_outw(0x0002, PORT_PRCR); 176 __raw_writew(0x0002, PORT_PRCR);
177 ctrl_outw(0x0000, PORT_PXCR); /* LCDC,CS6A */ 177 __raw_writew(0x0000, PORT_PXCR); /* LCDC,CS6A */
178 178
179 /* KEYSC */ 179 /* KEYSC */
180 ctrl_outw(0x0A10, PORT_PSELA); /* BS,SHHID2 */ 180 __raw_writew(0x0A10, PORT_PSELA); /* BS,SHHID2 */
181 ctrl_outw(0x0000, PORT_PYCR); 181 __raw_writew(0x0000, PORT_PYCR);
182 ctrl_outw(0x0000, PORT_PZCR); 182 __raw_writew(0x0000, PORT_PZCR);
183 ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA); 183 __raw_writew(__raw_readw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA);
184 ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC); 184 __raw_writew(__raw_readw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC);
185} 185}
186 186
187/* 187/*
diff --git a/arch/sh/boards/mach-se/7724/irq.c b/arch/sh/boards/mach-se/7724/irq.c
index f76cf3b49f2..e5e021a7d1e 100644
--- a/arch/sh/boards/mach-se/7724/irq.c
+++ b/arch/sh/boards/mach-se/7724/irq.c
@@ -72,14 +72,14 @@ static void disable_se7724_irq(unsigned int irq)
72{ 72{
73 struct fpga_irq set = get_fpga_irq(fpga2irq(irq)); 73 struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
74 unsigned int bit = irq - set.base; 74 unsigned int bit = irq - set.base;
75 ctrl_outw(ctrl_inw(set.mraddr) | 0x0001 << bit, set.mraddr); 75 __raw_writew(__raw_readw(set.mraddr) | 0x0001 << bit, set.mraddr);
76} 76}
77 77
78static void enable_se7724_irq(unsigned int irq) 78static void enable_se7724_irq(unsigned int irq)
79{ 79{
80 struct fpga_irq set = get_fpga_irq(fpga2irq(irq)); 80 struct fpga_irq set = get_fpga_irq(fpga2irq(irq));
81 unsigned int bit = irq - set.base; 81 unsigned int bit = irq - set.base;
82 ctrl_outw(ctrl_inw(set.mraddr) & ~(0x0001 << bit), set.mraddr); 82 __raw_writew(__raw_readw(set.mraddr) & ~(0x0001 << bit), set.mraddr);
83} 83}
84 84
85static struct irq_chip se7724_irq_chip __read_mostly = { 85static struct irq_chip se7724_irq_chip __read_mostly = {
@@ -92,7 +92,7 @@ static struct irq_chip se7724_irq_chip __read_mostly = {
92static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc) 92static void se7724_irq_demux(unsigned int irq, struct irq_desc *desc)
93{ 93{
94 struct fpga_irq set = get_fpga_irq(irq); 94 struct fpga_irq set = get_fpga_irq(irq);
95 unsigned short intv = ctrl_inw(set.sraddr); 95 unsigned short intv = __raw_readw(set.sraddr);
96 struct irq_desc *ext_desc; 96 struct irq_desc *ext_desc;
97 unsigned int ext_irq = set.base; 97 unsigned int ext_irq = set.base;
98 98
@@ -115,13 +115,13 @@ void __init init_se7724_IRQ(void)
115{ 115{
116 int i; 116 int i;
117 117
118 ctrl_outw(0xffff, IRQ0_MR); /* mask all */ 118 __raw_writew(0xffff, IRQ0_MR); /* mask all */
119 ctrl_outw(0xffff, IRQ1_MR); /* mask all */ 119 __raw_writew(0xffff, IRQ1_MR); /* mask all */
120 ctrl_outw(0xffff, IRQ2_MR); /* mask all */ 120 __raw_writew(0xffff, IRQ2_MR); /* mask all */
121 ctrl_outw(0x0000, IRQ0_SR); /* clear irq */ 121 __raw_writew(0x0000, IRQ0_SR); /* clear irq */
122 ctrl_outw(0x0000, IRQ1_SR); /* clear irq */ 122 __raw_writew(0x0000, IRQ1_SR); /* clear irq */
123 ctrl_outw(0x0000, IRQ2_SR); /* clear irq */ 123 __raw_writew(0x0000, IRQ2_SR); /* clear irq */
124 ctrl_outw(0x002a, IRQ_MODE); /* set irq type */ 124 __raw_writew(0x002a, IRQ_MODE); /* set irq type */
125 125
126 for (i = 0; i < SE7724_FPGA_IRQ_NR; i++) 126 for (i = 0; i < SE7724_FPGA_IRQ_NR; i++)
127 set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i, 127 set_irq_chip_and_handler_name(SE7724_FPGA_IRQ_BASE + i,
diff --git a/arch/sh/boards/mach-se/7724/setup.c b/arch/sh/boards/mach-se/7724/setup.c
index cbfba783ee4..242dc843f57 100644
--- a/arch/sh/boards/mach-se/7724/setup.c
+++ b/arch/sh/boards/mach-se/7724/setup.c
@@ -256,12 +256,12 @@ static struct platform_device ceu1_device = {
256#define FCLKACR 0xa4150008 256#define FCLKACR 0xa4150008
257static void fsimck_init(struct clk *clk) 257static void fsimck_init(struct clk *clk)
258{ 258{
259 u32 status = ctrl_inl(clk->enable_reg); 259 u32 status = __raw_readl(clk->enable_reg);
260 260
261 /* use external clock */ 261 /* use external clock */
262 status &= ~0x000000ff; 262 status &= ~0x000000ff;
263 status |= 0x00000080; 263 status |= 0x00000080;
264 ctrl_outl(status, clk->enable_reg); 264 __raw_writel(status, clk->enable_reg);
265} 265}
266 266
267static struct clk_ops fsimck_clk_ops = { 267static struct clk_ops fsimck_clk_ops = {
@@ -522,7 +522,7 @@ static int __init sh_eth_is_eeprom_ready(void)
522 int t = 10000; 522 int t = 10000;
523 523
524 while (t--) { 524 while (t--) {
525 if (!ctrl_inw(EEPROM_STAT)) 525 if (!__raw_readw(EEPROM_STAT))
526 return 1; 526 return 1;
527 cpu_relax(); 527 cpu_relax();
528 } 528 }
@@ -542,13 +542,13 @@ static void __init sh_eth_init(void)
542 542
543 /* read MAC addr from EEPROM */ 543 /* read MAC addr from EEPROM */
544 for (i = 0 ; i < 3 ; i++) { 544 for (i = 0 ; i < 3 ; i++) {
545 ctrl_outw(0x0, EEPROM_OP); /* read */ 545 __raw_writew(0x0, EEPROM_OP); /* read */
546 ctrl_outw(i*2, EEPROM_ADR); 546 __raw_writew(i*2, EEPROM_ADR);
547 ctrl_outw(0x1, EEPROM_STRT); 547 __raw_writew(0x1, EEPROM_STRT);
548 if (!sh_eth_is_eeprom_ready()) 548 if (!sh_eth_is_eeprom_ready())
549 return; 549 return;
550 550
551 mac = ctrl_inw(EEPROM_DATA); 551 mac = __raw_readw(EEPROM_DATA);
552 sh_eth_plat.mac_addr[i << 1] = mac & 0xff; 552 sh_eth_plat.mac_addr[i << 1] = mac & 0xff;
553 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8; 553 sh_eth_plat.mac_addr[(i << 1) + 1] = mac >> 8;
554 } 554 }
@@ -585,7 +585,7 @@ arch_initcall(arch_setup);
585 585
586static int __init devices_setup(void) 586static int __init devices_setup(void)
587{ 587{
588 u16 sw = ctrl_inw(SW4140); /* select camera, monitor */ 588 u16 sw = __raw_readw(SW4140); /* select camera, monitor */
589 struct clk *fsia_clk; 589 struct clk *fsia_clk;
590 590
591 /* register board specific self-refresh code */ 591 /* register board specific self-refresh code */
@@ -595,7 +595,7 @@ static int __init devices_setup(void)
595 &ms7724se_sdram_leave_start, 595 &ms7724se_sdram_leave_start,
596 &ms7724se_sdram_leave_end); 596 &ms7724se_sdram_leave_end);
597 /* Reset Release */ 597 /* Reset Release */
598 ctrl_outw(ctrl_inw(FPGA_OUT) & 598 __raw_writew(__raw_readw(FPGA_OUT) &
599 ~((1 << 1) | /* LAN */ 599 ~((1 << 1) | /* LAN */
600 (1 << 6) | /* VIDEO DAC */ 600 (1 << 6) | /* VIDEO DAC */
601 (1 << 7) | /* AK4643 */ 601 (1 << 7) | /* AK4643 */
@@ -604,7 +604,7 @@ static int __init devices_setup(void)
604 FPGA_OUT); 604 FPGA_OUT);
605 605
606 /* turn on USB clocks, use external clock */ 606 /* turn on USB clocks, use external clock */
607 ctrl_outw((ctrl_inw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB); 607 __raw_writew((__raw_readw(PORT_MSELCRB) & ~0xc000) | 0x8000, PORT_MSELCRB);
608 608
609#ifdef CONFIG_PM 609#ifdef CONFIG_PM
610 /* Let LED9 show STATUS2 */ 610 /* Let LED9 show STATUS2 */
@@ -633,10 +633,10 @@ static int __init devices_setup(void)
633#endif 633#endif
634 634
635 /* enable USB0 port */ 635 /* enable USB0 port */
636 ctrl_outw(0x0600, 0xa40501d4); 636 __raw_writew(0x0600, 0xa40501d4);
637 637
638 /* enable USB1 port */ 638 /* enable USB1 port */
639 ctrl_outw(0x0600, 0xa4050192); 639 __raw_writew(0x0600, 0xa4050192);
640 640
641 /* enable IRQ 0,1,2 */ 641 /* enable IRQ 0,1,2 */
642 gpio_request(GPIO_FN_INTC_IRQ0, NULL); 642 gpio_request(GPIO_FN_INTC_IRQ0, NULL);
@@ -684,7 +684,7 @@ static int __init devices_setup(void)
684 gpio_request(GPIO_FN_LCDVCPWC, NULL); 684 gpio_request(GPIO_FN_LCDVCPWC, NULL);
685 gpio_request(GPIO_FN_LCDRD, NULL); 685 gpio_request(GPIO_FN_LCDRD, NULL);
686 gpio_request(GPIO_FN_LCDLCLK, NULL); 686 gpio_request(GPIO_FN_LCDLCLK, NULL);
687 ctrl_outw((ctrl_inw(PORT_HIZA) & ~0x0001), PORT_HIZA); 687 __raw_writew((__raw_readw(PORT_HIZA) & ~0x0001), PORT_HIZA);
688 688
689 /* enable CEU0 */ 689 /* enable CEU0 */
690 gpio_request(GPIO_FN_VIO0_D15, NULL); 690 gpio_request(GPIO_FN_VIO0_D15, NULL);
diff --git a/arch/sh/boards/mach-se/7780/irq.c b/arch/sh/boards/mach-se/7780/irq.c
index 121744c0871..d5c9edc172a 100644
--- a/arch/sh/boards/mach-se/7780/irq.c
+++ b/arch/sh/boards/mach-se/7780/irq.c
@@ -24,30 +24,30 @@
24void __init init_se7780_IRQ(void) 24void __init init_se7780_IRQ(void)
25{ 25{
26 /* enable all interrupt at FPGA */ 26 /* enable all interrupt at FPGA */
27 ctrl_outw(0, FPGA_INTMSK1); 27 __raw_writew(0, FPGA_INTMSK1);
28 /* mask SM501 interrupt */ 28 /* mask SM501 interrupt */
29 ctrl_outw((ctrl_inw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1); 29 __raw_writew((__raw_readw(FPGA_INTMSK1) | 0x0002), FPGA_INTMSK1);
30 /* enable all interrupt at FPGA */ 30 /* enable all interrupt at FPGA */
31 ctrl_outw(0, FPGA_INTMSK2); 31 __raw_writew(0, FPGA_INTMSK2);
32 32
33 /* set FPGA INTSEL register */ 33 /* set FPGA INTSEL register */
34 /* FPGA + 0x06 */ 34 /* FPGA + 0x06 */
35 ctrl_outw( ((IRQPIN_SM501 << IRQPOS_SM501) | 35 __raw_writew( ((IRQPIN_SM501 << IRQPOS_SM501) |
36 (IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1); 36 (IRQPIN_SMC91CX << IRQPOS_SMC91CX)), FPGA_INTSEL1);
37 37
38 /* FPGA + 0x08 */ 38 /* FPGA + 0x08 */
39 ctrl_outw(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) | 39 __raw_writew(((IRQPIN_EXTINT4 << IRQPOS_EXTINT4) |
40 (IRQPIN_EXTINT3 << IRQPOS_EXTINT3) | 40 (IRQPIN_EXTINT3 << IRQPOS_EXTINT3) |
41 (IRQPIN_EXTINT2 << IRQPOS_EXTINT2) | 41 (IRQPIN_EXTINT2 << IRQPOS_EXTINT2) |
42 (IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2); 42 (IRQPIN_EXTINT1 << IRQPOS_EXTINT1)), FPGA_INTSEL2);
43 43
44 /* FPGA + 0x0A */ 44 /* FPGA + 0x0A */
45 ctrl_outw((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3); 45 __raw_writew((IRQPIN_PCCPW << IRQPOS_PCCPW), FPGA_INTSEL3);
46 46
47 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */ 47 plat_irq_setup_pins(IRQ_MODE_IRQ); /* install handlers for IRQ0-7 */
48 48
49 /* ICR1: detect low level(for 2ndcut) */ 49 /* ICR1: detect low level(for 2ndcut) */
50 ctrl_outl(0xAAAA0000, INTC_ICR1); 50 __raw_writel(0xAAAA0000, INTC_ICR1);
51 51
52 /* 52 /*
53 * FPGA PCISEL register initialize 53 * FPGA PCISEL register initialize
@@ -63,6 +63,6 @@ void __init init_se7780_IRQ(void)
63 * INTD || INTD | INTC | -- | INTA 63 * INTD || INTD | INTC | -- | INTA
64 * ------------------------------------- 64 * -------------------------------------
65 */ 65 */
66 ctrl_outw(0x0013, FPGA_PCI_INTSEL1); 66 __raw_writew(0x0013, FPGA_PCI_INTSEL1);
67 ctrl_outw(0xE402, FPGA_PCI_INTSEL2); 67 __raw_writew(0xE402, FPGA_PCI_INTSEL2);
68} 68}
diff --git a/arch/sh/boards/mach-se/7780/setup.c b/arch/sh/boards/mach-se/7780/setup.c
index f7bfb3f8369..6f7c207138e 100644
--- a/arch/sh/boards/mach-se/7780/setup.c
+++ b/arch/sh/boards/mach-se/7780/setup.c
@@ -75,14 +75,14 @@ device_initcall(se7780_devices_setup);
75static void __init se7780_setup(char **cmdline_p) 75static void __init se7780_setup(char **cmdline_p)
76{ 76{
77 /* "SH-Linux" on LED Display */ 77 /* "SH-Linux" on LED Display */
78 ctrl_outw( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) ); 78 __raw_writew( 'S' , PA_LED_DISP + (DISP_SEL0_ADDR << 1) );
79 ctrl_outw( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) ); 79 __raw_writew( 'H' , PA_LED_DISP + (DISP_SEL1_ADDR << 1) );
80 ctrl_outw( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) ); 80 __raw_writew( '-' , PA_LED_DISP + (DISP_SEL2_ADDR << 1) );
81 ctrl_outw( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) ); 81 __raw_writew( 'L' , PA_LED_DISP + (DISP_SEL3_ADDR << 1) );
82 ctrl_outw( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) ); 82 __raw_writew( 'i' , PA_LED_DISP + (DISP_SEL4_ADDR << 1) );
83 ctrl_outw( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) ); 83 __raw_writew( 'n' , PA_LED_DISP + (DISP_SEL5_ADDR << 1) );
84 ctrl_outw( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) ); 84 __raw_writew( 'u' , PA_LED_DISP + (DISP_SEL6_ADDR << 1) );
85 ctrl_outw( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) ); 85 __raw_writew( 'x' , PA_LED_DISP + (DISP_SEL7_ADDR << 1) );
86 86
87 printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n"); 87 printk(KERN_INFO "Hitachi UL Solutions Engine 7780SE03 support.\n");
88 88
@@ -93,15 +93,15 @@ static void __init se7780_setup(char **cmdline_p)
93 * REQ2/GNT2 -> Serial ATA 93 * REQ2/GNT2 -> Serial ATA
94 * REQ3/GNT3 -> PCI slot 94 * REQ3/GNT3 -> PCI slot
95 */ 95 */
96 ctrl_outw(0x0213, FPGA_REQSEL); 96 __raw_writew(0x0213, FPGA_REQSEL);
97 97
98 /* GPIO setting */ 98 /* GPIO setting */
99 ctrl_outw(0x0000, GPIO_PECR); 99 __raw_writew(0x0000, GPIO_PECR);
100 ctrl_outw(ctrl_inw(GPIO_PHCR)&0xfff3, GPIO_PHCR); 100 __raw_writew(__raw_readw(GPIO_PHCR)&0xfff3, GPIO_PHCR);
101 ctrl_outw(0x0c00, GPIO_PMSELR); 101 __raw_writew(0x0c00, GPIO_PMSELR);
102 102
103 /* iVDR Power ON */ 103 /* iVDR Power ON */
104 ctrl_outw(0x0001, FPGA_IVDRPW); 104 __raw_writew(0x0001, FPGA_IVDRPW);
105} 105}
106 106
107/* 107/*
diff --git a/arch/sh/boards/mach-sh03/rtc.c b/arch/sh/boards/mach-sh03/rtc.c
index a8b9f844ab5..1b200990500 100644
--- a/arch/sh/boards/mach-sh03/rtc.c
+++ b/arch/sh/boards/mach-sh03/rtc.c
@@ -44,15 +44,15 @@ unsigned long get_cmos_time(void)
44 spin_lock(&sh03_rtc_lock); 44 spin_lock(&sh03_rtc_lock);
45 again: 45 again:
46 do { 46 do {
47 sec = (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10; 47 sec = (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10;
48 min = (ctrl_inb(RTC_MIN1) & 0xf) + (ctrl_inb(RTC_MIN10) & 0xf) * 10; 48 min = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
49 hour = (ctrl_inb(RTC_HOU1) & 0xf) + (ctrl_inb(RTC_HOU10) & 0xf) * 10; 49 hour = (__raw_readb(RTC_HOU1) & 0xf) + (__raw_readb(RTC_HOU10) & 0xf) * 10;
50 day = (ctrl_inb(RTC_DAY1) & 0xf) + (ctrl_inb(RTC_DAY10) & 0xf) * 10; 50 day = (__raw_readb(RTC_DAY1) & 0xf) + (__raw_readb(RTC_DAY10) & 0xf) * 10;
51 mon = (ctrl_inb(RTC_MON1) & 0xf) + (ctrl_inb(RTC_MON10) & 0xf) * 10; 51 mon = (__raw_readb(RTC_MON1) & 0xf) + (__raw_readb(RTC_MON10) & 0xf) * 10;
52 year = (ctrl_inb(RTC_YEA1) & 0xf) + (ctrl_inb(RTC_YEA10) & 0xf) * 10 52 year = (__raw_readb(RTC_YEA1) & 0xf) + (__raw_readb(RTC_YEA10) & 0xf) * 10
53 + (ctrl_inb(RTC_YEA100 ) & 0xf) * 100 53 + (__raw_readb(RTC_YEA100 ) & 0xf) * 100
54 + (ctrl_inb(RTC_YEA1000) & 0xf) * 1000; 54 + (__raw_readb(RTC_YEA1000) & 0xf) * 1000;
55 } while (sec != (ctrl_inb(RTC_SEC1) & 0xf) + (ctrl_inb(RTC_SEC10) & 0x7) * 10); 55 } while (sec != (__raw_readb(RTC_SEC1) & 0xf) + (__raw_readb(RTC_SEC10) & 0x7) * 10);
56 if (year == 0 || mon < 1 || mon > 12 || day > 31 || day < 1 || 56 if (year == 0 || mon < 1 || mon > 12 || day > 31 || day < 1 ||
57 hour > 23 || min > 59 || sec > 59) { 57 hour > 23 || min > 59 || sec > 59) {
58 printk(KERN_ERR 58 printk(KERN_ERR
@@ -60,16 +60,16 @@ unsigned long get_cmos_time(void)
60 printk("year=%d, mon=%d, day=%d, hour=%d, min=%d, sec=%d\n", 60 printk("year=%d, mon=%d, day=%d, hour=%d, min=%d, sec=%d\n",
61 year, mon, day, hour, min, sec); 61 year, mon, day, hour, min, sec);
62 62
63 ctrl_outb(0, RTC_SEC1); ctrl_outb(0, RTC_SEC10); 63 __raw_writeb(0, RTC_SEC1); __raw_writeb(0, RTC_SEC10);
64 ctrl_outb(0, RTC_MIN1); ctrl_outb(0, RTC_MIN10); 64 __raw_writeb(0, RTC_MIN1); __raw_writeb(0, RTC_MIN10);
65 ctrl_outb(0, RTC_HOU1); ctrl_outb(0, RTC_HOU10); 65 __raw_writeb(0, RTC_HOU1); __raw_writeb(0, RTC_HOU10);
66 ctrl_outb(6, RTC_WEE1); 66 __raw_writeb(6, RTC_WEE1);
67 ctrl_outb(1, RTC_DAY1); ctrl_outb(0, RTC_DAY10); 67 __raw_writeb(1, RTC_DAY1); __raw_writeb(0, RTC_DAY10);
68 ctrl_outb(1, RTC_MON1); ctrl_outb(0, RTC_MON10); 68 __raw_writeb(1, RTC_MON1); __raw_writeb(0, RTC_MON10);
69 ctrl_outb(0, RTC_YEA1); ctrl_outb(0, RTC_YEA10); 69 __raw_writeb(0, RTC_YEA1); __raw_writeb(0, RTC_YEA10);
70 ctrl_outb(0, RTC_YEA100); 70 __raw_writeb(0, RTC_YEA100);
71 ctrl_outb(2, RTC_YEA1000); 71 __raw_writeb(2, RTC_YEA1000);
72 ctrl_outb(0, RTC_CTL); 72 __raw_writeb(0, RTC_CTL);
73 goto again; 73 goto again;
74 } 74 }
75 75
@@ -93,9 +93,9 @@ static int set_rtc_mmss(unsigned long nowtime)
93 /* gets recalled with irq locally disabled */ 93 /* gets recalled with irq locally disabled */
94 spin_lock(&sh03_rtc_lock); 94 spin_lock(&sh03_rtc_lock);
95 for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */ 95 for (i = 0 ; i < 1000000 ; i++) /* may take up to 1 second... */
96 if (!(ctrl_inb(RTC_CTL) & RTC_BUSY)) 96 if (!(__raw_readb(RTC_CTL) & RTC_BUSY))
97 break; 97 break;
98 cmos_minutes = (ctrl_inb(RTC_MIN1) & 0xf) + (ctrl_inb(RTC_MIN10) & 0xf) * 10; 98 cmos_minutes = (__raw_readb(RTC_MIN1) & 0xf) + (__raw_readb(RTC_MIN10) & 0xf) * 10;
99 real_seconds = nowtime % 60; 99 real_seconds = nowtime % 60;
100 real_minutes = nowtime / 60; 100 real_minutes = nowtime / 60;
101 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) 101 if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
@@ -103,10 +103,10 @@ static int set_rtc_mmss(unsigned long nowtime)
103 real_minutes %= 60; 103 real_minutes %= 60;
104 104
105 if (abs(real_minutes - cmos_minutes) < 30) { 105 if (abs(real_minutes - cmos_minutes) < 30) {
106 ctrl_outb(real_seconds % 10, RTC_SEC1); 106 __raw_writeb(real_seconds % 10, RTC_SEC1);
107 ctrl_outb(real_seconds / 10, RTC_SEC10); 107 __raw_writeb(real_seconds / 10, RTC_SEC10);
108 ctrl_outb(real_minutes % 10, RTC_MIN1); 108 __raw_writeb(real_minutes % 10, RTC_MIN1);
109 ctrl_outb(real_minutes / 10, RTC_MIN10); 109 __raw_writeb(real_minutes / 10, RTC_MIN10);
110 } else { 110 } else {
111 printk(KERN_WARNING 111 printk(KERN_WARNING
112 "set_rtc_mmss: can't update from %d to %d\n", 112 "set_rtc_mmss: can't update from %d to %d\n",
diff --git a/arch/sh/boards/mach-sh7763rdp/irq.c b/arch/sh/boards/mach-sh7763rdp/irq.c
index d8ebfa7d8c7..add698c8f2b 100644
--- a/arch/sh/boards/mach-sh7763rdp/irq.c
+++ b/arch/sh/boards/mach-sh7763rdp/irq.c
@@ -28,18 +28,18 @@
28void __init init_sh7763rdp_IRQ(void) 28void __init init_sh7763rdp_IRQ(void)
29{ 29{
30 /* GPIO enabled */ 30 /* GPIO enabled */
31 ctrl_outl(1 << 25, INTC_INT2MSKCR); 31 __raw_writel(1 << 25, INTC_INT2MSKCR);
32 32
33 /* enable GPIO interrupts */ 33 /* enable GPIO interrupts */
34 ctrl_outl((ctrl_inl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000, 34 __raw_writel((__raw_readl(INTC_INT2PRI7) & 0xFF00FFFF) | 0x000F0000,
35 INTC_INT2PRI7); 35 INTC_INT2PRI7);
36 36
37 /* USBH enabled */ 37 /* USBH enabled */
38 ctrl_outl(1 << 17, INTC_INT2MSKCR1); 38 __raw_writel(1 << 17, INTC_INT2MSKCR1);
39 39
40 /* GETHER enabled */ 40 /* GETHER enabled */
41 ctrl_outl(1 << 16, INTC_INT2MSKCR1); 41 __raw_writel(1 << 16, INTC_INT2MSKCR1);
42 42
43 /* DMAC enabled */ 43 /* DMAC enabled */
44 ctrl_outl(1 << 8, INTC_INT2MSKCR); 44 __raw_writel(1 << 8, INTC_INT2MSKCR);
45} 45}
diff --git a/arch/sh/boards/mach-sh7763rdp/setup.c b/arch/sh/boards/mach-sh7763rdp/setup.c
index 390534a0b35..f64a6918224 100644
--- a/arch/sh/boards/mach-sh7763rdp/setup.c
+++ b/arch/sh/boards/mach-sh7763rdp/setup.c
@@ -158,50 +158,50 @@ device_initcall(sh7763rdp_devices_setup);
158static void __init sh7763rdp_setup(char **cmdline_p) 158static void __init sh7763rdp_setup(char **cmdline_p)
159{ 159{
160 /* Board version check */ 160 /* Board version check */
161 if (ctrl_inw(CPLD_BOARD_ID_ERV_REG) == 0xECB1) 161 if (__raw_readw(CPLD_BOARD_ID_ERV_REG) == 0xECB1)
162 printk(KERN_INFO "RTE Standard Configuration\n"); 162 printk(KERN_INFO "RTE Standard Configuration\n");
163 else 163 else
164 printk(KERN_INFO "RTA Standard Configuration\n"); 164 printk(KERN_INFO "RTA Standard Configuration\n");
165 165
166 /* USB pin select bits (clear bit 5-2 to 0) */ 166 /* USB pin select bits (clear bit 5-2 to 0) */
167 ctrl_outw((ctrl_inw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2); 167 __raw_writew((__raw_readw(PORT_PSEL2) & 0xFFC3), PORT_PSEL2);
168 /* USBH setup port I controls to other (clear bits 4-9 to 0) */ 168 /* USBH setup port I controls to other (clear bits 4-9 to 0) */
169 ctrl_outw(ctrl_inw(PORT_PICR) & 0xFC0F, PORT_PICR); 169 __raw_writew(__raw_readw(PORT_PICR) & 0xFC0F, PORT_PICR);
170 170
171 /* Select USB Host controller */ 171 /* Select USB Host controller */
172 ctrl_outw(0x00, USB_USBHSC); 172 __raw_writew(0x00, USB_USBHSC);
173 173
174 /* For LCD */ 174 /* For LCD */
175 /* set PTJ7-1, bits 15-2 of PJCR to 0 */ 175 /* set PTJ7-1, bits 15-2 of PJCR to 0 */
176 ctrl_outw(ctrl_inw(PORT_PJCR) & 0x0003, PORT_PJCR); 176 __raw_writew(__raw_readw(PORT_PJCR) & 0x0003, PORT_PJCR);
177 /* set PTI5, bits 11-10 of PICR to 0 */ 177 /* set PTI5, bits 11-10 of PICR to 0 */
178 ctrl_outw(ctrl_inw(PORT_PICR) & 0xF3FF, PORT_PICR); 178 __raw_writew(__raw_readw(PORT_PICR) & 0xF3FF, PORT_PICR);
179 ctrl_outw(0, PORT_PKCR); 179 __raw_writew(0, PORT_PKCR);
180 ctrl_outw(0, PORT_PLCR); 180 __raw_writew(0, PORT_PLCR);
181 /* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */ 181 /* set PSEL2 bits 14-8, 5-4, of PSEL2 to 0 */
182 ctrl_outw((ctrl_inw(PORT_PSEL2) & 0x00C0), PORT_PSEL2); 182 __raw_writew((__raw_readw(PORT_PSEL2) & 0x00C0), PORT_PSEL2);
183 /* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */ 183 /* set PSEL3 bits 14-12, 6-4, 2-0 of PSEL3 to 0 */
184 ctrl_outw((ctrl_inw(PORT_PSEL3) & 0x0700), PORT_PSEL3); 184 __raw_writew((__raw_readw(PORT_PSEL3) & 0x0700), PORT_PSEL3);
185 185
186 /* For HAC */ 186 /* For HAC */
187 /* bit3-0 0100:HAC & SSI1 enable */ 187 /* bit3-0 0100:HAC & SSI1 enable */
188 ctrl_outw((ctrl_inw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1); 188 __raw_writew((__raw_readw(PORT_PSEL1) & 0xFFF0) | 0x0004, PORT_PSEL1);
189 /* bit14 1:SSI_HAC_CLK enable */ 189 /* bit14 1:SSI_HAC_CLK enable */
190 ctrl_outw(ctrl_inw(PORT_PSEL4) | 0x4000, PORT_PSEL4); 190 __raw_writew(__raw_readw(PORT_PSEL4) | 0x4000, PORT_PSEL4);
191 191
192 /* SH-Ether */ 192 /* SH-Ether */
193 ctrl_outw((ctrl_inw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1); 193 __raw_writew((__raw_readw(PORT_PSEL1) & ~0xff00) | 0x2400, PORT_PSEL1);
194 ctrl_outw(0x0, PORT_PFCR); 194 __raw_writew(0x0, PORT_PFCR);
195 ctrl_outw(0x0, PORT_PFCR); 195 __raw_writew(0x0, PORT_PFCR);
196 ctrl_outw(0x0, PORT_PFCR); 196 __raw_writew(0x0, PORT_PFCR);
197 197
198 /* MMC */ 198 /* MMC */
199 /*selects SCIF and MMC other functions */ 199 /*selects SCIF and MMC other functions */
200 ctrl_outw(0x0001, PORT_PSEL0); 200 __raw_writew(0x0001, PORT_PSEL0);
201 /* MMC clock operates */ 201 /* MMC clock operates */
202 ctrl_outl(ctrl_inl(MSTPCR1) & ~0x8, MSTPCR1); 202 __raw_writel(__raw_readl(MSTPCR1) & ~0x8, MSTPCR1);
203 ctrl_outw(ctrl_inw(PORT_PACR) & ~0x3000, PORT_PACR); 203 __raw_writew(__raw_readw(PORT_PACR) & ~0x3000, PORT_PACR);
204 ctrl_outw(ctrl_inw(PORT_PCCR) & ~0xCFC3, PORT_PCCR); 204 __raw_writew(__raw_readw(PORT_PCCR) & ~0xCFC3, PORT_PCCR);
205} 205}
206 206
207static struct sh_machine_vector mv_sh7763rdp __initmv = { 207static struct sh_machine_vector mv_sh7763rdp __initmv = {
diff --git a/arch/sh/boards/mach-snapgear/setup.c b/arch/sh/boards/mach-snapgear/setup.c
index a3277a23cf1..331745dee37 100644
--- a/arch/sh/boards/mach-snapgear/setup.c
+++ b/arch/sh/boards/mach-snapgear/setup.c
@@ -30,7 +30,7 @@
30 30
31static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id) 31static irqreturn_t eraseconfig_interrupt(int irq, void *dev_id)
32{ 32{
33 (void)ctrl_inb(0xb8000000); /* dummy read */ 33 (void)__raw_readb(0xb8000000); /* dummy read */
34 34
35 printk("SnapGear: erase switch interrupt!\n"); 35 printk("SnapGear: erase switch interrupt!\n");
36 36
diff --git a/arch/sh/boards/mach-systemh/irq.c b/arch/sh/boards/mach-systemh/irq.c
index 986a0e71d22..523aea5dc94 100644
--- a/arch/sh/boards/mach-systemh/irq.c
+++ b/arch/sh/boards/mach-systemh/irq.c
@@ -41,13 +41,13 @@ static void disable_systemh_irq(unsigned int irq)
41 unsigned long val, mask = 0x01 << 1; 41 unsigned long val, mask = 0x01 << 1;
42 42
43 /* Clear the "irq"th bit in the mask and set it in the request */ 43 /* Clear the "irq"th bit in the mask and set it in the request */
44 val = ctrl_inl((unsigned long)systemh_irq_mask_register); 44 val = __raw_readl((unsigned long)systemh_irq_mask_register);
45 val &= ~mask; 45 val &= ~mask;
46 ctrl_outl(val, (unsigned long)systemh_irq_mask_register); 46 __raw_writel(val, (unsigned long)systemh_irq_mask_register);
47 47
48 val = ctrl_inl((unsigned long)systemh_irq_request_register); 48 val = __raw_readl((unsigned long)systemh_irq_request_register);
49 val |= mask; 49 val |= mask;
50 ctrl_outl(val, (unsigned long)systemh_irq_request_register); 50 __raw_writel(val, (unsigned long)systemh_irq_request_register);
51 } 51 }
52} 52}
53 53
@@ -57,9 +57,9 @@ static void enable_systemh_irq(unsigned int irq)
57 unsigned long val, mask = 0x01 << 1; 57 unsigned long val, mask = 0x01 << 1;
58 58
59 /* Set "irq"th bit in the mask register */ 59 /* Set "irq"th bit in the mask register */
60 val = ctrl_inl((unsigned long)systemh_irq_mask_register); 60 val = __raw_readl((unsigned long)systemh_irq_mask_register);
61 val |= mask; 61 val |= mask;
62 ctrl_outl(val, (unsigned long)systemh_irq_mask_register); 62 __raw_writel(val, (unsigned long)systemh_irq_mask_register);
63 } 63 }
64} 64}
65 65
diff --git a/arch/sh/boards/mach-titan/io.c b/arch/sh/boards/mach-titan/io.c
index 0130e9826ac..29754c5091f 100644
--- a/arch/sh/boards/mach-titan/io.c
+++ b/arch/sh/boards/mach-titan/io.c
@@ -16,8 +16,8 @@ static inline unsigned int port2adr(unsigned int port)
16u8 titan_inb(unsigned long port) 16u8 titan_inb(unsigned long port)
17{ 17{
18 if (PXSEG(port)) 18 if (PXSEG(port))
19 return ctrl_inb(port); 19 return __raw_readb(port);
20 return ctrl_inw(port2adr(port)) & 0xff; 20 return __raw_readw(port2adr(port)) & 0xff;
21} 21}
22 22
23u8 titan_inb_p(unsigned long port) 23u8 titan_inb_p(unsigned long port)
@@ -25,9 +25,9 @@ u8 titan_inb_p(unsigned long port)
25 u8 v; 25 u8 v;
26 26
27 if (PXSEG(port)) 27 if (PXSEG(port))
28 v = ctrl_inb(port); 28 v = __raw_readb(port);
29 else 29 else
30 v = ctrl_inw(port2adr(port)) & 0xff; 30 v = __raw_readw(port2adr(port)) & 0xff;
31 ctrl_delay(); 31 ctrl_delay();
32 return v; 32 return v;
33} 33}
@@ -35,9 +35,9 @@ u8 titan_inb_p(unsigned long port)
35u16 titan_inw(unsigned long port) 35u16 titan_inw(unsigned long port)
36{ 36{
37 if (PXSEG(port)) 37 if (PXSEG(port))
38 return ctrl_inw(port); 38 return __raw_readw(port);
39 else if (port >= 0x2000) 39 else if (port >= 0x2000)
40 return ctrl_inw(port2adr(port)); 40 return __raw_readw(port2adr(port));
41 else 41 else
42 maybebadio(port); 42 maybebadio(port);
43 return 0; 43 return 0;
@@ -46,9 +46,9 @@ u16 titan_inw(unsigned long port)
46u32 titan_inl(unsigned long port) 46u32 titan_inl(unsigned long port)
47{ 47{
48 if (PXSEG(port)) 48 if (PXSEG(port))
49 return ctrl_inl(port); 49 return __raw_readl(port);
50 else if (port >= 0x2000) 50 else if (port >= 0x2000)
51 return ctrl_inw(port2adr(port)); 51 return __raw_readw(port2adr(port));
52 else 52 else
53 maybebadio(port); 53 maybebadio(port);
54 return 0; 54 return 0;
@@ -57,26 +57,26 @@ u32 titan_inl(unsigned long port)
57void titan_outb(u8 value, unsigned long port) 57void titan_outb(u8 value, unsigned long port)
58{ 58{
59 if (PXSEG(port)) 59 if (PXSEG(port))
60 ctrl_outb(value, port); 60 __raw_writeb(value, port);
61 else 61 else
62 ctrl_outw(value, port2adr(port)); 62 __raw_writew(value, port2adr(port));
63} 63}
64 64
65void titan_outb_p(u8 value, unsigned long port) 65void titan_outb_p(u8 value, unsigned long port)
66{ 66{
67 if (PXSEG(port)) 67 if (PXSEG(port))
68 ctrl_outb(value, port); 68 __raw_writeb(value, port);
69 else 69 else
70 ctrl_outw(value, port2adr(port)); 70 __raw_writew(value, port2adr(port));
71 ctrl_delay(); 71 ctrl_delay();
72} 72}
73 73
74void titan_outw(u16 value, unsigned long port) 74void titan_outw(u16 value, unsigned long port)
75{ 75{
76 if (PXSEG(port)) 76 if (PXSEG(port))
77 ctrl_outw(value, port); 77 __raw_writew(value, port);
78 else if (port >= 0x2000) 78 else if (port >= 0x2000)
79 ctrl_outw(value, port2adr(port)); 79 __raw_writew(value, port2adr(port));
80 else 80 else
81 maybebadio(port); 81 maybebadio(port);
82} 82}
@@ -84,7 +84,7 @@ void titan_outw(u16 value, unsigned long port)
84void titan_outl(u32 value, unsigned long port) 84void titan_outl(u32 value, unsigned long port)
85{ 85{
86 if (PXSEG(port)) 86 if (PXSEG(port))
87 ctrl_outl(value, port); 87 __raw_writel(value, port);
88 else 88 else
89 maybebadio(port); 89 maybebadio(port);
90} 90}
diff --git a/arch/sh/boards/mach-x3proto/ilsel.c b/arch/sh/boards/mach-x3proto/ilsel.c
index b5c673c3933..5c9842704c6 100644
--- a/arch/sh/boards/mach-x3proto/ilsel.c
+++ b/arch/sh/boards/mach-x3proto/ilsel.c
@@ -70,10 +70,10 @@ static void __ilsel_enable(ilsel_source_t set, unsigned int bit)
70 pr_debug("%s: bit#%d: addr - 0x%08lx (shift %d, set %d)\n", 70 pr_debug("%s: bit#%d: addr - 0x%08lx (shift %d, set %d)\n",
71 __func__, bit, addr, shift, set); 71 __func__, bit, addr, shift, set);
72 72
73 tmp = ctrl_inw(addr); 73 tmp = __raw_readw(addr);
74 tmp &= ~(0xf << shift); 74 tmp &= ~(0xf << shift);
75 tmp |= set << shift; 75 tmp |= set << shift;
76 ctrl_outw(tmp, addr); 76 __raw_writew(tmp, addr);
77} 77}
78 78
79/** 79/**
@@ -142,9 +142,9 @@ void ilsel_disable(unsigned int irq)
142 142
143 addr = mk_ilsel_addr(irq); 143 addr = mk_ilsel_addr(irq);
144 144
145 tmp = ctrl_inw(addr); 145 tmp = __raw_readw(addr);
146 tmp &= ~(0xf << mk_ilsel_shift(irq)); 146 tmp &= ~(0xf << mk_ilsel_shift(irq));
147 ctrl_outw(tmp, addr); 147 __raw_writew(tmp, addr);
148 148
149 clear_bit(irq, &ilsel_level_map); 149 clear_bit(irq, &ilsel_level_map);
150} 150}
diff --git a/arch/sh/boards/mach-x3proto/setup.c b/arch/sh/boards/mach-x3proto/setup.c
index efe4cb9f8a7..e284592fd42 100644
--- a/arch/sh/boards/mach-x3proto/setup.c
+++ b/arch/sh/boards/mach-x3proto/setup.c
@@ -149,7 +149,7 @@ static void __init x3proto_init_irq(void)
149 plat_irq_setup_pins(IRQ_MODE_IRL3210); 149 plat_irq_setup_pins(IRQ_MODE_IRL3210);
150 150
151 /* Set ICR0.LVLMODE */ 151 /* Set ICR0.LVLMODE */
152 ctrl_outl(ctrl_inl(0xfe410000) | (1 << 21), 0xfe410000); 152 __raw_writel(__raw_readl(0xfe410000) | (1 << 21), 0xfe410000);
153} 153}
154 154
155static struct sh_machine_vector mv_x3proto __initmv = { 155static struct sh_machine_vector mv_x3proto __initmv = {
diff --git a/arch/sh/cchips/hd6446x/hd64461.c b/arch/sh/cchips/hd6446x/hd64461.c
index 50aa0c1f76e..cbfedfb42e0 100644
--- a/arch/sh/cchips/hd6446x/hd64461.c
+++ b/arch/sh/cchips/hd6446x/hd64461.c
@@ -55,7 +55,7 @@ static struct irq_chip hd64461_irq_chip = {
55 55
56static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc) 56static void hd64461_irq_demux(unsigned int irq, struct irq_desc *desc)
57{ 57{
58 unsigned short intv = ctrl_inw(HD64461_NIRR); 58 unsigned short intv = __raw_readw(HD64461_NIRR);
59 struct irq_desc *ext_desc; 59 struct irq_desc *ext_desc;
60 unsigned int ext_irq = HD64461_IRQBASE; 60 unsigned int ext_irq = HD64461_IRQBASE;
61 61
diff --git a/arch/sh/drivers/dma/dma-pvr2.c b/arch/sh/drivers/dma/dma-pvr2.c
index 391cbe1c295..3cee58e7f1e 100644
--- a/arch/sh/drivers/dma/dma-pvr2.c
+++ b/arch/sh/drivers/dma/dma-pvr2.c
@@ -40,10 +40,10 @@ static irqreturn_t pvr2_dma_interrupt(int irq, void *dev_id)
40 40
41static int pvr2_request_dma(struct dma_channel *chan) 41static int pvr2_request_dma(struct dma_channel *chan)
42{ 42{
43 if (ctrl_inl(PVR2_DMA_MODE) != 0) 43 if (__raw_readl(PVR2_DMA_MODE) != 0)
44 return -EBUSY; 44 return -EBUSY;
45 45
46 ctrl_outl(0, PVR2_DMA_LMMODE0); 46 __raw_writel(0, PVR2_DMA_LMMODE0);
47 47
48 return 0; 48 return 0;
49} 49}
@@ -60,9 +60,9 @@ static int pvr2_xfer_dma(struct dma_channel *chan)
60 60
61 xfer_complete = 0; 61 xfer_complete = 0;
62 62
63 ctrl_outl(chan->dar, PVR2_DMA_ADDR); 63 __raw_writel(chan->dar, PVR2_DMA_ADDR);
64 ctrl_outl(chan->count, PVR2_DMA_COUNT); 64 __raw_writel(chan->count, PVR2_DMA_COUNT);
65 ctrl_outl(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE); 65 __raw_writel(chan->mode & DMA_MODE_MASK, PVR2_DMA_MODE);
66 66
67 return 0; 67 return 0;
68} 68}
diff --git a/arch/sh/drivers/dma/dma-sh.c b/arch/sh/drivers/dma/dma-sh.c
index 37fb5b8bbc3..565cc1a4cbb 100644
--- a/arch/sh/drivers/dma/dma-sh.c
+++ b/arch/sh/drivers/dma/dma-sh.c
@@ -54,7 +54,7 @@ static inline unsigned int get_dmte_irq(unsigned int chan)
54 */ 54 */
55static inline unsigned int calc_xmit_shift(struct dma_channel *chan) 55static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
56{ 56{
57 u32 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); 57 u32 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
58 58
59 return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT]; 59 return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
60} 60}
@@ -70,13 +70,13 @@ static irqreturn_t dma_tei(int irq, void *dev_id)
70 struct dma_channel *chan = dev_id; 70 struct dma_channel *chan = dev_id;
71 u32 chcr; 71 u32 chcr;
72 72
73 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); 73 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
74 74
75 if (!(chcr & CHCR_TE)) 75 if (!(chcr & CHCR_TE))
76 return IRQ_NONE; 76 return IRQ_NONE;
77 77
78 chcr &= ~(CHCR_IE | CHCR_DE); 78 chcr &= ~(CHCR_IE | CHCR_DE);
79 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); 79 __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
80 80
81 wake_up(&chan->wait_queue); 81 wake_up(&chan->wait_queue);
82 82
@@ -115,7 +115,7 @@ sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
115 chan->flags &= ~DMA_TEI_CAPABLE; 115 chan->flags &= ~DMA_TEI_CAPABLE;
116 } 116 }
117 117
118 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); 118 __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
119 119
120 chan->flags |= DMA_CONFIGURED; 120 chan->flags |= DMA_CONFIGURED;
121 return 0; 121 return 0;
@@ -126,13 +126,13 @@ static void sh_dmac_enable_dma(struct dma_channel *chan)
126 int irq; 126 int irq;
127 u32 chcr; 127 u32 chcr;
128 128
129 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); 129 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
130 chcr |= CHCR_DE; 130 chcr |= CHCR_DE;
131 131
132 if (chan->flags & DMA_TEI_CAPABLE) 132 if (chan->flags & DMA_TEI_CAPABLE)
133 chcr |= CHCR_IE; 133 chcr |= CHCR_IE;
134 134
135 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); 135 __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
136 136
137 if (chan->flags & DMA_TEI_CAPABLE) { 137 if (chan->flags & DMA_TEI_CAPABLE) {
138 irq = get_dmte_irq(chan->chan); 138 irq = get_dmte_irq(chan->chan);
@@ -150,9 +150,9 @@ static void sh_dmac_disable_dma(struct dma_channel *chan)
150 disable_irq(irq); 150 disable_irq(irq);
151 } 151 }
152 152
153 chcr = ctrl_inl(dma_base_addr[chan->chan] + CHCR); 153 chcr = __raw_readl(dma_base_addr[chan->chan] + CHCR);
154 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE); 154 chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
155 ctrl_outl(chcr, (dma_base_addr[chan->chan] + CHCR)); 155 __raw_writel(chcr, (dma_base_addr[chan->chan] + CHCR));
156} 156}
157 157
158static int sh_dmac_xfer_dma(struct dma_channel *chan) 158static int sh_dmac_xfer_dma(struct dma_channel *chan)
@@ -183,12 +183,12 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
183 */ 183 */
184 if (chan->sar || (mach_is_dreamcast() && 184 if (chan->sar || (mach_is_dreamcast() &&
185 chan->chan == PVR2_CASCADE_CHAN)) 185 chan->chan == PVR2_CASCADE_CHAN))
186 ctrl_outl(chan->sar, (dma_base_addr[chan->chan]+SAR)); 186 __raw_writel(chan->sar, (dma_base_addr[chan->chan]+SAR));
187 if (chan->dar || (mach_is_dreamcast() && 187 if (chan->dar || (mach_is_dreamcast() &&
188 chan->chan == PVR2_CASCADE_CHAN)) 188 chan->chan == PVR2_CASCADE_CHAN))
189 ctrl_outl(chan->dar, (dma_base_addr[chan->chan] + DAR)); 189 __raw_writel(chan->dar, (dma_base_addr[chan->chan] + DAR));
190 190
191 ctrl_outl(chan->count >> calc_xmit_shift(chan), 191 __raw_writel(chan->count >> calc_xmit_shift(chan),
192 (dma_base_addr[chan->chan] + TCR)); 192 (dma_base_addr[chan->chan] + TCR));
193 193
194 sh_dmac_enable_dma(chan); 194 sh_dmac_enable_dma(chan);
@@ -198,10 +198,10 @@ static int sh_dmac_xfer_dma(struct dma_channel *chan)
198 198
199static int sh_dmac_get_dma_residue(struct dma_channel *chan) 199static int sh_dmac_get_dma_residue(struct dma_channel *chan)
200{ 200{
201 if (!(ctrl_inl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE)) 201 if (!(__raw_readl(dma_base_addr[chan->chan] + CHCR) & CHCR_DE))
202 return 0; 202 return 0;
203 203
204 return ctrl_inl(dma_base_addr[chan->chan] + TCR) 204 return __raw_readl(dma_base_addr[chan->chan] + TCR)
205 << calc_xmit_shift(chan); 205 << calc_xmit_shift(chan);
206} 206}
207 207
diff --git a/arch/sh/drivers/dma/dmabrg.c b/arch/sh/drivers/dma/dmabrg.c
index 5e22689c2fc..72622e30761 100644
--- a/arch/sh/drivers/dma/dmabrg.c
+++ b/arch/sh/drivers/dma/dmabrg.c
@@ -86,8 +86,8 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
86 unsigned long dcr; 86 unsigned long dcr;
87 unsigned int i; 87 unsigned int i;
88 88
89 dcr = ctrl_inl(DMABRGCR); 89 dcr = __raw_readl(DMABRGCR);
90 ctrl_outl(dcr & ~0x00ff0003, DMABRGCR); /* ack all */ 90 __raw_writel(dcr & ~0x00ff0003, DMABRGCR); /* ack all */
91 dcr &= dcr >> 8; /* ignore masked */ 91 dcr &= dcr >> 8; /* ignore masked */
92 92
93 /* USB stuff, get it out of the way first */ 93 /* USB stuff, get it out of the way first */
@@ -109,17 +109,17 @@ static irqreturn_t dmabrg_irq(int irq, void *data)
109static void dmabrg_disable_irq(unsigned int dmairq) 109static void dmabrg_disable_irq(unsigned int dmairq)
110{ 110{
111 unsigned long dcr; 111 unsigned long dcr;
112 dcr = ctrl_inl(DMABRGCR); 112 dcr = __raw_readl(DMABRGCR);
113 dcr &= ~(1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8)); 113 dcr &= ~(1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
114 ctrl_outl(dcr, DMABRGCR); 114 __raw_writel(dcr, DMABRGCR);
115} 115}
116 116
117static void dmabrg_enable_irq(unsigned int dmairq) 117static void dmabrg_enable_irq(unsigned int dmairq)
118{ 118{
119 unsigned long dcr; 119 unsigned long dcr;
120 dcr = ctrl_inl(DMABRGCR); 120 dcr = __raw_readl(DMABRGCR);
121 dcr |= (1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8)); 121 dcr |= (1 << ((dmairq > 1) ? dmairq + 22 : dmairq + 8));
122 ctrl_outl(dcr, DMABRGCR); 122 __raw_writel(dcr, DMABRGCR);
123} 123}
124 124
125int dmabrg_request_irq(unsigned int dmairq, void(*handler)(void*), 125int dmabrg_request_irq(unsigned int dmairq, void(*handler)(void*),
@@ -165,13 +165,13 @@ static int __init dmabrg_init(void)
165 printk(KERN_INFO "DMABRG: DMAC ch0 not reserved!\n"); 165 printk(KERN_INFO "DMABRG: DMAC ch0 not reserved!\n");
166#endif 166#endif
167 167
168 ctrl_outl(0, DMABRGCR); 168 __raw_writel(0, DMABRGCR);
169 ctrl_outl(0, DMACHCR0); 169 __raw_writel(0, DMACHCR0);
170 ctrl_outl(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */ 170 __raw_writel(0x94000000, DMARSRA); /* enable DMABRG in DMAC 0 */
171 171
172 /* enable DMABRG mode, enable the DMAC */ 172 /* enable DMABRG mode, enable the DMAC */
173 or = ctrl_inl(DMAOR); 173 or = __raw_readl(DMAOR);
174 ctrl_outl(or | DMAOR_BRG | DMAOR_DMEN, DMAOR); 174 __raw_writel(or | DMAOR_BRG | DMAOR_DMEN, DMAOR);
175 175
176 ret = request_irq(DMABRGI0, dmabrg_irq, IRQF_DISABLED, 176 ret = request_irq(DMABRGI0, dmabrg_irq, IRQF_DISABLED,
177 "DMABRG USB address error", NULL); 177 "DMABRG USB address error", NULL);
diff --git a/arch/sh/drivers/pci/fixups-rts7751r2d.c b/arch/sh/drivers/pci/fixups-rts7751r2d.c
index 7898f14d664..e248516118a 100644
--- a/arch/sh/drivers/pci/fixups-rts7751r2d.c
+++ b/arch/sh/drivers/pci/fixups-rts7751r2d.c
@@ -43,7 +43,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
43{ 43{
44 unsigned long bcr1, mcr; 44 unsigned long bcr1, mcr;
45 45
46 bcr1 = ctrl_inl(SH7751_BCR1); 46 bcr1 = __raw_readl(SH7751_BCR1);
47 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ 47 bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */
48 pci_write_reg(chan, bcr1, SH4_PCIBCR1); 48 pci_write_reg(chan, bcr1, SH4_PCIBCR1);
49 49
@@ -54,7 +54,7 @@ int pci_fixup_pcic(struct pci_channel *chan)
54 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1); 54 pci_write_reg(chan, 0xfb900047, SH7751_PCICONF1);
55 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4); 55 pci_write_reg(chan, 0xab000001, SH7751_PCICONF4);
56 56
57 mcr = ctrl_inl(SH7751_MCR); 57 mcr = __raw_readl(SH7751_MCR);
58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; 58 mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF;
59 pci_write_reg(chan, mcr, SH4_PCIMCR); 59 pci_write_reg(chan, mcr, SH4_PCIMCR);
60 60
diff --git a/arch/sh/drivers/pci/pci-sh4.h b/arch/sh/drivers/pci/pci-sh4.h
index 3d5296cde62..4744a7dede0 100644
--- a/arch/sh/drivers/pci/pci-sh4.h
+++ b/arch/sh/drivers/pci/pci-sh4.h
@@ -167,13 +167,13 @@ struct sh4_pci_address_map {
167static inline void pci_write_reg(struct pci_channel *chan, 167static inline void pci_write_reg(struct pci_channel *chan,
168 unsigned long val, unsigned long reg) 168 unsigned long val, unsigned long reg)
169{ 169{
170 ctrl_outl(val, chan->reg_base + reg); 170 __raw_writel(val, chan->reg_base + reg);
171} 171}
172 172
173static inline unsigned long pci_read_reg(struct pci_channel *chan, 173static inline unsigned long pci_read_reg(struct pci_channel *chan,
174 unsigned long reg) 174 unsigned long reg)
175{ 175{
176 return ctrl_inl(chan->reg_base + reg); 176 return __raw_readl(chan->reg_base + reg);
177} 177}
178 178
179#endif /* __PCI_SH4_H */ 179#endif /* __PCI_SH4_H */
diff --git a/arch/sh/drivers/pci/pci-sh5.h b/arch/sh/drivers/pci/pci-sh5.h
index f277628221f..3f01decb430 100644
--- a/arch/sh/drivers/pci/pci-sh5.h
+++ b/arch/sh/drivers/pci/pci-sh5.h
@@ -86,14 +86,14 @@ extern unsigned long pcicr_virt;
86/* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */ 86/* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */
87 87
88/* Write I/O functions */ 88/* Write I/O functions */
89#define SH5PCI_WRITE(reg,val) ctrl_outl((u32)(val),PCISH5_ICR_REG(reg)) 89#define SH5PCI_WRITE(reg,val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg))
90#define SH5PCI_WRITE_SHORT(reg,val) ctrl_outw((u16)(val),PCISH5_ICR_REG(reg)) 90#define SH5PCI_WRITE_SHORT(reg,val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg))
91#define SH5PCI_WRITE_BYTE(reg,val) ctrl_outb((u8)(val),PCISH5_ICR_REG(reg)) 91#define SH5PCI_WRITE_BYTE(reg,val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg))
92 92
93/* Read I/O functions */ 93/* Read I/O functions */
94#define SH5PCI_READ(reg) ctrl_inl(PCISH5_ICR_REG(reg)) 94#define SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg))
95#define SH5PCI_READ_SHORT(reg) ctrl_inw(PCISH5_ICR_REG(reg)) 95#define SH5PCI_READ_SHORT(reg) __raw_readw(PCISH5_ICR_REG(reg))
96#define SH5PCI_READ_BYTE(reg) ctrl_inb(PCISH5_ICR_REG(reg)) 96#define SH5PCI_READ_BYTE(reg) __raw_readb(PCISH5_ICR_REG(reg))
97 97
98/* Set PCI config bits */ 98/* Set PCI config bits */
99#define SET_CONFIG_BITS(bus,devfn,where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000) 99#define SET_CONFIG_BITS(bus,devfn,where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000)
diff --git a/arch/sh/drivers/pci/pci-sh7751.c b/arch/sh/drivers/pci/pci-sh7751.c
index 70c1999a0ec..2455cf32db5 100644
--- a/arch/sh/drivers/pci/pci-sh7751.c
+++ b/arch/sh/drivers/pci/pci-sh7751.c
@@ -97,9 +97,9 @@ static int __init sh7751_pci_init(void)
97 return ret; 97 return ret;
98 98
99 /* Set the BCR's to enable PCI access */ 99 /* Set the BCR's to enable PCI access */
100 reg = ctrl_inl(SH7751_BCR1); 100 reg = __raw_readl(SH7751_BCR1);
101 reg |= 0x80000; 101 reg |= 0x80000;
102 ctrl_outl(reg, SH7751_BCR1); 102 __raw_writel(reg, SH7751_BCR1);
103 103
104 /* Turn the clocks back on (not done in reset)*/ 104 /* Turn the clocks back on (not done in reset)*/
105 pci_write_reg(chan, 0, SH4_PCICLKR); 105 pci_write_reg(chan, 0, SH4_PCICLKR);
@@ -159,13 +159,13 @@ static int __init sh7751_pci_init(void)
159 return -1; 159 return -1;
160 160
161 /* configure the wait control registers */ 161 /* configure the wait control registers */
162 word = ctrl_inl(SH7751_WCR1); 162 word = __raw_readl(SH7751_WCR1);
163 pci_write_reg(chan, word, SH4_PCIWCR1); 163 pci_write_reg(chan, word, SH4_PCIWCR1);
164 word = ctrl_inl(SH7751_WCR2); 164 word = __raw_readl(SH7751_WCR2);
165 pci_write_reg(chan, word, SH4_PCIWCR2); 165 pci_write_reg(chan, word, SH4_PCIWCR2);
166 word = ctrl_inl(SH7751_WCR3); 166 word = __raw_readl(SH7751_WCR3);
167 pci_write_reg(chan, word, SH4_PCIWCR3); 167 pci_write_reg(chan, word, SH4_PCIWCR3);
168 word = ctrl_inl(SH7751_MCR); 168 word = __raw_readl(SH7751_MCR);
169 pci_write_reg(chan, word, SH4_PCIMCR); 169 pci_write_reg(chan, word, SH4_PCIMCR);
170 170
171 /* NOTE: I'm ignoring the PCI error IRQs for now.. 171 /* NOTE: I'm ignoring the PCI error IRQs for now..
diff --git a/arch/sh/drivers/superhyway/ops-sh4-202.c b/arch/sh/drivers/superhyway/ops-sh4-202.c
index 3b14bf860db..6da62e9475c 100644
--- a/arch/sh/drivers/superhyway/ops-sh4-202.c
+++ b/arch/sh/drivers/superhyway/ops-sh4-202.c
@@ -134,8 +134,8 @@ static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr)
134 * 134 *
135 * Do not trust the documentation, for it is evil. 135 * Do not trust the documentation, for it is evil.
136 */ 136 */
137 vcrh = ctrl_inl(base); 137 vcrh = __raw_readl(base);
138 vcrl = ctrl_inl(base + sizeof(u32)); 138 vcrl = __raw_readl(base + sizeof(u32));
139 139
140 tmp = ((u64)vcrh << 32) | vcrl; 140 tmp = ((u64)vcrh << 32) | vcrl;
141 memcpy(vcr, &tmp, sizeof(u64)); 141 memcpy(vcr, &tmp, sizeof(u64));
@@ -147,8 +147,8 @@ static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr)
147{ 147{
148 u64 tmp = *(u64 *)&vcr; 148 u64 tmp = *(u64 *)&vcr;
149 149
150 ctrl_outl((tmp >> 32) & 0xffffffff, base); 150 __raw_writel((tmp >> 32) & 0xffffffff, base);
151 ctrl_outl(tmp & 0xffffffff, base + sizeof(u32)); 151 __raw_writel(tmp & 0xffffffff, base + sizeof(u32));
152 152
153 return 0; 153 return 0;
154} 154}
diff --git a/arch/sh/include/asm/dma-sh.h b/arch/sh/include/asm/dma-sh.h
index 78eed3e0bdf..47de1097699 100644
--- a/arch/sh/include/asm/dma-sh.h
+++ b/arch/sh/include/asm/dma-sh.h
@@ -20,14 +20,14 @@
20 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 20 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
21 defined(CONFIG_CPU_SUBTYPE_SH7785) 21 defined(CONFIG_CPU_SUBTYPE_SH7785)
22#define dmaor_read_reg(n) \ 22#define dmaor_read_reg(n) \
23 (n ? ctrl_inw(SH_DMAC_BASE1 + DMAOR) \ 23 (n ? __raw_readw(SH_DMAC_BASE1 + DMAOR) \
24 : ctrl_inw(SH_DMAC_BASE0 + DMAOR)) 24 : __raw_readw(SH_DMAC_BASE0 + DMAOR))
25#define dmaor_write_reg(n, data) \ 25#define dmaor_write_reg(n, data) \
26 (n ? ctrl_outw(data, SH_DMAC_BASE1 + DMAOR) \ 26 (n ? __raw_writew(data, SH_DMAC_BASE1 + DMAOR) \
27 : ctrl_outw(data, SH_DMAC_BASE0 + DMAOR)) 27 : __raw_writew(data, SH_DMAC_BASE0 + DMAOR))
28#else /* Other CPU */ 28#else /* Other CPU */
29#define dmaor_read_reg(n) ctrl_inw(SH_DMAC_BASE0 + DMAOR) 29#define dmaor_read_reg(n) __raw_readw(SH_DMAC_BASE0 + DMAOR)
30#define dmaor_write_reg(n, data) ctrl_outw(data, SH_DMAC_BASE0 + DMAOR) 30#define dmaor_write_reg(n, data) __raw_writew(data, SH_DMAC_BASE0 + DMAOR)
31#endif 31#endif
32 32
33static int dmte_irq_map[] __maybe_unused = { 33static int dmte_irq_map[] __maybe_unused = {
diff --git a/arch/sh/include/asm/mmu_context.h b/arch/sh/include/asm/mmu_context.h
index 41080b173a7..384c7471a37 100644
--- a/arch/sh/include/asm/mmu_context.h
+++ b/arch/sh/include/asm/mmu_context.h
@@ -158,7 +158,7 @@ static inline void enable_mmu(void)
158 unsigned int cpu = smp_processor_id(); 158 unsigned int cpu = smp_processor_id();
159 159
160 /* Enable MMU */ 160 /* Enable MMU */
161 ctrl_outl(MMU_CONTROL_INIT, MMUCR); 161 __raw_writel(MMU_CONTROL_INIT, MMUCR);
162 ctrl_barrier(); 162 ctrl_barrier();
163 163
164 if (asid_cache(cpu) == NO_CONTEXT) 164 if (asid_cache(cpu) == NO_CONTEXT)
@@ -171,9 +171,9 @@ static inline void disable_mmu(void)
171{ 171{
172 unsigned long cr; 172 unsigned long cr;
173 173
174 cr = ctrl_inl(MMUCR); 174 cr = __raw_readl(MMUCR);
175 cr &= ~MMU_CONTROL_INIT; 175 cr &= ~MMU_CONTROL_INIT;
176 ctrl_outl(cr, MMUCR); 176 __raw_writel(cr, MMUCR);
177 177
178 ctrl_barrier(); 178 ctrl_barrier();
179} 179}
diff --git a/arch/sh/include/asm/mmu_context_32.h b/arch/sh/include/asm/mmu_context_32.h
index 8ef800c549a..10e2e17210d 100644
--- a/arch/sh/include/asm/mmu_context_32.h
+++ b/arch/sh/include/asm/mmu_context_32.h
@@ -49,11 +49,11 @@ static inline unsigned long get_asid(void)
49/* MMU_TTB is used for optimizing the fault handling. */ 49/* MMU_TTB is used for optimizing the fault handling. */
50static inline void set_TTB(pgd_t *pgd) 50static inline void set_TTB(pgd_t *pgd)
51{ 51{
52 ctrl_outl((unsigned long)pgd, MMU_TTB); 52 __raw_writel((unsigned long)pgd, MMU_TTB);
53} 53}
54 54
55static inline pgd_t *get_TTB(void) 55static inline pgd_t *get_TTB(void)
56{ 56{
57 return (pgd_t *)ctrl_inl(MMU_TTB); 57 return (pgd_t *)__raw_readl(MMU_TTB);
58} 58}
59#endif /* __ASM_SH_MMU_CONTEXT_32_H */ 59#endif /* __ASM_SH_MMU_CONTEXT_32_H */
diff --git a/arch/sh/include/asm/watchdog.h b/arch/sh/include/asm/watchdog.h
index 19dfff5c851..85a7aca7fb8 100644
--- a/arch/sh/include/asm/watchdog.h
+++ b/arch/sh/include/asm/watchdog.h
@@ -70,7 +70,7 @@
70 */ 70 */
71static inline __u32 sh_wdt_read_cnt(void) 71static inline __u32 sh_wdt_read_cnt(void)
72{ 72{
73 return ctrl_inl(WTCNT_R); 73 return __raw_readl(WTCNT_R);
74} 74}
75 75
76/** 76/**
@@ -82,7 +82,7 @@ static inline __u32 sh_wdt_read_cnt(void)
82 */ 82 */
83static inline void sh_wdt_write_cnt(__u32 val) 83static inline void sh_wdt_write_cnt(__u32 val)
84{ 84{
85 ctrl_outl((WTCNT_HIGH << 24) | (__u32)val, WTCNT); 85 __raw_writel((WTCNT_HIGH << 24) | (__u32)val, WTCNT);
86} 86}
87 87
88/** 88/**
@@ -94,7 +94,7 @@ static inline void sh_wdt_write_cnt(__u32 val)
94 */ 94 */
95static inline void sh_wdt_write_bst(__u32 val) 95static inline void sh_wdt_write_bst(__u32 val)
96{ 96{
97 ctrl_outl((WTBST_HIGH << 24) | (__u32)val, WTBST); 97 __raw_writel((WTBST_HIGH << 24) | (__u32)val, WTBST);
98} 98}
99/** 99/**
100 * sh_wdt_read_csr - Read from Control/Status Register 100 * sh_wdt_read_csr - Read from Control/Status Register
@@ -103,7 +103,7 @@ static inline void sh_wdt_write_bst(__u32 val)
103 */ 103 */
104static inline __u32 sh_wdt_read_csr(void) 104static inline __u32 sh_wdt_read_csr(void)
105{ 105{
106 return ctrl_inl(WTCSR_R); 106 return __raw_readl(WTCSR_R);
107} 107}
108 108
109/** 109/**
@@ -115,7 +115,7 @@ static inline __u32 sh_wdt_read_csr(void)
115 */ 115 */
116static inline void sh_wdt_write_csr(__u32 val) 116static inline void sh_wdt_write_csr(__u32 val)
117{ 117{
118 ctrl_outl((WTCSR_HIGH << 24) | (__u32)val, WTCSR); 118 __raw_writel((WTCSR_HIGH << 24) | (__u32)val, WTCSR);
119} 119}
120#else 120#else
121/** 121/**
@@ -124,7 +124,7 @@ static inline void sh_wdt_write_csr(__u32 val)
124 */ 124 */
125static inline __u8 sh_wdt_read_cnt(void) 125static inline __u8 sh_wdt_read_cnt(void)
126{ 126{
127 return ctrl_inb(WTCNT_R); 127 return __raw_readb(WTCNT_R);
128} 128}
129 129
130/** 130/**
@@ -136,7 +136,7 @@ static inline __u8 sh_wdt_read_cnt(void)
136 */ 136 */
137static inline void sh_wdt_write_cnt(__u8 val) 137static inline void sh_wdt_write_cnt(__u8 val)
138{ 138{
139 ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, WTCNT); 139 __raw_writew((WTCNT_HIGH << 8) | (__u16)val, WTCNT);
140} 140}
141 141
142/** 142/**
@@ -146,7 +146,7 @@ static inline void sh_wdt_write_cnt(__u8 val)
146 */ 146 */
147static inline __u8 sh_wdt_read_csr(void) 147static inline __u8 sh_wdt_read_csr(void)
148{ 148{
149 return ctrl_inb(WTCSR_R); 149 return __raw_readb(WTCSR_R);
150} 150}
151 151
152/** 152/**
@@ -158,7 +158,7 @@ static inline __u8 sh_wdt_read_csr(void)
158 */ 158 */
159static inline void sh_wdt_write_csr(__u8 val) 159static inline void sh_wdt_write_csr(__u8 val)
160{ 160{
161 ctrl_outw((WTCSR_HIGH << 8) | (__u16)val, WTCSR); 161 __raw_writew((WTCSR_HIGH << 8) | (__u16)val, WTCSR);
162} 162}
163#endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */ 163#endif /* CONFIG_CPU_SUBTYPE_SH7785 || CONFIG_CPU_SUBTYPE_SH7780 */
164#endif /* __KERNEL__ */ 164#endif /* __KERNEL__ */
diff --git a/arch/sh/include/cpu-sh2/cpu/watchdog.h b/arch/sh/include/cpu-sh2/cpu/watchdog.h
index 393161c9c6d..1eab8aa63a6 100644
--- a/arch/sh/include/cpu-sh2/cpu/watchdog.h
+++ b/arch/sh/include/cpu-sh2/cpu/watchdog.h
@@ -44,7 +44,7 @@ static inline __u8 sh_wdt_read_rstcsr(void)
44 /* 44 /*
45 * Same read/write brain-damage as for WTCNT here.. 45 * Same read/write brain-damage as for WTCNT here..
46 */ 46 */
47 return ctrl_inb(RSTCSR_R); 47 return __raw_readb(RSTCSR_R);
48} 48}
49 49
50/** 50/**
@@ -62,7 +62,7 @@ static inline void sh_wdt_write_rstcsr(__u8 val)
62 * we can't presently touch the WOVF bit, since the upper byte 62 * we can't presently touch the WOVF bit, since the upper byte
63 * has to be swapped for this. So just leave it alone.. 63 * has to be swapped for this. So just leave it alone..
64 */ 64 */
65 ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR); 65 __raw_writeb((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
66} 66}
67 67
68#endif /* __ASM_CPU_SH2_WATCHDOG_H */ 68#endif /* __ASM_CPU_SH2_WATCHDOG_H */
diff --git a/arch/sh/include/cpu-sh3/cpu/dac.h b/arch/sh/include/cpu-sh3/cpu/dac.h
index 05fda8316eb..98f1d15f0ab 100644
--- a/arch/sh/include/cpu-sh3/cpu/dac.h
+++ b/arch/sh/include/cpu-sh3/cpu/dac.h
@@ -17,25 +17,25 @@
17static __inline__ void sh_dac_enable(int channel) 17static __inline__ void sh_dac_enable(int channel)
18{ 18{
19 unsigned char v; 19 unsigned char v;
20 v = ctrl_inb(DACR); 20 v = __raw_readb(DACR);
21 if(channel) v |= DACR_DAOE1; 21 if(channel) v |= DACR_DAOE1;
22 else v |= DACR_DAOE0; 22 else v |= DACR_DAOE0;
23 ctrl_outb(v,DACR); 23 __raw_writeb(v,DACR);
24} 24}
25 25
26static __inline__ void sh_dac_disable(int channel) 26static __inline__ void sh_dac_disable(int channel)
27{ 27{
28 unsigned char v; 28 unsigned char v;
29 v = ctrl_inb(DACR); 29 v = __raw_readb(DACR);
30 if(channel) v &= ~DACR_DAOE1; 30 if(channel) v &= ~DACR_DAOE1;
31 else v &= ~DACR_DAOE0; 31 else v &= ~DACR_DAOE0;
32 ctrl_outb(v,DACR); 32 __raw_writeb(v,DACR);
33} 33}
34 34
35static __inline__ void sh_dac_output(u8 value, int channel) 35static __inline__ void sh_dac_output(u8 value, int channel)
36{ 36{
37 if(channel) ctrl_outb(value,DADR1); 37 if(channel) __raw_writeb(value,DADR1);
38 else ctrl_outb(value,DADR0); 38 else __raw_writeb(value,DADR0);
39} 39}
40 40
41#endif /* __ASM_CPU_SH3_DAC_H */ 41#endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/arch/sh/include/mach-common/mach/magicpanelr2.h b/arch/sh/include/mach-common/mach/magicpanelr2.h
index c644a77ee35..183a2f74425 100644
--- a/arch/sh/include/mach-common/mach/magicpanelr2.h
+++ b/arch/sh/include/mach-common/mach/magicpanelr2.h
@@ -19,12 +19,12 @@
19#include <asm/io_generic.h> 19#include <asm/io_generic.h>
20 20
21 21
22#define SETBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) | mask, reg) 22#define SETBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) | mask, reg)
23#define SETBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) | mask, reg) 23#define SETBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) | mask, reg)
24#define SETBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) | mask, reg) 24#define SETBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) | mask, reg)
25#define CLRBITS_OUTB(mask, reg) ctrl_outb(ctrl_inb(reg) & ~mask, reg) 25#define CLRBITS_OUTB(mask, reg) __raw_writeb(__raw_readb(reg) & ~mask, reg)
26#define CLRBITS_OUTW(mask, reg) ctrl_outw(ctrl_inw(reg) & ~mask, reg) 26#define CLRBITS_OUTW(mask, reg) __raw_writew(__raw_readw(reg) & ~mask, reg)
27#define CLRBITS_OUTL(mask, reg) ctrl_outl(ctrl_inl(reg) & ~mask, reg) 27#define CLRBITS_OUTL(mask, reg) __raw_writel(__raw_readl(reg) & ~mask, reg)
28 28
29 29
30#define PA_LED PORT_PADR /* LED */ 30#define PA_LED PORT_PADR /* LED */
diff --git a/arch/sh/kernel/cpu/adc.c b/arch/sh/kernel/cpu/adc.c
index da3d6877f93..d307571d54b 100644
--- a/arch/sh/kernel/cpu/adc.c
+++ b/arch/sh/kernel/cpu/adc.c
@@ -18,19 +18,19 @@ int adc_single(unsigned int channel)
18 18
19 off = (channel & 0x03) << 2; 19 off = (channel & 0x03) << 2;
20 20
21 csr = ctrl_inb(ADCSR); 21 csr = __raw_readb(ADCSR);
22 csr = channel | ADCSR_ADST | ADCSR_CKS; 22 csr = channel | ADCSR_ADST | ADCSR_CKS;
23 ctrl_outb(csr, ADCSR); 23 __raw_writeb(csr, ADCSR);
24 24
25 do { 25 do {
26 csr = ctrl_inb(ADCSR); 26 csr = __raw_readb(ADCSR);
27 } while ((csr & ADCSR_ADF) == 0); 27 } while ((csr & ADCSR_ADF) == 0);
28 28
29 csr &= ~(ADCSR_ADF | ADCSR_ADST); 29 csr &= ~(ADCSR_ADF | ADCSR_ADST);
30 ctrl_outb(csr, ADCSR); 30 __raw_writeb(csr, ADCSR);
31 31
32 return (((ctrl_inb(ADDRAH + off) << 8) | 32 return (((__raw_readb(ADDRAH + off) << 8) |
33 ctrl_inb(ADDRAL + off)) >> 6); 33 __raw_readb(ADDRAL + off)) >> 6);
34} 34}
35 35
36EXPORT_SYMBOL(adc_single); 36EXPORT_SYMBOL(adc_single);
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index 05a7d2a373b..6311b0b1789 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -61,10 +61,10 @@ onchip_setup(dsp);
61static void __init speculative_execution_init(void) 61static void __init speculative_execution_init(void)
62{ 62{
63 /* Clear RABD */ 63 /* Clear RABD */
64 ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM); 64 __raw_writel(__raw_readl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
65 65
66 /* Flush the update */ 66 /* Flush the update */
67 (void)ctrl_inl(CPUOPM); 67 (void)__raw_readl(CPUOPM);
68 ctrl_barrier(); 68 ctrl_barrier();
69} 69}
70#else 70#else
@@ -111,7 +111,7 @@ static void cache_init(void)
111 unsigned long ccr, flags; 111 unsigned long ccr, flags;
112 112
113 jump_to_uncached(); 113 jump_to_uncached();
114 ccr = ctrl_inl(CCR); 114 ccr = __raw_readl(CCR);
115 115
116 /* 116 /*
117 * At this point we don't know whether the cache is enabled or not - a 117 * At this point we don't know whether the cache is enabled or not - a
@@ -155,7 +155,7 @@ static void cache_init(void)
155 for (addr = addrstart; 155 for (addr = addrstart;
156 addr < addrstart + waysize; 156 addr < addrstart + waysize;
157 addr += current_cpu_data.dcache.linesz) 157 addr += current_cpu_data.dcache.linesz)
158 ctrl_outl(0, addr); 158 __raw_writel(0, addr);
159 159
160 addrstart += current_cpu_data.dcache.way_incr; 160 addrstart += current_cpu_data.dcache.way_incr;
161 } while (--ways); 161 } while (--ways);
@@ -188,7 +188,7 @@ static void cache_init(void)
188 188
189 l2_cache_init(); 189 l2_cache_init();
190 190
191 ctrl_outl(flags, CCR); 191 __raw_writel(flags, CCR);
192 back_to_cached(); 192 back_to_cached();
193} 193}
194#else 194#else
diff --git a/arch/sh/kernel/cpu/irq/intc-sh5.c b/arch/sh/kernel/cpu/irq/intc-sh5.c
index 06e7e2959b5..96a23958394 100644
--- a/arch/sh/kernel/cpu/irq/intc-sh5.c
+++ b/arch/sh/kernel/cpu/irq/intc-sh5.c
@@ -123,7 +123,7 @@ static void enable_intc_irq(unsigned int irq)
123 bitmask = 1 << (irq - 32); 123 bitmask = 1 << (irq - 32);
124 } 124 }
125 125
126 ctrl_outl(bitmask, reg); 126 __raw_writel(bitmask, reg);
127} 127}
128 128
129static void disable_intc_irq(unsigned int irq) 129static void disable_intc_irq(unsigned int irq)
@@ -139,7 +139,7 @@ static void disable_intc_irq(unsigned int irq)
139 bitmask = 1 << (irq - 32); 139 bitmask = 1 << (irq - 32);
140 } 140 }
141 141
142 ctrl_outl(bitmask, reg); 142 __raw_writel(bitmask, reg);
143} 143}
144 144
145static void mask_and_ack_intc(unsigned int irq) 145static void mask_and_ack_intc(unsigned int irq)
@@ -170,11 +170,11 @@ void __init plat_irq_setup(void)
170 170
171 171
172 /* Disable all interrupts and set all priorities to 0 to avoid trouble */ 172 /* Disable all interrupts and set all priorities to 0 to avoid trouble */
173 ctrl_outl(-1, INTC_INTDSB_0); 173 __raw_writel(-1, INTC_INTDSB_0);
174 ctrl_outl(-1, INTC_INTDSB_1); 174 __raw_writel(-1, INTC_INTDSB_1);
175 175
176 for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8) 176 for (reg = INTC_INTPRI_0, i = 0; i < INTC_INTPRI_PREGS; i++, reg += 8)
177 ctrl_outl( NO_PRIORITY, reg); 177 __raw_writel( NO_PRIORITY, reg);
178 178
179 179
180#ifdef CONFIG_SH_CAYMAN 180#ifdef CONFIG_SH_CAYMAN
@@ -199,7 +199,7 @@ void __init plat_irq_setup(void)
199 reg = INTC_ICR_SET; 199 reg = INTC_ICR_SET;
200 i = IRQ_IRL0; 200 i = IRQ_IRL0;
201 } 201 }
202 ctrl_outl(INTC_ICR_IRLM, reg); 202 __raw_writel(INTC_ICR_IRLM, reg);
203 203
204 /* Set interrupt priorities according to platform description */ 204 /* Set interrupt priorities according to platform description */
205 for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) { 205 for (data = 0, reg = INTC_INTPRI_0; i < NR_INTC_IRQS; i++) {
@@ -207,7 +207,7 @@ void __init plat_irq_setup(void)
207 ((i % INTC_INTPRI_PPREG) * 4); 207 ((i % INTC_INTPRI_PPREG) * 4);
208 if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) { 208 if ((i % INTC_INTPRI_PPREG) == (INTC_INTPRI_PPREG - 1)) {
209 /* Upon the 7th, set Priority Register */ 209 /* Upon the 7th, set Priority Register */
210 ctrl_outl(data, reg); 210 __raw_writel(data, reg);
211 data = 0; 211 data = 0;
212 reg += 8; 212 reg += 8;
213 } 213 }
diff --git a/arch/sh/kernel/cpu/sh2/clock-sh7619.c b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
index 4fe863170e3..0c9f24d7a02 100644
--- a/arch/sh/kernel/cpu/sh2/clock-sh7619.c
+++ b/arch/sh/kernel/cpu/sh2/clock-sh7619.c
@@ -31,7 +31,7 @@ static const int pfc_divisors[] = {1,2,0,4};
31 31
32static void master_clk_init(struct clk *clk) 32static void master_clk_init(struct clk *clk)
33{ 33{
34 clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; 34 clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
35} 35}
36 36
37static struct clk_ops sh7619_master_clk_ops = { 37static struct clk_ops sh7619_master_clk_ops = {
@@ -40,7 +40,7 @@ static struct clk_ops sh7619_master_clk_ops = {
40 40
41static unsigned long module_clk_recalc(struct clk *clk) 41static unsigned long module_clk_recalc(struct clk *clk)
42{ 42{
43 int idx = (ctrl_inw(FREQCR) & 0x0007); 43 int idx = (__raw_readw(FREQCR) & 0x0007);
44 return clk->parent->rate / pfc_divisors[idx]; 44 return clk->parent->rate / pfc_divisors[idx];
45} 45}
46 46
@@ -50,7 +50,7 @@ static struct clk_ops sh7619_module_clk_ops = {
50 50
51static unsigned long bus_clk_recalc(struct clk *clk) 51static unsigned long bus_clk_recalc(struct clk *clk)
52{ 52{
53 return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 7]; 53 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
54} 54}
55 55
56static struct clk_ops sh7619_bus_clk_ops = { 56static struct clk_ops sh7619_bus_clk_ops = {
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
index 7814c76159a..b26264dc2ae 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7201.c
@@ -34,7 +34,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
34 34
35static void master_clk_init(struct clk *clk) 35static void master_clk_init(struct clk *clk)
36{ 36{
37 return 10000000 * PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 37 return 10000000 * PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
38} 38}
39 39
40static struct clk_ops sh7201_master_clk_ops = { 40static struct clk_ops sh7201_master_clk_ops = {
@@ -43,7 +43,7 @@ static struct clk_ops sh7201_master_clk_ops = {
43 43
44static unsigned long module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int idx = (ctrl_inw(FREQCR) & 0x0007); 46 int idx = (__raw_readw(FREQCR) & 0x0007);
47 return clk->parent->rate / pfc_divisors[idx]; 47 return clk->parent->rate / pfc_divisors[idx];
48} 48}
49 49
@@ -53,7 +53,7 @@ static struct clk_ops sh7201_module_clk_ops = {
53 53
54static unsigned long bus_clk_recalc(struct clk *clk) 54static unsigned long bus_clk_recalc(struct clk *clk)
55{ 55{
56 int idx = (ctrl_inw(FREQCR) & 0x0007); 56 int idx = (__raw_readw(FREQCR) & 0x0007);
57 return clk->parent->rate / pfc_divisors[idx]; 57 return clk->parent->rate / pfc_divisors[idx];
58} 58}
59 59
@@ -63,7 +63,7 @@ static struct clk_ops sh7201_bus_clk_ops = {
63 63
64static unsigned long cpu_clk_recalc(struct clk *clk) 64static unsigned long cpu_clk_recalc(struct clk *clk)
65{ 65{
66 int idx = ((ctrl_inw(FREQCR) >> 4) & 0x0007); 66 int idx = ((__raw_readw(FREQCR) >> 4) & 0x0007);
67 return clk->parent->rate / ifc_divisors[idx]; 67 return clk->parent->rate / ifc_divisors[idx];
68} 68}
69 69
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
index 94098696510..7e75d8f7950 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7203.c
@@ -39,7 +39,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
39 39
40static void master_clk_init(struct clk *clk) 40static void master_clk_init(struct clk *clk)
41{ 41{
42 clk->rate *= pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0003] * PLL2 ; 42 clk->rate *= pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0003] * PLL2 ;
43} 43}
44 44
45static struct clk_ops sh7203_master_clk_ops = { 45static struct clk_ops sh7203_master_clk_ops = {
@@ -48,7 +48,7 @@ static struct clk_ops sh7203_master_clk_ops = {
48 48
49static unsigned long module_clk_recalc(struct clk *clk) 49static unsigned long module_clk_recalc(struct clk *clk)
50{ 50{
51 int idx = (ctrl_inw(FREQCR) & 0x0007); 51 int idx = (__raw_readw(FREQCR) & 0x0007);
52 return clk->parent->rate / pfc_divisors[idx]; 52 return clk->parent->rate / pfc_divisors[idx];
53} 53}
54 54
@@ -58,7 +58,7 @@ static struct clk_ops sh7203_module_clk_ops = {
58 58
59static unsigned long bus_clk_recalc(struct clk *clk) 59static unsigned long bus_clk_recalc(struct clk *clk)
60{ 60{
61 int idx = (ctrl_inw(FREQCR) & 0x0007); 61 int idx = (__raw_readw(FREQCR) & 0x0007);
62 return clk->parent->rate / pfc_divisors[idx-2]; 62 return clk->parent->rate / pfc_divisors[idx-2];
63} 63}
64 64
diff --git a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
index c2268bdecee..b27a5e2687a 100644
--- a/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
+++ b/arch/sh/kernel/cpu/sh2a/clock-sh7206.c
@@ -34,7 +34,7 @@ static const int pfc_divisors[]={1,2,3,4,6,8,12};
34 34
35static void master_clk_init(struct clk *clk) 35static void master_clk_init(struct clk *clk)
36{ 36{
37 clk->rate *= PLL2 * pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 37 clk->rate *= PLL2 * pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
38} 38}
39 39
40static struct clk_ops sh7206_master_clk_ops = { 40static struct clk_ops sh7206_master_clk_ops = {
@@ -43,7 +43,7 @@ static struct clk_ops sh7206_master_clk_ops = {
43 43
44static unsigned long module_clk_recalc(struct clk *clk) 44static unsigned long module_clk_recalc(struct clk *clk)
45{ 45{
46 int idx = (ctrl_inw(FREQCR) & 0x0007); 46 int idx = (__raw_readw(FREQCR) & 0x0007);
47 return clk->parent->rate / pfc_divisors[idx]; 47 return clk->parent->rate / pfc_divisors[idx];
48} 48}
49 49
@@ -53,7 +53,7 @@ static struct clk_ops sh7206_module_clk_ops = {
53 53
54static unsigned long bus_clk_recalc(struct clk *clk) 54static unsigned long bus_clk_recalc(struct clk *clk)
55{ 55{
56 return clk->parent->rate / pll1rate[(ctrl_inw(FREQCR) >> 8) & 0x0007]; 56 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 0x0007];
57} 57}
58 58
59static struct clk_ops sh7206_bus_clk_ops = { 59static struct clk_ops sh7206_bus_clk_ops = {
@@ -62,7 +62,7 @@ static struct clk_ops sh7206_bus_clk_ops = {
62 62
63static unsigned long cpu_clk_recalc(struct clk *clk) 63static unsigned long cpu_clk_recalc(struct clk *clk)
64{ 64{
65 int idx = (ctrl_inw(FREQCR) & 0x0007); 65 int idx = (__raw_readw(FREQCR) & 0x0007);
66 return clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh3.c b/arch/sh/kernel/cpu/sh3/clock-sh3.c
index 27b8738f0b0..b78384afac0 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh3.c
@@ -28,7 +28,7 @@ static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
28 28
29static void master_clk_init(struct clk *clk) 29static void master_clk_init(struct clk *clk)
30{ 30{
31 int frqcr = ctrl_inw(FRQCR); 31 int frqcr = __raw_readw(FRQCR);
32 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 32 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
33 33
34 clk->rate *= pfc_divisors[idx]; 34 clk->rate *= pfc_divisors[idx];
@@ -40,7 +40,7 @@ static struct clk_ops sh3_master_clk_ops = {
40 40
41static unsigned long module_clk_recalc(struct clk *clk) 41static unsigned long module_clk_recalc(struct clk *clk)
42{ 42{
43 int frqcr = ctrl_inw(FRQCR); 43 int frqcr = __raw_readw(FRQCR);
44 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 44 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
45 45
46 return clk->parent->rate / pfc_divisors[idx]; 46 return clk->parent->rate / pfc_divisors[idx];
@@ -52,7 +52,7 @@ static struct clk_ops sh3_module_clk_ops = {
52 52
53static unsigned long bus_clk_recalc(struct clk *clk) 53static unsigned long bus_clk_recalc(struct clk *clk)
54{ 54{
55 int frqcr = ctrl_inw(FRQCR); 55 int frqcr = __raw_readw(FRQCR);
56 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); 56 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
57 57
58 return clk->parent->rate / stc_multipliers[idx]; 58 return clk->parent->rate / stc_multipliers[idx];
@@ -64,7 +64,7 @@ static struct clk_ops sh3_bus_clk_ops = {
64 64
65static unsigned long cpu_clk_recalc(struct clk *clk) 65static unsigned long cpu_clk_recalc(struct clk *clk)
66{ 66{
67 int frqcr = ctrl_inw(FRQCR); 67 int frqcr = __raw_readw(FRQCR);
68 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 68 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
69 69
70 return clk->parent->rate / ifc_divisors[idx]; 70 return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7705.c b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
index 0ca8f2c3646..0ecea1451c6 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7705.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7705.c
@@ -32,7 +32,7 @@ static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
32 32
33static void master_clk_init(struct clk *clk) 33static void master_clk_init(struct clk *clk)
34{ 34{
35 clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0003]; 35 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0003];
36} 36}
37 37
38static struct clk_ops sh7705_master_clk_ops = { 38static struct clk_ops sh7705_master_clk_ops = {
@@ -41,7 +41,7 @@ static struct clk_ops sh7705_master_clk_ops = {
41 41
42static unsigned long module_clk_recalc(struct clk *clk) 42static unsigned long module_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ctrl_inw(FRQCR) & 0x0003; 44 int idx = __raw_readw(FRQCR) & 0x0003;
45 return clk->parent->rate / pfc_divisors[idx]; 45 return clk->parent->rate / pfc_divisors[idx];
46} 46}
47 47
@@ -51,7 +51,7 @@ static struct clk_ops sh7705_module_clk_ops = {
51 51
52static unsigned long bus_clk_recalc(struct clk *clk) 52static unsigned long bus_clk_recalc(struct clk *clk)
53{ 53{
54 int idx = (ctrl_inw(FRQCR) & 0x0300) >> 8; 54 int idx = (__raw_readw(FRQCR) & 0x0300) >> 8;
55 return clk->parent->rate / stc_multipliers[idx]; 55 return clk->parent->rate / stc_multipliers[idx];
56} 56}
57 57
@@ -61,7 +61,7 @@ static struct clk_ops sh7705_bus_clk_ops = {
61 61
62static unsigned long cpu_clk_recalc(struct clk *clk) 62static unsigned long cpu_clk_recalc(struct clk *clk)
63{ 63{
64 int idx = (ctrl_inw(FRQCR) & 0x0030) >> 4; 64 int idx = (__raw_readw(FRQCR) & 0x0030) >> 4;
65 return clk->parent->rate / ifc_divisors[idx]; 65 return clk->parent->rate / ifc_divisors[idx];
66} 66}
67 67
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7706.c b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
index 4bf7887d310..6f9ff8b57dd 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7706.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7706.c
@@ -24,7 +24,7 @@ static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
24 24
25static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
26{ 26{
27 int frqcr = ctrl_inw(FRQCR); 27 int frqcr = __raw_readw(FRQCR);
28 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 28 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
29 29
30 clk->rate *= pfc_divisors[idx]; 30 clk->rate *= pfc_divisors[idx];
@@ -36,7 +36,7 @@ static struct clk_ops sh7706_master_clk_ops = {
36 36
37static unsigned long module_clk_recalc(struct clk *clk) 37static unsigned long module_clk_recalc(struct clk *clk)
38{ 38{
39 int frqcr = ctrl_inw(FRQCR); 39 int frqcr = __raw_readw(FRQCR);
40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
41 41
42 return clk->parent->rate / pfc_divisors[idx]; 42 return clk->parent->rate / pfc_divisors[idx];
@@ -48,7 +48,7 @@ static struct clk_ops sh7706_module_clk_ops = {
48 48
49static unsigned long bus_clk_recalc(struct clk *clk) 49static unsigned long bus_clk_recalc(struct clk *clk)
50{ 50{
51 int frqcr = ctrl_inw(FRQCR); 51 int frqcr = __raw_readw(FRQCR);
52 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4); 52 int idx = ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4);
53 53
54 return clk->parent->rate / stc_multipliers[idx]; 54 return clk->parent->rate / stc_multipliers[idx];
@@ -60,7 +60,7 @@ static struct clk_ops sh7706_bus_clk_ops = {
60 60
61static unsigned long cpu_clk_recalc(struct clk *clk) 61static unsigned long cpu_clk_recalc(struct clk *clk)
62{ 62{
63 int frqcr = ctrl_inw(FRQCR); 63 int frqcr = __raw_readw(FRQCR);
64 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 64 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
65 65
66 return clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7709.c b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
index e8749505bd2..f302ba09e68 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7709.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7709.c
@@ -24,7 +24,7 @@ static int pfc_divisors[] = { 1, 2, 4, 1, 3, 6, 1, 1 };
24 24
25static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
26{ 26{
27 int frqcr = ctrl_inw(FRQCR); 27 int frqcr = __raw_readw(FRQCR);
28 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 28 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
29 29
30 clk->rate *= pfc_divisors[idx]; 30 clk->rate *= pfc_divisors[idx];
@@ -36,7 +36,7 @@ static struct clk_ops sh7709_master_clk_ops = {
36 36
37static unsigned long module_clk_recalc(struct clk *clk) 37static unsigned long module_clk_recalc(struct clk *clk)
38{ 38{
39 int frqcr = ctrl_inw(FRQCR); 39 int frqcr = __raw_readw(FRQCR);
40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003); 40 int idx = ((frqcr & 0x2000) >> 11) | (frqcr & 0x0003);
41 41
42 return clk->parent->rate / pfc_divisors[idx]; 42 return clk->parent->rate / pfc_divisors[idx];
@@ -48,7 +48,7 @@ static struct clk_ops sh7709_module_clk_ops = {
48 48
49static unsigned long bus_clk_recalc(struct clk *clk) 49static unsigned long bus_clk_recalc(struct clk *clk)
50{ 50{
51 int frqcr = ctrl_inw(FRQCR); 51 int frqcr = __raw_readw(FRQCR);
52 int idx = (frqcr & 0x0080) ? 52 int idx = (frqcr & 0x0080) ?
53 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1; 53 ((frqcr & 0x8000) >> 13) | ((frqcr & 0x0030) >> 4) : 1;
54 54
@@ -61,7 +61,7 @@ static struct clk_ops sh7709_bus_clk_ops = {
61 61
62static unsigned long cpu_clk_recalc(struct clk *clk) 62static unsigned long cpu_clk_recalc(struct clk *clk)
63{ 63{
64 int frqcr = ctrl_inw(FRQCR); 64 int frqcr = __raw_readw(FRQCR);
65 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2); 65 int idx = ((frqcr & 0x4000) >> 12) | ((frqcr & 0x000c) >> 2);
66 66
67 return clk->parent->rate / ifc_divisors[idx]; 67 return clk->parent->rate / ifc_divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7710.c b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
index 030a58ba18a..29a87d8946a 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7710.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7710.c
@@ -26,7 +26,7 @@ static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
26 26
27static void master_clk_init(struct clk *clk) 27static void master_clk_init(struct clk *clk)
28{ 28{
29 clk->rate *= md_table[ctrl_inw(FRQCR) & 0x0007]; 29 clk->rate *= md_table[__raw_readw(FRQCR) & 0x0007];
30} 30}
31 31
32static struct clk_ops sh7710_master_clk_ops = { 32static struct clk_ops sh7710_master_clk_ops = {
@@ -35,7 +35,7 @@ static struct clk_ops sh7710_master_clk_ops = {
35 35
36static unsigned long module_clk_recalc(struct clk *clk) 36static unsigned long module_clk_recalc(struct clk *clk)
37{ 37{
38 int idx = (ctrl_inw(FRQCR) & 0x0007); 38 int idx = (__raw_readw(FRQCR) & 0x0007);
39 return clk->parent->rate / md_table[idx]; 39 return clk->parent->rate / md_table[idx];
40} 40}
41 41
@@ -45,7 +45,7 @@ static struct clk_ops sh7710_module_clk_ops = {
45 45
46static unsigned long bus_clk_recalc(struct clk *clk) 46static unsigned long bus_clk_recalc(struct clk *clk)
47{ 47{
48 int idx = (ctrl_inw(FRQCR) & 0x0700) >> 8; 48 int idx = (__raw_readw(FRQCR) & 0x0700) >> 8;
49 return clk->parent->rate / md_table[idx]; 49 return clk->parent->rate / md_table[idx];
50} 50}
51 51
@@ -55,7 +55,7 @@ static struct clk_ops sh7710_bus_clk_ops = {
55 55
56static unsigned long cpu_clk_recalc(struct clk *clk) 56static unsigned long cpu_clk_recalc(struct clk *clk)
57{ 57{
58 int idx = (ctrl_inw(FRQCR) & 0x0070) >> 4; 58 int idx = (__raw_readw(FRQCR) & 0x0070) >> 4;
59 return clk->parent->rate / md_table[idx]; 59 return clk->parent->rate / md_table[idx];
60} 60}
61 61
diff --git a/arch/sh/kernel/cpu/sh3/clock-sh7712.c b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
index 6428ee6c77e..b0d0c520399 100644
--- a/arch/sh/kernel/cpu/sh3/clock-sh7712.c
+++ b/arch/sh/kernel/cpu/sh3/clock-sh7712.c
@@ -23,7 +23,7 @@ static int divisors[] = { 1, 2, 3, 4, 6 };
23 23
24static void master_clk_init(struct clk *clk) 24static void master_clk_init(struct clk *clk)
25{ 25{
26 int frqcr = ctrl_inw(FRQCR); 26 int frqcr = __raw_readw(FRQCR);
27 int idx = (frqcr & 0x0300) >> 8; 27 int idx = (frqcr & 0x0300) >> 8;
28 28
29 clk->rate *= multipliers[idx]; 29 clk->rate *= multipliers[idx];
@@ -35,7 +35,7 @@ static struct clk_ops sh7712_master_clk_ops = {
35 35
36static unsigned long module_clk_recalc(struct clk *clk) 36static unsigned long module_clk_recalc(struct clk *clk)
37{ 37{
38 int frqcr = ctrl_inw(FRQCR); 38 int frqcr = __raw_readw(FRQCR);
39 int idx = frqcr & 0x0007; 39 int idx = frqcr & 0x0007;
40 40
41 return clk->parent->rate / divisors[idx]; 41 return clk->parent->rate / divisors[idx];
@@ -47,7 +47,7 @@ static struct clk_ops sh7712_module_clk_ops = {
47 47
48static unsigned long cpu_clk_recalc(struct clk *clk) 48static unsigned long cpu_clk_recalc(struct clk *clk)
49{ 49{
50 int frqcr = ctrl_inw(FRQCR); 50 int frqcr = __raw_readw(FRQCR);
51 int idx = (frqcr & 0x0030) >> 4; 51 int idx = (frqcr & 0x0030) >> 4;
52 52
53 return clk->parent->rate / divisors[idx]; 53 return clk->parent->rate / divisors[idx];
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index c2db65719f4..295ec4c99e9 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -30,23 +30,23 @@ int detect_cpu_and_cache_system(void)
30 addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12); 30 addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
31 31
32 /* First, write back & invalidate */ 32 /* First, write back & invalidate */
33 data0 = ctrl_inl(addr0); 33 data0 = __raw_readl(addr0);
34 ctrl_outl(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0); 34 __raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
35 data1 = ctrl_inl(addr1); 35 data1 = __raw_readl(addr1);
36 ctrl_outl(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1); 36 __raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
37 37
38 /* Next, check if there's shadow or not */ 38 /* Next, check if there's shadow or not */
39 data0 = ctrl_inl(addr0); 39 data0 = __raw_readl(addr0);
40 data0 ^= SH_CACHE_VALID; 40 data0 ^= SH_CACHE_VALID;
41 ctrl_outl(data0, addr0); 41 __raw_writel(data0, addr0);
42 data1 = ctrl_inl(addr1); 42 data1 = __raw_readl(addr1);
43 data2 = data1 ^ SH_CACHE_VALID; 43 data2 = data1 ^ SH_CACHE_VALID;
44 ctrl_outl(data2, addr1); 44 __raw_writel(data2, addr1);
45 data3 = ctrl_inl(addr0); 45 data3 = __raw_readl(addr0);
46 46
47 /* Lastly, invaliate them. */ 47 /* Lastly, invaliate them. */
48 ctrl_outl(data0&~SH_CACHE_VALID, addr0); 48 __raw_writel(data0&~SH_CACHE_VALID, addr0);
49 ctrl_outl(data2&~SH_CACHE_VALID, addr1); 49 __raw_writel(data2&~SH_CACHE_VALID, addr1);
50 50
51 back_to_cached(); 51 back_to_cached();
52 52
@@ -94,9 +94,9 @@ int detect_cpu_and_cache_system(void)
94 boot_cpu_data.dcache.way_incr = (1 << 13); 94 boot_cpu_data.dcache.way_incr = (1 << 13);
95 boot_cpu_data.dcache.entry_mask = 0x1ff0; 95 boot_cpu_data.dcache.entry_mask = 0x1ff0;
96 boot_cpu_data.dcache.sets = 512; 96 boot_cpu_data.dcache.sets = 512;
97 ctrl_outl(CCR_CACHE_32KB, CCR3_REG); 97 __raw_writel(CCR_CACHE_32KB, CCR3_REG);
98#else 98#else
99 ctrl_outl(CCR_CACHE_16KB, CCR3_REG); 99 __raw_writel(CCR_CACHE_16KB, CCR3_REG);
100#endif 100#endif
101#endif 101#endif
102 } 102 }
diff --git a/arch/sh/kernel/cpu/sh3/setup-sh3.c b/arch/sh/kernel/cpu/sh3/setup-sh3.c
index c9884685785..53be70b9811 100644
--- a/arch/sh/kernel/cpu/sh3/setup-sh3.c
+++ b/arch/sh/kernel/cpu/sh3/setup-sh3.c
@@ -58,7 +58,7 @@ static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45",
58void __init plat_irq_setup_pins(int mode) 58void __init plat_irq_setup_pins(int mode)
59{ 59{
60 if (mode == IRQ_MODE_IRQ) { 60 if (mode == IRQ_MODE_IRQ) {
61 ctrl_outw(ctrl_inw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1); 61 __raw_writew(__raw_readw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
62 register_intc_controller(&intc_desc_irq0123); 62 register_intc_controller(&intc_desc_irq0123);
63 return; 63 return;
64 } 64 }
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 21421e34e7d..6b80850294d 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -23,7 +23,7 @@ static int frqcr3_values[] = { 0, 1, 2, 3, 4, 5, 6 };
23 23
24static unsigned long emi_clk_recalc(struct clk *clk) 24static unsigned long emi_clk_recalc(struct clk *clk)
25{ 25{
26 int idx = ctrl_inl(CPG2_FRQCR3) & 0x0007; 26 int idx = __raw_readl(CPG2_FRQCR3) & 0x0007;
27 return clk->parent->rate / frqcr3_divisors[idx]; 27 return clk->parent->rate / frqcr3_divisors[idx];
28} 28}
29 29
@@ -52,7 +52,7 @@ static struct clk sh4202_emi_clk = {
52 52
53static unsigned long femi_clk_recalc(struct clk *clk) 53static unsigned long femi_clk_recalc(struct clk *clk)
54{ 54{
55 int idx = (ctrl_inl(CPG2_FRQCR3) >> 3) & 0x0007; 55 int idx = (__raw_readl(CPG2_FRQCR3) >> 3) & 0x0007;
56 return clk->parent->rate / frqcr3_divisors[idx]; 56 return clk->parent->rate / frqcr3_divisors[idx];
57} 57}
58 58
@@ -92,7 +92,7 @@ static void shoc_clk_init(struct clk *clk)
92 92
93static unsigned long shoc_clk_recalc(struct clk *clk) 93static unsigned long shoc_clk_recalc(struct clk *clk)
94{ 94{
95 int idx = (ctrl_inl(CPG2_FRQCR3) >> 6) & 0x0007; 95 int idx = (__raw_readl(CPG2_FRQCR3) >> 6) & 0x0007;
96 return clk->parent->rate / frqcr3_divisors[idx]; 96 return clk->parent->rate / frqcr3_divisors[idx];
97} 97}
98 98
@@ -122,10 +122,10 @@ static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id)
122 122
123 tmp = frqcr3_lookup(clk, rate); 123 tmp = frqcr3_lookup(clk, rate);
124 124
125 frqcr3 = ctrl_inl(CPG2_FRQCR3); 125 frqcr3 = __raw_readl(CPG2_FRQCR3);
126 frqcr3 &= ~(0x0007 << 6); 126 frqcr3 &= ~(0x0007 << 6);
127 frqcr3 |= tmp << 6; 127 frqcr3 |= tmp << 6;
128 ctrl_outl(frqcr3, CPG2_FRQCR3); 128 __raw_writel(frqcr3, CPG2_FRQCR3);
129 129
130 clk->rate = clk->parent->rate / frqcr3_divisors[tmp]; 130 clk->rate = clk->parent->rate / frqcr3_divisors[tmp];
131 131
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4.c b/arch/sh/kernel/cpu/sh4/clock-sh4.c
index 73294d9cd04..5add75c1f53 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4.c
@@ -28,7 +28,7 @@ static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
28 28
29static void master_clk_init(struct clk *clk) 29static void master_clk_init(struct clk *clk)
30{ 30{
31 clk->rate *= pfc_divisors[ctrl_inw(FRQCR) & 0x0007]; 31 clk->rate *= pfc_divisors[__raw_readw(FRQCR) & 0x0007];
32} 32}
33 33
34static struct clk_ops sh4_master_clk_ops = { 34static struct clk_ops sh4_master_clk_ops = {
@@ -37,7 +37,7 @@ static struct clk_ops sh4_master_clk_ops = {
37 37
38static unsigned long module_clk_recalc(struct clk *clk) 38static unsigned long module_clk_recalc(struct clk *clk)
39{ 39{
40 int idx = (ctrl_inw(FRQCR) & 0x0007); 40 int idx = (__raw_readw(FRQCR) & 0x0007);
41 return clk->parent->rate / pfc_divisors[idx]; 41 return clk->parent->rate / pfc_divisors[idx];
42} 42}
43 43
@@ -47,7 +47,7 @@ static struct clk_ops sh4_module_clk_ops = {
47 47
48static unsigned long bus_clk_recalc(struct clk *clk) 48static unsigned long bus_clk_recalc(struct clk *clk)
49{ 49{
50 int idx = (ctrl_inw(FRQCR) >> 3) & 0x0007; 50 int idx = (__raw_readw(FRQCR) >> 3) & 0x0007;
51 return clk->parent->rate / bfc_divisors[idx]; 51 return clk->parent->rate / bfc_divisors[idx];
52} 52}
53 53
@@ -57,7 +57,7 @@ static struct clk_ops sh4_bus_clk_ops = {
57 57
58static unsigned long cpu_clk_recalc(struct clk *clk) 58static unsigned long cpu_clk_recalc(struct clk *clk)
59{ 59{
60 int idx = (ctrl_inw(FRQCR) >> 6) & 0x0007; 60 int idx = (__raw_readw(FRQCR) >> 6) & 0x0007;
61 return clk->parent->rate / ifc_divisors[idx]; 61 return clk->parent->rate / ifc_divisors[idx];
62} 62}
63 63
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index cc02b3145cc..822977a06d8 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -28,9 +28,9 @@ int __init detect_cpu_and_cache_system(void)
28 [9] = (1 << 16) 28 [9] = (1 << 16)
29 }; 29 };
30 30
31 pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffffff; 31 pvr = (__raw_readl(CCN_PVR) >> 8) & 0xffffff;
32 prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff; 32 prr = (__raw_readl(CCN_PRR) >> 4) & 0xff;
33 cvr = (ctrl_inl(CCN_CVR)); 33 cvr = (__raw_readl(CCN_CVR));
34 34
35 /* 35 /*
36 * Setup some sane SH-4 defaults for the icache 36 * Setup some sane SH-4 defaults for the icache
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
index 4b733715cdb..b9b7e10ad68 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh4-202.c
@@ -198,7 +198,7 @@ void __init plat_irq_setup_pins(int mode)
198{ 198{
199 switch (mode) { 199 switch (mode) {
200 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 200 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
201 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 201 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
202 register_intc_controller(&intc_desc_irlm); 202 register_intc_controller(&intc_desc_irlm);
203 break; 203 break;
204 default: 204 default:
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7750.c b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
index b2a9df1af64..ffd79e57254 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7750.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7750.c
@@ -442,7 +442,7 @@ void __init plat_irq_setup_pins(int mode)
442 442
443 switch (mode) { 443 switch (mode) {
444 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */ 444 case IRQ_MODE_IRQ: /* individual interrupt mode for IRL3-0 */
445 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 445 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
446 register_intc_controller(&intc_desc_irlm); 446 register_intc_controller(&intc_desc_irlm);
447 break; 447 break;
448 default: 448 default:
diff --git a/arch/sh/kernel/cpu/sh4/setup-sh7760.c b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
index 5b74cc0b43d..a16eb3656f4 100644
--- a/arch/sh/kernel/cpu/sh4/setup-sh7760.c
+++ b/arch/sh/kernel/cpu/sh4/setup-sh7760.c
@@ -319,7 +319,7 @@ void __init plat_irq_setup_pins(int mode)
319{ 319{
320 switch (mode) { 320 switch (mode) {
321 case IRQ_MODE_IRQ: 321 case IRQ_MODE_IRQ:
322 ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR); 322 __raw_writew(__raw_readw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
323 register_intc_controller(&intc_desc_irq); 323 register_intc_controller(&intc_desc_irq);
324 break; 324 break;
325 default: 325 default:
diff --git a/arch/sh/kernel/cpu/sh4/sq.c b/arch/sh/kernel/cpu/sh4/sq.c
index 8a8a993f55e..97aea9d69b0 100644
--- a/arch/sh/kernel/cpu/sh4/sq.c
+++ b/arch/sh/kernel/cpu/sh4/sq.c
@@ -43,9 +43,9 @@ static unsigned long *sq_bitmap;
43 43
44#define store_queue_barrier() \ 44#define store_queue_barrier() \
45do { \ 45do { \
46 (void)ctrl_inl(P4SEG_STORE_QUE); \ 46 (void)__raw_readl(P4SEG_STORE_QUE); \
47 ctrl_outl(0, P4SEG_STORE_QUE + 0); \ 47 __raw_writel(0, P4SEG_STORE_QUE + 0); \
48 ctrl_outl(0, P4SEG_STORE_QUE + 8); \ 48 __raw_writel(0, P4SEG_STORE_QUE + 8); \
49} while (0); 49} while (0);
50 50
51/** 51/**
@@ -123,8 +123,8 @@ static int __sq_remap(struct sq_mapping *map, unsigned long flags)
123 * straightforward, as we can just load up each queue's QACR with 123 * straightforward, as we can just load up each queue's QACR with
124 * the physical address appropriately masked. 124 * the physical address appropriately masked.
125 */ 125 */
126 ctrl_outl(((map->addr >> 26) << 2) & 0x1c, SQ_QACR0); 126 __raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR0);
127 ctrl_outl(((map->addr >> 26) << 2) & 0x1c, SQ_QACR1); 127 __raw_writel(((map->addr >> 26) << 2) & 0x1c, SQ_QACR1);
128#endif 128#endif
129 129
130 return 0; 130 return 0;
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
index ddc235ca966..86aae60677d 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -35,7 +35,7 @@ static struct clk_ops sh7757_master_clk_ops = {
35 35
36static void module_clk_recalc(struct clk *clk) 36static void module_clk_recalc(struct clk *clk)
37{ 37{
38 int idx = ctrl_inl(FRQCR) & 0x0000000f; 38 int idx = __raw_readl(FRQCR) & 0x0000000f;
39 clk->rate = clk->parent->rate / p1fc_divisors[idx]; 39 clk->rate = clk->parent->rate / p1fc_divisors[idx];
40} 40}
41 41
@@ -45,7 +45,7 @@ static struct clk_ops sh7757_module_clk_ops = {
45 45
46static void bus_clk_recalc(struct clk *clk) 46static void bus_clk_recalc(struct clk *clk)
47{ 47{
48 int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f; 48 int idx = (__raw_readl(FRQCR) >> 8) & 0x0000000f;
49 clk->rate = clk->parent->rate / bfc_divisors[idx]; 49 clk->rate = clk->parent->rate / bfc_divisors[idx];
50} 50}
51 51
@@ -55,7 +55,7 @@ static struct clk_ops sh7757_bus_clk_ops = {
55 55
56static void cpu_clk_recalc(struct clk *clk) 56static void cpu_clk_recalc(struct clk *clk)
57{ 57{
58 int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f; 58 int idx = (__raw_readl(FRQCR) >> 20) & 0x0000000f;
59 clk->rate = clk->parent->rate / ifc_divisors[idx]; 59 clk->rate = clk->parent->rate / ifc_divisors[idx];
60} 60}
61 61
@@ -78,7 +78,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
78 78
79static void shyway_clk_recalc(struct clk *clk) 79static void shyway_clk_recalc(struct clk *clk)
80{ 80{
81 int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f; 81 int idx = (__raw_readl(FRQCR) >> 12) & 0x0000000f;
82 clk->rate = clk->parent->rate / sfc_divisors[idx]; 82 clk->rate = clk->parent->rate / sfc_divisors[idx];
83} 83}
84 84
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
index 370cd47642e..9f401163e71 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7763.c
@@ -22,7 +22,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
22 22
23static void master_clk_init(struct clk *clk) 23static void master_clk_init(struct clk *clk)
24{ 24{
25 clk->rate *= p0fc_divisors[(ctrl_inl(FRQCR) >> 4) & 0x07]; 25 clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
26} 26}
27 27
28static struct clk_ops sh7763_master_clk_ops = { 28static struct clk_ops sh7763_master_clk_ops = {
@@ -31,7 +31,7 @@ static struct clk_ops sh7763_master_clk_ops = {
31 31
32static unsigned long module_clk_recalc(struct clk *clk) 32static unsigned long module_clk_recalc(struct clk *clk)
33{ 33{
34 int idx = ((ctrl_inl(FRQCR) >> 4) & 0x07); 34 int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);
35 return clk->parent->rate / p0fc_divisors[idx]; 35 return clk->parent->rate / p0fc_divisors[idx];
36} 36}
37 37
@@ -41,7 +41,7 @@ static struct clk_ops sh7763_module_clk_ops = {
41 41
42static unsigned long bus_clk_recalc(struct clk *clk) 42static unsigned long bus_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x07); 44 int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);
45 return clk->parent->rate / bfc_divisors[idx]; 45 return clk->parent->rate / bfc_divisors[idx];
46} 46}
47 47
@@ -68,7 +68,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
68 68
69static unsigned long shyway_clk_recalc(struct clk *clk) 69static unsigned long shyway_clk_recalc(struct clk *clk)
70{ 70{
71 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x07); 71 int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);
72 return clk->parent->rate / cfc_divisors[idx]; 72 return clk->parent->rate / cfc_divisors[idx];
73} 73}
74 74
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
index e0b89676920..9e3354365d4 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7770.c
@@ -21,7 +21,7 @@ static int pfc_divisors[] = { 1, 8, 1,10,12,16, 1, 1 };
21 21
22static void master_clk_init(struct clk *clk) 22static void master_clk_init(struct clk *clk)
23{ 23{
24 clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> 28) & 0x000f]; 24 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> 28) & 0x000f];
25} 25}
26 26
27static struct clk_ops sh7770_master_clk_ops = { 27static struct clk_ops sh7770_master_clk_ops = {
@@ -30,7 +30,7 @@ static struct clk_ops sh7770_master_clk_ops = {
30 30
31static unsigned long module_clk_recalc(struct clk *clk) 31static unsigned long module_clk_recalc(struct clk *clk)
32{ 32{
33 int idx = ((ctrl_inl(FRQCR) >> 28) & 0x000f); 33 int idx = ((__raw_readl(FRQCR) >> 28) & 0x000f);
34 return clk->parent->rate / pfc_divisors[idx]; 34 return clk->parent->rate / pfc_divisors[idx];
35} 35}
36 36
@@ -40,7 +40,7 @@ static struct clk_ops sh7770_module_clk_ops = {
40 40
41static unsigned long bus_clk_recalc(struct clk *clk) 41static unsigned long bus_clk_recalc(struct clk *clk)
42{ 42{
43 int idx = (ctrl_inl(FRQCR) & 0x000f); 43 int idx = (__raw_readl(FRQCR) & 0x000f);
44 return clk->parent->rate / bfc_divisors[idx]; 44 return clk->parent->rate / bfc_divisors[idx];
45} 45}
46 46
@@ -50,7 +50,7 @@ static struct clk_ops sh7770_bus_clk_ops = {
50 50
51static unsigned long cpu_clk_recalc(struct clk *clk) 51static unsigned long cpu_clk_recalc(struct clk *clk)
52{ 52{
53 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x000f); 53 int idx = ((__raw_readl(FRQCR) >> 24) & 0x000f);
54 return clk->parent->rate / ifc_divisors[idx]; 54 return clk->parent->rate / ifc_divisors[idx];
55} 55}
56 56
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
index a249d823578..150963a6001 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7780.c
@@ -22,7 +22,7 @@ static int cfc_divisors[] = { 1, 1, 4, 1, 6, 1, 1, 1 };
22 22
23static void master_clk_init(struct clk *clk) 23static void master_clk_init(struct clk *clk)
24{ 24{
25 clk->rate *= pfc_divisors[ctrl_inl(FRQCR) & 0x0003]; 25 clk->rate *= pfc_divisors[__raw_readl(FRQCR) & 0x0003];
26} 26}
27 27
28static struct clk_ops sh7780_master_clk_ops = { 28static struct clk_ops sh7780_master_clk_ops = {
@@ -31,7 +31,7 @@ static struct clk_ops sh7780_master_clk_ops = {
31 31
32static unsigned long module_clk_recalc(struct clk *clk) 32static unsigned long module_clk_recalc(struct clk *clk)
33{ 33{
34 int idx = (ctrl_inl(FRQCR) & 0x0003); 34 int idx = (__raw_readl(FRQCR) & 0x0003);
35 return clk->parent->rate / pfc_divisors[idx]; 35 return clk->parent->rate / pfc_divisors[idx];
36} 36}
37 37
@@ -41,7 +41,7 @@ static struct clk_ops sh7780_module_clk_ops = {
41 41
42static unsigned long bus_clk_recalc(struct clk *clk) 42static unsigned long bus_clk_recalc(struct clk *clk)
43{ 43{
44 int idx = ((ctrl_inl(FRQCR) >> 16) & 0x0007); 44 int idx = ((__raw_readl(FRQCR) >> 16) & 0x0007);
45 return clk->parent->rate / bfc_divisors[idx]; 45 return clk->parent->rate / bfc_divisors[idx];
46} 46}
47 47
@@ -51,7 +51,7 @@ static struct clk_ops sh7780_bus_clk_ops = {
51 51
52static unsigned long cpu_clk_recalc(struct clk *clk) 52static unsigned long cpu_clk_recalc(struct clk *clk)
53{ 53{
54 int idx = ((ctrl_inl(FRQCR) >> 24) & 0x0001); 54 int idx = ((__raw_readl(FRQCR) >> 24) & 0x0001);
55 return clk->parent->rate / ifc_divisors[idx]; 55 return clk->parent->rate / ifc_divisors[idx];
56} 56}
57 57
@@ -74,7 +74,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
74 74
75static unsigned long shyway_clk_recalc(struct clk *clk) 75static unsigned long shyway_clk_recalc(struct clk *clk)
76{ 76{
77 int idx = ((ctrl_inl(FRQCR) >> 20) & 0x0007); 77 int idx = ((__raw_readl(FRQCR) >> 20) & 0x0007);
78 return clk->parent->rate / cfc_divisors[idx]; 78 return clk->parent->rate / cfc_divisors[idx];
79} 79}
80 80
diff --git a/arch/sh/kernel/cpu/sh4a/clock-shx3.c b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
index 23c27d32d98..e75c57bdfa5 100644
--- a/arch/sh/kernel/cpu/sh4a/clock-shx3.c
+++ b/arch/sh/kernel/cpu/sh4a/clock-shx3.c
@@ -33,7 +33,7 @@ static int cfc_divisors[] = { 1, 1, 4, 6 };
33 33
34static void master_clk_init(struct clk *clk) 34static void master_clk_init(struct clk *clk)
35{ 35{
36 clk->rate *= pfc_divisors[(ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK]; 36 clk->rate *= pfc_divisors[(__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK];
37} 37}
38 38
39static struct clk_ops shx3_master_clk_ops = { 39static struct clk_ops shx3_master_clk_ops = {
@@ -42,7 +42,7 @@ static struct clk_ops shx3_master_clk_ops = {
42 42
43static unsigned long module_clk_recalc(struct clk *clk) 43static unsigned long module_clk_recalc(struct clk *clk)
44{ 44{
45 int idx = ((ctrl_inl(FRQCR) >> PFC_POS) & PFC_MSK); 45 int idx = ((__raw_readl(FRQCR) >> PFC_POS) & PFC_MSK);
46 return clk->parent->rate / pfc_divisors[idx]; 46 return clk->parent->rate / pfc_divisors[idx];
47} 47}
48 48
@@ -52,7 +52,7 @@ static struct clk_ops shx3_module_clk_ops = {
52 52
53static unsigned long bus_clk_recalc(struct clk *clk) 53static unsigned long bus_clk_recalc(struct clk *clk)
54{ 54{
55 int idx = ((ctrl_inl(FRQCR) >> BFC_POS) & BFC_MSK); 55 int idx = ((__raw_readl(FRQCR) >> BFC_POS) & BFC_MSK);
56 return clk->parent->rate / bfc_divisors[idx]; 56 return clk->parent->rate / bfc_divisors[idx];
57} 57}
58 58
@@ -62,7 +62,7 @@ static struct clk_ops shx3_bus_clk_ops = {
62 62
63static unsigned long cpu_clk_recalc(struct clk *clk) 63static unsigned long cpu_clk_recalc(struct clk *clk)
64{ 64{
65 int idx = ((ctrl_inl(FRQCR) >> IFC_POS) & IFC_MSK); 65 int idx = ((__raw_readl(FRQCR) >> IFC_POS) & IFC_MSK);
66 return clk->parent->rate / ifc_divisors[idx]; 66 return clk->parent->rate / ifc_divisors[idx];
67} 67}
68 68
@@ -85,7 +85,7 @@ void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
85 85
86static unsigned long shyway_clk_recalc(struct clk *clk) 86static unsigned long shyway_clk_recalc(struct clk *clk)
87{ 87{
88 int idx = ((ctrl_inl(FRQCR) >> CFC_POS) & CFC_MSK); 88 int idx = ((__raw_readl(FRQCR) >> CFC_POS) & CFC_MSK);
89 return clk->parent->rate / cfc_divisors[idx]; 89 return clk->parent->rate / cfc_divisors[idx];
90} 90}
91 91
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 9d426258aa0..9e8620e3ad3 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -596,7 +596,7 @@ void __init plat_early_device_setup(void)
596void l2_cache_init(void) 596void l2_cache_init(void)
597{ 597{
598 /* Enable L2 cache */ 598 /* Enable L2 cache */
599 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 599 __raw_writel(L2_CACHE_ENABLE, RAMCR);
600} 600}
601 601
602enum { 602enum {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index 578e9f80271..aa0f6e9bb89 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -718,7 +718,7 @@ void __init plat_early_device_setup(void)
718void l2_cache_init(void) 718void l2_cache_init(void)
719{ 719{
720 /* Enable L2 cache */ 720 /* Enable L2 cache */
721 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 721 __raw_writel(L2_CACHE_ENABLE, RAMCR);
722} 722}
723 723
724enum { 724enum {
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
index 37e32efbbaa..e75edf58796 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -487,17 +487,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
487void __init plat_irq_setup(void) 487void __init plat_irq_setup(void)
488{ 488{
489 /* disable IRQ3-0 + IRQ7-4 */ 489 /* disable IRQ3-0 + IRQ7-4 */
490 ctrl_outl(0xff000000, INTC_INTMSK0); 490 __raw_writel(0xff000000, INTC_INTMSK0);
491 491
492 /* disable IRL3-0 + IRL7-4 */ 492 /* disable IRL3-0 + IRL7-4 */
493 ctrl_outl(0xc0000000, INTC_INTMSK1); 493 __raw_writel(0xc0000000, INTC_INTMSK1);
494 ctrl_outl(0xfffefffe, INTC_INTMSK2); 494 __raw_writel(0xfffefffe, INTC_INTMSK2);
495 495
496 /* select IRL mode for IRL3-0 + IRL7-4 */ 496 /* select IRL mode for IRL3-0 + IRL7-4 */
497 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 497 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
498 498
499 /* disable holding function, ie enable "SH-4 Mode" */ 499 /* disable holding function, ie enable "SH-4 Mode" */
500 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 500 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
501 501
502 register_intc_controller(&intc_desc); 502 register_intc_controller(&intc_desc);
503} 503}
@@ -507,32 +507,32 @@ void __init plat_irq_setup_pins(int mode)
507 switch (mode) { 507 switch (mode) {
508 case IRQ_MODE_IRQ7654: 508 case IRQ_MODE_IRQ7654:
509 /* select IRQ mode for IRL7-4 */ 509 /* select IRQ mode for IRL7-4 */
510 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); 510 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
511 register_intc_controller(&intc_desc_irq4567); 511 register_intc_controller(&intc_desc_irq4567);
512 break; 512 break;
513 case IRQ_MODE_IRQ3210: 513 case IRQ_MODE_IRQ3210:
514 /* select IRQ mode for IRL3-0 */ 514 /* select IRQ mode for IRL3-0 */
515 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); 515 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
516 register_intc_controller(&intc_desc_irq0123); 516 register_intc_controller(&intc_desc_irq0123);
517 break; 517 break;
518 case IRQ_MODE_IRL7654: 518 case IRQ_MODE_IRL7654:
519 /* enable IRL7-4 but don't provide any masking */ 519 /* enable IRL7-4 but don't provide any masking */
520 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 520 __raw_writel(0x40000000, INTC_INTMSKCLR1);
521 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 521 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
522 break; 522 break;
523 case IRQ_MODE_IRL3210: 523 case IRQ_MODE_IRL3210:
524 /* enable IRL0-3 but don't provide any masking */ 524 /* enable IRL0-3 but don't provide any masking */
525 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 525 __raw_writel(0x80000000, INTC_INTMSKCLR1);
526 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 526 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
527 break; 527 break;
528 case IRQ_MODE_IRL7654_MASK: 528 case IRQ_MODE_IRL7654_MASK:
529 /* enable IRL7-4 and mask using cpu intc controller */ 529 /* enable IRL7-4 and mask using cpu intc controller */
530 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 530 __raw_writel(0x40000000, INTC_INTMSKCLR1);
531 register_intc_controller(&intc_desc_irl4567); 531 register_intc_controller(&intc_desc_irl4567);
532 break; 532 break;
533 case IRQ_MODE_IRL3210_MASK: 533 case IRQ_MODE_IRL3210_MASK:
534 /* enable IRL0-3 and mask using cpu intc controller */ 534 /* enable IRL0-3 and mask using cpu intc controller */
535 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 535 __raw_writel(0x80000000, INTC_INTMSKCLR1);
536 register_intc_controller(&intc_desc_irl0123); 536 register_intc_controller(&intc_desc_irl0123);
537 break; 537 break;
538 default: 538 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
index 6aba26fec41..7f6b0a5f7f8 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7763.c
@@ -538,11 +538,11 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7763-irl3210", irl_vectors,
538void __init plat_irq_setup(void) 538void __init plat_irq_setup(void)
539{ 539{
540 /* disable IRQ7-0 */ 540 /* disable IRQ7-0 */
541 ctrl_outl(0xff000000, INTC_INTMSK0); 541 __raw_writel(0xff000000, INTC_INTMSK0);
542 542
543 /* disable IRL3-0 + IRL7-4 */ 543 /* disable IRL3-0 + IRL7-4 */
544 ctrl_outl(0xc0000000, INTC_INTMSK1); 544 __raw_writel(0xc0000000, INTC_INTMSK1);
545 ctrl_outl(0xfffefffe, INTC_INTMSK2); 545 __raw_writel(0xfffefffe, INTC_INTMSK2);
546 546
547 register_intc_controller(&intc_desc); 547 register_intc_controller(&intc_desc);
548} 548}
@@ -552,27 +552,27 @@ void __init plat_irq_setup_pins(int mode)
552 switch (mode) { 552 switch (mode) {
553 case IRQ_MODE_IRQ: 553 case IRQ_MODE_IRQ:
554 /* select IRQ mode for IRL3-0 + IRL7-4 */ 554 /* select IRQ mode for IRL3-0 + IRL7-4 */
555 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 555 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
556 register_intc_controller(&intc_irq_desc); 556 register_intc_controller(&intc_irq_desc);
557 break; 557 break;
558 case IRQ_MODE_IRL7654: 558 case IRQ_MODE_IRL7654:
559 /* enable IRL7-4 but don't provide any masking */ 559 /* enable IRL7-4 but don't provide any masking */
560 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 560 __raw_writel(0x40000000, INTC_INTMSKCLR1);
561 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 561 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
562 break; 562 break;
563 case IRQ_MODE_IRL3210: 563 case IRQ_MODE_IRL3210:
564 /* enable IRL0-3 but don't provide any masking */ 564 /* enable IRL0-3 but don't provide any masking */
565 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 565 __raw_writel(0x80000000, INTC_INTMSKCLR1);
566 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 566 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
567 break; 567 break;
568 case IRQ_MODE_IRL7654_MASK: 568 case IRQ_MODE_IRL7654_MASK:
569 /* enable IRL7-4 and mask using cpu intc controller */ 569 /* enable IRL7-4 and mask using cpu intc controller */
570 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 570 __raw_writel(0x40000000, INTC_INTMSKCLR1);
571 register_intc_controller(&intc_irl7654_desc); 571 register_intc_controller(&intc_irl7654_desc);
572 break; 572 break;
573 case IRQ_MODE_IRL3210_MASK: 573 case IRQ_MODE_IRL3210_MASK:
574 /* enable IRL0-3 and mask using cpu intc controller */ 574 /* enable IRL0-3 and mask using cpu intc controller */
575 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 575 __raw_writel(0x80000000, INTC_INTMSKCLR1);
576 register_intc_controller(&intc_irl3210_desc); 576 register_intc_controller(&intc_irl3210_desc);
577 break; 577 break;
578 default: 578 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
index c1643bc9590..86d681ecf90 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7770.c
@@ -694,17 +694,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
694void __init plat_irq_setup(void) 694void __init plat_irq_setup(void)
695{ 695{
696 /* disable IRQ7-0 */ 696 /* disable IRQ7-0 */
697 ctrl_outl(0xff000000, INTC_INTMSK0); 697 __raw_writel(0xff000000, INTC_INTMSK0);
698 698
699 /* disable IRL3-0 + IRL7-4 */ 699 /* disable IRL3-0 + IRL7-4 */
700 ctrl_outl(0xc0000000, INTC_INTMSK1); 700 __raw_writel(0xc0000000, INTC_INTMSK1);
701 ctrl_outl(0xfffefffe, INTC_INTMSK2); 701 __raw_writel(0xfffefffe, INTC_INTMSK2);
702 702
703 /* select IRL mode for IRL3-0 + IRL7-4 */ 703 /* select IRL mode for IRL3-0 + IRL7-4 */
704 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 704 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
705 705
706 /* disable holding function, ie enable "SH-4 Mode" */ 706 /* disable holding function, ie enable "SH-4 Mode" */
707 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 707 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
708 708
709 register_intc_controller(&intc_desc); 709 register_intc_controller(&intc_desc);
710} 710}
@@ -714,27 +714,27 @@ void __init plat_irq_setup_pins(int mode)
714 switch (mode) { 714 switch (mode) {
715 case IRQ_MODE_IRQ: 715 case IRQ_MODE_IRQ:
716 /* select IRQ mode for IRL3-0 + IRL7-4 */ 716 /* select IRQ mode for IRL3-0 + IRL7-4 */
717 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 717 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
718 register_intc_controller(&intc_irq_desc); 718 register_intc_controller(&intc_irq_desc);
719 break; 719 break;
720 case IRQ_MODE_IRL7654: 720 case IRQ_MODE_IRL7654:
721 /* enable IRL7-4 but don't provide any masking */ 721 /* enable IRL7-4 but don't provide any masking */
722 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 722 __raw_writel(0x40000000, INTC_INTMSKCLR1);
723 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 723 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
724 break; 724 break;
725 case IRQ_MODE_IRL3210: 725 case IRQ_MODE_IRL3210:
726 /* enable IRL0-3 but don't provide any masking */ 726 /* enable IRL0-3 but don't provide any masking */
727 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 727 __raw_writel(0x80000000, INTC_INTMSKCLR1);
728 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 728 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
729 break; 729 break;
730 case IRQ_MODE_IRL7654_MASK: 730 case IRQ_MODE_IRL7654_MASK:
731 /* enable IRL7-4 and mask using cpu intc controller */ 731 /* enable IRL7-4 and mask using cpu intc controller */
732 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 732 __raw_writel(0x40000000, INTC_INTMSKCLR1);
733 register_intc_controller(&intc_irl7654_desc); 733 register_intc_controller(&intc_irl7654_desc);
734 break; 734 break;
735 case IRQ_MODE_IRL3210_MASK: 735 case IRQ_MODE_IRL3210_MASK:
736 /* enable IRL0-3 and mask using cpu intc controller */ 736 /* enable IRL0-3 and mask using cpu intc controller */
737 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 737 __raw_writel(0x80000000, INTC_INTMSKCLR1);
738 register_intc_controller(&intc_irl3210_desc); 738 register_intc_controller(&intc_irl3210_desc);
739 break; 739 break;
740 default: 740 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
index c310558490d..f8f21618d78 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7780.c
@@ -461,17 +461,17 @@ static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
461void __init plat_irq_setup(void) 461void __init plat_irq_setup(void)
462{ 462{
463 /* disable IRQ7-0 */ 463 /* disable IRQ7-0 */
464 ctrl_outl(0xff000000, INTC_INTMSK0); 464 __raw_writel(0xff000000, INTC_INTMSK0);
465 465
466 /* disable IRL3-0 + IRL7-4 */ 466 /* disable IRL3-0 + IRL7-4 */
467 ctrl_outl(0xc0000000, INTC_INTMSK1); 467 __raw_writel(0xc0000000, INTC_INTMSK1);
468 ctrl_outl(0xfffefffe, INTC_INTMSK2); 468 __raw_writel(0xfffefffe, INTC_INTMSK2);
469 469
470 /* select IRL mode for IRL3-0 + IRL7-4 */ 470 /* select IRL mode for IRL3-0 + IRL7-4 */
471 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 471 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
472 472
473 /* disable holding function, ie enable "SH-4 Mode" */ 473 /* disable holding function, ie enable "SH-4 Mode" */
474 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 474 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
475 475
476 register_intc_controller(&intc_desc); 476 register_intc_controller(&intc_desc);
477} 477}
@@ -481,27 +481,27 @@ void __init plat_irq_setup_pins(int mode)
481 switch (mode) { 481 switch (mode) {
482 case IRQ_MODE_IRQ: 482 case IRQ_MODE_IRQ:
483 /* select IRQ mode for IRL3-0 + IRL7-4 */ 483 /* select IRQ mode for IRL3-0 + IRL7-4 */
484 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0); 484 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
485 register_intc_controller(&intc_irq_desc); 485 register_intc_controller(&intc_irq_desc);
486 break; 486 break;
487 case IRQ_MODE_IRL7654: 487 case IRQ_MODE_IRL7654:
488 /* enable IRL7-4 but don't provide any masking */ 488 /* enable IRL7-4 but don't provide any masking */
489 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 489 __raw_writel(0x40000000, INTC_INTMSKCLR1);
490 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 490 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
491 break; 491 break;
492 case IRQ_MODE_IRL3210: 492 case IRQ_MODE_IRL3210:
493 /* enable IRL0-3 but don't provide any masking */ 493 /* enable IRL0-3 but don't provide any masking */
494 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 494 __raw_writel(0x80000000, INTC_INTMSKCLR1);
495 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 495 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
496 break; 496 break;
497 case IRQ_MODE_IRL7654_MASK: 497 case IRQ_MODE_IRL7654_MASK:
498 /* enable IRL7-4 and mask using cpu intc controller */ 498 /* enable IRL7-4 and mask using cpu intc controller */
499 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 499 __raw_writel(0x40000000, INTC_INTMSKCLR1);
500 register_intc_controller(&intc_irl7654_desc); 500 register_intc_controller(&intc_irl7654_desc);
501 break; 501 break;
502 case IRQ_MODE_IRL3210_MASK: 502 case IRQ_MODE_IRL3210_MASK:
503 /* enable IRL0-3 and mask using cpu intc controller */ 503 /* enable IRL0-3 and mask using cpu intc controller */
504 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 504 __raw_writel(0x80000000, INTC_INTMSKCLR1);
505 register_intc_controller(&intc_irl3210_desc); 505 register_intc_controller(&intc_irl3210_desc);
506 break; 506 break;
507 default: 507 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
index f685b9b2199..23448d8c671 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7785.c
@@ -541,17 +541,17 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7785-irl4567", vectors_irl4567,
541void __init plat_irq_setup(void) 541void __init plat_irq_setup(void)
542{ 542{
543 /* disable IRQ3-0 + IRQ7-4 */ 543 /* disable IRQ3-0 + IRQ7-4 */
544 ctrl_outl(0xff000000, INTC_INTMSK0); 544 __raw_writel(0xff000000, INTC_INTMSK0);
545 545
546 /* disable IRL3-0 + IRL7-4 */ 546 /* disable IRL3-0 + IRL7-4 */
547 ctrl_outl(0xc0000000, INTC_INTMSK1); 547 __raw_writel(0xc0000000, INTC_INTMSK1);
548 ctrl_outl(0xfffefffe, INTC_INTMSK2); 548 __raw_writel(0xfffefffe, INTC_INTMSK2);
549 549
550 /* select IRL mode for IRL3-0 + IRL7-4 */ 550 /* select IRL mode for IRL3-0 + IRL7-4 */
551 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 551 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
552 552
553 /* disable holding function, ie enable "SH-4 Mode" */ 553 /* disable holding function, ie enable "SH-4 Mode" */
554 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0); 554 __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
555 555
556 register_intc_controller(&intc_desc); 556 register_intc_controller(&intc_desc);
557} 557}
@@ -561,32 +561,32 @@ void __init plat_irq_setup_pins(int mode)
561 switch (mode) { 561 switch (mode) {
562 case IRQ_MODE_IRQ7654: 562 case IRQ_MODE_IRQ7654:
563 /* select IRQ mode for IRL7-4 */ 563 /* select IRQ mode for IRL7-4 */
564 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); 564 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
565 register_intc_controller(&intc_desc_irq4567); 565 register_intc_controller(&intc_desc_irq4567);
566 break; 566 break;
567 case IRQ_MODE_IRQ3210: 567 case IRQ_MODE_IRQ3210:
568 /* select IRQ mode for IRL3-0 */ 568 /* select IRQ mode for IRL3-0 */
569 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); 569 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
570 register_intc_controller(&intc_desc_irq0123); 570 register_intc_controller(&intc_desc_irq0123);
571 break; 571 break;
572 case IRQ_MODE_IRL7654: 572 case IRQ_MODE_IRL7654:
573 /* enable IRL7-4 but don't provide any masking */ 573 /* enable IRL7-4 but don't provide any masking */
574 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 574 __raw_writel(0x40000000, INTC_INTMSKCLR1);
575 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 575 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
576 break; 576 break;
577 case IRQ_MODE_IRL3210: 577 case IRQ_MODE_IRL3210:
578 /* enable IRL0-3 but don't provide any masking */ 578 /* enable IRL0-3 but don't provide any masking */
579 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 579 __raw_writel(0x80000000, INTC_INTMSKCLR1);
580 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 580 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
581 break; 581 break;
582 case IRQ_MODE_IRL7654_MASK: 582 case IRQ_MODE_IRL7654_MASK:
583 /* enable IRL7-4 and mask using cpu intc controller */ 583 /* enable IRL7-4 and mask using cpu intc controller */
584 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 584 __raw_writel(0x40000000, INTC_INTMSKCLR1);
585 register_intc_controller(&intc_desc_irl4567); 585 register_intc_controller(&intc_desc_irl4567);
586 break; 586 break;
587 case IRQ_MODE_IRL3210_MASK: 587 case IRQ_MODE_IRL3210_MASK:
588 /* enable IRL0-3 and mask using cpu intc controller */ 588 /* enable IRL0-3 and mask using cpu intc controller */
589 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 589 __raw_writel(0x80000000, INTC_INTMSKCLR1);
590 register_intc_controller(&intc_desc_irl0123); 590 register_intc_controller(&intc_desc_irl0123);
591 break; 591 break;
592 default: 592 default:
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
index 71673487ace..7e585320710 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7786.c
@@ -867,14 +867,14 @@ static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
867void __init plat_irq_setup(void) 867void __init plat_irq_setup(void)
868{ 868{
869 /* disable IRQ3-0 + IRQ7-4 */ 869 /* disable IRQ3-0 + IRQ7-4 */
870 ctrl_outl(0xff000000, INTC_INTMSK0); 870 __raw_writel(0xff000000, INTC_INTMSK0);
871 871
872 /* disable IRL3-0 + IRL7-4 */ 872 /* disable IRL3-0 + IRL7-4 */
873 ctrl_outl(0xc0000000, INTC_INTMSK1); 873 __raw_writel(0xc0000000, INTC_INTMSK1);
874 ctrl_outl(0xfffefffe, INTC_INTMSK2); 874 __raw_writel(0xfffefffe, INTC_INTMSK2);
875 875
876 /* select IRL mode for IRL3-0 + IRL7-4 */ 876 /* select IRL mode for IRL3-0 + IRL7-4 */
877 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0); 877 __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
878 878
879 register_intc_controller(&intc_desc); 879 register_intc_controller(&intc_desc);
880} 880}
@@ -884,32 +884,32 @@ void __init plat_irq_setup_pins(int mode)
884 switch (mode) { 884 switch (mode) {
885 case IRQ_MODE_IRQ7654: 885 case IRQ_MODE_IRQ7654:
886 /* select IRQ mode for IRL7-4 */ 886 /* select IRQ mode for IRL7-4 */
887 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0); 887 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
888 register_intc_controller(&intc_desc_irq4567); 888 register_intc_controller(&intc_desc_irq4567);
889 break; 889 break;
890 case IRQ_MODE_IRQ3210: 890 case IRQ_MODE_IRQ3210:
891 /* select IRQ mode for IRL3-0 */ 891 /* select IRQ mode for IRL3-0 */
892 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0); 892 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
893 register_intc_controller(&intc_desc_irq0123); 893 register_intc_controller(&intc_desc_irq0123);
894 break; 894 break;
895 case IRQ_MODE_IRL7654: 895 case IRQ_MODE_IRL7654:
896 /* enable IRL7-4 but don't provide any masking */ 896 /* enable IRL7-4 but don't provide any masking */
897 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 897 __raw_writel(0x40000000, INTC_INTMSKCLR1);
898 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2); 898 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
899 break; 899 break;
900 case IRQ_MODE_IRL3210: 900 case IRQ_MODE_IRL3210:
901 /* enable IRL0-3 but don't provide any masking */ 901 /* enable IRL0-3 but don't provide any masking */
902 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 902 __raw_writel(0x80000000, INTC_INTMSKCLR1);
903 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); 903 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
904 break; 904 break;
905 case IRQ_MODE_IRL7654_MASK: 905 case IRQ_MODE_IRL7654_MASK:
906 /* enable IRL7-4 and mask using cpu intc controller */ 906 /* enable IRL7-4 and mask using cpu intc controller */
907 ctrl_outl(0x40000000, INTC_INTMSKCLR1); 907 __raw_writel(0x40000000, INTC_INTMSKCLR1);
908 register_intc_controller(&intc_desc_irl4567); 908 register_intc_controller(&intc_desc_irl4567);
909 break; 909 break;
910 case IRQ_MODE_IRL3210_MASK: 910 case IRQ_MODE_IRL3210_MASK:
911 /* enable IRL0-3 and mask using cpu intc controller */ 911 /* enable IRL0-3 and mask using cpu intc controller */
912 ctrl_outl(0x80000000, INTC_INTMSKCLR1); 912 __raw_writel(0x80000000, INTC_INTMSKCLR1);
913 register_intc_controller(&intc_desc_irl0123); 913 register_intc_controller(&intc_desc_irl0123);
914 break; 914 break;
915 default: 915 default:
diff --git a/arch/sh/kernel/cpu/sh5/clock-sh5.c b/arch/sh/kernel/cpu/sh5/clock-sh5.c
index 7f864ebc51d..9cfc19b8dbe 100644
--- a/arch/sh/kernel/cpu/sh5/clock-sh5.c
+++ b/arch/sh/kernel/cpu/sh5/clock-sh5.c
@@ -24,7 +24,7 @@ static unsigned long cprc_base;
24 24
25static void master_clk_init(struct clk *clk) 25static void master_clk_init(struct clk *clk)
26{ 26{
27 int idx = (ctrl_inl(cprc_base + 0x00) >> 6) & 0x0007; 27 int idx = (__raw_readl(cprc_base + 0x00) >> 6) & 0x0007;
28 clk->rate *= ifc_table[idx]; 28 clk->rate *= ifc_table[idx];
29} 29}
30 30
@@ -34,7 +34,7 @@ static struct clk_ops sh5_master_clk_ops = {
34 34
35static unsigned long module_clk_recalc(struct clk *clk) 35static unsigned long module_clk_recalc(struct clk *clk)
36{ 36{
37 int idx = (ctrl_inw(cprc_base) >> 12) & 0x0007; 37 int idx = (__raw_readw(cprc_base) >> 12) & 0x0007;
38 return clk->parent->rate / ifc_table[idx]; 38 return clk->parent->rate / ifc_table[idx];
39} 39}
40 40
@@ -44,7 +44,7 @@ static struct clk_ops sh5_module_clk_ops = {
44 44
45static unsigned long bus_clk_recalc(struct clk *clk) 45static unsigned long bus_clk_recalc(struct clk *clk)
46{ 46{
47 int idx = (ctrl_inw(cprc_base) >> 3) & 0x0007; 47 int idx = (__raw_readw(cprc_base) >> 3) & 0x0007;
48 return clk->parent->rate / ifc_table[idx]; 48 return clk->parent->rate / ifc_table[idx];
49} 49}
50 50
@@ -54,7 +54,7 @@ static struct clk_ops sh5_bus_clk_ops = {
54 54
55static unsigned long cpu_clk_recalc(struct clk *clk) 55static unsigned long cpu_clk_recalc(struct clk *clk)
56{ 56{
57 int idx = (ctrl_inw(cprc_base) & 0x0007); 57 int idx = (__raw_readw(cprc_base) & 0x0007);
58 return clk->parent->rate / ifc_table[idx]; 58 return clk->parent->rate / ifc_table[idx];
59} 59}
60 60
diff --git a/arch/sh/kernel/io_trapped.c b/arch/sh/kernel/io_trapped.c
index 69be603aa2d..16b83cc89a4 100644
--- a/arch/sh/kernel/io_trapped.c
+++ b/arch/sh/kernel/io_trapped.c
@@ -184,31 +184,31 @@ static unsigned long long copy_word(unsigned long src_addr, int src_len,
184 184
185 switch (src_len) { 185 switch (src_len) {
186 case 1: 186 case 1:
187 tmp = ctrl_inb(src_addr); 187 tmp = __raw_readb(src_addr);
188 break; 188 break;
189 case 2: 189 case 2:
190 tmp = ctrl_inw(src_addr); 190 tmp = __raw_readw(src_addr);
191 break; 191 break;
192 case 4: 192 case 4:
193 tmp = ctrl_inl(src_addr); 193 tmp = __raw_readl(src_addr);
194 break; 194 break;
195 case 8: 195 case 8:
196 tmp = ctrl_inq(src_addr); 196 tmp = __raw_readq(src_addr);
197 break; 197 break;
198 } 198 }
199 199
200 switch (dst_len) { 200 switch (dst_len) {
201 case 1: 201 case 1:
202 ctrl_outb(tmp, dst_addr); 202 __raw_writeb(tmp, dst_addr);
203 break; 203 break;
204 case 2: 204 case 2:
205 ctrl_outw(tmp, dst_addr); 205 __raw_writew(tmp, dst_addr);
206 break; 206 break;
207 case 4: 207 case 4:
208 ctrl_outl(tmp, dst_addr); 208 __raw_writel(tmp, dst_addr);
209 break; 209 break;
210 case 8: 210 case 8:
211 ctrl_outq(tmp, dst_addr); 211 __raw_writeq(tmp, dst_addr);
212 break; 212 break;
213 } 213 }
214 214
diff --git a/arch/sh/kernel/process_32.c b/arch/sh/kernel/process_32.c
index b6f43f0ea74..3cb88f114d7 100644
--- a/arch/sh/kernel/process_32.c
+++ b/arch/sh/kernel/process_32.c
@@ -41,7 +41,7 @@ void show_regs(struct pt_regs * regs)
41 printk("PC : %08lx SP : %08lx SR : %08lx ", 41 printk("PC : %08lx SP : %08lx SR : %08lx ",
42 regs->pc, regs->regs[15], regs->sr); 42 regs->pc, regs->regs[15], regs->sr);
43#ifdef CONFIG_MMU 43#ifdef CONFIG_MMU
44 printk("TEA : %08x\n", ctrl_inl(MMU_TEA)); 44 printk("TEA : %08x\n", __raw_readl(MMU_TEA));
45#else 45#else
46 printk("\n"); 46 printk("\n");
47#endif 47#endif
diff --git a/arch/sh/kernel/signal_32.c b/arch/sh/kernel/signal_32.c
index 6a7cce79eb4..579cd2ca358 100644
--- a/arch/sh/kernel/signal_32.c
+++ b/arch/sh/kernel/signal_32.c
@@ -528,7 +528,7 @@ handle_syscall_restart(unsigned long save_r0, struct pt_regs *regs,
528 /* fallthrough */ 528 /* fallthrough */
529 case -ERESTARTNOINTR: 529 case -ERESTARTNOINTR:
530 regs->regs[0] = save_r0; 530 regs->regs[0] = save_r0;
531 regs->pc -= instruction_size(ctrl_inw(regs->pc - 4)); 531 regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
532 break; 532 break;
533 } 533 }
534} 534}
@@ -626,9 +626,9 @@ no_signal:
626 regs->regs[0] == -ERESTARTSYS || 626 regs->regs[0] == -ERESTARTSYS ||
627 regs->regs[0] == -ERESTARTNOINTR) { 627 regs->regs[0] == -ERESTARTNOINTR) {
628 regs->regs[0] = save_r0; 628 regs->regs[0] = save_r0;
629 regs->pc -= instruction_size(ctrl_inw(regs->pc - 4)); 629 regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
630 } else if (regs->regs[0] == -ERESTART_RESTARTBLOCK) { 630 } else if (regs->regs[0] == -ERESTART_RESTARTBLOCK) {
631 regs->pc -= instruction_size(ctrl_inw(regs->pc - 4)); 631 regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
632 regs->regs[3] = __NR_restart_syscall; 632 regs->regs[3] = __NR_restart_syscall;
633 } 633 }
634 } 634 }
diff --git a/arch/sh/kernel/traps.c b/arch/sh/kernel/traps.c
index 7b036339dc9..0830c2a9f71 100644
--- a/arch/sh/kernel/traps.c
+++ b/arch/sh/kernel/traps.c
@@ -58,7 +58,7 @@ BUILD_TRAP_HANDLER(debug)
58 TRAP_HANDLER_DECL; 58 TRAP_HANDLER_DECL;
59 59
60 /* Rewind */ 60 /* Rewind */
61 regs->pc -= instruction_size(ctrl_inw(regs->pc - 4)); 61 regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
62 62
63 if (notify_die(DIE_TRAP, "debug trap", regs, 0, vec & 0xff, 63 if (notify_die(DIE_TRAP, "debug trap", regs, 0, vec & 0xff,
64 SIGTRAP) == NOTIFY_STOP) 64 SIGTRAP) == NOTIFY_STOP)
@@ -75,7 +75,7 @@ BUILD_TRAP_HANDLER(bug)
75 TRAP_HANDLER_DECL; 75 TRAP_HANDLER_DECL;
76 76
77 /* Rewind */ 77 /* Rewind */
78 regs->pc -= instruction_size(ctrl_inw(regs->pc - 4)); 78 regs->pc -= instruction_size(__raw_readw(regs->pc - 4));
79 79
80 if (notify_die(DIE_TRAP, "bug trap", regs, 0, TRAPA_BUG_OPCODE & 0xff, 80 if (notify_die(DIE_TRAP, "bug trap", regs, 0, TRAPA_BUG_OPCODE & 0xff,
81 SIGTRAP) == NOTIFY_STOP) 81 SIGTRAP) == NOTIFY_STOP)
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 48ce82ee9fd..690ed010d00 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -36,7 +36,7 @@ static int cache_seq_show(struct seq_file *file, void *iter)
36 */ 36 */
37 jump_to_uncached(); 37 jump_to_uncached();
38 38
39 ccr = ctrl_inl(CCR); 39 ccr = __raw_readl(CCR);
40 if ((ccr & CCR_CACHE_ENABLE) == 0) { 40 if ((ccr & CCR_CACHE_ENABLE) == 0) {
41 back_to_cached(); 41 back_to_cached();
42 42
@@ -89,7 +89,7 @@ static int cache_seq_show(struct seq_file *file, void *iter)
89 for (addr = addrstart, line = 0; 89 for (addr = addrstart, line = 0;
90 addr < addrstart + waysize; 90 addr < addrstart + waysize;
91 addr += cache->linesz, line++) { 91 addr += cache->linesz, line++) {
92 unsigned long data = ctrl_inl(addr); 92 unsigned long data = __raw_readl(addr);
93 93
94 /* Check the V bit, ignore invalid cachelines */ 94 /* Check the V bit, ignore invalid cachelines */
95 if ((data & 1) == 0) 95 if ((data & 1) == 0)
diff --git a/arch/sh/mm/cache-sh2.c b/arch/sh/mm/cache-sh2.c
index 699a71f4632..defcf719f2e 100644
--- a/arch/sh/mm/cache-sh2.c
+++ b/arch/sh/mm/cache-sh2.c
@@ -28,10 +28,10 @@ static void sh2__flush_wback_region(void *start, int size)
28 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0); 28 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0);
29 int way; 29 int way;
30 for (way = 0; way < 4; way++) { 30 for (way = 0; way < 4; way++) {
31 unsigned long data = ctrl_inl(addr | (way << 12)); 31 unsigned long data = __raw_readl(addr | (way << 12));
32 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { 32 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
33 data &= ~SH_CACHE_UPDATED; 33 data &= ~SH_CACHE_UPDATED;
34 ctrl_outl(data, addr | (way << 12)); 34 __raw_writel(data, addr | (way << 12));
35 } 35 }
36 } 36 }
37 } 37 }
@@ -47,7 +47,7 @@ static void sh2__flush_purge_region(void *start, int size)
47 & ~(L1_CACHE_BYTES-1); 47 & ~(L1_CACHE_BYTES-1);
48 48
49 for (v = begin; v < end; v+=L1_CACHE_BYTES) 49 for (v = begin; v < end; v+=L1_CACHE_BYTES)
50 ctrl_outl((v & CACHE_PHYSADDR_MASK), 50 __raw_writel((v & CACHE_PHYSADDR_MASK),
51 CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); 51 CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
52} 52}
53 53
@@ -63,9 +63,9 @@ static void sh2__flush_invalidate_region(void *start, int size)
63 local_irq_save(flags); 63 local_irq_save(flags);
64 jump_to_uncached(); 64 jump_to_uncached();
65 65
66 ccr = ctrl_inl(CCR); 66 ccr = __raw_readl(CCR);
67 ccr |= CCR_CACHE_INVALIDATE; 67 ccr |= CCR_CACHE_INVALIDATE;
68 ctrl_outl(ccr, CCR); 68 __raw_writel(ccr, CCR);
69 69
70 back_to_cached(); 70 back_to_cached();
71 local_irq_restore(flags); 71 local_irq_restore(flags);
@@ -78,7 +78,7 @@ static void sh2__flush_invalidate_region(void *start, int size)
78 & ~(L1_CACHE_BYTES-1); 78 & ~(L1_CACHE_BYTES-1);
79 79
80 for (v = begin; v < end; v+=L1_CACHE_BYTES) 80 for (v = begin; v < end; v+=L1_CACHE_BYTES)
81 ctrl_outl((v & CACHE_PHYSADDR_MASK), 81 __raw_writel((v & CACHE_PHYSADDR_MASK),
82 CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008); 82 CACHE_OC_ADDRESS_ARRAY | (v & 0x00000ff0) | 0x00000008);
83#endif 83#endif
84} 84}
diff --git a/arch/sh/mm/cache-sh2a.c b/arch/sh/mm/cache-sh2a.c
index 975899d8356..1f51225426a 100644
--- a/arch/sh/mm/cache-sh2a.c
+++ b/arch/sh/mm/cache-sh2a.c
@@ -32,10 +32,10 @@ static void sh2a__flush_wback_region(void *start, int size)
32 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0); 32 unsigned long addr = CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0);
33 int way; 33 int way;
34 for (way = 0; way < 4; way++) { 34 for (way = 0; way < 4; way++) {
35 unsigned long data = ctrl_inl(addr | (way << 11)); 35 unsigned long data = __raw_readl(addr | (way << 11));
36 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { 36 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
37 data &= ~SH_CACHE_UPDATED; 37 data &= ~SH_CACHE_UPDATED;
38 ctrl_outl(data, addr | (way << 11)); 38 __raw_writel(data, addr | (way << 11));
39 } 39 }
40 } 40 }
41 } 41 }
@@ -58,7 +58,7 @@ static void sh2a__flush_purge_region(void *start, int size)
58 jump_to_uncached(); 58 jump_to_uncached();
59 59
60 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 60 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
61 ctrl_outl((v & CACHE_PHYSADDR_MASK), 61 __raw_writel((v & CACHE_PHYSADDR_MASK),
62 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); 62 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
63 } 63 }
64 back_to_cached(); 64 back_to_cached();
@@ -78,17 +78,17 @@ static void sh2a__flush_invalidate_region(void *start, int size)
78 jump_to_uncached(); 78 jump_to_uncached();
79 79
80#ifdef CONFIG_CACHE_WRITEBACK 80#ifdef CONFIG_CACHE_WRITEBACK
81 ctrl_outl(ctrl_inl(CCR) | CCR_OCACHE_INVALIDATE, CCR); 81 __raw_writel(__raw_readl(CCR) | CCR_OCACHE_INVALIDATE, CCR);
82 /* I-cache invalidate */ 82 /* I-cache invalidate */
83 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 83 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
84 ctrl_outl((v & CACHE_PHYSADDR_MASK), 84 __raw_writel((v & CACHE_PHYSADDR_MASK),
85 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); 85 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
86 } 86 }
87#else 87#else
88 for (v = begin; v < end; v+=L1_CACHE_BYTES) { 88 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
89 ctrl_outl((v & CACHE_PHYSADDR_MASK), 89 __raw_writel((v & CACHE_PHYSADDR_MASK),
90 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); 90 CACHE_IC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
91 ctrl_outl((v & CACHE_PHYSADDR_MASK), 91 __raw_writel((v & CACHE_PHYSADDR_MASK),
92 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008); 92 CACHE_OC_ADDRESS_ARRAY | (v & 0x000007f0) | 0x00000008);
93 } 93 }
94#endif 94#endif
@@ -115,14 +115,14 @@ static void sh2a_flush_icache_range(void *args)
115 int way; 115 int way;
116 /* O-Cache writeback */ 116 /* O-Cache writeback */
117 for (way = 0; way < 4; way++) { 117 for (way = 0; way < 4; way++) {
118 unsigned long data = ctrl_inl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11)); 118 unsigned long data = __raw_readl(CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
119 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) { 119 if ((data & CACHE_PHYSADDR_MASK) == (v & CACHE_PHYSADDR_MASK)) {
120 data &= ~SH_CACHE_UPDATED; 120 data &= ~SH_CACHE_UPDATED;
121 ctrl_outl(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11)); 121 __raw_writel(data, CACHE_OC_ADDRESS_ARRAY | addr | (way << 11));
122 } 122 }
123 } 123 }
124 /* I-Cache invalidate */ 124 /* I-Cache invalidate */
125 ctrl_outl(addr, 125 __raw_writel(addr,
126 CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008); 126 CACHE_IC_ADDRESS_ARRAY | addr | 0x00000008);
127 } 127 }
128 128
diff --git a/arch/sh/mm/cache-sh3.c b/arch/sh/mm/cache-sh3.c
index faef80c9813..e37523f6519 100644
--- a/arch/sh/mm/cache-sh3.c
+++ b/arch/sh/mm/cache-sh3.c
@@ -50,12 +50,12 @@ static void sh3__flush_wback_region(void *start, int size)
50 p = __pa(v); 50 p = __pa(v);
51 addr = addrstart | (v & current_cpu_data.dcache.entry_mask); 51 addr = addrstart | (v & current_cpu_data.dcache.entry_mask);
52 local_irq_save(flags); 52 local_irq_save(flags);
53 data = ctrl_inl(addr); 53 data = __raw_readl(addr);
54 54
55 if ((data & CACHE_PHYSADDR_MASK) == 55 if ((data & CACHE_PHYSADDR_MASK) ==
56 (p & CACHE_PHYSADDR_MASK)) { 56 (p & CACHE_PHYSADDR_MASK)) {
57 data &= ~SH_CACHE_UPDATED; 57 data &= ~SH_CACHE_UPDATED;
58 ctrl_outl(data, addr); 58 __raw_writel(data, addr);
59 local_irq_restore(flags); 59 local_irq_restore(flags);
60 break; 60 break;
61 } 61 }
@@ -86,7 +86,7 @@ static void sh3__flush_purge_region(void *start, int size)
86 data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */ 86 data = (v & 0xfffffc00); /* _Virtual_ address, ~U, ~V */
87 addr = CACHE_OC_ADDRESS_ARRAY | 87 addr = CACHE_OC_ADDRESS_ARRAY |
88 (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC; 88 (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC;
89 ctrl_outl(data, addr); 89 __raw_writel(data, addr);
90 } 90 }
91} 91}
92 92
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index 87115b3ee70..2cfae81914a 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -132,9 +132,9 @@ static void flush_icache_all(void)
132 jump_to_uncached(); 132 jump_to_uncached();
133 133
134 /* Flush I-cache */ 134 /* Flush I-cache */
135 ccr = ctrl_inl(CCR); 135 ccr = __raw_readl(CCR);
136 ccr |= CCR_CACHE_ICI; 136 ccr |= CCR_CACHE_ICI;
137 ctrl_outl(ccr, CCR); 137 __raw_writel(ccr, CCR);
138 138
139 /* 139 /*
140 * back_to_cached() will take care of the barrier for us, don't add 140 * back_to_cached() will take care of the barrier for us, don't add
@@ -377,9 +377,9 @@ extern void __weak sh4__flush_region_init(void);
377void __init sh4_cache_init(void) 377void __init sh4_cache_init(void)
378{ 378{
379 printk("PVR=%08x CVR=%08x PRR=%08x\n", 379 printk("PVR=%08x CVR=%08x PRR=%08x\n",
380 ctrl_inl(CCN_PVR), 380 __raw_readl(CCN_PVR),
381 ctrl_inl(CCN_CVR), 381 __raw_readl(CCN_CVR),
382 ctrl_inl(CCN_PRR)); 382 __raw_readl(CCN_PRR));
383 383
384 local_flush_icache_range = sh4_flush_icache_range; 384 local_flush_icache_range = sh4_flush_icache_range;
385 local_flush_dcache_page = sh4_flush_dcache_page; 385 local_flush_dcache_page = sh4_flush_dcache_page;
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c
index 870293ee539..f498da1cce7 100644
--- a/arch/sh/mm/cache-sh7705.c
+++ b/arch/sh/mm/cache-sh7705.c
@@ -48,10 +48,10 @@ static inline void cache_wback_all(void)
48 unsigned long data; 48 unsigned long data;
49 int v = SH_CACHE_UPDATED | SH_CACHE_VALID; 49 int v = SH_CACHE_UPDATED | SH_CACHE_VALID;
50 50
51 data = ctrl_inl(addr); 51 data = __raw_readl(addr);
52 52
53 if ((data & v) == v) 53 if ((data & v) == v)
54 ctrl_outl(data & ~v, addr); 54 __raw_writel(data & ~v, addr);
55 55
56 } 56 }
57 57
@@ -115,10 +115,10 @@ static void __flush_dcache_page(unsigned long phys)
115 addr += current_cpu_data.dcache.linesz) { 115 addr += current_cpu_data.dcache.linesz) {
116 unsigned long data; 116 unsigned long data;
117 117
118 data = ctrl_inl(addr) & (0x1ffffC00 | SH_CACHE_VALID); 118 data = __raw_readl(addr) & (0x1ffffC00 | SH_CACHE_VALID);
119 if (data == phys) { 119 if (data == phys) {
120 data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED); 120 data &= ~(SH_CACHE_VALID | SH_CACHE_UPDATED);
121 ctrl_outl(data, addr); 121 __raw_writel(data, addr);
122 } 122 }
123 } 123 }
124 124
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index 3d5eece7e6d..3c9bf5b5c36 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -112,7 +112,7 @@ static void pmb_free(struct pmb_entry *pmbe)
112static void __set_pmb_entry(unsigned long vpn, unsigned long ppn, 112static void __set_pmb_entry(unsigned long vpn, unsigned long ppn,
113 unsigned long flags, int pos) 113 unsigned long flags, int pos)
114{ 114{
115 ctrl_outl(vpn | PMB_V, mk_pmb_addr(pos)); 115 __raw_writel(vpn | PMB_V, mk_pmb_addr(pos));
116 116
117#ifdef CONFIG_CACHE_WRITETHROUGH 117#ifdef CONFIG_CACHE_WRITETHROUGH
118 /* 118 /*
@@ -124,7 +124,7 @@ static void __set_pmb_entry(unsigned long vpn, unsigned long ppn,
124 flags |= PMB_WT; 124 flags |= PMB_WT;
125#endif 125#endif
126 126
127 ctrl_outl(ppn | flags | PMB_V, mk_pmb_data(pos)); 127 __raw_writel(ppn | flags | PMB_V, mk_pmb_data(pos));
128} 128}
129 129
130static void set_pmb_entry(struct pmb_entry *pmbe) 130static void set_pmb_entry(struct pmb_entry *pmbe)
@@ -146,10 +146,10 @@ static void clear_pmb_entry(struct pmb_entry *pmbe)
146 146
147 /* Clear V-bit */ 147 /* Clear V-bit */
148 addr = mk_pmb_addr(entry); 148 addr = mk_pmb_addr(entry);
149 ctrl_outl(ctrl_inl(addr) & ~PMB_V, addr); 149 __raw_writel(__raw_readl(addr) & ~PMB_V, addr);
150 150
151 addr = mk_pmb_data(entry); 151 addr = mk_pmb_data(entry);
152 ctrl_outl(ctrl_inl(addr) & ~PMB_V, addr); 152 __raw_writel(__raw_readl(addr) & ~PMB_V, addr);
153 153
154 back_to_cached(); 154 back_to_cached();
155} 155}
@@ -395,7 +395,7 @@ int pmb_init(void)
395 unsigned long vpn, ppn, flags; 395 unsigned long vpn, ppn, flags;
396 396
397 addr = PMB_DATA + (i << PMB_E_SHIFT); 397 addr = PMB_DATA + (i << PMB_E_SHIFT);
398 data = ctrl_inl(addr); 398 data = __raw_readl(addr);
399 if (!(data & PMB_V)) 399 if (!(data & PMB_V))
400 continue; 400 continue;
401 401
@@ -408,7 +408,7 @@ int pmb_init(void)
408 data &= ~(PMB_C | PMB_WT); 408 data &= ~(PMB_C | PMB_WT);
409#endif 409#endif
410 } 410 }
411 ctrl_outl(data, addr); 411 __raw_writel(data, addr);
412 412
413 ppn = data & PMB_PFN_MASK; 413 ppn = data & PMB_PFN_MASK;
414 414
@@ -416,7 +416,7 @@ int pmb_init(void)
416 flags |= data & PMB_SZ_MASK; 416 flags |= data & PMB_SZ_MASK;
417 417
418 addr = PMB_ADDR + (i << PMB_E_SHIFT); 418 addr = PMB_ADDR + (i << PMB_E_SHIFT);
419 data = ctrl_inl(addr); 419 data = __raw_readl(addr);
420 420
421 vpn = data & PMB_PFN_MASK; 421 vpn = data & PMB_PFN_MASK;
422 422
@@ -424,12 +424,12 @@ int pmb_init(void)
424 WARN_ON(IS_ERR(pmbe)); 424 WARN_ON(IS_ERR(pmbe));
425 } 425 }
426 426
427 ctrl_outl(0, PMB_IRMCR); 427 __raw_writel(0, PMB_IRMCR);
428 428
429 /* Flush out the TLB */ 429 /* Flush out the TLB */
430 i = ctrl_inl(MMUCR); 430 i = __raw_readl(MMUCR);
431 i |= MMUCR_TI; 431 i |= MMUCR_TI;
432 ctrl_outl(i, MMUCR); 432 __raw_writel(i, MMUCR);
433 433
434 back_to_cached(); 434 back_to_cached();
435 435
@@ -454,8 +454,8 @@ static int pmb_seq_show(struct seq_file *file, void *iter)
454 unsigned int size; 454 unsigned int size;
455 char *sz_str = NULL; 455 char *sz_str = NULL;
456 456
457 addr = ctrl_inl(mk_pmb_addr(i)); 457 addr = __raw_readl(mk_pmb_addr(i));
458 data = ctrl_inl(mk_pmb_data(i)); 458 data = __raw_readl(mk_pmb_data(i));
459 459
460 size = data & PMB_SZ_MASK; 460 size = data & PMB_SZ_MASK;
461 sz_str = (size == PMB_SZ_16M) ? " 16MB": 461 sz_str = (size == PMB_SZ_16M) ? " 16MB":
diff --git a/arch/sh/mm/tlb-sh3.c b/arch/sh/mm/tlb-sh3.c
index ace8e6d2f59..4f5f7cbdd50 100644
--- a/arch/sh/mm/tlb-sh3.c
+++ b/arch/sh/mm/tlb-sh3.c
@@ -41,14 +41,14 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
41 41
42 /* Set PTEH register */ 42 /* Set PTEH register */
43 vpn = (address & MMU_VPN_MASK) | get_asid(); 43 vpn = (address & MMU_VPN_MASK) | get_asid();
44 ctrl_outl(vpn, MMU_PTEH); 44 __raw_writel(vpn, MMU_PTEH);
45 45
46 pteval = pte_val(pte); 46 pteval = pte_val(pte);
47 47
48 /* Set PTEL register */ 48 /* Set PTEL register */
49 pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */ 49 pteval &= _PAGE_FLAGS_HARDWARE_MASK; /* drop software flags */
50 /* conveniently, we want all the software flags to be 0 anyway */ 50 /* conveniently, we want all the software flags to be 0 anyway */
51 ctrl_outl(pteval, MMU_PTEL); 51 __raw_writel(pteval, MMU_PTEL);
52 52
53 /* Load the TLB */ 53 /* Load the TLB */
54 asm volatile("ldtlb": /* no output */ : /* no input */ : "memory"); 54 asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
@@ -75,5 +75,5 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
75 } 75 }
76 76
77 for (i = 0; i < ways; i++) 77 for (i = 0; i < ways; i++)
78 ctrl_outl(data, addr + (i << 8)); 78 __raw_writel(data, addr + (i << 8));
79} 79}
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index 624c1daa9f3..ccac77f504a 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -29,7 +29,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
29 29
30 /* Set PTEH register */ 30 /* Set PTEH register */
31 vpn = (address & MMU_VPN_MASK) | get_asid(); 31 vpn = (address & MMU_VPN_MASK) | get_asid();
32 ctrl_outl(vpn, MMU_PTEH); 32 __raw_writel(vpn, MMU_PTEH);
33 33
34 pteval = pte.pte_low; 34 pteval = pte.pte_low;
35 35
@@ -41,13 +41,13 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
41 * the protection bits (with the exception of the compat-mode SZ 41 * the protection bits (with the exception of the compat-mode SZ
42 * and PR bits, which are cleared) being written out in PTEL. 42 * and PR bits, which are cleared) being written out in PTEL.
43 */ 43 */
44 ctrl_outl(pte.pte_high, MMU_PTEA); 44 __raw_writel(pte.pte_high, MMU_PTEA);
45#else 45#else
46 if (cpu_data->flags & CPU_HAS_PTEA) { 46 if (cpu_data->flags & CPU_HAS_PTEA) {
47 /* The last 3 bits and the first one of pteval contains 47 /* The last 3 bits and the first one of pteval contains
48 * the PTEA timing control and space attribute bits 48 * the PTEA timing control and space attribute bits
49 */ 49 */
50 ctrl_outl(copy_ptea_attributes(pteval), MMU_PTEA); 50 __raw_writel(copy_ptea_attributes(pteval), MMU_PTEA);
51 } 51 }
52#endif 52#endif
53 53
@@ -57,7 +57,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
57 pteval |= _PAGE_WT; 57 pteval |= _PAGE_WT;
58#endif 58#endif
59 /* conveniently, we want all the software flags to be 0 anyway */ 59 /* conveniently, we want all the software flags to be 0 anyway */
60 ctrl_outl(pteval, MMU_PTEL); 60 __raw_writel(pteval, MMU_PTEL);
61 61
62 /* Load the TLB */ 62 /* Load the TLB */
63 asm volatile("ldtlb": /* no output */ : /* no input */ : "memory"); 63 asm volatile("ldtlb": /* no output */ : /* no input */ : "memory");
@@ -77,6 +77,6 @@ void local_flush_tlb_one(unsigned long asid, unsigned long page)
77 addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT; 77 addr = MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT;
78 data = page | asid; /* VALID bit is off */ 78 data = page | asid; /* VALID bit is off */
79 jump_to_uncached(); 79 jump_to_uncached();
80 ctrl_outl(data, addr); 80 __raw_writel(data, addr);
81 back_to_cached(); 81 back_to_cached();
82} 82}
diff --git a/arch/sh/mm/tlbflush_32.c b/arch/sh/mm/tlbflush_32.c
index 6f45c1f8a7f..004bb3f25b5 100644
--- a/arch/sh/mm/tlbflush_32.c
+++ b/arch/sh/mm/tlbflush_32.c
@@ -132,9 +132,9 @@ void local_flush_tlb_all(void)
132 * It's same position, bit #2. 132 * It's same position, bit #2.
133 */ 133 */
134 local_irq_save(flags); 134 local_irq_save(flags);
135 status = ctrl_inl(MMUCR); 135 status = __raw_readl(MMUCR);
136 status |= 0x04; 136 status |= 0x04;
137 ctrl_outl(status, MMUCR); 137 __raw_writel(status, MMUCR);
138 ctrl_barrier(); 138 ctrl_barrier();
139 local_irq_restore(flags); 139 local_irq_restore(flags);
140} 140}