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authorPaul Mundt <lethal@linux-sh.org>2010-11-15 20:11:20 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-11-15 20:11:20 -0500
commit849653372d3f98332bf84e9fb814d9f9a02eeda2 (patch)
tree0ccb6899ceb664024cc98ddfdf4b55572c45ec32
parent6800e4c0ea3e96cf78953b8b5743381cb1bb9e37 (diff)
parent549015c36baadc6e67861bba6e927259e34c4d59 (diff)
Merge branch 'common/clkfwk' into sh-fixes-for-linus
-rw-r--r--Documentation/DocBook/sh.tmpl4
-rw-r--r--Documentation/sh/clk.txt32
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c6
-rw-r--r--arch/sh/kernel/cpu/sh4/clock-sh4-202.c2
-rw-r--r--drivers/sh/clk/core.c13
-rw-r--r--drivers/sh/clk/cpg.c5
-rw-r--r--include/linux/sh_clk.h34
7 files changed, 11 insertions, 85 deletions
diff --git a/Documentation/DocBook/sh.tmpl b/Documentation/DocBook/sh.tmpl
index d858d92cf6d..4a38f604fa6 100644
--- a/Documentation/DocBook/sh.tmpl
+++ b/Documentation/DocBook/sh.tmpl
@@ -79,10 +79,6 @@
79 </sect2> 79 </sect2>
80 </sect1> 80 </sect1>
81 </chapter> 81 </chapter>
82 <chapter id="clk">
83 <title>Clock Framework Extensions</title>
84!Iinclude/linux/sh_clk.h
85 </chapter>
86 <chapter id="mach"> 82 <chapter id="mach">
87 <title>Machine Specific Interfaces</title> 83 <title>Machine Specific Interfaces</title>
88 <sect1 id="dreamcast"> 84 <sect1 id="dreamcast">
diff --git a/Documentation/sh/clk.txt b/Documentation/sh/clk.txt
deleted file mode 100644
index 114b595cfa9..00000000000
--- a/Documentation/sh/clk.txt
+++ /dev/null
@@ -1,32 +0,0 @@
1Clock framework on SuperH architecture
2
3The framework on SH extends existing API by the function clk_set_rate_ex,
4which prototype is as follows:
5
6 clk_set_rate_ex (struct clk *clk, unsigned long rate, int algo_id)
7
8The algo_id parameter is used to specify algorithm used to recalculate clocks,
9adjanced to clock, specified as first argument. It is assumed that algo_id==0
10means no changes to adjanced clock
11
12Internally, the clk_set_rate_ex forwards request to clk->ops->set_rate method,
13if it is present in ops structure. The method should set the clock rate and adjust
14all needed clocks according to the passed algo_id.
15Exact values for algo_id are machine-dependent. For the sh7722, the following
16values are defined:
17
18 NO_CHANGE = 0,
19 IUS_N1_N1, /* I:U = N:1, U:Sh = N:1 */
20 IUS_322, /* I:U:Sh = 3:2:2 */
21 IUS_522, /* I:U:Sh = 5:2:2 */
22 IUS_N11, /* I:U:Sh = N:1:1 */
23 SB_N1, /* Sh:B = N:1 */
24 SB3_N1, /* Sh:B3 = N:1 */
25 SB3_32, /* Sh:B3 = 3:2 */
26 SB3_43, /* Sh:B3 = 4:3 */
27 SB3_54, /* Sh:B3 = 5:4 */
28 BP_N1, /* B:P = N:1 */
29 IP_N1 /* I:P = N:1 */
30
31Each of these constants means relation between clocks that can be set via the FRQCR
32register
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index 7db31e6c6bf..b25ce90a346 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -220,8 +220,7 @@ static void pllc2_disable(struct clk *clk)
220 __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR); 220 __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
221} 221}
222 222
223static int pllc2_set_rate(struct clk *clk, 223static int pllc2_set_rate(struct clk *clk, unsigned long rate)
224 unsigned long rate, int algo_id)
225{ 224{
226 unsigned long value; 225 unsigned long value;
227 int idx; 226 int idx;
@@ -463,8 +462,7 @@ static int fsidiv_enable(struct clk *clk)
463 return 0; 462 return 0;
464} 463}
465 464
466static int fsidiv_set_rate(struct clk *clk, 465static int fsidiv_set_rate(struct clk *clk, unsigned long rate)
467 unsigned long rate, int algo_id)
468{ 466{
469 int idx; 467 int idx;
470 468
diff --git a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
index 4eabc68cd75..b601fa3978d 100644
--- a/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
+++ b/arch/sh/kernel/cpu/sh4/clock-sh4-202.c
@@ -110,7 +110,7 @@ static int shoc_clk_verify_rate(struct clk *clk, unsigned long rate)
110 return 0; 110 return 0;
111} 111}
112 112
113static int shoc_clk_set_rate(struct clk *clk, unsigned long rate, int algo_id) 113static int shoc_clk_set_rate(struct clk *clk, unsigned long rate)
114{ 114{
115 unsigned long frqcr3; 115 unsigned long frqcr3;
116 unsigned int tmp; 116 unsigned int tmp;
diff --git a/drivers/sh/clk/core.c b/drivers/sh/clk/core.c
index cb12a8e1466..87743e7d4d4 100644
--- a/drivers/sh/clk/core.c
+++ b/drivers/sh/clk/core.c
@@ -455,19 +455,13 @@ EXPORT_SYMBOL_GPL(clk_get_rate);
455 455
456int clk_set_rate(struct clk *clk, unsigned long rate) 456int clk_set_rate(struct clk *clk, unsigned long rate)
457{ 457{
458 return clk_set_rate_ex(clk, rate, 0);
459}
460EXPORT_SYMBOL_GPL(clk_set_rate);
461
462int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id)
463{
464 int ret = -EOPNOTSUPP; 458 int ret = -EOPNOTSUPP;
465 unsigned long flags; 459 unsigned long flags;
466 460
467 spin_lock_irqsave(&clock_lock, flags); 461 spin_lock_irqsave(&clock_lock, flags);
468 462
469 if (likely(clk->ops && clk->ops->set_rate)) { 463 if (likely(clk->ops && clk->ops->set_rate)) {
470 ret = clk->ops->set_rate(clk, rate, algo_id); 464 ret = clk->ops->set_rate(clk, rate);
471 if (ret != 0) 465 if (ret != 0)
472 goto out_unlock; 466 goto out_unlock;
473 } else { 467 } else {
@@ -485,7 +479,7 @@ out_unlock:
485 479
486 return ret; 480 return ret;
487} 481}
488EXPORT_SYMBOL_GPL(clk_set_rate_ex); 482EXPORT_SYMBOL_GPL(clk_set_rate);
489 483
490int clk_set_parent(struct clk *clk, struct clk *parent) 484int clk_set_parent(struct clk *clk, struct clk *parent)
491{ 485{
@@ -653,8 +647,7 @@ static int clks_sysdev_suspend(struct sys_device *dev, pm_message_t state)
653 clkp->ops->set_parent(clkp, 647 clkp->ops->set_parent(clkp,
654 clkp->parent); 648 clkp->parent);
655 if (likely(clkp->ops->set_rate)) 649 if (likely(clkp->ops->set_rate))
656 clkp->ops->set_rate(clkp, 650 clkp->ops->set_rate(clkp, rate);
657 rate, NO_CHANGE);
658 else if (likely(clkp->ops->recalc)) 651 else if (likely(clkp->ops->recalc))
659 clkp->rate = clkp->ops->recalc(clkp); 652 clkp->rate = clkp->ops->recalc(clkp);
660 } 653 }
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 3aea5f0ceb0..359e9a322c7 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -110,8 +110,7 @@ static int sh_clk_div6_set_parent(struct clk *clk, struct clk *parent)
110 return 0; 110 return 0;
111} 111}
112 112
113static int sh_clk_div6_set_rate(struct clk *clk, 113static int sh_clk_div6_set_rate(struct clk *clk, unsigned long rate)
114 unsigned long rate, int algo_id)
115{ 114{
116 unsigned long value; 115 unsigned long value;
117 int idx; 116 int idx;
@@ -253,7 +252,7 @@ static int sh_clk_div4_set_parent(struct clk *clk, struct clk *parent)
253 return 0; 252 return 0;
254} 253}
255 254
256static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate, int algo_id) 255static int sh_clk_div4_set_rate(struct clk *clk, unsigned long rate)
257{ 256{
258 struct clk_div4_table *d4t = clk->priv; 257 struct clk_div4_table *d4t = clk->priv;
259 unsigned long value; 258 unsigned long value;
diff --git a/include/linux/sh_clk.h b/include/linux/sh_clk.h
index cea0c38e7a6..9a52f72527d 100644
--- a/include/linux/sh_clk.h
+++ b/include/linux/sh_clk.h
@@ -19,11 +19,13 @@ struct clk_mapping {
19}; 19};
20 20
21struct clk_ops { 21struct clk_ops {
22#ifdef CONFIG_SH_CLK_CPG_LEGACY
22 void (*init)(struct clk *clk); 23 void (*init)(struct clk *clk);
24#endif
23 int (*enable)(struct clk *clk); 25 int (*enable)(struct clk *clk);
24 void (*disable)(struct clk *clk); 26 void (*disable)(struct clk *clk);
25 unsigned long (*recalc)(struct clk *clk); 27 unsigned long (*recalc)(struct clk *clk);
26 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id); 28 int (*set_rate)(struct clk *clk, unsigned long rate);
27 int (*set_parent)(struct clk *clk, struct clk *parent); 29 int (*set_parent)(struct clk *clk, struct clk *parent);
28 long (*round_rate)(struct clk *clk, unsigned long rate); 30 long (*round_rate)(struct clk *clk, unsigned long rate);
29}; 31};
@@ -67,36 +69,6 @@ int clk_register(struct clk *);
67void clk_unregister(struct clk *); 69void clk_unregister(struct clk *);
68void clk_enable_init_clocks(void); 70void clk_enable_init_clocks(void);
69 71
70/**
71 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
72 * @clk: clock source
73 * @rate: desired clock rate in Hz
74 * @algo_id: algorithm id to be passed down to ops->set_rate
75 *
76 * Returns success (0) or negative errno.
77 */
78int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
79
80enum clk_sh_algo_id {
81 NO_CHANGE = 0,
82
83 IUS_N1_N1,
84 IUS_322,
85 IUS_522,
86 IUS_N11,
87
88 SB_N1,
89
90 SB3_N1,
91 SB3_32,
92 SB3_43,
93 SB3_54,
94
95 BP_N1,
96
97 IP_N1,
98};
99
100struct clk_div_mult_table { 72struct clk_div_mult_table {
101 unsigned int *divisors; 73 unsigned int *divisors;
102 unsigned int nr_divisors; 74 unsigned int nr_divisors;