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authorLei Wen <leiwen@marvell.com>2011-06-07 06:01:06 -0400
committerGreg Kroah-Hartman <gregkh@suse.de>2011-11-11 12:37:16 -0500
commit7b333e0ef8a1efa488ad98956c6701884b0c2b4b (patch)
tree0c27d9bee5160f43c203ba97019fdcfa9f1e58fa
parent1bd1046f37d0a9a76bbcd45284229edacb8d890d (diff)
mtd: pxa3xx_nand: fix nand detection issue
commit 0fab028b77d714ad302404b23306cf7adb885223 upstream. When keep_config is set, the detection would goes different routine. That the driver would read out the setting which is set previously by bootloader. While most bootloader keep the irq mask as off, and current driver need all irq default open, keep_config behavior would lead to no irq at all. Signed-off-by: Lei Wen <leiwen@marvell.com> Tested-by: Daniel Mack <zonque@gmail.com> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/mtd/nand/pxa3xx_nand.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/drivers/mtd/nand/pxa3xx_nand.c b/drivers/mtd/nand/pxa3xx_nand.c
index 1fb3b3a8058..faa0edd2825 100644
--- a/drivers/mtd/nand/pxa3xx_nand.c
+++ b/drivers/mtd/nand/pxa3xx_nand.c
@@ -813,7 +813,7 @@ static int pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
813 info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512; 813 info->page_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
814 /* set info fields needed to read id */ 814 /* set info fields needed to read id */
815 info->read_id_bytes = (info->page_size == 2048) ? 4 : 2; 815 info->read_id_bytes = (info->page_size == 2048) ? 4 : 2;
816 info->reg_ndcr = ndcr; 816 info->reg_ndcr = ndcr & ~NDCR_INT_MASK;
817 info->cmdset = &default_cmdset; 817 info->cmdset = &default_cmdset;
818 818
819 info->ndtr0cs0 = nand_readl(info, NDTR0CS0); 819 info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
@@ -882,7 +882,7 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
882 struct pxa3xx_nand_info *info = mtd->priv; 882 struct pxa3xx_nand_info *info = mtd->priv;
883 struct platform_device *pdev = info->pdev; 883 struct platform_device *pdev = info->pdev;
884 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data; 884 struct pxa3xx_nand_platform_data *pdata = pdev->dev.platform_data;
885 struct nand_flash_dev pxa3xx_flash_ids[2] = { {NULL,}, {NULL,} }; 885 struct nand_flash_dev pxa3xx_flash_ids[2], *def = NULL;
886 const struct pxa3xx_nand_flash *f = NULL; 886 const struct pxa3xx_nand_flash *f = NULL;
887 struct nand_chip *chip = mtd->priv; 887 struct nand_chip *chip = mtd->priv;
888 uint32_t id = -1; 888 uint32_t id = -1;
@@ -942,8 +942,10 @@ static int pxa3xx_nand_scan(struct mtd_info *mtd)
942 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block; 942 pxa3xx_flash_ids[0].erasesize = f->page_size * f->page_per_block;
943 if (f->flash_width == 16) 943 if (f->flash_width == 16)
944 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16; 944 pxa3xx_flash_ids[0].options = NAND_BUSWIDTH_16;
945 pxa3xx_flash_ids[1].name = NULL;
946 def = pxa3xx_flash_ids;
945KEEP_CONFIG: 947KEEP_CONFIG:
946 if (nand_scan_ident(mtd, 1, pxa3xx_flash_ids)) 948 if (nand_scan_ident(mtd, 1, def))
947 return -ENODEV; 949 return -ENODEV;
948 /* calculate addressing information */ 950 /* calculate addressing information */
949 info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1; 951 info->col_addr_cycles = (mtd->writesize >= 2048) ? 2 : 1;
@@ -954,9 +956,9 @@ KEEP_CONFIG:
954 info->row_addr_cycles = 2; 956 info->row_addr_cycles = 2;
955 mtd->name = mtd_names[0]; 957 mtd->name = mtd_names[0];
956 chip->ecc.mode = NAND_ECC_HW; 958 chip->ecc.mode = NAND_ECC_HW;
957 chip->ecc.size = f->page_size; 959 chip->ecc.size = info->page_size;
958 960
959 chip->options = (f->flash_width == 16) ? NAND_BUSWIDTH_16 : 0; 961 chip->options = (info->reg_ndcr & NDCR_DWIDTH_M) ? NAND_BUSWIDTH_16 : 0;
960 chip->options |= NAND_NO_AUTOINCR; 962 chip->options |= NAND_NO_AUTOINCR;
961 chip->options |= NAND_NO_READRDY; 963 chip->options |= NAND_NO_READRDY;
962 964