Merge git://git.kernel.org/pub/scm/linux/kernel/git/nico/orion into devel-stable

152 files changed, 1549 insertions, 1249 deletions

diff --git a/Documentation/DocBook/filesystems.tmpl b/Documentation/DocBook/filesystems.tmpl
index 5e87ad58c0b..f51f28531b8 100644
--- a/Documentation/DocBook/filesystems.tmpl
+++ b/Documentation/DocBook/filesystems.tmpl
@@ -82,6 +82,11 @@
      </sect1>
   </chapter>
 
+  <chapter id="fs_events">
+     <title>Events based on file descriptors</title>
+!Efs/eventfd.c
+  </chapter>
+
   <chapter id="sysfs">
      <title>The Filesystem for Exporting Kernel Objects</title>
 !Efs/sysfs/file.c
diff --git a/Documentation/hwmon/jc42 b/Documentation/hwmon/jc42
index 0e76ef12e4c..a22ecf48f25 100644
--- a/Documentation/hwmon/jc42
+++ b/Documentation/hwmon/jc42
@@ -51,7 +51,8 @@ Supported chips:
   * JEDEC JC 42.4 compliant temperature sensor chips
     Prefix: 'jc42'
     Addresses scanned: I2C 0x18 - 0x1f
-    Datasheet: -
+    Datasheet:
+        http://www.jedec.org/sites/default/files/docs/4_01_04R19.pdf
 
 Author:
         Guenter Roeck <guenter.roeck@ericsson.com>
@@ -60,7 +61,11 @@ Author:
 Description
 -----------
 
-This driver implements support for JEDEC JC 42.4 compliant temperature sensors.
+This driver implements support for JEDEC JC 42.4 compliant temperature sensors,
+which are used on many DDR3 memory modules for mobile devices and servers. Some
+systems use the sensor to prevent memory overheating by automatically throttling
+the memory controller.
+
 The driver auto-detects the chips listed above, but can be manually instantiated
 to support other JC 42.4 compliant chips.
 
@@ -81,15 +86,19 @@ limits. The chip supports only a single register to configure the hysteresis,
 which applies to all limits. This register can be written by writing into
 temp1_crit_hyst. Other hysteresis attributes are read-only.
 
+If the BIOS has configured the sensor for automatic temperature management, it
+is likely that it has locked the registers, i.e., that the temperature limits
+cannot be changed.
+
 Sysfs entries
 -------------
 
 temp1_input             Temperature (RO)
-temp1_min               Minimum temperature (RW)
-temp1_max               Maximum temperature (RW)
-temp1_crit              Critical high temperature (RW)
+temp1_min               Minimum temperature (RO or RW)
+temp1_max               Maximum temperature (RO or RW)
+temp1_crit              Critical high temperature (RO or RW)
 
-temp1_crit_hyst         Critical hysteresis temperature (RW)
+temp1_crit_hyst         Critical hysteresis temperature (RO or RW)
 temp1_max_hyst          Maximum hysteresis temperature (RO)
 
 temp1_min_alarm         Temperature low alarm
diff --git a/Documentation/hwmon/k10temp b/Documentation/hwmon/k10temp
index 6526eee525a..d2b56a4fd1f 100644
--- a/Documentation/hwmon/k10temp
+++ b/Documentation/hwmon/k10temp
@@ -9,6 +9,8 @@ Supported chips:
   Socket S1G3: Athlon II, Sempron, Turion II
 * AMD Family 11h processors:
   Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
+* AMD Family 12h processors: "Llano"
+* AMD Family 14h processors: "Brazos" (C/E/G-Series)
 
   Prefix: 'k10temp'
   Addresses scanned: PCI space
@@ -17,10 +19,14 @@ Supported chips:
     http://support.amd.com/us/Processor_TechDocs/31116.pdf
   BIOS and Kernel Developer's Guide (BKDG) for AMD Family 11h Processors:
     http://support.amd.com/us/Processor_TechDocs/41256.pdf
+  BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
+    http://support.amd.com/us/Processor_TechDocs/43170.pdf
   Revision Guide for AMD Family 10h Processors:
     http://support.amd.com/us/Processor_TechDocs/41322.pdf
   Revision Guide for AMD Family 11h Processors:
     http://support.amd.com/us/Processor_TechDocs/41788.pdf
+  Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
+    http://support.amd.com/us/Processor_TechDocs/47534.pdf
   AMD Family 11h Processor Power and Thermal Data Sheet for Notebooks:
     http://support.amd.com/us/Processor_TechDocs/43373.pdf
   AMD Family 10h Server and Workstation Processor Power and Thermal Data Sheet:
@@ -34,7 +40,7 @@ Description
 -----------
 
 This driver permits reading of the internal temperature sensor of AMD
-Family 10h and 11h processors.
+Family 10h/11h/12h/14h processors.
 
 All these processors have a sensor, but on those for Socket F or AM2+,
 the sensor may return inconsistent values (erratum 319).  The driver
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index 89835a4766a..f4a04c0c7ed 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -144,6 +144,11 @@ a fixed number of characters. This limit depends on the architecture
 and is between 256 and 4096 characters. It is defined in the file
 ./include/asm/setup.h as COMMAND_LINE_SIZE.
 
+Finally, the [KMG] suffix is commonly described after a number of kernel
+parameter values. These 'K', 'M', and 'G' letters represent the _binary_
+multipliers 'Kilo', 'Mega', and 'Giga', equalling 2^10, 2^20, and 2^30
+bytes respectively. Such letter suffixes can also be entirely omitted.
+
 
         acpi=           [HW,ACPI,X86]
                         Advanced Configuration and Power Interface
@@ -545,16 +550,20 @@ and is between 256 and 4096 characters. It is defined in the file
                         Format:
                         <first_slot>,<last_slot>,<port>,<enum_bit>[,<debug>]
 
-        crashkernel=nn[KMG]@ss[KMG]
-                        [KNL] Reserve a chunk of physical memory to
-                        hold a kernel to switch to with kexec on panic.
+        crashkernel=size[KMG][@offset[KMG]]
+                        [KNL] Using kexec, Linux can switch to a 'crash kernel'
+                        upon panic. This parameter reserves the physical
+                        memory region [offset, offset + size] for that kernel
+                        image. If '@offset' is omitted, then a suitable offset
+                        is selected automatically. Check
+                        Documentation/kdump/kdump.txt for further details.
 
         crashkernel=range1:size1[,range2:size2,...][@offset]
                         [KNL] Same as above, but depends on the memory
                         in the running system. The syntax of range is
                         start-[end] where start and end are both
                         a memory unit (amount[KMG]). See also
-                        Documentation/kdump/kdump.txt for a example.
+                        Documentation/kdump/kdump.txt for an example.
 
         cs89x0_dma=     [HW,NET]
                         Format: <dma>
@@ -1262,10 +1271,9 @@ and is between 256 and 4096 characters. It is defined in the file
                         6 (KERN_INFO)           informational
                         7 (KERN_DEBUG)          debug-level messages
 
-        log_buf_len=n   Sets the size of the printk ring buffer, in bytes.
-                        Format: { n | nk | nM }
-                        n must be a power of two.  The default size
-                        is set in the kernel config file.
+        log_buf_len=n[KMG]      Sets the size of the printk ring buffer,
+                        in bytes.  n must be a power of two.  The default
+                        size is set in the kernel config file.
 
         logo.nologo     [FB] Disables display of the built-in Linux logo.
                         This may be used to provide more screen space for
diff --git a/MAINTAINERS b/MAINTAINERS
index 5dd6c751e6a..6f99e1260db 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -885,7 +885,7 @@ S:	Supported
 
 ARM/QUALCOMM MSM MACHINE SUPPORT
 M:      David Brown <davidb@codeaurora.org>
-M:      Daniel Walker <dwalker@codeaurora.org>
+M:      Daniel Walker <dwalker@fifo99.com>
 M:      Bryan Huntsman <bryanh@codeaurora.org>
 L:      linux-arm-msm@vger.kernel.org
 F:      arch/arm/mach-msm/
@@ -2873,7 +2873,6 @@ M:	Guenter Roeck <guenter.roeck@ericsson.com>
 L:      lm-sensors@lm-sensors.org
 W:      http://www.lm-sensors.org/
 T:      quilt kernel.org/pub/linux/kernel/people/jdelvare/linux-2.6/jdelvare-hwmon/
-T:      quilt kernel.org/pub/linux/kernel/people/groeck/linux-staging/
 T:      git git://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git
 S:      Maintained
 F:      Documentation/hwmon/
diff --git a/Makefile b/Makefile
index 5e40aa2acbf..26d7d824db5 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 2
 PATCHLEVEL = 6
 SUBLEVEL = 38
-EXTRAVERSION = -rc5
+EXTRAVERSION = -rc6
 NAME = Flesh-Eating Bats with Fangs
 
 # *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 26d45e5b636..166efa2a19c 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1177,6 +1177,31 @@ config ARM_ERRATA_743622
           visible impact on the overall performance or power consumption of the
           processor.
 
+config ARM_ERRATA_751472
+        bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
+        depends on CPU_V7 && SMP
+        help
+          This option enables the workaround for the 751472 Cortex-A9 (prior
+          to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
+          completion of a following broadcasted operation if the second
+          operation is received by a CPU before the ICIALLUIS has completed,
+          potentially leading to corrupted entries in the cache or TLB.
+
+config ARM_ERRATA_753970
+        bool "ARM errata: cache sync operation may be faulty"
+        depends on CACHE_PL310
+        help
+          This option enables the workaround for the 753970 PL310 (r3p0) erratum.
+
+          Under some condition the effect of cache sync operation on
+          the store buffer still remains when the operation completes.
+          This means that the store buffer is always asked to drain and
+          this prevents it from merging any further writes. The workaround
+          is to replace the normal offset of cache sync operation (0x730)
+          by another offset targeting an unmapped PL310 register 0x740.
+          This has the same effect as the cache sync operation: store buffer
+          drain and waiting for all buffers empty.
+
 endmenu
 
 source "arch/arm/common/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c22c1adfedd..6f7b29294c8 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -15,7 +15,7 @@ ifeq ($(CONFIG_CPU_ENDIAN_BE8),y)
 LDFLAGS_vmlinux += --be8
 endif
 
-OBJCOPYFLAGS    :=-O binary -R .note -R .note.gnu.build-id -R .comment -S
+OBJCOPYFLAGS    :=-O binary -R .comment -S
 GZFLAGS         :=-9
 #KBUILD_CFLAGS  +=-pipe
 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index ab204db594d..c6028967d33 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -1,3 +1,7 @@
 font.c
-piggy.gz
+lib1funcs.S
+piggy.gzip
+piggy.lzo
+piggy.lzma
+vmlinux
 vmlinux.lds
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index 2f704281376..aeb3af541fe 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -24,6 +24,7 @@ CONFIG_MACH_OPENRD_ULTIMATE=y
 CONFIG_MACH_NETSPACE_V2=y
 CONFIG_MACH_INETSPACE_V2=y
 CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_D2NET_V2=y
 CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
diff --git a/arch/arm/include/asm/hardware/cache-l2x0.h b/arch/arm/include/asm/hardware/cache-l2x0.h
index 5aeec1e1735..16bd4803158 100644
--- a/arch/arm/include/asm/hardware/cache-l2x0.h
+++ b/arch/arm/include/asm/hardware/cache-l2x0.h
@@ -36,6 +36,7 @@
 #define L2X0_RAW_INTR_STAT              0x21C
 #define L2X0_INTR_CLEAR                 0x220
 #define L2X0_CACHE_SYNC                 0x730
+#define L2X0_DUMMY_REG                  0x740
 #define L2X0_INV_LINE_PA                0x770
 #define L2X0_INV_WAY                    0x77C
 #define L2X0_CLEAN_LINE_PA              0x7B0
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
index 721847dc68a..e0d1c0cfa54 100644
--- a/arch/arm/include/asm/hardware/sp810.h
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -58,6 +58,9 @@
 
 static inline void sysctl_soft_reset(void __iomem *base)
 {
+        /* switch to slow mode */
+        writel(0x2, base + SCCTRL);
+
         /* writing any value to SCSYSSTAT reg will reset system */
         writel(0, base + SCSYSSTAT);
 }
diff --git a/arch/arm/include/asm/kexec.h b/arch/arm/include/asm/kexec.h
index c0094d8edae..c2b9b4bdec0 100644
--- a/arch/arm/include/asm/kexec.h
+++ b/arch/arm/include/asm/kexec.h
@@ -50,6 +50,9 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
         }
 }
 
+/* Function pointer to optional machine-specific reinitialization */
+extern void (*kexec_reinit)(void);
+
 #endif /* __ASSEMBLY__ */
 
 #endif /* CONFIG_KEXEC */
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index f41a6f57cd1..82dfe5d0c41 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -18,16 +18,34 @@
 #define __ASMARM_TLB_H
 
 #include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
 
 #ifndef CONFIG_MMU
 
 #include <linux/pagemap.h>
+
+#define tlb_flush(tlb)  ((void) tlb)
+
 #include <asm-generic/tlb.h>
 
 #else /* !CONFIG_MMU */
 
+#include <linux/swap.h>
 #include <asm/pgalloc.h>
+#include <asm/tlbflush.h>
+
+/*
+ * We need to delay page freeing for SMP as other CPUs can access pages
+ * which have been removed but not yet had their TLB entries invalidated.
+ * Also, as ARMv7 speculative prefetch can drag new entries into the TLB,
+ * we need to apply this same delaying tactic to ensure correct operation.
+ */
+#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
+#define tlb_fast_mode(tlb)      0
+#define FREE_PTE_NR             500
+#else
+#define tlb_fast_mode(tlb)      1
+#define FREE_PTE_NR             0
+#endif
 
 /*
  * TLB handling.  This allows us to remove pages from the page
@@ -36,12 +54,58 @@
 struct mmu_gather {
         struct mm_struct        *mm;
         unsigned int            fullmm;
+        struct vm_area_struct   *vma;
         unsigned long           range_start;
         unsigned long           range_end;
+        unsigned int            nr;
+        struct page             *pages[FREE_PTE_NR];
 };
 
 DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
 
+/*
+ * This is unnecessarily complex.  There's three ways the TLB shootdown
+ * code is used:
+ *  1. Unmapping a range of vmas.  See zap_page_range(), unmap_region().
+ *     tlb->fullmm = 0, and tlb_start_vma/tlb_end_vma will be called.
+ *     tlb->vma will be non-NULL.
+ *  2. Unmapping all vmas.  See exit_mmap().
+ *     tlb->fullmm = 1, and tlb_start_vma/tlb_end_vma will be called.
+ *     tlb->vma will be non-NULL.  Additionally, page tables will be freed.
+ *  3. Unmapping argument pages.  See shift_arg_pages().
+ *     tlb->fullmm = 0, but tlb_start_vma/tlb_end_vma will not be called.
+ *     tlb->vma will be NULL.
+ */
+static inline void tlb_flush(struct mmu_gather *tlb)
+{
+        if (tlb->fullmm || !tlb->vma)
+                flush_tlb_mm(tlb->mm);
+        else if (tlb->range_end > 0) {
+                flush_tlb_range(tlb->vma, tlb->range_start, tlb->range_end);
+                tlb->range_start = TASK_SIZE;
+                tlb->range_end = 0;
+        }
+}
+
+static inline void tlb_add_flush(struct mmu_gather *tlb, unsigned long addr)
+{
+        if (!tlb->fullmm) {
+                if (addr < tlb->range_start)
+                        tlb->range_start = addr;
+                if (addr + PAGE_SIZE > tlb->range_end)
+                        tlb->range_end = addr + PAGE_SIZE;
+        }
+}
+
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+        tlb_flush(tlb);
+        if (!tlb_fast_mode(tlb)) {
+                free_pages_and_swap_cache(tlb->pages, tlb->nr);
+                tlb->nr = 0;
+        }
+}
+
 static inline struct mmu_gather *
 tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 {
@@ -49,6 +113,8 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 
         tlb->mm = mm;
         tlb->fullmm = full_mm_flush;
+        tlb->vma = NULL;
+        tlb->nr = 0;
 
         return tlb;
 }
@@ -56,8 +122,7 @@ tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
 static inline void
 tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 {
-        if (tlb->fullmm)
-                flush_tlb_mm(tlb->mm);
+        tlb_flush_mmu(tlb);
 
         /* keep the page table cache within bounds */
         check_pgt_cache();
@@ -71,12 +136,7 @@ tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
 static inline void
 tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep, unsigned long addr)
 {
-        if (!tlb->fullmm) {
-                if (addr < tlb->range_start)
-                        tlb->range_start = addr;
-                if (addr + PAGE_SIZE > tlb->range_end)
-                        tlb->range_end = addr + PAGE_SIZE;
-        }
+        tlb_add_flush(tlb, addr);
 }
 
 /*
@@ -89,6 +149,7 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 {
         if (!tlb->fullmm) {
                 flush_cache_range(vma, vma->vm_start, vma->vm_end);
+                tlb->vma = vma;
                 tlb->range_start = TASK_SIZE;
                 tlb->range_end = 0;
         }
@@ -97,12 +158,30 @@ tlb_start_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 static inline void
 tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
 {
-        if (!tlb->fullmm && tlb->range_end > 0)
-                flush_tlb_range(vma, tlb->range_start, tlb->range_end);
+        if (!tlb->fullmm)
+                tlb_flush(tlb);
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+        if (tlb_fast_mode(tlb)) {
+                free_page_and_swap_cache(page);
+        } else {
+                tlb->pages[tlb->nr++] = page;
+                if (tlb->nr >= FREE_PTE_NR)
+                        tlb_flush_mmu(tlb);
+        }
+}
+
+static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
+        unsigned long addr)
+{
+        pgtable_page_dtor(pte);
+        tlb_add_flush(tlb, addr);
+        tlb_remove_page(tlb, pte);
 }
 
-#define tlb_remove_page(tlb,page)       free_page_and_swap_cache(page)
-#define pte_free_tlb(tlb, ptep, addr)   pte_free((tlb)->mm, ptep)
+#define pte_free_tlb(tlb, ptep, addr)   __pte_free_tlb(tlb, ptep, addr)
 #define pmd_free_tlb(tlb, pmdp, addr)   pmd_free((tlb)->mm, pmdp)
 
 #define tlb_migrate_finish(mm)          do { } while (0)
diff --git a/arch/arm/include/asm/tlbflush.h b/arch/arm/include/asm/tlbflush.h
index ce7378ea15a..d2005de383b 100644
--- a/arch/arm/include/asm/tlbflush.h
+++ b/arch/arm/include/asm/tlbflush.h
@@ -10,12 +10,7 @@
 #ifndef _ASMARM_TLBFLUSH_H
 #define _ASMARM_TLBFLUSH_H
 
-
-#ifndef CONFIG_MMU
-
-#define tlb_flush(tlb)  ((void) tlb)
-
-#else /* CONFIG_MMU */
+#ifdef CONFIG_MMU
 
 #include <asm/glue.h>
 
diff --git a/arch/arm/kernel/kprobes-decode.c b/arch/arm/kernel/kprobes-decode.c
index 2c1f0050c9c..8f6ed43861f 100644
--- a/arch/arm/kernel/kprobes-decode.c
+++ b/arch/arm/kernel/kprobes-decode.c
@@ -1437,7 +1437,7 @@ arm_kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi)
 
                 return space_cccc_1100_010x(insn, asi);
 
-        } else if ((insn & 0x0e000000) == 0x0c400000) {
+        } else if ((insn & 0x0e000000) == 0x0c000000) {
 
                 return space_cccc_110x(insn, asi);
 
diff --git a/arch/arm/kernel/machine_kexec.c b/arch/arm/kernel/machine_kexec.c
index 30ead135ff5..e59bbd496c3 100644
--- a/arch/arm/kernel/machine_kexec.c
+++ b/arch/arm/kernel/machine_kexec.c
@@ -75,6 +75,11 @@ void machine_crash_shutdown(struct pt_regs *regs)
         printk(KERN_INFO "Loading crashdump kernel...\n");
 }
 
+/*
+ * Function pointer to optional machine-specific reinitialization
+ */
+void (*kexec_reinit)(void);
+
 void machine_kexec(struct kimage *image)
 {
         unsigned long page_list;
@@ -104,6 +109,8 @@ void machine_kexec(struct kimage *image)
                            (unsigned long) reboot_code_buffer + KEXEC_CONTROL_PAGE_SIZE);
         printk(KERN_INFO "Bye!\n");
 
+        if (kexec_reinit)
+                kexec_reinit();
         local_irq_disable();
         local_fiq_disable();
         setup_mm_for_reboot(0); /* mode is not used, so just pass 0*/
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
index b8af96ea62e..2c79eec1926 100644
--- a/arch/arm/kernel/pmu.c
+++ b/arch/arm/kernel/pmu.c
@@ -97,28 +97,34 @@ set_irq_affinity(int irq,
                            irq, cpu);
         return err;
 #else
-        return 0;
+        return -EINVAL;
 #endif
 }
 
 static int
 init_cpu_pmu(void)
 {
-        int i, err = 0;
+        int i, irqs, err = 0;
         struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU];
 
-        if (!pdev) {
-                err = -ENODEV;
-                goto out;
-        }
+        if (!pdev)
+                return -ENODEV;
+
+        irqs = pdev->num_resources;
+
+        /*
+         * If we have a single PMU interrupt that we can't shift, assume that
+         * we're running on a uniprocessor machine and continue.
+         */
+        if (irqs == 1 && !irq_can_set_affinity(platform_get_irq(pdev, 0)))
+                return 0;
 
-        for (i = 0; i < pdev->num_resources; ++i) {
+        for (i = 0; i < irqs; ++i) {
                 err = set_irq_affinity(platform_get_irq(pdev, i), i);
                 if (err)
                         break;
         }
 
-out:
         return err;
 }
 
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 420b8d6485d..5ea4fb718b9 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -226,8 +226,8 @@ int cpu_architecture(void)
                  * Register 0 and check for VMSAv7 or PMSAv7 */
                 asm("mrc        p15, 0, %0, c0, c1, 4"
                     : "=r" (mmfr0));
-                if ((mmfr0 & 0x0000000f) == 0x00000003 ||
-                    (mmfr0 & 0x000000f0) == 0x00000030)
+                if ((mmfr0 & 0x0000000f) >= 0x00000003 ||
+                    (mmfr0 & 0x000000f0) >= 0x00000030)
                         cpu_arch = CPU_ARCH_ARMv7;
                 else if ((mmfr0 & 0x0000000f) == 0x00000002 ||
                          (mmfr0 & 0x000000f0) == 0x00000020)
diff --git a/arch/arm/kernel/signal.c b/arch/arm/kernel/signal.c
index 907d5a620bc..abaf8445ce2 100644
--- a/arch/arm/kernel/signal.c
+++ b/arch/arm/kernel/signal.c
@@ -474,7 +474,9 @@ setup_return(struct pt_regs *regs, struct k_sigaction *ka,
         unsigned long handler = (unsigned long)ka->sa.sa_handler;
         unsigned long retcode;
         int thumb = 0;
-        unsigned long cpsr = regs->ARM_cpsr & ~PSR_f;
+        unsigned long cpsr = regs->ARM_cpsr & ~(PSR_f | PSR_E_BIT);
+
+        cpsr |= PSR_ENDSTATE;
 
         /*
          * Maybe we need to deliver a 32-bit signal to a 26-bit task.
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index 86b66f3f203..61462790757 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -21,6 +21,12 @@
 #define ARM_CPU_KEEP(x)
 #endif
 
+#if defined(CONFIG_SMP_ON_UP) && !defined(CONFIG_DEBUG_SPINLOCK)
+#define ARM_EXIT_KEEP(x)        x
+#else
+#define ARM_EXIT_KEEP(x)
+#endif
+
 OUTPUT_ARCH(arm)
 ENTRY(stext)
 
@@ -43,6 +49,7 @@ SECTIONS
                 _sinittext = .;
                         HEAD_TEXT
                         INIT_TEXT
+                        ARM_EXIT_KEEP(EXIT_TEXT)
                 _einittext = .;
                 ARM_CPU_DISCARD(PROC_INFO)
                 __arch_info_begin = .;
@@ -67,6 +74,7 @@ SECTIONS
 #ifndef CONFIG_XIP_KERNEL
                 __init_begin = _stext;
                 INIT_DATA
+                ARM_EXIT_KEEP(EXIT_DATA)
 #endif
         }
 
@@ -162,6 +170,7 @@ SECTIONS
                 . = ALIGN(PAGE_SIZE);
                 __init_begin = .;
                 INIT_DATA
+                ARM_EXIT_KEEP(EXIT_DATA)
                 . = ALIGN(PAGE_SIZE);
                 __init_end = .;
 #endif
@@ -247,6 +256,8 @@ SECTIONS
         }
 #endif
 
+        NOTES
+
         BSS_SECTION(0, 0, 0)
         _end = .;
 
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 96e0e94e5fa..03e11f9dca9 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -90,6 +90,7 @@ MACHINE_START(CM_A510, "Compulab CM-A510 Board")
         .boot_params    = 0x00000100,
         .init_machine   = cm_a510_init,
         .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
         .init_irq       = dove_init_irq,
         .timer          = &dove_timer,
 MACHINE_END
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index fe627aba6da..e06a88f1f81 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -532,6 +532,11 @@ void __init dove_i2c_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init dove_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 static int get_tclk(void)
 {
         /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
@@ -540,7 +545,8 @@ static int get_tclk(void)
 
 static void dove_timer_init(void)
 {
-        orion_time_init(IRQ_DOVE_BRIDGE, get_tclk());
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_DOVE_BRIDGE, get_tclk());
 }
 
 struct sys_timer dove_timer = {
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index a51517c3fe7..6a2046e4470 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -22,6 +22,7 @@ extern struct mbus_dram_target_info dove_mbus_dram_info;
  */
 void dove_map_io(void);
 void dove_init(void);
+void dove_init_early(void);
 void dove_init_irq(void);
 void dove_setup_cpu_mbus(void);
 void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index 95925aa76dd..2ac34ecfa74 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -97,6 +97,7 @@ MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = dove_db_init,
         .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
         .init_irq       = dove_init_irq,
         .timer          = &dove_timer,
 MACHINE_END
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index 214a4c31f06..226949dc4ac 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -26,10 +26,6 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define  SOFT_RESET             0x00000001
 
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define  BRIDGE_INT_TIMER0      0x0002
-#define  BRIDGE_INT_TIMER1      0x0004
 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index 27b414578f2..e5fcdd3f5bf 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -130,7 +130,8 @@
 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
 #define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
 #define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
-#define DOVE_GPIO_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
 #define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
 #define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
diff --git a/arch/arm/mach-dove/include/mach/gpio.h b/arch/arm/mach-dove/include/mach/gpio.h
index 340bb7af529..e7e5101e35a 100644
--- a/arch/arm/mach-dove/include/mach/gpio.h
+++ b/arch/arm/mach-dove/include/mach/gpio.h
@@ -6,46 +6,4 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <asm/errno.h>
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-#define GPIO_MAX        72
-
-#define GPIO_BASE_LO            (DOVE_GPIO_VIRT_BASE + 0x00)
-#define GPIO_BASE_HI            (DOVE_GPIO_VIRT_BASE + 0x20)
-
-#define GPIO_BASE(pin)          ((pin < 32) ? GPIO_BASE_LO :            \
-                                 ((pin < 64) ? GPIO_BASE_HI :           \
-                                  DOVE_GPIO2_VIRT_BASE))
-
-#define GPIO_OUT(pin)           (GPIO_BASE(pin) + 0x00)
-#define GPIO_IO_CONF(pin)       (GPIO_BASE(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)      (GPIO_BASE(pin) + 0x08)
-#define GPIO_IN_POL(pin)        (GPIO_BASE(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)       (GPIO_BASE(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)    (GPIO_BASE(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)     (GPIO_BASE(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)    (GPIO_BASE(pin) + 0x1c)
-
-static inline int gpio_to_irq(int pin)
-{
-        if (pin < NR_GPIO_IRQS)
-                return pin + IRQ_DOVE_GPIO_START;
-
-        return -EINVAL;
-}
-
-static inline int irq_to_gpio(int irq)
-{
-        if (IRQ_DOVE_GPIO_START < irq && irq < NR_IRQS)
-                return irq - IRQ_DOVE_GPIO_START;
-
-        return -EINVAL;
-}
-
-#endif
diff --git a/arch/arm/mach-dove/include/mach/irqs.h b/arch/arm/mach-dove/include/mach/irqs.h
index 46681466f92..03d401d2045 100644
--- a/arch/arm/mach-dove/include/mach/irqs.h
+++ b/arch/arm/mach-dove/include/mach/irqs.h
@@ -92,10 +92,5 @@
 
 #define NR_IRQS                 (IRQ_DOVE_PMU_START + NR_PMU_IRQS)
 
-/* Required for compatability with PXA AC97 driver.     */
-#define IRQ_AC97                IRQ_DOVE_AC97
-/* Required for compatability with PXA DMA driver.      */
-#define IRQ_DMA                 IRQ_DOVE_PDMA
-/* Required for compatability with PXA NAND driver      */
-#define IRQ_NAND                IRQ_DOVE_NAND
+
 #endif
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 9317f0558b5..101707fa2e2 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -99,11 +99,21 @@ void __init dove_init_irq(void)
         orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
 
         /*
-         * Mask and clear GPIO IRQ interrupts.
+         * Initialize gpiolib for GPIOs 0-71.
          */
-        writel(0, GPIO_LEVEL_MASK(0));
-        writel(0, GPIO_EDGE_MASK(0));
-        writel(0, GPIO_EDGE_CAUSE(0));
+        orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
+        set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
+
+        orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START + 32);
+        set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
+
+        orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
+                        IRQ_DOVE_GPIO_START + 64);
 
         /*
          * Mask and clear PMU interrupts
@@ -111,18 +121,6 @@ void __init dove_init_irq(void)
         writel(0, PMU_INTERRUPT_MASK);
         writel(0, PMU_INTERRUPT_CAUSE);
 
-        for (i = IRQ_DOVE_GPIO_START; i < IRQ_DOVE_PMU_START; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
-        set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
-        set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
-
         for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
                 set_irq_chip(i, &pmu_irq_chip);
                 set_irq_handler(i, handle_level_irq);
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 3688123b5ad..20e71df3e3b 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -21,6 +21,7 @@
 #include <net/dsa.h>
 #include <asm/page.h>
 #include <asm/timex.h>
+#include <asm/kexec.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
 #include <mach/kirkwood.h>
@@ -846,9 +847,14 @@ static void __init kirkwood_wdt_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init kirkwood_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 int kirkwood_tclk;
 
-int __init kirkwood_find_tclk(void)
+static int __init kirkwood_find_tclk(void)
 {
         u32 dev, rev;
 
@@ -864,7 +870,9 @@ int __init kirkwood_find_tclk(void)
 static void __init kirkwood_timer_init(void)
 {
         kirkwood_tclk = kirkwood_find_tclk();
-        orion_time_init(IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
+
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_KIRKWOOD_BRIDGE, kirkwood_tclk);
 }
 
 struct sys_timer kirkwood_timer = {
@@ -1003,6 +1011,10 @@ void __init kirkwood_init(void)
         kirkwood_xor0_init();
         kirkwood_xor1_init();
         kirkwood_crypto_init();
+
+#ifdef CONFIG_KEXEC 
+        kexec_reinit = kirkwood_enable_pcie;
+#endif
 }
 
 static int __init kirkwood_clock_gate(void)
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 95bb0a73adf..b9b0f0968a3 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -27,11 +27,13 @@ struct kirkwood_asoc_platform_data;
  */
 void kirkwood_map_io(void);
 void kirkwood_init(void);
+void kirkwood_init_early(void);
 void kirkwood_init_irq(void);
 
 extern struct mbus_dram_target_info kirkwood_mbus_dram_info;
 void kirkwood_setup_cpu_mbus(void);
 
+void kirkwood_enable_pcie(void);
 void kirkwood_pcie_id(u32 *dev, u32 *rev);
 
 void kirkwood_ehci_init(void);
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index a31c9499ab3..043cfd5e140 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -224,6 +224,7 @@ MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
         .boot_params    = 0x00000100,
         .init_machine   = d2net_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index 9ea71182d31..bff04e04d67 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -100,6 +100,7 @@ MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = db88f6281_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index 433ea368c06..f14dfb8508c 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -105,6 +105,7 @@ MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
         .boot_params    = 0x00000100,
         .init_machine   = dockstar_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 8f47dc0a2fe..41d1b40696a 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -124,6 +124,7 @@ MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
         .boot_params    = 0x00000100,
         .init_machine   = guruplug_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index aff0e1327e3..957bd7997d7 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -29,9 +29,6 @@
 #define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
 #define WDT_INT_REQ             0x0008
 
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-kirkwood/include/mach/gpio.h b/arch/arm/mach-kirkwood/include/mach/gpio.h
index 81b335eb62e..84f340b546c 100644
--- a/arch/arm/mach-kirkwood/include/mach/gpio.h
+++ b/arch/arm/mach-kirkwood/include/mach/gpio.h
@@ -6,33 +6,4 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-#define GPIO_MAX                50
-#define GPIO_OFF(pin)           (((pin) >> 5) ? 0x0140 : 0x0100)
-#define GPIO_OUT(pin)           (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin)       (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin)      (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin)        (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin)       (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin)    (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)     (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin)    (DEV_BUS_VIRT_BASE + GPIO_OFF(pin) + 0x1c)
-
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_KIRKWOOD_GPIO_START;
-}
-
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_KIRKWOOD_GPIO_START;
-}
-
-
-#endif
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index 6e924b39891..010bdeb4ac5 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -69,6 +69,8 @@
 #define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
 #define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
 #define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
+#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE | 0x0100)
+#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE | 0x0140)
 #define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
 #define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
 #define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x1000)
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 28020abf49e..cbdb5863d13 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -27,31 +27,21 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 void __init kirkwood_init_irq(void)
 {
-        int i;
-
         orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
         orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
 
         /*
-         * Mask and clear GPIO IRQ interrupts.
+         * Initialize gpiolib for GPIOs 0-49.
          */
-        writel(0, GPIO_LEVEL_MASK(0));
-        writel(0, GPIO_EDGE_MASK(0));
-        writel(0, GPIO_EDGE_CAUSE(0));
-        writel(0, GPIO_LEVEL_MASK(32));
-        writel(0, GPIO_EDGE_MASK(32));
-        writel(0, GPIO_EDGE_CAUSE(32));
-
-        for (i = IRQ_KIRKWOOD_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
+        orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
+                        IRQ_KIRKWOOD_GPIO_START);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
+
+        orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
+                        IRQ_KIRKWOOD_GPIO_START + 32);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
         set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 27901f702fe..7ce20184806 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -49,9 +49,6 @@ void __init kirkwood_mpp_conf(unsigned int *mpp_list)
         if (!variant_mask)
                 return;
 
-        /* Initialize gpiolib. */
-        orion_gpio_init();
-
         printk(KERN_DEBUG "initial MPP regs:");
         for (i = 0; i < MPP_NR_REGS; i++) {
                 mpp_ctrl[i] = readl(MPP_CTRL(i));
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 1e5266f57e2..00cca22eca6 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -166,6 +166,7 @@ MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
         .boot_params    = 0x00000100,
         .init_machine   = mv88f6281gtw_ge_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 65ee21fd2f3..7cdab577645 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -261,6 +261,7 @@ MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
         .boot_params    = 0x00000100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -271,6 +272,7 @@ MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
         .boot_params    = 0x00000100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -281,6 +283,7 @@ MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
         .boot_params    = 0x00000100,
         .init_machine   = netspace_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 93afd3c8bfd..6be627deb0f 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -402,6 +402,7 @@ MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
         .boot_params    = 0x00000100,
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -412,6 +413,7 @@ MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
         .boot_params    = 0x00000100,
         .init_machine   = netxbig_v2_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index cfcca4174e2..f69beeff445 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -217,6 +217,7 @@ MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
         .boot_params    = 0x00000100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -228,6 +229,7 @@ MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
         .boot_params    = 0x00000100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -239,6 +241,7 @@ MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
         .boot_params    = 0x00000100,
         .init_machine   = openrd_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 513ad3102d7..ca294ff6d5b 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -18,8 +18,16 @@
 #include <mach/bridge-regs.h>
 #include "common.h"
 
+void kirkwood_enable_pcie(void)
+{
+        u32 curr = readl(CLOCK_GATING_CTRL);
+        if (!(curr & CGC_PEX0))
+                writel(curr | CGC_PEX0, CLOCK_GATING_CTRL);
+}
+
 void __init kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
+        kirkwood_enable_pcie();
         *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
         *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 0049614cd32..75c6601b8d8 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -82,6 +82,7 @@ MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f6192_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 0998a08cf42..0f75494d590 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -118,6 +118,7 @@ MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f6281_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index d2eec35dfe0..0a95063f6d3 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -134,6 +134,7 @@ MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
         .boot_params    = 0x00000100,
         .init_machine   = sheevaplug_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
@@ -144,6 +145,7 @@ MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
         .boot_params    = 0x00000100,
         .init_machine   = sheevaplug_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index ce50e61aac9..e6b9b1b22a3 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -23,6 +23,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <sound/alc5623.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -134,6 +135,7 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
         MPP33_GE1_TXCTL,
         MPP39_AU_I2SBCLK,
         MPP40_AU_I2SDO,
+        MPP43_AU_I2SDI,
         MPP41_AU_I2SLRCLK,
         MPP42_AU_I2SMCLK,
         MPP45_GPIO,             /* Power button */
@@ -141,6 +143,18 @@ static unsigned int hp_t5325_mpp_config[] __initdata = {
         0
 };
 
+static struct alc5623_platform_data alc5621_data = {
+        .add_ctrl = 0x3700,
+        .jack_det_ctrl = 0x4810,
+};
+
+static struct i2c_board_info i2c_board_info[] __initdata = {
+        {
+                I2C_BOARD_INFO("alc5621", 0x1a),
+                .platform_data = &alc5621_data,
+        },
+};
+
 #define HP_T5325_GPIO_POWER_OFF         48
 
 static void hp_t5325_power_off(void)
@@ -166,6 +180,9 @@ static void __init hp_t5325_init(void)
         kirkwood_ehci_init();
         platform_device_register(&hp_t5325_button_device);
 
+        i2c_register_board_info(0, i2c_board_info, ARRAY_SIZE(i2c_board_info));
+        kirkwood_audio_init();
+
         if (gpio_request(HP_T5325_GPIO_POWER_OFF, "power-off") == 0 &&
             gpio_direction_output(HP_T5325_GPIO_POWER_OFF, 0) == 0)
                 pm_power_off = hp_t5325_power_off;
@@ -187,6 +204,7 @@ MACHINE_START(T5325, "HP t5325 Thin Client")
         .boot_params    = 0x00000100,
         .init_machine   = hp_t5325_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index dc999c4c580..68f32f2bf55 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -135,6 +135,7 @@ MACHINE_START(TS219, "QNAP TS-119/TS-219")
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts219_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 9a44029915e..d5d00997070 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -154,6 +154,8 @@ static void __init qnap_ts41x_init(void)
 static int __init ts41x_pci_init(void)
 {
         if (machine_is_ts41x()) {
+                u32 dev, rev;
+
                 /*
                  * Without this explicit reset, the PCIe SATA controller
                  * (Marvell 88sx7042/sata_mv) is known to stop working
@@ -161,7 +163,11 @@ static int __init ts41x_pci_init(void)
                  */
                 orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
 
-                kirkwood_pcie_init(KW_PCIE0);
+                kirkwood_pcie_id(&dev, &rev);
+                if (dev == MV88F6282_DEV_ID)
+                        kirkwood_pcie_init(KW_PCIE1 | KW_PCIE0);
+                else
+                        kirkwood_pcie_init(KW_PCIE0);
         }
 
    return 0;
@@ -173,6 +179,7 @@ MACHINE_START(TS41X, "QNAP TS-41x")
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts41x_init,
         .map_io         = kirkwood_map_io,
+        .init_early     = kirkwood_init_early,
         .init_irq       = kirkwood_init_irq,
         .timer          = &kirkwood_timer,
 MACHINE_END
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index 818f19d7ab1..e41e909cf8f 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -18,6 +18,7 @@
 #include <asm/timex.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <mach/bridge-regs.h>
 #include <mach/loki.h>
 #include <plat/orion_nand.h>
 #include <plat/time.h>
@@ -290,9 +291,15 @@ void __init loki_uart1_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init loki_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 static void loki_timer_init(void)
 {
-        orion_time_init(IRQ_LOKI_BRIDGE, LOKI_TCLK);
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_LOKI_BRIDGE, LOKI_TCLK);
 }
 
 struct sys_timer loki_timer = {
diff --git a/arch/arm/mach-loki/common.h b/arch/arm/mach-loki/common.h
index 26054fd0f05..a315dcf8887 100644
--- a/arch/arm/mach-loki/common.h
+++ b/arch/arm/mach-loki/common.h
@@ -18,6 +18,7 @@ struct mv643xx_eth_platform_data;
  */
 void loki_map_io(void);
 void loki_init(void);
+void loki_init_early(void);
 void loki_init_irq(void);
 
 extern struct mbus_dram_target_info loki_mbus_dram_info;
diff --git a/arch/arm/mach-loki/include/mach/bridge-regs.h b/arch/arm/mach-loki/include/mach/bridge-regs.h
index a3fabf70044..fd87732097c 100644
--- a/arch/arm/mach-loki/include/mach/bridge-regs.h
+++ b/arch/arm/mach-loki/include/mach/bridge-regs.h
@@ -17,11 +17,6 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define SOFT_RESET              0x00000001
 
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
-
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   0x0004
 
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-loki/lb88rc8480-setup.c b/arch/arm/mach-loki/lb88rc8480-setup.c
index a1e75e7fc50..35eae4e6abb 100644
--- a/arch/arm/mach-loki/lb88rc8480-setup.c
+++ b/arch/arm/mach-loki/lb88rc8480-setup.c
@@ -93,6 +93,7 @@ MACHINE_START(LB88RC8480, "Marvell LB88RC8480 Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = lb88rc8480_init,
         .map_io         = loki_map_io,
+        .init_early     = loki_init_early,
         .init_irq       = loki_init_irq,
         .timer          = &loki_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 29e390e89ff..20f3f125ed2 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -148,6 +148,7 @@ MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
         .boot_params    = 0x00000100,
         .init_machine   = wxl_init,
         .map_io         = mv78xx0_map_io,
+        .init_early     = mv78xx0_init_early,
         .init_irq       = mv78xx0_init_irq,
         .timer          = &mv78xx0_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 08465eb6a2c..44fb4e55be0 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -818,9 +818,15 @@ void __init mv78xx0_uart3_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init mv78xx0_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 static void mv78xx0_timer_init(void)
 {
-        orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
+        orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_MV78XX0_TIMER_1, get_tclk());
 }
 
 struct sys_timer mv78xx0_timer = {
diff --git a/arch/arm/mach-mv78xx0/common.h b/arch/arm/mach-mv78xx0/common.h
index befc2247546..632e63d65e7 100644
--- a/arch/arm/mach-mv78xx0/common.h
+++ b/arch/arm/mach-mv78xx0/common.h
@@ -20,6 +20,7 @@ struct mv_sata_platform_data;
 int mv78xx0_core_index(void);
 void mv78xx0_map_io(void);
 void mv78xx0_init(void);
+void mv78xx0_init_early(void);
 void mv78xx0_init_irq(void);
 
 extern struct mbus_dram_target_info mv78xx0_mbus_dram_info;
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index 207c95e403b..df5aebe5b0f 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -96,6 +96,7 @@ MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = db78x00_init,
         .map_io         = mv78xx0_map_io,
+        .init_early     = mv78xx0_init_early,
         .init_irq       = mv78xx0_init_irq,
         .timer          = &mv78xx0_timer,
 MACHINE_END
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index 2d14c4fe294..c64dbb96dba 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -20,10 +20,6 @@
 #define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
 #define SOFT_RESET              0x00000001
 
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
-#define BRIDGE_MASK             (BRIDGE_VIRT_BASE | 0x0114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
 #define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
diff --git a/arch/arm/mach-mv78xx0/include/mach/gpio.h b/arch/arm/mach-mv78xx0/include/mach/gpio.h
index d9d1535ea10..77e1b843e76 100644
--- a/arch/arm/mach-mv78xx0/include/mach/gpio.h
+++ b/arch/arm/mach-mv78xx0/include/mach/gpio.h
@@ -6,35 +6,4 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-extern int mv78xx0_core_index(void);
-
-#define GPIO_MAX                32
-#define GPIO_OUT(pin)           (DEV_BUS_VIRT_BASE + 0x0100)
-#define GPIO_IO_CONF(pin)       (DEV_BUS_VIRT_BASE + 0x0104)
-#define GPIO_BLINK_EN(pin)      (DEV_BUS_VIRT_BASE + 0x0108)
-#define GPIO_IN_POL(pin)        (DEV_BUS_VIRT_BASE + 0x010c)
-#define GPIO_DATA_IN(pin)       (DEV_BUS_VIRT_BASE + 0x0110)
-#define GPIO_EDGE_CAUSE(pin)    (DEV_BUS_VIRT_BASE + 0x0114)
-#define GPIO_MASK_OFF           (mv78xx0_core_index() ? 0x18 : 0)
-#define GPIO_EDGE_MASK(pin)     (DEV_BUS_VIRT_BASE + 0x0118 + GPIO_MASK_OFF)
-#define GPIO_LEVEL_MASK(pin)    (DEV_BUS_VIRT_BASE + 0x011c + GPIO_MASK_OFF)
-
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_MV78XX0_GPIO_START;
-}
-
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_MV78XX0_GPIO_START;
-}
-
-
-#endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index 3eff39921d4..3674497162e 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -71,6 +71,7 @@
 #define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
 #define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
 #define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
+#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE | 0x0100)
 #define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1000)
 #define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1100)
 #define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 22b4ff893b3..08da497c39c 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -26,28 +26,18 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 void __init mv78xx0_init_irq(void)
 {
-        int i;
-
-        /* Initialize gpiolib. */
-        orion_gpio_init();
-
         orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
         orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
         orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
 
         /*
-         * Mask and clear GPIO IRQ interrupts.
+         * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
+         * registers for core #1 are at an offset of 0x18 from those of
+         * core #0.)
          */
-        writel(0, GPIO_LEVEL_MASK(0));
-        writel(0, GPIO_EDGE_MASK(0));
-        writel(0, GPIO_EDGE_CAUSE(0));
-
-        for (i = IRQ_MV78XX0_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
+        orion_gpio_init(0, 32, GPIO_VIRT_BASE,
+                        mv78xx0_core_index() ? 0x18 : 0,
+                        IRQ_MV78XX0_GPIO_START);
         set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
         set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
         set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 84db2dfc475..65b72c454cb 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -44,9 +44,6 @@ void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
         if (!variant_mask)
                 return;
 
-        /* Initialize gpiolib. */
-        orion_gpio_init();
-
         printk(KERN_DEBUG "initial MPP regs:");
         for (i = 0; i < MPP_NR_REGS; i++) {
                 mpp_ctrl[i] = readl(MPP_CTRL(i));
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index 3511ad4d973..d927f14c681 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -81,6 +81,7 @@ MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = rd78x00_masa_init,
         .map_io         = mv78xx0_map_io,
+        .init_early     = mv78xx0_init_early,
         .init_irq       = mv78xx0_init_irq,
         .timer          = &mv78xx0_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 8dc2c76d226..986c3bf4e6b 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -26,6 +26,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
+#include <mach/bridge-regs.h>
 #include <mach/hardware.h>
 #include <mach/orion5x.h>
 #include <plat/ehci-orion.h>
@@ -599,6 +600,11 @@ void __init orion5x_wdt_init(void)
 /*****************************************************************************
  * Time handling
  ****************************************************************************/
+void __init orion5x_init_early(void)
+{
+        orion_time_set_base(TIMER_VIRT_BASE);
+}
+
 int orion5x_tclk;
 
 int __init orion5x_find_tclk(void)
@@ -616,7 +622,9 @@ int __init orion5x_find_tclk(void)
 static void orion5x_timer_init(void)
 {
         orion5x_tclk = orion5x_find_tclk();
-        orion_time_init(IRQ_ORION5X_BRIDGE, orion5x_tclk);
+
+        orion_time_init(ORION5X_BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
+                        IRQ_ORION5X_BRIDGE, orion5x_tclk);
 }
 
 struct sys_timer orion5x_timer = {
diff --git a/arch/arm/mach-orion5x/common.h b/arch/arm/mach-orion5x/common.h
index 8f004503c96..f2b2b35e864 100644
--- a/arch/arm/mach-orion5x/common.h
+++ b/arch/arm/mach-orion5x/common.h
@@ -9,6 +9,7 @@ struct mv_sata_platform_data;
  * Basic Orion init functions used early by machine-setup.
  */
 void orion5x_map_io(void);
+void orion5x_init_early(void);
 void orion5x_init_irq(void);
 void orion5x_init(void);
 extern int orion5x_tclk;
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index b1c451f5ee2..42580757930 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -339,6 +339,7 @@ MACHINE_START(D2NET, "LaCie d2 Network")
         .boot_params    = 0x00000100,
         .init_machine   = d2net_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
@@ -350,6 +351,7 @@ MACHINE_START(BIGDISK, "LaCie Big Disk Network")
         .boot_params    = 0x00000100,
         .init_machine   = d2net_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index df1083f5b6e..c10a1171537 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -361,6 +361,7 @@ MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
         .boot_params    = 0x00000100,
         .init_machine   = db88f5281_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 3a7bc0e3698..90ab022eabe 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -733,6 +733,7 @@ MACHINE_START(DNS323, "D-Link DNS-323")
         .boot_params    = 0x00000100,
         .init_machine   = dns323_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index ba98459f44b..d037a90c216 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -254,6 +254,7 @@ MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
         .boot_params    = 0x00000100,
         .init_machine   = edmini_v2_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 5c9744cd8ef..96484bcd34c 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -22,14 +22,12 @@
 
 #define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
 
+#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+
 #define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
 
-#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
 #define WDT_INT_REQ             0x0008
 
-#define BRIDGE_MASK             (ORION5X_BRIDGE_VIRT_BASE | 0x114)
-#define BRIDGE_INT_TIMER0       0x0002
-#define BRIDGE_INT_TIMER1       0x0004
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
 #define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE | 0x200)
diff --git a/arch/arm/mach-orion5x/include/mach/gpio.h b/arch/arm/mach-orion5x/include/mach/gpio.h
index d8182e87ac1..a1d0b78decb 100644
--- a/arch/arm/mach-orion5x/include/mach/gpio.h
+++ b/arch/arm/mach-orion5x/include/mach/gpio.h
@@ -6,32 +6,4 @@
  * warranty of any kind, whether express or implied.
  */
 
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <mach/irqs.h>
 #include <plat/gpio.h>
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-#define GPIO_MAX                32
-#define GPIO_OUT(pin)           ORION5X_DEV_BUS_REG(0x100)
-#define GPIO_IO_CONF(pin)       ORION5X_DEV_BUS_REG(0x104)
-#define GPIO_BLINK_EN(pin)      ORION5X_DEV_BUS_REG(0x108)
-#define GPIO_IN_POL(pin)        ORION5X_DEV_BUS_REG(0x10c)
-#define GPIO_DATA_IN(pin)       ORION5X_DEV_BUS_REG(0x110)
-#define GPIO_EDGE_CAUSE(pin)    ORION5X_DEV_BUS_REG(0x114)
-#define GPIO_EDGE_MASK(pin)     ORION5X_DEV_BUS_REG(0x118)
-#define GPIO_LEVEL_MASK(pin)    ORION5X_DEV_BUS_REG(0x11c)
-
-static inline int gpio_to_irq(int pin)
-{
-        return pin + IRQ_ORION5X_GPIO_START;
-}
-
-static inline int irq_to_gpio(int irq)
-{
-        return irq - IRQ_ORION5X_GPIO_START;
-}
-
-
-#endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 2d876657053..0a28bbc7689 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -73,6 +73,7 @@
 #define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
 #define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
 #define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define  GPIO_VIRT_BASE                 ORION5X_DEV_BUS_REG(0x0100)
 #define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
 #define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
 #define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index d7512b925a8..ed85891f869 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -28,27 +28,12 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
 void __init orion5x_init_irq(void)
 {
-        int i;
-
         orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
 
         /*
-         * Mask and clear GPIO IRQ interrupts
-         */
-        writel(0x0, GPIO_LEVEL_MASK(0));
-        writel(0x0, GPIO_EDGE_MASK(0));
-        writel(0x0, GPIO_EDGE_CAUSE(0));
-
-        /*
-         * Register chained level handlers for GPIO IRQs by default.
-         * User can use set_type() if he wants to use edge types handlers.
+         * Initialize gpiolib for GPIOs 0-31.
          */
-        for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
-                set_irq_chip(i, &orion_gpio_irq_chip);
-                set_irq_handler(i, handle_level_irq);
-                irq_desc[i].status |= IRQ_LEVEL;
-                set_irq_flags(i, IRQF_VALID);
-        }
+        orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
         set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
         set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
         set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 4be9aa08de6..47497c76162 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -382,6 +382,7 @@ MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
         .boot_params    = 0x00000100,
         .init_machine   = kurobox_pro_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
@@ -394,6 +395,7 @@ MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
         .boot_params    = 0x00000100,
         .init_machine   = kurobox_pro_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 20a9b66cbaf..6ae12aa6d75 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -321,6 +321,7 @@ MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
         .boot_params    = 0x00000100,
         .init_machine   = lschl_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 437364b7168..7adafd79cf9 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -268,6 +268,7 @@ MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
         .boot_params    = 0x00000100,
         .init_machine   = ls_hgl_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index ab9b0cf0a90..869958f5c39 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -270,6 +270,7 @@ MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
         .boot_params    = 0x00000100,
         .init_machine   = lsmini_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index db485d3b814..2288207726e 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -124,9 +124,6 @@ void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
         u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
         u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
 
-        /* Initialize gpiolib. */
-        orion_gpio_init();
-
         for ( ; mode->mpp >= 0; mode++) {
                 u32 *reg;
                 int num_type;
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index 2f0e16cd7e8..b43b208153c 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -264,6 +264,7 @@ MACHINE_START(MSS2, "Maxtor Shared Storage II")
         .boot_params    = 0x00000100,
         .init_machine   = mss2_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index b3d90f25de9..c55d071707f 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -232,6 +232,7 @@ MACHINE_START(MV2120, "HP Media Vault mv2120")
         .boot_params    = 0x00000100,
         .init_machine   = mv2120_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index d6665b31665..429ecafe9fd 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -422,6 +422,7 @@ MACHINE_START(NET2BIG, "LaCie 2Big Network")
         .boot_params    = 0x00000100,
         .init_machine   = net2big_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index f4c26fd731f..34310ab56e2 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -172,6 +172,7 @@ MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5181l_fxo_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index b5942909bab..c1f79fa014e 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -184,6 +184,7 @@ MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5181l_ge_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 165ed87029b..67ec6959b26 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -308,6 +308,7 @@ MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f5182_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 02ff45f3e2e..b080c6966d1 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -126,6 +126,7 @@ MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
         .boot_params    = 0x00000100,
         .init_machine   = rd88f6183ap_ge_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 4403fae5ab0..5653ee6c71d 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -361,6 +361,7 @@ MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
         .boot_params    = 0x00000100,
         .init_machine   = tsp2_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 1e196129d76..8bbd27ea673 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -325,6 +325,7 @@ MACHINE_START(TS209, "QNAP TS-109/TS-209")
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts209_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 428af2046e3..92f393f08fa 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -314,6 +314,7 @@ MACHINE_START(TS409, "QNAP TS-409")
         .boot_params    = 0x00000100,
         .init_machine   = qnap_ts409_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/ts78xx-fpga.h b/arch/arm/mach-orion5x/ts78xx-fpga.h
index 37b3d487529..151e89e1e67 100644
--- a/arch/arm/mach-orion5x/ts78xx-fpga.h
+++ b/arch/arm/mach-orion5x/ts78xx-fpga.h
@@ -1,3 +1,4 @@
+#define TS7800_FPGA_MAGIC 0x00b480
 #define FPGAID(_magic, _rev) ((_magic << 8) + _rev)
 
 /*
@@ -6,11 +7,15 @@
  */
 enum fpga_ids {
         /* Technologic Systems */
-        TS7800_REV_1    = FPGAID(0x00b480, 0x01),
-        TS7800_REV_2    = FPGAID(0x00b480, 0x02),
-        TS7800_REV_3    = FPGAID(0x00b480, 0x03),
-        TS7800_REV_4    = FPGAID(0x00b480, 0x04),
-        TS7800_REV_5    = FPGAID(0x00b480, 0x05),
+        TS7800_REV_1    = FPGAID(TS7800_FPGA_MAGIC, 0x01),
+        TS7800_REV_2    = FPGAID(TS7800_FPGA_MAGIC, 0x02),
+        TS7800_REV_3    = FPGAID(TS7800_FPGA_MAGIC, 0x03),
+        TS7800_REV_4    = FPGAID(TS7800_FPGA_MAGIC, 0x04),
+        TS7800_REV_5    = FPGAID(TS7800_FPGA_MAGIC, 0x05),
+        TS7800_REV_6    = FPGAID(TS7800_FPGA_MAGIC, 0x06),
+        TS7800_REV_7    = FPGAID(TS7800_FPGA_MAGIC, 0x07),
+        TS7800_REV_8    = FPGAID(TS7800_FPGA_MAGIC, 0x08),
+        TS7800_REV_9    = FPGAID(TS7800_FPGA_MAGIC, 0x09),
 
         /* Unaffordable & Expensive */
         UAE_DUMMY       = FPGAID(0xffffff, 0x01),
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index c1c1cd04bdd..8554707d20a 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -191,6 +191,60 @@ static int ts78xx_ts_nand_dev_ready(struct mtd_info *mtd)
         return readb(TS_NAND_CTRL) & 0x20;
 }
 
+static void ts78xx_ts_nand_write_buf(struct mtd_info *mtd,
+                        const uint8_t *buf, int len)
+{
+        struct nand_chip *chip = mtd->priv;
+        void __iomem *io_base = chip->IO_ADDR_W;
+        unsigned long off = ((unsigned long)buf & 3);
+        int sz;
+
+        if (off) {
+                sz = min_t(int, 4 - off, len);
+                writesb(io_base, buf, sz);
+                buf += sz;
+                len -= sz;
+        }
+
+        sz = len >> 2;
+        if (sz) {
+                u32 *buf32 = (u32 *)buf;
+                writesl(io_base, buf32, sz);
+                buf += sz << 2;
+                len -= sz << 2;
+        }
+
+        if (len)
+                writesb(io_base, buf, len);
+}
+
+static void ts78xx_ts_nand_read_buf(struct mtd_info *mtd,
+                        uint8_t *buf, int len)
+{
+        struct nand_chip *chip = mtd->priv;
+        void __iomem *io_base = chip->IO_ADDR_R;
+        unsigned long off = ((unsigned long)buf & 3);
+        int sz;
+
+        if (off) {
+                sz = min_t(int, 4 - off, len);
+                readsb(io_base, buf, sz);
+                buf += sz;
+                len -= sz;
+        }
+
+        sz = len >> 2;
+        if (sz) {
+                u32 *buf32 = (u32 *)buf;
+                readsl(io_base, buf32, sz);
+                buf += sz << 2;
+                len -= sz << 2;
+        }
+
+        if (len)
+                readsb(io_base, buf, len);
+}
+
 const char *ts_nand_part_probes[] = { "cmdlinepart", NULL };
 
 static struct mtd_partition ts78xx_ts_nand_parts[] = {
@@ -233,6 +287,8 @@ static struct platform_nand_data ts78xx_ts_nand_data = {
                  */
                 .cmd_ctrl               = ts78xx_ts_nand_cmd_ctrl,
                 .dev_ready              = ts78xx_ts_nand_dev_ready,
+                .write_buf              = ts78xx_ts_nand_write_buf,
+                .read_buf               = ts78xx_ts_nand_read_buf,
         },
 };
 
@@ -334,14 +390,29 @@ static void ts78xx_fpga_supports(void)
         case TS7800_REV_3:
         case TS7800_REV_4:
         case TS7800_REV_5:
+        case TS7800_REV_6:
+        case TS7800_REV_7:
+        case TS7800_REV_8:
+        case TS7800_REV_9:
                 ts78xx_fpga.supports.ts_rtc.present = 1;
                 ts78xx_fpga.supports.ts_nand.present = 1;
                 ts78xx_fpga.supports.ts_rng.present = 1;
                 break;
         default:
-                ts78xx_fpga.supports.ts_rtc.present = 0;
-                ts78xx_fpga.supports.ts_nand.present = 0;
-                ts78xx_fpga.supports.ts_rng.present = 0;
+                /* enable devices if magic matches */
+                switch ((ts78xx_fpga.id >> 8) & 0xffffff) {
+                case TS7800_FPGA_MAGIC:
+                        printk(KERN_WARNING "TS-7800 FPGA: unrecognized revision 0x%.2x\n",
+                                        ts78xx_fpga.id & 0xff);
+                        ts78xx_fpga.supports.ts_rtc.present = 1;
+                        ts78xx_fpga.supports.ts_nand.present = 1;
+                        ts78xx_fpga.supports.ts_rng.present = 1;
+                        break;
+                default:
+                        ts78xx_fpga.supports.ts_rtc.present = 0;
+                        ts78xx_fpga.supports.ts_nand.present = 0;
+                        ts78xx_fpga.supports.ts_rng.present = 0;
+                }
         }
 }
 
@@ -553,6 +624,7 @@ MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
         .boot_params    = 0x00000100,
         .init_machine   = ts78xx_init,
         .map_io         = ts78xx_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
 MACHINE_END
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 7994d6ec08a..4e5216be074 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -175,6 +175,7 @@ MACHINE_START(WNR854T, "Netgear WNR854T")
         .boot_params    = 0x00000100,
         .init_machine   = wnr854t_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index a5989b7eb53..fab79d09cc5 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -263,6 +263,7 @@ MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
         .boot_params    = 0x00000100,
         .init_machine   = wrt350n_v2_init,
         .map_io         = orion5x_map_io,
+        .init_early     = orion5x_init_early,
         .init_irq       = orion5x_init_irq,
         .timer          = &orion5x_timer,
         .fixup          = tag_fixup_mem32,
diff --git a/arch/arm/mach-s5p6442/include/mach/map.h b/arch/arm/mach-s5p6442/include/mach/map.h
index 203dd5a18bd..058dab4482a 100644
--- a/arch/arm/mach-s5p6442/include/mach/map.h
+++ b/arch/arm/mach-s5p6442/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5p6442/include/mach/map.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
  * S5P6442 - Memory map definitions
@@ -16,56 +16,61 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-#define S5P6442_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5P6442_PA_CHIPID
+#define S5P6442_PA_SDRAM        0x20000000
 
-#define S5P6442_PA_SYSCON       (0xE0100000)
-#define S5P_PA_SYSCON           S5P6442_PA_SYSCON
+#define S5P6442_PA_I2S0         0xC0B00000
+#define S5P6442_PA_I2S1         0xF2200000
 
-#define S5P6442_PA_GPIO         (0xE0200000)
+#define S5P6442_PA_CHIPID       0xE0000000
 
-#define S5P6442_PA_VIC0         (0xE4000000)
-#define S5P6442_PA_VIC1         (0xE4100000)
-#define S5P6442_PA_VIC2         (0xE4200000)
+#define S5P6442_PA_SYSCON       0xE0100000
 
-#define S5P6442_PA_SROMC        (0xE7000000)
-#define S5P_PA_SROMC            S5P6442_PA_SROMC
+#define S5P6442_PA_GPIO         0xE0200000
 
-#define S5P6442_PA_MDMA         0xE8000000
-#define S5P6442_PA_PDMA         0xE9000000
+#define S5P6442_PA_VIC0         0xE4000000
+#define S5P6442_PA_VIC1         0xE4100000
+#define S5P6442_PA_VIC2         0xE4200000
 
-#define S5P6442_PA_TIMER        (0xEA000000)
-#define S5P_PA_TIMER            S5P6442_PA_TIMER
+#define S5P6442_PA_SROMC        0xE7000000
 
-#define S5P6442_PA_SYSTIMER     (0xEA100000)
+#define S5P6442_PA_MDMA         0xE8000000
+#define S5P6442_PA_PDMA         0xE9000000
 
-#define S5P6442_PA_WATCHDOG     (0xEA200000)
+#define S5P6442_PA_TIMER        0xEA000000
 
-#define S5P6442_PA_UART         (0xEC000000)
+#define S5P6442_PA_SYSTIMER     0xEA100000
 
-#define S5P_PA_UART0            (S5P6442_PA_UART + 0x0)
-#define S5P_PA_UART1            (S5P6442_PA_UART + 0x400)
-#define S5P_PA_UART2            (S5P6442_PA_UART + 0x800)
-#define S5P_SZ_UART             SZ_256
+#define S5P6442_PA_WATCHDOG     0xEA200000
 
-#define S5P6442_PA_IIC0         (0xEC100000)
+#define S5P6442_PA_UART         0xEC000000
 
-#define S5P6442_PA_SDRAM        (0x20000000)
-#define S5P_PA_SDRAM            S5P6442_PA_SDRAM
+#define S5P6442_PA_IIC0         0xEC100000
 
 #define S5P6442_PA_SPI          0xEC300000
 
-/* I2S */
-#define S5P6442_PA_I2S0         0xC0B00000
-#define S5P6442_PA_I2S1         0xF2200000
-
-/* PCM */
 #define S5P6442_PA_PCM0         0xF2400000
 #define S5P6442_PA_PCM1         0xF2500000
 
-/* compatibiltiy defines. */
+/* Compatibiltiy Defines */
+
+#define S3C_PA_IIC              S5P6442_PA_IIC0
 #define S3C_PA_WDT              S5P6442_PA_WATCHDOG
+
+#define S5P_PA_CHIPID           S5P6442_PA_CHIPID
+#define S5P_PA_SDRAM            S5P6442_PA_SDRAM
+#define S5P_PA_SROMC            S5P6442_PA_SROMC
+#define S5P_PA_SYSCON           S5P6442_PA_SYSCON
+#define S5P_PA_TIMER            S5P6442_PA_TIMER
+
+/* UART */
+
 #define S3C_PA_UART             S5P6442_PA_UART
-#define S3C_PA_IIC              S5P6442_PA_IIC0
+
+#define S5P_PA_UART(x)          (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0            S5P_PA_UART(0)
+#define S5P_PA_UART1            S5P_PA_UART(1)
+#define S5P_PA_UART2            S5P_PA_UART(2)
+
+#define S5P_SZ_UART             SZ_256
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
index a9365e5ba61..95c91257c7c 100644
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ b/arch/arm/mach-s5p64x0/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5p64x0/include/mach/map.h
  *
- * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com
  *
  * S5P64X0 - Memory map definitions
@@ -16,64 +16,46 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-#define S5P64X0_PA_SDRAM        (0x20000000)
+#define S5P64X0_PA_SDRAM        0x20000000
 
-#define S5P64X0_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
-
-#define S5P64X0_PA_SYSCON       (0xE0100000)
-#define S5P_PA_SYSCON           S5P64X0_PA_SYSCON
-
-#define S5P64X0_PA_GPIO         (0xE0308000)
-
-#define S5P64X0_PA_VIC0         (0xE4000000)
-#define S5P64X0_PA_VIC1         (0xE4100000)
+#define S5P64X0_PA_CHIPID       0xE0000000
 
-#define S5P64X0_PA_SROMC        (0xE7000000)
-#define S5P_PA_SROMC            S5P64X0_PA_SROMC
-
-#define S5P64X0_PA_PDMA         (0xE9000000)
-
-#define S5P64X0_PA_TIMER        (0xEA000000)
-#define S5P_PA_TIMER            S5P64X0_PA_TIMER
+#define S5P64X0_PA_SYSCON       0xE0100000
 
-#define S5P64X0_PA_RTC          (0xEA100000)
+#define S5P64X0_PA_GPIO         0xE0308000
 
-#define S5P64X0_PA_WDT          (0xEA200000)
+#define S5P64X0_PA_VIC0         0xE4000000
+#define S5P64X0_PA_VIC1         0xE4100000
 
-#define S5P6440_PA_UART(x)      (0xEC000000 + ((x) * S3C_UART_OFFSET))
-#define S5P6450_PA_UART(x)      ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
+#define S5P64X0_PA_SROMC        0xE7000000
 
-#define S5P_PA_UART0            S5P6450_PA_UART(0)
-#define S5P_PA_UART1            S5P6450_PA_UART(1)
-#define S5P_PA_UART2            S5P6450_PA_UART(2)
-#define S5P_PA_UART3            S5P6450_PA_UART(3)
-#define S5P_PA_UART4            S5P6450_PA_UART(4)
-#define S5P_PA_UART5            S5P6450_PA_UART(5)
+#define S5P64X0_PA_PDMA         0xE9000000
 
-#define S5P_SZ_UART             SZ_256
+#define S5P64X0_PA_TIMER        0xEA000000
+#define S5P64X0_PA_RTC          0xEA100000
+#define S5P64X0_PA_WDT          0xEA200000
 
-#define S5P6440_PA_IIC0         (0xEC104000)
-#define S5P6440_PA_IIC1         (0xEC20F000)
-#define S5P6450_PA_IIC0         (0xEC100000)
-#define S5P6450_PA_IIC1         (0xEC200000)
+#define S5P6440_PA_IIC0         0xEC104000
+#define S5P6440_PA_IIC1         0xEC20F000
+#define S5P6450_PA_IIC0         0xEC100000
+#define S5P6450_PA_IIC1         0xEC200000
 
-#define S5P64X0_PA_SPI0         (0xEC400000)
-#define S5P64X0_PA_SPI1         (0xEC500000)
+#define S5P64X0_PA_SPI0         0xEC400000
+#define S5P64X0_PA_SPI1         0xEC500000
 
-#define S5P64X0_PA_HSOTG        (0xED100000)
+#define S5P64X0_PA_HSOTG        0xED100000
 
 #define S5P64X0_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
 
-#define S5P64X0_PA_I2S          (0xF2000000)
+#define S5P64X0_PA_I2S          0xF2000000
 #define S5P6450_PA_I2S1         0xF2800000
 #define S5P6450_PA_I2S2         0xF2900000
 
-#define S5P64X0_PA_PCM          (0xF2100000)
+#define S5P64X0_PA_PCM          0xF2100000
 
-#define S5P64X0_PA_ADC          (0xF3000000)
+#define S5P64X0_PA_ADC          0xF3000000
 
-/* compatibiltiy defines. */
+/* Compatibiltiy Defines */
 
 #define S3C_PA_HSMMC0           S5P64X0_PA_HSMMC(0)
 #define S3C_PA_HSMMC1           S5P64X0_PA_HSMMC(1)
@@ -83,6 +65,25 @@
 #define S3C_PA_RTC              S5P64X0_PA_RTC
 #define S3C_PA_WDT              S5P64X0_PA_WDT
 
+#define S5P_PA_CHIPID           S5P64X0_PA_CHIPID
+#define S5P_PA_SROMC            S5P64X0_PA_SROMC
+#define S5P_PA_SYSCON           S5P64X0_PA_SYSCON
+#define S5P_PA_TIMER            S5P64X0_PA_TIMER
+
 #define SAMSUNG_PA_ADC          S5P64X0_PA_ADC
 
+/* UART */
+
+#define S5P6440_PA_UART(x)      (0xEC000000 + ((x) * S3C_UART_OFFSET))
+#define S5P6450_PA_UART(x)      ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
+
+#define S5P_PA_UART0            S5P6450_PA_UART(0)
+#define S5P_PA_UART1            S5P6450_PA_UART(1)
+#define S5P_PA_UART2            S5P6450_PA_UART(2)
+#define S5P_PA_UART3            S5P6450_PA_UART(3)
+#define S5P_PA_UART4            S5P6450_PA_UART(4)
+#define S5P_PA_UART5            S5P6450_PA_UART(5)
+
+#define S5P_SZ_UART             SZ_256
+
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
index 328467b346a..ccbe6b767f7 100644
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ b/arch/arm/mach-s5pc100/include/mach/map.h
@@ -1,5 +1,8 @@
 /* linux/arch/arm/mach-s5pc100/include/mach/map.h
  *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ *              http://www.samsung.com/
+ *
  * Copyright 2009 Samsung Electronics Co.
  *      Byungho Min <bhmin@samsung.com>
  *
@@ -16,145 +19,115 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-/*
- * map-base.h has already defined virtual memory address
- * S3C_VA_IRQ           S3C_ADDR(0x00000000)    irq controller(s)
- * S3C_VA_SYS           S3C_ADDR(0x00100000)    system control
- * S3C_VA_MEM           S3C_ADDR(0x00200000)    system control (not used)
- * S3C_VA_TIMER         S3C_ADDR(0x00300000)    timer block
- * S3C_VA_WATCHDOG      S3C_ADDR(0x00400000)    watchdog
- * S3C_VA_UART          S3C_ADDR(0x01000000)    UART
- *
- * S5PC100 specific virtual memory address can be defined here
- * S5PC1XX_VA_GPIO      S3C_ADDR(0x00500000)    GPIO
- *
- */
+#define S5PC100_PA_SDRAM                0x20000000
+
+#define S5PC100_PA_ONENAND              0xE7100000
+#define S5PC100_PA_ONENAND_BUF          0xB0000000
+
+#define S5PC100_PA_CHIPID               0xE0000000
 
-#define S5PC100_PA_ONENAND_BUF  (0xB0000000)
-#define S5PC100_SZ_ONENAND_BUF  (SZ_256M - SZ_32M)
+#define S5PC100_PA_SYSCON               0xE0100000
 
-/* Chip ID */
+#define S5PC100_PA_OTHERS               0xE0200000
 
-#define S5PC100_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5PC100_PA_CHIPID
+#define S5PC100_PA_GPIO                 0xE0300000
 
-#define S5PC100_PA_SYSCON       (0xE0100000)
-#define S5P_PA_SYSCON           S5PC100_PA_SYSCON
+#define S5PC100_PA_VIC0                 0xE4000000
+#define S5PC100_PA_VIC1                 0xE4100000
+#define S5PC100_PA_VIC2                 0xE4200000
 
-#define S5PC100_PA_OTHERS       (0xE0200000)
-#define S5PC100_VA_OTHERS       (S3C_VA_SYS + 0x10000)
+#define S5PC100_PA_SROMC                0xE7000000
 
-#define S5PC100_PA_GPIO         (0xE0300000)
-#define S5PC1XX_VA_GPIO         S3C_ADDR(0x00500000)
+#define S5PC100_PA_CFCON                0xE7800000
 
-/* Interrupt */
-#define S5PC100_PA_VIC0         (0xE4000000)
-#define S5PC100_PA_VIC1         (0xE4100000)
-#define S5PC100_PA_VIC2         (0xE4200000)
-#define S5PC100_VA_VIC          S3C_VA_IRQ
-#define S5PC100_VA_VIC_OFFSET   0x10000
-#define S5PC1XX_VA_VIC(x)       (S5PC100_VA_VIC + ((x) * S5PC100_VA_VIC_OFFSET))
+#define S5PC100_PA_MDMA                 0xE8100000
+#define S5PC100_PA_PDMA0                0xE9000000
+#define S5PC100_PA_PDMA1                0xE9200000
 
-#define S5PC100_PA_SROMC        (0xE7000000)
-#define S5P_PA_SROMC            S5PC100_PA_SROMC
+#define S5PC100_PA_TIMER                0xEA000000
+#define S5PC100_PA_SYSTIMER             0xEA100000
+#define S5PC100_PA_WATCHDOG             0xEA200000
+#define S5PC100_PA_RTC                  0xEA300000
 
-#define S5PC100_PA_ONENAND      (0xE7100000)
+#define S5PC100_PA_UART                 0xEC000000
 
-#define S5PC100_PA_CFCON        (0xE7800000)
+#define S5PC100_PA_IIC0                 0xEC100000
+#define S5PC100_PA_IIC1                 0xEC200000
 
-/* DMA */
-#define S5PC100_PA_MDMA         (0xE8100000)
-#define S5PC100_PA_PDMA0        (0xE9000000)
-#define S5PC100_PA_PDMA1        (0xE9200000)
+#define S5PC100_PA_SPI0                 0xEC300000
+#define S5PC100_PA_SPI1                 0xEC400000
+#define S5PC100_PA_SPI2                 0xEC500000
 
-/* Timer */
-#define S5PC100_PA_TIMER        (0xEA000000)
-#define S5P_PA_TIMER            S5PC100_PA_TIMER
+#define S5PC100_PA_USB_HSOTG            0xED200000
+#define S5PC100_PA_USB_HSPHY            0xED300000
 
-#define S5PC100_PA_SYSTIMER     (0xEA100000)
+#define S5PC100_PA_HSMMC(x)             (0xED800000 + ((x) * 0x100000))
 
-#define S5PC100_PA_WATCHDOG     (0xEA200000)
-#define S5PC100_PA_RTC          (0xEA300000)
+#define S5PC100_PA_FB                   0xEE000000
 
-#define S5PC100_PA_UART         (0xEC000000)
+#define S5PC100_PA_FIMC0                0xEE200000
+#define S5PC100_PA_FIMC1                0xEE300000
+#define S5PC100_PA_FIMC2                0xEE400000
 
-#define S5P_PA_UART0            (S5PC100_PA_UART + 0x0)
-#define S5P_PA_UART1            (S5PC100_PA_UART + 0x400)
-#define S5P_PA_UART2            (S5PC100_PA_UART + 0x800)
-#define S5P_PA_UART3            (S5PC100_PA_UART + 0xC00)
-#define S5P_SZ_UART             SZ_256
+#define S5PC100_PA_I2S0                 0xF2000000
+#define S5PC100_PA_I2S1                 0xF2100000
+#define S5PC100_PA_I2S2                 0xF2200000
 
-#define S5PC100_PA_IIC0         (0xEC100000)
-#define S5PC100_PA_IIC1         (0xEC200000)
+#define S5PC100_PA_AC97                 0xF2300000
 
-/* SPI */
-#define S5PC100_PA_SPI0         0xEC300000
-#define S5PC100_PA_SPI1         0xEC400000
-#define S5PC100_PA_SPI2         0xEC500000
+#define S5PC100_PA_PCM0                 0xF2400000
+#define S5PC100_PA_PCM1                 0xF2500000
 
-/* USB HS OTG */
-#define S5PC100_PA_USB_HSOTG    (0xED200000)
-#define S5PC100_PA_USB_HSPHY    (0xED300000)
+#define S5PC100_PA_SPDIF                0xF2600000
 
-#define S5PC100_PA_FB           (0xEE000000)
+#define S5PC100_PA_TSADC                0xF3000000
 
-#define S5PC100_PA_FIMC0        (0xEE200000)
-#define S5PC100_PA_FIMC1        (0xEE300000)
-#define S5PC100_PA_FIMC2        (0xEE400000)
+#define S5PC100_PA_KEYPAD               0xF3100000
 
-#define S5PC100_PA_I2S0         (0xF2000000)
-#define S5PC100_PA_I2S1         (0xF2100000)
-#define S5PC100_PA_I2S2         (0xF2200000)
+/* Compatibiltiy Defines */
 
-#define S5PC100_PA_AC97         0xF2300000
+#define S3C_PA_FB                       S5PC100_PA_FB
+#define S3C_PA_HSMMC0                   S5PC100_PA_HSMMC(0)
+#define S3C_PA_HSMMC1                   S5PC100_PA_HSMMC(1)
+#define S3C_PA_HSMMC2                   S5PC100_PA_HSMMC(2)
+#define S3C_PA_IIC                      S5PC100_PA_IIC0
+#define S3C_PA_IIC1                     S5PC100_PA_IIC1
+#define S3C_PA_KEYPAD                   S5PC100_PA_KEYPAD
+#define S3C_PA_ONENAND                  S5PC100_PA_ONENAND
+#define S3C_PA_ONENAND_BUF              S5PC100_PA_ONENAND_BUF
+#define S3C_PA_RTC                      S5PC100_PA_RTC
+#define S3C_PA_TSADC                    S5PC100_PA_TSADC
+#define S3C_PA_USB_HSOTG                S5PC100_PA_USB_HSOTG
+#define S3C_PA_USB_HSPHY                S5PC100_PA_USB_HSPHY
+#define S3C_PA_WDT                      S5PC100_PA_WATCHDOG
 
-/* PCM */
-#define S5PC100_PA_PCM0         0xF2400000
-#define S5PC100_PA_PCM1         0xF2500000
+#define S5P_PA_CHIPID                   S5PC100_PA_CHIPID
+#define S5P_PA_FIMC0                    S5PC100_PA_FIMC0
+#define S5P_PA_FIMC1                    S5PC100_PA_FIMC1
+#define S5P_PA_FIMC2                    S5PC100_PA_FIMC2
+#define S5P_PA_SDRAM                    S5PC100_PA_SDRAM
+#define S5P_PA_SROMC                    S5PC100_PA_SROMC
+#define S5P_PA_SYSCON                   S5PC100_PA_SYSCON
+#define S5P_PA_TIMER                    S5PC100_PA_TIMER
 
-#define S5PC100_PA_SPDIF        0xF2600000
+#define SAMSUNG_PA_ADC                  S5PC100_PA_TSADC
+#define SAMSUNG_PA_CFCON                S5PC100_PA_CFCON
+#define SAMSUNG_PA_KEYPAD               S5PC100_PA_KEYPAD
 
-#define S5PC100_PA_TSADC        (0xF3000000)
+#define S5PC100_VA_OTHERS               (S3C_VA_SYS + 0x10000)
 
-/* KEYPAD */
-#define S5PC100_PA_KEYPAD       (0xF3100000)
+#define S3C_SZ_ONENAND_BUF              (SZ_256M - SZ_32M)
 
-#define S5PC100_PA_HSMMC(x)     (0xED800000 + ((x) * 0x100000))
+/* UART */
 
-#define S5PC100_PA_SDRAM        (0x20000000)
-#define S5P_PA_SDRAM            S5PC100_PA_SDRAM
+#define S3C_PA_UART                     S5PC100_PA_UART
 
-/* compatibiltiy defines. */
-#define S3C_PA_UART             S5PC100_PA_UART
-#define S3C_PA_IIC              S5PC100_PA_IIC0
-#define S3C_PA_IIC1             S5PC100_PA_IIC1
-#define S3C_PA_FB               S5PC100_PA_FB
-#define S3C_PA_G2D              S5PC100_PA_G2D
-#define S3C_PA_G3D              S5PC100_PA_G3D
-#define S3C_PA_JPEG             S5PC100_PA_JPEG
-#define S3C_PA_ROTATOR          S5PC100_PA_ROTATOR
-#define S5P_VA_VIC0             S5PC1XX_VA_VIC(0)
-#define S5P_VA_VIC1             S5PC1XX_VA_VIC(1)
-#define S5P_VA_VIC2             S5PC1XX_VA_VIC(2)
-#define S3C_PA_USB_HSOTG        S5PC100_PA_USB_HSOTG
-#define S3C_PA_USB_HSPHY        S5PC100_PA_USB_HSPHY
-#define S3C_PA_HSMMC0           S5PC100_PA_HSMMC(0)
-#define S3C_PA_HSMMC1           S5PC100_PA_HSMMC(1)
-#define S3C_PA_HSMMC2           S5PC100_PA_HSMMC(2)
-#define S3C_PA_KEYPAD           S5PC100_PA_KEYPAD
-#define S3C_PA_WDT              S5PC100_PA_WATCHDOG
-#define S3C_PA_TSADC            S5PC100_PA_TSADC
-#define S3C_PA_ONENAND          S5PC100_PA_ONENAND
-#define S3C_PA_ONENAND_BUF      S5PC100_PA_ONENAND_BUF
-#define S3C_SZ_ONENAND_BUF      S5PC100_SZ_ONENAND_BUF
-#define S3C_PA_RTC              S5PC100_PA_RTC
-
-#define SAMSUNG_PA_ADC          S5PC100_PA_TSADC
-#define SAMSUNG_PA_CFCON        S5PC100_PA_CFCON
-#define SAMSUNG_PA_KEYPAD       S5PC100_PA_KEYPAD
+#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                    S5P_PA_UART(0)
+#define S5P_PA_UART1                    S5P_PA_UART(1)
+#define S5P_PA_UART2                    S5P_PA_UART(2)
+#define S5P_PA_UART3                    S5P_PA_UART(3)
 
-#define S5P_PA_FIMC0            S5PC100_PA_FIMC0
-#define S5P_PA_FIMC1            S5PC100_PA_FIMC1
-#define S5P_PA_FIMC2            S5PC100_PA_FIMC2
+#define S5P_SZ_UART                     SZ_256
 
-#endif /* __ASM_ARCH_C100_MAP_H */
+#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/include/mach/map.h b/arch/arm/mach-s5pv210/include/mach/map.h
index 3611492ad68..1dd58836fd4 100644
--- a/arch/arm/mach-s5pv210/include/mach/map.h
+++ b/arch/arm/mach-s5pv210/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5pv210/include/mach/map.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
  * S5PV210 - Memory map definitions
@@ -16,122 +16,120 @@
 #include <plat/map-base.h>
 #include <plat/map-s5p.h>
 
-#define S5PV210_PA_SROM_BANK5   (0xA8000000)
+#define S5PV210_PA_SDRAM                0x20000000
 
-#define S5PC110_PA_ONENAND      (0xB0000000)
-#define S5P_PA_ONENAND          S5PC110_PA_ONENAND
+#define S5PV210_PA_SROM_BANK5           0xA8000000
 
-#define S5PC110_PA_ONENAND_DMA  (0xB0600000)
-#define S5P_PA_ONENAND_DMA      S5PC110_PA_ONENAND_DMA
+#define S5PC110_PA_ONENAND              0xB0000000
+#define S5PC110_PA_ONENAND_DMA          0xB0600000
 
-#define S5PV210_PA_CHIPID       (0xE0000000)
-#define S5P_PA_CHIPID           S5PV210_PA_CHIPID
+#define S5PV210_PA_CHIPID               0xE0000000
 
-#define S5PV210_PA_SYSCON       (0xE0100000)
-#define S5P_PA_SYSCON           S5PV210_PA_SYSCON
+#define S5PV210_PA_SYSCON               0xE0100000
 
-#define S5PV210_PA_GPIO         (0xE0200000)
+#define S5PV210_PA_GPIO                 0xE0200000
 
-/* SPI */
-#define S5PV210_PA_SPI0         0xE1300000
-#define S5PV210_PA_SPI1         0xE1400000
+#define S5PV210_PA_SPDIF                0xE1100000
 
-#define S5PV210_PA_KEYPAD       (0xE1600000)
+#define S5PV210_PA_SPI0                 0xE1300000
+#define S5PV210_PA_SPI1                 0xE1400000
 
-#define S5PV210_PA_IIC0         (0xE1800000)
-#define S5PV210_PA_IIC1         (0xFAB00000)
-#define S5PV210_PA_IIC2         (0xE1A00000)
+#define S5PV210_PA_KEYPAD               0xE1600000
 
-#define S5PV210_PA_TIMER        (0xE2500000)
-#define S5P_PA_TIMER            S5PV210_PA_TIMER
+#define S5PV210_PA_ADC                  0xE1700000
 
-#define S5PV210_PA_SYSTIMER     (0xE2600000)
+#define S5PV210_PA_IIC0                 0xE1800000
+#define S5PV210_PA_IIC1                 0xFAB00000
+#define S5PV210_PA_IIC2                 0xE1A00000
 
-#define S5PV210_PA_WATCHDOG     (0xE2700000)
+#define S5PV210_PA_AC97                 0xE2200000
 
-#define S5PV210_PA_RTC          (0xE2800000)
-#define S5PV210_PA_UART         (0xE2900000)
+#define S5PV210_PA_PCM0                 0xE2300000
+#define S5PV210_PA_PCM1                 0xE1200000
+#define S5PV210_PA_PCM2                 0xE2B00000
 
-#define S5P_PA_UART0            (S5PV210_PA_UART + 0x0)
-#define S5P_PA_UART1            (S5PV210_PA_UART + 0x400)
-#define S5P_PA_UART2            (S5PV210_PA_UART + 0x800)
-#define S5P_PA_UART3            (S5PV210_PA_UART + 0xC00)
+#define S5PV210_PA_TIMER                0xE2500000
+#define S5PV210_PA_SYSTIMER             0xE2600000
+#define S5PV210_PA_WATCHDOG             0xE2700000
+#define S5PV210_PA_RTC                  0xE2800000
 
-#define S5P_SZ_UART             SZ_256
+#define S5PV210_PA_UART                 0xE2900000
 
-#define S3C_VA_UARTx(x)         (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
+#define S5PV210_PA_SROMC                0xE8000000
 
-#define S5PV210_PA_SROMC        (0xE8000000)
-#define S5P_PA_SROMC            S5PV210_PA_SROMC
+#define S5PV210_PA_CFCON                0xE8200000
 
-#define S5PV210_PA_CFCON        (0xE8200000)
+#define S5PV210_PA_HSMMC(x)             (0xEB000000 + ((x) * 0x100000))
 
-#define S5PV210_PA_MDMA         0xFA200000
-#define S5PV210_PA_PDMA0        0xE0900000
-#define S5PV210_PA_PDMA1        0xE0A00000
+#define S5PV210_PA_HSOTG                0xEC000000
+#define S5PV210_PA_HSPHY                0xEC100000
 
-#define S5PV210_PA_FB           (0xF8000000)
+#define S5PV210_PA_IIS0                 0xEEE30000
+#define S5PV210_PA_IIS1                 0xE2100000
+#define S5PV210_PA_IIS2                 0xE2A00000
 
-#define S5PV210_PA_FIMC0        (0xFB200000)
-#define S5PV210_PA_FIMC1        (0xFB300000)
-#define S5PV210_PA_FIMC2        (0xFB400000)
+#define S5PV210_PA_DMC0                 0xF0000000
+#define S5PV210_PA_DMC1                 0xF1400000
 
-#define S5PV210_PA_HSMMC(x)     (0xEB000000 + ((x) * 0x100000))
+#define S5PV210_PA_VIC0                 0xF2000000
+#define S5PV210_PA_VIC1                 0xF2100000
+#define S5PV210_PA_VIC2                 0xF2200000
+#define S5PV210_PA_VIC3                 0xF2300000
 
-#define S5PV210_PA_HSOTG        (0xEC000000)
-#define S5PV210_PA_HSPHY        (0xEC100000)
+#define S5PV210_PA_FB                   0xF8000000
 
-#define S5PV210_PA_VIC0         (0xF2000000)
-#define S5PV210_PA_VIC1         (0xF2100000)
-#define S5PV210_PA_VIC2         (0xF2200000)
-#define S5PV210_PA_VIC3         (0xF2300000)
+#define S5PV210_PA_MDMA                 0xFA200000
+#define S5PV210_PA_PDMA0                0xE0900000
+#define S5PV210_PA_PDMA1                0xE0A00000
 
-#define S5PV210_PA_SDRAM        (0x20000000)
-#define S5P_PA_SDRAM            S5PV210_PA_SDRAM
+#define S5PV210_PA_MIPI_CSIS            0xFA600000
 
-/* S/PDIF */
-#define S5PV210_PA_SPDIF        0xE1100000
+#define S5PV210_PA_FIMC0                0xFB200000
+#define S5PV210_PA_FIMC1                0xFB300000
+#define S5PV210_PA_FIMC2                0xFB400000
 
-/* I2S */
-#define S5PV210_PA_IIS0         0xEEE30000
-#define S5PV210_PA_IIS1         0xE2100000
-#define S5PV210_PA_IIS2         0xE2A00000
+/* Compatibiltiy Defines */
 
-/* PCM */
-#define S5PV210_PA_PCM0         0xE2300000
-#define S5PV210_PA_PCM1         0xE1200000
-#define S5PV210_PA_PCM2         0xE2B00000
+#define S3C_PA_FB                       S5PV210_PA_FB
+#define S3C_PA_HSMMC0                   S5PV210_PA_HSMMC(0)
+#define S3C_PA_HSMMC1                   S5PV210_PA_HSMMC(1)
+#define S3C_PA_HSMMC2                   S5PV210_PA_HSMMC(2)
+#define S3C_PA_HSMMC3                   S5PV210_PA_HSMMC(3)
+#define S3C_PA_IIC                      S5PV210_PA_IIC0
+#define S3C_PA_IIC1                     S5PV210_PA_IIC1
+#define S3C_PA_IIC2                     S5PV210_PA_IIC2
+#define S3C_PA_RTC                      S5PV210_PA_RTC
+#define S3C_PA_USB_HSOTG                S5PV210_PA_HSOTG
+#define S3C_PA_WDT                      S5PV210_PA_WATCHDOG
 
-/* AC97 */
-#define S5PV210_PA_AC97         0xE2200000
+#define S5P_PA_CHIPID                   S5PV210_PA_CHIPID
+#define S5P_PA_FIMC0                    S5PV210_PA_FIMC0
+#define S5P_PA_FIMC1                    S5PV210_PA_FIMC1
+#define S5P_PA_FIMC2                    S5PV210_PA_FIMC2
+#define S5P_PA_MIPI_CSIS0               S5PV210_PA_MIPI_CSIS
+#define S5P_PA_ONENAND                  S5PC110_PA_ONENAND
+#define S5P_PA_ONENAND_DMA              S5PC110_PA_ONENAND_DMA
+#define S5P_PA_SDRAM                    S5PV210_PA_SDRAM
+#define S5P_PA_SROMC                    S5PV210_PA_SROMC
+#define S5P_PA_SYSCON                   S5PV210_PA_SYSCON
+#define S5P_PA_TIMER                    S5PV210_PA_TIMER
 
-#define S5PV210_PA_ADC          (0xE1700000)
+#define SAMSUNG_PA_ADC                  S5PV210_PA_ADC
+#define SAMSUNG_PA_CFCON                S5PV210_PA_CFCON
+#define SAMSUNG_PA_KEYPAD               S5PV210_PA_KEYPAD
 
-#define S5PV210_PA_DMC0         (0xF0000000)
-#define S5PV210_PA_DMC1         (0xF1400000)
+/* UART */
 
-#define S5PV210_PA_MIPI_CSIS    0xFA600000
+#define S3C_VA_UARTx(x)                 (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
 
-/* compatibiltiy defines. */
-#define S3C_PA_UART             S5PV210_PA_UART
-#define S3C_PA_HSMMC0           S5PV210_PA_HSMMC(0)
-#define S3C_PA_HSMMC1           S5PV210_PA_HSMMC(1)
-#define S3C_PA_HSMMC2           S5PV210_PA_HSMMC(2)
-#define S3C_PA_HSMMC3           S5PV210_PA_HSMMC(3)
-#define S3C_PA_IIC              S5PV210_PA_IIC0
-#define S3C_PA_IIC1             S5PV210_PA_IIC1
-#define S3C_PA_IIC2             S5PV210_PA_IIC2
-#define S3C_PA_FB               S5PV210_PA_FB
-#define S3C_PA_RTC              S5PV210_PA_RTC
-#define S3C_PA_WDT              S5PV210_PA_WATCHDOG
-#define S3C_PA_USB_HSOTG        S5PV210_PA_HSOTG
-#define S5P_PA_FIMC0            S5PV210_PA_FIMC0
-#define S5P_PA_FIMC1            S5PV210_PA_FIMC1
-#define S5P_PA_FIMC2            S5PV210_PA_FIMC2
-#define S5P_PA_MIPI_CSIS0       S5PV210_PA_MIPI_CSIS
+#define S3C_PA_UART                     S5PV210_PA_UART
 
-#define SAMSUNG_PA_ADC          S5PV210_PA_ADC
-#define SAMSUNG_PA_CFCON        S5PV210_PA_CFCON
-#define SAMSUNG_PA_KEYPAD       S5PV210_PA_KEYPAD
+#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                    S5P_PA_UART(0)
+#define S5P_PA_UART1                    S5P_PA_UART(1)
+#define S5P_PA_UART2                    S5P_PA_UART(2)
+#define S5P_PA_UART3                    S5P_PA_UART(3)
+
+#define S5P_SZ_UART                     SZ_256
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 461aa035afc..557add4fc56 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -149,7 +149,7 @@ static struct regulator_init_data aquila_ldo2_data = {
 
 static struct regulator_init_data aquila_ldo3_data = {
         .constraints    = {
-                .name           = "VUSB/MIPI_1.1V",
+                .name           = "VUSB+MIPI_1.1V",
                 .min_uV         = 1100000,
                 .max_uV         = 1100000,
                 .apply_uV       = 1,
@@ -197,7 +197,7 @@ static struct regulator_init_data aquila_ldo7_data = {
 
 static struct regulator_init_data aquila_ldo8_data = {
         .constraints    = {
-                .name           = "VUSB/VADC_3.3V",
+                .name           = "VUSB+VADC_3.3V",
                 .min_uV         = 3300000,
                 .max_uV         = 3300000,
                 .apply_uV       = 1,
@@ -207,7 +207,7 @@ static struct regulator_init_data aquila_ldo8_data = {
 
 static struct regulator_init_data aquila_ldo9_data = {
         .constraints    = {
-                .name           = "VCC/VCAM_2.8V",
+                .name           = "VCC+VCAM_2.8V",
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
@@ -381,9 +381,12 @@ static struct max8998_platform_data aquila_max8998_pdata = {
         .buck1_set1     = S5PV210_GPH0(3),
         .buck1_set2     = S5PV210_GPH0(4),
         .buck2_set3     = S5PV210_GPH0(5),
-        .buck1_max_voltage1 = 1200000,
-        .buck1_max_voltage2 = 1200000,
-        .buck2_max_voltage = 1200000,
+        .buck1_voltage1 = 1200000,
+        .buck1_voltage2 = 1200000,
+        .buck1_voltage3 = 1200000,
+        .buck1_voltage4 = 1200000,
+        .buck2_voltage1 = 1200000,
+        .buck2_voltage2 = 1200000,
 };
 #endif
 
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index e22d5112fd4..056f5c769b0 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -288,7 +288,7 @@ static struct regulator_init_data goni_ldo2_data = {
 
 static struct regulator_init_data goni_ldo3_data = {
         .constraints    = {
-                .name           = "VUSB/MIPI_1.1V",
+                .name           = "VUSB+MIPI_1.1V",
                 .min_uV         = 1100000,
                 .max_uV         = 1100000,
                 .apply_uV       = 1,
@@ -337,7 +337,7 @@ static struct regulator_init_data goni_ldo7_data = {
 
 static struct regulator_init_data goni_ldo8_data = {
         .constraints    = {
-                .name           = "VUSB/VADC_3.3V",
+                .name           = "VUSB+VADC_3.3V",
                 .min_uV         = 3300000,
                 .max_uV         = 3300000,
                 .apply_uV       = 1,
@@ -347,7 +347,7 @@ static struct regulator_init_data goni_ldo8_data = {
 
 static struct regulator_init_data goni_ldo9_data = {
         .constraints    = {
-                .name           = "VCC/VCAM_2.8V",
+                .name           = "VCC+VCAM_2.8V",
                 .min_uV         = 2800000,
                 .max_uV         = 2800000,
                 .apply_uV       = 1,
@@ -521,9 +521,12 @@ static struct max8998_platform_data goni_max8998_pdata = {
         .buck1_set1     = S5PV210_GPH0(3),
         .buck1_set2     = S5PV210_GPH0(4),
         .buck2_set3     = S5PV210_GPH0(5),
-        .buck1_max_voltage1 = 1200000,
-        .buck1_max_voltage2 = 1200000,
-        .buck2_max_voltage = 1200000,
+        .buck1_voltage1 = 1200000,
+        .buck1_voltage2 = 1200000,
+        .buck1_voltage3 = 1200000,
+        .buck1_voltage4 = 1200000,
+        .buck2_voltage1 = 1200000,
+        .buck2_voltage2 = 1200000,
 };
 #endif
 
diff --git a/arch/arm/mach-s5pv310/include/mach/map.h b/arch/arm/mach-s5pv310/include/mach/map.h
index 3060f78e12a..901657fa7a1 100644
--- a/arch/arm/mach-s5pv310/include/mach/map.h
+++ b/arch/arm/mach-s5pv310/include/mach/map.h
@@ -1,6 +1,6 @@
 /* linux/arch/arm/mach-s5pv310/include/mach/map.h
  *
- * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  *              http://www.samsung.com/
  *
  * S5PV310 - Memory map definitions
@@ -23,90 +23,43 @@
 
 #include <plat/map-s5p.h>
 
-#define S5PV310_PA_SYSRAM               (0x02025000)
+#define S5PV310_PA_SYSRAM               0x02025000
 
-#define S5PV310_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
-
-#define S5PC210_PA_ONENAND              (0x0C000000)
-#define S5P_PA_ONENAND                  S5PC210_PA_ONENAND
-
-#define S5PC210_PA_ONENAND_DMA          (0x0C600000)
-#define S5P_PA_ONENAND_DMA              S5PC210_PA_ONENAND_DMA
-
-#define S5PV310_PA_CHIPID               (0x10000000)
-#define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
-
-#define S5PV310_PA_SYSCON               (0x10010000)
-#define S5P_PA_SYSCON                   S5PV310_PA_SYSCON
+#define S5PV310_PA_I2S0                 0x03830000
+#define S5PV310_PA_I2S1                 0xE3100000
+#define S5PV310_PA_I2S2                 0xE2A00000
 
-#define S5PV310_PA_PMU                  (0x10020000)
+#define S5PV310_PA_PCM0                 0x03840000
+#define S5PV310_PA_PCM1                 0x13980000
+#define S5PV310_PA_PCM2                 0x13990000
 
-#define S5PV310_PA_CMU                  (0x10030000)
-
-#define S5PV310_PA_WATCHDOG             (0x10060000)
-#define S5PV310_PA_RTC                  (0x10070000)
-
-#define S5PV310_PA_DMC0                 (0x10400000)
-
-#define S5PV310_PA_COMBINER             (0x10448000)
-
-#define S5PV310_PA_COREPERI             (0x10500000)
-#define S5PV310_PA_GIC_CPU              (0x10500100)
-#define S5PV310_PA_TWD                  (0x10500600)
-#define S5PV310_PA_GIC_DIST             (0x10501000)
-#define S5PV310_PA_L2CC                 (0x10502000)
-
-/* DMA */
-#define S5PV310_PA_MDMA         0x10810000
-#define S5PV310_PA_PDMA0        0x12680000
-#define S5PV310_PA_PDMA1        0x12690000
-
-#define S5PV310_PA_GPIO1                (0x11400000)
-#define S5PV310_PA_GPIO2                (0x11000000)
-#define S5PV310_PA_GPIO3                (0x03860000)
-
-#define S5PV310_PA_MIPI_CSIS0           0x11880000
-#define S5PV310_PA_MIPI_CSIS1           0x11890000
+#define S5PV310_PA_SROM_BANK(x)         (0x04000000 + ((x) * 0x01000000))
 
-#define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
+#define S5PC210_PA_ONENAND              0x0C000000
+#define S5PC210_PA_ONENAND_DMA          0x0C600000
 
-#define S5PV310_PA_SROMC                (0x12570000)
-#define S5P_PA_SROMC                    S5PV310_PA_SROMC
+#define S5PV310_PA_CHIPID               0x10000000
 
-/* S/PDIF */
-#define S5PV310_PA_SPDIF        0xE1100000
+#define S5PV310_PA_SYSCON               0x10010000
+#define S5PV310_PA_PMU                  0x10020000
+#define S5PV310_PA_CMU                  0x10030000
 
-/* I2S */
-#define S5PV310_PA_I2S0         0x03830000
-#define S5PV310_PA_I2S1         0xE3100000
-#define S5PV310_PA_I2S2         0xE2A00000
+#define S5PV310_PA_WATCHDOG             0x10060000
+#define S5PV310_PA_RTC                  0x10070000
 
-/* PCM */
-#define S5PV310_PA_PCM0         0x03840000
-#define S5PV310_PA_PCM1         0x13980000
-#define S5PV310_PA_PCM2         0x13990000
+#define S5PV310_PA_DMC0                 0x10400000
 
-/* AC97 */
-#define S5PV310_PA_AC97         0x139A0000
+#define S5PV310_PA_COMBINER             0x10448000
 
-#define S5PV310_PA_UART                 (0x13800000)
+#define S5PV310_PA_COREPERI             0x10500000
+#define S5PV310_PA_GIC_CPU              0x10500100
+#define S5PV310_PA_TWD                  0x10500600
+#define S5PV310_PA_GIC_DIST             0x10501000
+#define S5PV310_PA_L2CC                 0x10502000
 
-#define S5P_PA_UART(x)                  (S5PV310_PA_UART + ((x) * S3C_UART_OFFSET))
-#define S5P_PA_UART0                    S5P_PA_UART(0)
-#define S5P_PA_UART1                    S5P_PA_UART(1)
-#define S5P_PA_UART2                    S5P_PA_UART(2)
-#define S5P_PA_UART3                    S5P_PA_UART(3)
-#define S5P_PA_UART4                    S5P_PA_UART(4)
-
-#define S5P_SZ_UART                     SZ_256
-
-#define S5PV310_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
-
-#define S5PV310_PA_TIMER                (0x139D0000)
-#define S5P_PA_TIMER                    S5PV310_PA_TIMER
-
-#define S5PV310_PA_SDRAM                (0x40000000)
-#define S5P_PA_SDRAM                    S5PV310_PA_SDRAM
+#define S5PV310_PA_MDMA                 0x10810000
+#define S5PV310_PA_PDMA0                0x12680000
+#define S5PV310_PA_PDMA1                0x12690000
 
 #define S5PV310_PA_SYSMMU_MDMA          0x10A40000
 #define S5PV310_PA_SYSMMU_SSS           0x10A50000
@@ -125,8 +78,31 @@
 #define S5PV310_PA_SYSMMU_MFC_L         0x13620000
 #define S5PV310_PA_SYSMMU_MFC_R         0x13630000
 
-/* compatibiltiy defines. */
-#define S3C_PA_UART                     S5PV310_PA_UART
+#define S5PV310_PA_GPIO1                0x11400000
+#define S5PV310_PA_GPIO2                0x11000000
+#define S5PV310_PA_GPIO3                0x03860000
+
+#define S5PV310_PA_MIPI_CSIS0           0x11880000
+#define S5PV310_PA_MIPI_CSIS1           0x11890000
+
+#define S5PV310_PA_HSMMC(x)             (0x12510000 + ((x) * 0x10000))
+
+#define S5PV310_PA_SROMC                0x12570000
+
+#define S5PV310_PA_UART                 0x13800000
+
+#define S5PV310_PA_IIC(x)               (0x13860000 + ((x) * 0x10000))
+
+#define S5PV310_PA_AC97                 0x139A0000
+
+#define S5PV310_PA_TIMER                0x139D0000
+
+#define S5PV310_PA_SDRAM                0x40000000
+
+#define S5PV310_PA_SPDIF                0xE1100000
+
+/* Compatibiltiy Defines */
+
 #define S3C_PA_HSMMC0                   S5PV310_PA_HSMMC(0)
 #define S3C_PA_HSMMC1                   S5PV310_PA_HSMMC(1)
 #define S3C_PA_HSMMC2                   S5PV310_PA_HSMMC(2)
@@ -141,7 +117,28 @@
 #define S3C_PA_IIC7                     S5PV310_PA_IIC(7)
 #define S3C_PA_RTC                      S5PV310_PA_RTC
 #define S3C_PA_WDT                      S5PV310_PA_WATCHDOG
+
+#define S5P_PA_CHIPID                   S5PV310_PA_CHIPID
 #define S5P_PA_MIPI_CSIS0               S5PV310_PA_MIPI_CSIS0
 #define S5P_PA_MIPI_CSIS1               S5PV310_PA_MIPI_CSIS1
+#define S5P_PA_ONENAND                  S5PC210_PA_ONENAND
+#define S5P_PA_ONENAND_DMA              S5PC210_PA_ONENAND_DMA
+#define S5P_PA_SDRAM                    S5PV310_PA_SDRAM
+#define S5P_PA_SROMC                    S5PV310_PA_SROMC
+#define S5P_PA_SYSCON                   S5PV310_PA_SYSCON
+#define S5P_PA_TIMER                    S5PV310_PA_TIMER
+
+/* UART */
+
+#define S3C_PA_UART                     S5PV310_PA_UART
+
+#define S5P_PA_UART(x)                  (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
+#define S5P_PA_UART0                    S5P_PA_UART(0)
+#define S5P_PA_UART1                    S5P_PA_UART(1)
+#define S5P_PA_UART2                    S5P_PA_UART(2)
+#define S5P_PA_UART3                    S5P_PA_UART(3)
+#define S5P_PA_UART4                    S5P_PA_UART(4)
+
+#define S5P_SZ_UART                     SZ_256
 
 #endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index cacf17a958c..53677e464d4 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -62,7 +62,7 @@
 #define SPEAR320_SMII1_BASE             0xAB000000
 #define SPEAR320_SMII1_SIZE             0x01000000
 
-#define SPEAR320_SOC_CONFIG_BASE        0xB4000000
+#define SPEAR320_SOC_CONFIG_BASE        0xB3000000
 #define SPEAR320_SOC_CONFIG_SIZE        0x00000070
 /* Interrupt registers offsets and masks */
 #define INT_STS_MASK_REG                0x04
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 170c9bb9586..f2ce38e085d 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -49,7 +49,13 @@ static inline void cache_wait(void __iomem *reg, unsigned long mask)
 static inline void cache_sync(void)
 {
         void __iomem *base = l2x0_base;
+
+#ifdef CONFIG_ARM_ERRATA_753970
+        /* write to an unmmapped register */
+        writel_relaxed(0, base + L2X0_DUMMY_REG);
+#else
         writel_relaxed(0, base + L2X0_CACHE_SYNC);
+#endif
         cache_wait(base + L2X0_CACHE_SYNC, 1);
 }
 
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 0c1172b56b4..8e335623913 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -264,6 +264,12 @@ __v7_setup:
         orreq   r10, r10, #1 << 6               @ set bit #6
         mcreq   p15, 0, r10, c15, c0, 1         @ write diagnostic register
 #endif
+#ifdef CONFIG_ARM_ERRATA_751472
+        cmp     r6, #0x30                       @ present prior to r3p0
+        mrclt   p15, 0, r10, c15, c0, 1         @ read diagnostic register
+        orrlt   r10, r10, #1 << 11              @ set bit #11
+        mcrlt   p15, 0, r10, c15, c0, 1         @ write diagnostic register
+#endif
 
 3:      mov     r10, #0
 #ifdef HARVARD_CACHE
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index 5f352231481..078894bc3b9 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -17,55 +17,123 @@
 #include <linux/io.h>
 #include <linux/gpio.h>
 
-static DEFINE_SPINLOCK(gpio_lock);
-static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
-static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
+/*
+ * GPIO unit register offsets.
+ */
+#define GPIO_OUT_OFF            0x0000
+#define GPIO_IO_CONF_OFF        0x0004
+#define GPIO_BLINK_EN_OFF       0x0008
+#define GPIO_IN_POL_OFF         0x000c
+#define GPIO_DATA_IN_OFF        0x0010
+#define GPIO_EDGE_CAUSE_OFF     0x0014
+#define GPIO_EDGE_MASK_OFF      0x0018
+#define GPIO_LEVEL_MASK_OFF     0x001c
+
+struct orion_gpio_chip {
+        struct gpio_chip        chip;
+        spinlock_t              lock;
+        void __iomem            *base;
+        unsigned long           valid_input;
+        unsigned long           valid_output;
+        int                     mask_offset;
+        int                     secondary_irq_base;
+};
+
+static void __iomem *GPIO_OUT(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_OUT_OFF;
+}
+
+static void __iomem *GPIO_IO_CONF(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_IO_CONF_OFF;
+}
+
+static void __iomem *GPIO_BLINK_EN(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_BLINK_EN_OFF;
+}
+
+static void __iomem *GPIO_IN_POL(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_IN_POL_OFF;
+}
+
+static void __iomem *GPIO_DATA_IN(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_DATA_IN_OFF;
+}
+
+static void __iomem *GPIO_EDGE_CAUSE(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + GPIO_EDGE_CAUSE_OFF;
+}
+
+static void __iomem *GPIO_EDGE_MASK(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + ochip->mask_offset + GPIO_EDGE_MASK_OFF;
+}
+
+static void __iomem *GPIO_LEVEL_MASK(struct orion_gpio_chip *ochip)
+{
+        return ochip->base + ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
+}
+
 
-static inline void __set_direction(unsigned pin, int input)
+static struct orion_gpio_chip orion_gpio_chips[2];
+static int orion_gpio_chip_count;
+
+static inline void
+__set_direction(struct orion_gpio_chip *ochip, unsigned pin, int input)
 {
         u32 u;
 
-        u = readl(GPIO_IO_CONF(pin));
+        u = readl(GPIO_IO_CONF(ochip));
         if (input)
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
         else
-                u &= ~(1 << (pin & 31));
-        writel(u, GPIO_IO_CONF(pin));
+                u &= ~(1 << pin);
+        writel(u, GPIO_IO_CONF(ochip));
 }
 
-static void __set_level(unsigned pin, int high)
+static void __set_level(struct orion_gpio_chip *ochip, unsigned pin, int high)
 {
         u32 u;
 
-        u = readl(GPIO_OUT(pin));
+        u = readl(GPIO_OUT(ochip));
         if (high)
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
         else
-                u &= ~(1 << (pin & 31));
-        writel(u, GPIO_OUT(pin));
+                u &= ~(1 << pin);
+        writel(u, GPIO_OUT(ochip));
 }
 
-static inline void __set_blinking(unsigned pin, int blink)
+static inline void
+__set_blinking(struct orion_gpio_chip *ochip, unsigned pin, int blink)
 {
         u32 u;
 
-        u = readl(GPIO_BLINK_EN(pin));
+        u = readl(GPIO_BLINK_EN(ochip));
         if (blink)
-                u |= 1 << (pin & 31);
+                u |= 1 << pin;
         else
-                u &= ~(1 << (pin & 31));
-        writel(u, GPIO_BLINK_EN(pin));
+                u &= ~(1 << pin);
+        writel(u, GPIO_BLINK_EN(ochip));
 }
 
-static inline int orion_gpio_is_valid(unsigned pin, int mode)
+static inline int
+orion_gpio_is_valid(struct orion_gpio_chip *ochip, unsigned pin, int mode)
 {
-        if (pin < GPIO_MAX) {
-                if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input))
-                        goto err_out;
-                if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output))
-                        goto err_out;
-                return true;
-        }
+        if (pin >= ochip->chip.ngpio)
+                goto err_out;
+
+        if ((mode & GPIO_INPUT_OK) && !test_bit(pin, &ochip->valid_input))
+                goto err_out;
+
+        if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, &ochip->valid_output))
+                goto err_out;
+
+        return 1;
 
 err_out:
         pr_debug("%s: invalid GPIO %d\n", __func__, pin);
@@ -75,134 +143,155 @@ err_out:
 /*
  * GENERIC_GPIO primitives.
  */
+static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
+
+        if (orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK) ||
+            orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
+                return 0;
+
+        return -EINVAL;
+}
+
 static int orion_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
         unsigned long flags;
 
-        if (!orion_gpio_is_valid(pin, GPIO_INPUT_OK))
+        if (!orion_gpio_is_valid(ochip, pin, GPIO_INPUT_OK))
                 return -EINVAL;
 
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        /* Configure GPIO direction. */
-        __set_direction(pin, 1);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_direction(ochip, pin, 1);
+        spin_unlock_irqrestore(&ochip->lock, flags);
 
         return 0;
 }
 
-static int orion_gpio_get_value(struct gpio_chip *chip, unsigned pin)
+static int orion_gpio_get(struct gpio_chip *chip, unsigned pin)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
         int val;
 
-        if (readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31)))
-                val = readl(GPIO_DATA_IN(pin)) ^ readl(GPIO_IN_POL(pin));
-        else
-                val = readl(GPIO_OUT(pin));
+        if (readl(GPIO_IO_CONF(ochip)) & (1 << pin)) {
+                val = readl(GPIO_DATA_IN(ochip)) ^ readl(GPIO_IN_POL(ochip));
+        } else {
+                val = readl(GPIO_OUT(ochip));
+        }
 
-        return (val >> (pin & 31)) & 1;
+        return (val >> pin) & 1;
 }
 
-static int orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
-        int value)
+static int
+orion_gpio_direction_output(struct gpio_chip *chip, unsigned pin, int value)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
         unsigned long flags;
 
-        if (!orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
+        if (!orion_gpio_is_valid(ochip, pin, GPIO_OUTPUT_OK))
                 return -EINVAL;
 
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        /* Disable blinking. */
-        __set_blinking(pin, 0);
-
-        /* Configure GPIO output value. */
-        __set_level(pin, value);
-
-        /* Configure GPIO direction. */
-        __set_direction(pin, 0);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_blinking(ochip, pin, 0);
+        __set_level(ochip, pin, value);
+        __set_direction(ochip, pin, 0);
+        spin_unlock_irqrestore(&ochip->lock, flags);
 
         return 0;
 }
 
-static void orion_gpio_set_value(struct gpio_chip *chip, unsigned pin,
-        int value)
+static void orion_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
 {
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
         unsigned long flags;
 
-        spin_lock_irqsave(&gpio_lock, flags);
-
-        /* Configure GPIO output value. */
-        __set_level(pin, value);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_level(ochip, pin, value);
+        spin_unlock_irqrestore(&ochip->lock, flags);
 }
 
-static int orion_gpio_request(struct gpio_chip *chip, unsigned pin)
+static int orion_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 {
-        if (orion_gpio_is_valid(pin, GPIO_INPUT_OK) ||
-            orion_gpio_is_valid(pin, GPIO_OUTPUT_OK))
-                return 0;
-        return -EINVAL;
-}
+        struct orion_gpio_chip *ochip =
+                container_of(chip, struct orion_gpio_chip, chip);
 
-static struct gpio_chip orion_gpiochip = {
-        .label                  = "orion_gpio",
-        .direction_input        = orion_gpio_direction_input,
-        .get                    = orion_gpio_get_value,
-        .direction_output       = orion_gpio_direction_output,
-        .set                    = orion_gpio_set_value,
-        .request                = orion_gpio_request,
-        .base                   = 0,
-        .ngpio                  = GPIO_MAX,
-        .can_sleep              = 0,
-};
-
-void __init orion_gpio_init(void)
-{
-        gpiochip_add(&orion_gpiochip);
+        return ochip->secondary_irq_base + pin;
 }
 
+
 /*
  * Orion-specific GPIO API extensions.
  */
+static struct orion_gpio_chip *orion_gpio_chip_find(int pin)
+{
+        int i;
+
+        for (i = 0; i < orion_gpio_chip_count; i++) {
+                struct orion_gpio_chip *ochip = orion_gpio_chips + i;
+                struct gpio_chip *chip = &ochip->chip;
+
+                if (pin >= chip->base && pin < chip->base + chip->ngpio)
+                        return ochip;
+        }
+
+        return NULL;
+}
+
 void __init orion_gpio_set_unused(unsigned pin)
 {
+        struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
+
+        if (ochip == NULL)
+                return;
+
+        pin -= ochip->chip.base;
+
         /* Configure as output, drive low. */
-        __set_level(pin, 0);
-        __set_direction(pin, 0);
+        __set_level(ochip, pin, 0);
+        __set_direction(ochip, pin, 0);
 }
 
 void __init orion_gpio_set_valid(unsigned pin, int mode)
 {
+        struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
+
+        if (ochip == NULL)
+                return;
+
+        pin -= ochip->chip.base;
+
         if (mode == 1)
                 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK;
+
         if (mode & GPIO_INPUT_OK)
-                __set_bit(pin, gpio_valid_input);
+                __set_bit(pin, &ochip->valid_input);
         else
-                __clear_bit(pin, gpio_valid_input);
+                __clear_bit(pin, &ochip->valid_input);
+
         if (mode & GPIO_OUTPUT_OK)
-                __set_bit(pin, gpio_valid_output);
+                __set_bit(pin, &ochip->valid_output);
         else
-                __clear_bit(pin, gpio_valid_output);
+                __clear_bit(pin, &ochip->valid_output);
 }
 
 void orion_gpio_set_blink(unsigned pin, int blink)
 {
+        struct orion_gpio_chip *ochip = orion_gpio_chip_find(pin);
         unsigned long flags;
 
-        spin_lock_irqsave(&gpio_lock, flags);
+        if (ochip == NULL)
+                return;
 
-        /* Set output value to zero. */
-        __set_level(pin, 0);
-
-        /* Set blinking. */
-        __set_blinking(pin, blink);
-
-        spin_unlock_irqrestore(&gpio_lock, flags);
+        spin_lock_irqsave(&ochip->lock, flags);
+        __set_level(ochip, pin, 0);
+        __set_blinking(ochip, pin, blink);
+        spin_unlock_irqrestore(&ochip->lock, flags);
 }
 EXPORT_SYMBOL(orion_gpio_set_blink);
 
@@ -234,59 +323,78 @@ EXPORT_SYMBOL(orion_gpio_set_blink);
  ****************************************************************************/
 static void gpio_irq_ack(struct irq_data *d)
 {
-        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        int type;
+
+        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                int pin = irq_to_gpio(d->irq);
-                writel(~(1 << (pin & 31)), GPIO_EDGE_CAUSE(pin));
+                int pin = d->irq - ochip->secondary_irq_base;
+
+                writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
         }
 }
 
 static void gpio_irq_mask(struct irq_data *d)
 {
-        int pin = irq_to_gpio(d->irq);
-        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
-        u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
-                GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
-        u32 u = readl(reg);
-        u &= ~(1 << (pin & 31));
-        writel(u, reg);
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        int type;
+        void __iomem *reg;
+        int pin;
+
+        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+                reg = GPIO_EDGE_MASK(ochip);
+        else
+                reg = GPIO_LEVEL_MASK(ochip);
+
+        pin = d->irq - ochip->secondary_irq_base;
+
+        writel(readl(reg) & ~(1 << pin), reg);
 }
 
 static void gpio_irq_unmask(struct irq_data *d)
 {
-        int pin = irq_to_gpio(d->irq);
-        int type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
-        u32 reg = (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) ?
-                GPIO_EDGE_MASK(pin) : GPIO_LEVEL_MASK(pin);
-        u32 u = readl(reg);
-        u |= 1 << (pin & 31);
-        writel(u, reg);
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        int type;
+        void __iomem *reg;
+        int pin;
+
+        type = irq_desc[d->irq].status & IRQ_TYPE_SENSE_MASK;
+        if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+                reg = GPIO_EDGE_MASK(ochip);
+        else
+                reg = GPIO_LEVEL_MASK(ochip);
+
+        pin = d->irq - ochip->secondary_irq_base;
+
+        writel(readl(reg) | (1 << pin), reg);
 }
 
 static int gpio_irq_set_type(struct irq_data *d, u32 type)
 {
-        int pin = irq_to_gpio(d->irq);
-        struct irq_desc *desc;
+        struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+        int pin;
         u32 u;
 
-        u = readl(GPIO_IO_CONF(pin)) & (1 << (pin & 31));
+        pin = d->irq - ochip->secondary_irq_base;
+
+        u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
         if (!u) {
                 printk(KERN_ERR "orion gpio_irq_set_type failed "
                                 "(irq %d, pin %d).\n", d->irq, pin);
                 return -EINVAL;
         }
 
-        desc = irq_desc + d->irq;
-
         /*
          * Set edge/level type.
          */
         if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
-                desc->handle_irq = handle_edge_irq;
+                set_irq_handler(d->irq, handle_edge_irq);
         } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
-                desc->handle_irq = handle_level_irq;
+                set_irq_handler(d->irq, handle_level_irq);
         } else {
-                printk(KERN_ERR "failed to set irq=%d (type=%d)\n", d->irq, type);
+                printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
+                       d->irq, type);
                 return -EINVAL;
         }
 
@@ -294,31 +402,29 @@ static int gpio_irq_set_type(struct irq_data *d, u32 type)
          * Configure interrupt polarity.
          */
         if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH) {
-                u = readl(GPIO_IN_POL(pin));
-                u &= ~(1 << (pin & 31));
-                writel(u, GPIO_IN_POL(pin));
+                u = readl(GPIO_IN_POL(ochip));
+                u &= ~(1 << pin);
+                writel(u, GPIO_IN_POL(ochip));
         } else if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW) {
-                u = readl(GPIO_IN_POL(pin));
-                u |= 1 << (pin & 31);
-                writel(u, GPIO_IN_POL(pin));
+                u = readl(GPIO_IN_POL(ochip));
+                u |= 1 << pin;
+                writel(u, GPIO_IN_POL(ochip));
         } else if (type == IRQ_TYPE_EDGE_BOTH) {
                 u32 v;
 
-                v = readl(GPIO_IN_POL(pin)) ^ readl(GPIO_DATA_IN(pin));
+                v = readl(GPIO_IN_POL(ochip)) ^ readl(GPIO_DATA_IN(ochip));
 
                 /*
                  * set initial polarity based on current input level
                  */
-                u = readl(GPIO_IN_POL(pin));
-                if (v & (1 << (pin & 31)))
-                        u |= 1 << (pin & 31);           /* falling */
+                u = readl(GPIO_IN_POL(ochip));
+                if (v & (1 << pin))
+                        u |= 1 << pin;          /* falling */
                 else
-                        u &= ~(1 << (pin & 31));        /* rising */
-                writel(u, GPIO_IN_POL(pin));
+                        u &= ~(1 << pin);       /* rising */
+                writel(u, GPIO_IN_POL(ochip));
         }
 
-        desc->status = (desc->status & ~IRQ_TYPE_SENSE_MASK) | type;
-
         return 0;
 }
 
@@ -330,29 +436,87 @@ struct irq_chip orion_gpio_irq_chip = {
         .irq_set_type   = gpio_irq_set_type,
 };
 
+void __init orion_gpio_init(int gpio_base, int ngpio,
+                            u32 base, int mask_offset, int secondary_irq_base)
+{
+        struct orion_gpio_chip *ochip;
+        int i;
+
+        if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
+                return;
+
+        ochip = orion_gpio_chips + orion_gpio_chip_count;
+        ochip->chip.label = "orion_gpio";
+        ochip->chip.request = orion_gpio_request;
+        ochip->chip.direction_input = orion_gpio_direction_input;
+        ochip->chip.get = orion_gpio_get;
+        ochip->chip.direction_output = orion_gpio_direction_output;
+        ochip->chip.set = orion_gpio_set;
+        ochip->chip.to_irq = orion_gpio_to_irq;
+        ochip->chip.base = gpio_base;
+        ochip->chip.ngpio = ngpio;
+        ochip->chip.can_sleep = 0;
+        spin_lock_init(&ochip->lock);
+        ochip->base = (void __iomem *)base;
+        ochip->valid_input = 0;
+        ochip->valid_output = 0;
+        ochip->mask_offset = mask_offset;
+        ochip->secondary_irq_base = secondary_irq_base;
+
+        gpiochip_add(&ochip->chip);
+
+        orion_gpio_chip_count++;
+
+        /*
+         * Mask and clear GPIO interrupts.
+         */
+        writel(0, GPIO_EDGE_CAUSE(ochip));
+        writel(0, GPIO_EDGE_MASK(ochip));
+        writel(0, GPIO_LEVEL_MASK(ochip));
+
+        for (i = 0; i < ngpio; i++) {
+                unsigned int irq = secondary_irq_base + i;
+
+                set_irq_chip(irq, &orion_gpio_irq_chip);
+                set_irq_handler(irq, handle_level_irq);
+                set_irq_chip_data(irq, ochip);
+                irq_desc[irq].status |= IRQ_LEVEL;
+                set_irq_flags(irq, IRQF_VALID);
+        }
+}
+
 void orion_gpio_irq_handler(int pinoff)
 {
+        struct orion_gpio_chip *ochip;
         u32 cause;
-        int pin;
+        int i;
 
-        cause = readl(GPIO_DATA_IN(pinoff)) & readl(GPIO_LEVEL_MASK(pinoff));
-        cause |= readl(GPIO_EDGE_CAUSE(pinoff)) & readl(GPIO_EDGE_MASK(pinoff));
+        ochip = orion_gpio_chip_find(pinoff);
+        if (ochip == NULL)
+                return;
 
-        for (pin = pinoff; pin < pinoff + 8; pin++) {
-                int irq = gpio_to_irq(pin);
-                struct irq_desc *desc = irq_desc + irq;
+        cause = readl(GPIO_DATA_IN(ochip)) & readl(GPIO_LEVEL_MASK(ochip));
+        cause |= readl(GPIO_EDGE_CAUSE(ochip)) & readl(GPIO_EDGE_MASK(ochip));
 
-                if (!(cause & (1 << (pin & 31))))
+        for (i = 0; i < ochip->chip.ngpio; i++) {
+                int irq;
+                struct irq_desc *desc;
+
+                irq = ochip->secondary_irq_base + i;
+
+                if (!(cause & (1 << i)))
                         continue;
 
+                desc = irq_desc + irq;
                 if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
                         /* Swap polarity (race with GPIO line) */
                         u32 polarity;
 
-                        polarity = readl(GPIO_IN_POL(pin));
-                        polarity ^= 1 << (pin & 31);
-                        writel(polarity, GPIO_IN_POL(pin));
+                        polarity = readl(GPIO_IN_POL(ochip));
+                        polarity ^= 1 << i;
+                        writel(polarity, GPIO_IN_POL(ochip));
                 }
+
                 desc_handle_irq(irq, desc);
         }
 }
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 07c430fdc9e..5578b9803fc 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -12,6 +12,7 @@
 #define __PLAT_GPIO_H
 
 #include <linux/init.h>
+#include <asm-generic/gpio.h>
 
 /*
  * GENERIC_GPIO primitives.
@@ -19,6 +20,7 @@
 #define gpio_get_value  __gpio_get_value
 #define gpio_set_value  __gpio_set_value
 #define gpio_cansleep   __gpio_cansleep
+#define gpio_to_irq     __gpio_to_irq
 
 /*
  * Orion-specific GPIO API extensions.
@@ -31,7 +33,8 @@ void orion_gpio_set_blink(unsigned pin, int blink);
 void orion_gpio_set_valid(unsigned pin, int mode);
 
 /* Initialize gpiolib. */
-void __init orion_gpio_init(void);
+void __init orion_gpio_init(int gpio_base, int ngpio,
+                            u32 base, int mask_offset, int secondary_irq_base);
 
 /*
  * GPIO interrupt handling.
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index c06ca35f361..4d5f1f6e18d 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,7 +11,10 @@
 #ifndef __PLAT_TIME_H
 #define __PLAT_TIME_H
 
-void orion_time_init(unsigned int irq, unsigned int tclk);
+void orion_time_set_base(u32 timer_base);
+
+void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+                     unsigned int irq, unsigned int tclk);
 
 
 #endif
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index c3da2478b2a..742b0323c57 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -18,28 +18,42 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <asm/sched_clock.h>
-#include <asm/mach/time.h>
-#include <mach/bridge-regs.h>
-#include <mach/hardware.h>
 
 /*
- * Number of timer ticks per jiffy.
+ * MBus bridge block registers.
  */
-static u32 ticks_per_jiffy;
+#define BRIDGE_CAUSE_OFF        0x0110
+#define BRIDGE_MASK_OFF         0x0114
+#define  BRIDGE_INT_TIMER0       0x0002
+#define  BRIDGE_INT_TIMER1       0x0004
 
 
 /*
  * Timer block registers.
  */
-#define TIMER_CTRL              (TIMER_VIRT_BASE + 0x0000)
-#define  TIMER0_EN              0x0001
-#define  TIMER0_RELOAD_EN       0x0002
-#define  TIMER1_EN              0x0004
-#define  TIMER1_RELOAD_EN       0x0008
-#define TIMER0_RELOAD           (TIMER_VIRT_BASE + 0x0010)
-#define TIMER0_VAL              (TIMER_VIRT_BASE + 0x0014)
-#define TIMER1_RELOAD           (TIMER_VIRT_BASE + 0x0018)
-#define TIMER1_VAL              (TIMER_VIRT_BASE + 0x001c)
+#define TIMER_CTRL_OFF          0x0000
+#define  TIMER0_EN               0x0001
+#define  TIMER0_RELOAD_EN        0x0002
+#define  TIMER1_EN               0x0004
+#define  TIMER1_RELOAD_EN        0x0008
+#define TIMER0_RELOAD_OFF       0x0010
+#define TIMER0_VAL_OFF          0x0014
+#define TIMER1_RELOAD_OFF       0x0018
+#define TIMER1_VAL_OFF          0x001c
+
+
+/*
+ * SoC-specific data.
+ */
+static void __iomem *bridge_base;
+static u32 bridge_timer1_clr_mask;
+static void __iomem *timer_base;
+
+
+/*
+ * Number of timer ticks per jiffy.
+ */
+static u32 ticks_per_jiffy;
 
 
 /*
@@ -50,14 +64,14 @@ static DEFINE_CLOCK_DATA(cd);
 
 unsigned long long notrace sched_clock(void)
 {
-        u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+        u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
         return cyc_to_sched_clock(&cd, cyc, (u32)~0);
 }
 
 
 static void notrace orion_update_sched_clock(void)
 {
-        u32 cyc = 0xffffffff - readl(TIMER0_VAL);
+        u32 cyc = ~readl(timer_base + TIMER0_VAL_OFF);
         update_sched_clock(&cd, cyc, (u32)~0);
 }
 
@@ -71,7 +85,7 @@ static void __init setup_sched_clock(unsigned long tclk)
  */
 static cycle_t orion_clksrc_read(struct clocksource *cs)
 {
-        return 0xffffffff - readl(TIMER0_VAL);
+        return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
 }
 
 static struct clocksource orion_clksrc = {
@@ -101,23 +115,23 @@ orion_clkevt_next_event(unsigned long delta, struct clock_event_device *dev)
         /*
          * Clear and enable clockevent timer interrupt.
          */
-        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+        writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 
-        u = readl(BRIDGE_MASK);
+        u = readl(bridge_base + BRIDGE_MASK_OFF);
         u |= BRIDGE_INT_TIMER1;
-        writel(u, BRIDGE_MASK);
+        writel(u, bridge_base + BRIDGE_MASK_OFF);
 
         /*
          * Setup new clockevent timer value.
          */
-        writel(delta, TIMER1_VAL);
+        writel(delta, timer_base + TIMER1_VAL_OFF);
 
         /*
          * Enable the timer.
          */
-        u = readl(TIMER_CTRL);
+        u = readl(timer_base + TIMER_CTRL_OFF);
         u = (u & ~TIMER1_RELOAD_EN) | TIMER1_EN;
-        writel(u, TIMER_CTRL);
+        writel(u, timer_base + TIMER_CTRL_OFF);
 
         local_irq_restore(flags);
 
@@ -135,37 +149,38 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
                 /*
                  * Setup timer to fire at 1/HZ intervals.
                  */
-                writel(ticks_per_jiffy - 1, TIMER1_RELOAD);
-                writel(ticks_per_jiffy - 1, TIMER1_VAL);
+                writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD_OFF);
+                writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL_OFF);
 
                 /*
                  * Enable timer interrupt.
                  */
-                u = readl(BRIDGE_MASK);
-                writel(u | BRIDGE_INT_TIMER1, BRIDGE_MASK);
+                u = readl(bridge_base + BRIDGE_MASK_OFF);
+                writel(u | BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
 
                 /*
                  * Enable timer.
                  */
-                u = readl(TIMER_CTRL);
-                writel(u | TIMER1_EN | TIMER1_RELOAD_EN, TIMER_CTRL);
+                u = readl(timer_base + TIMER_CTRL_OFF);
+                writel(u | TIMER1_EN | TIMER1_RELOAD_EN,
+                       timer_base + TIMER_CTRL_OFF);
         } else {
                 /*
                  * Disable timer.
                  */
-                u = readl(TIMER_CTRL);
-                writel(u & ~TIMER1_EN, TIMER_CTRL);
+                u = readl(timer_base + TIMER_CTRL_OFF);
+                writel(u & ~TIMER1_EN, timer_base + TIMER_CTRL_OFF);
 
                 /*
                  * Disable timer interrupt.
                  */
-                u = readl(BRIDGE_MASK);
-                writel(u & ~BRIDGE_INT_TIMER1, BRIDGE_MASK);
+                u = readl(bridge_base + BRIDGE_MASK_OFF);
+                writel(u & ~BRIDGE_INT_TIMER1, bridge_base + BRIDGE_MASK_OFF);
 
                 /*
                  * ACK pending timer interrupt.
                  */
-                writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+                writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
 
         }
         local_irq_restore(flags);
@@ -185,7 +200,7 @@ static irqreturn_t orion_timer_interrupt(int irq, void *dev_id)
         /*
          * ACK timer interrupt and call event handler.
          */
-        writel(BRIDGE_INT_TIMER1_CLR, BRIDGE_CAUSE);
+        writel(bridge_timer1_clr_mask, bridge_base + BRIDGE_CAUSE_OFF);
         orion_clkevt.event_handler(&orion_clkevt);
 
         return IRQ_HANDLED;
@@ -197,31 +212,45 @@ static struct irqaction orion_timer_irq = {
         .handler        = orion_timer_interrupt
 };
 
-void __init orion_time_init(unsigned int irq, unsigned int tclk)
+void __init
+orion_time_set_base(u32 _timer_base)
+{
+        timer_base = (void __iomem *)_timer_base;
+}
+
+void __init
+orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+                unsigned int irq, unsigned int tclk)
 {
         u32 u;
 
+        /*
+         * Set SoC-specific data.
+         */
+        bridge_base = (void __iomem *)_bridge_base;
+        bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
+
         ticks_per_jiffy = (tclk + HZ/2) / HZ;
 
         /*
-         * Set scale and timer for sched_clock
+         * Set scale and timer for sched_clock.
          */
         setup_sched_clock(tclk);
 
         /*
          * Setup free-running clocksource timer (interrupts
-         * disabled.)
+         * disabled).
          */
-        writel(0xffffffff, TIMER0_VAL);
-        writel(0xffffffff, TIMER0_RELOAD);
-        u = readl(BRIDGE_MASK);
-        writel(u & ~BRIDGE_INT_TIMER0, BRIDGE_MASK);
-        u = readl(TIMER_CTRL);
-        writel(u | TIMER0_EN | TIMER0_RELOAD_EN, TIMER_CTRL);
+        writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
+        writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
+        u = readl(bridge_base + BRIDGE_MASK_OFF);
+        writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
+        u = readl(timer_base + TIMER_CTRL_OFF);
+        writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
         clocksource_register_hz(&orion_clksrc, tclk);
 
         /*
-         * Setup clockevent timer (interrupt-driven.)
+         * Setup clockevent timer (interrupt-driven).
          */
         setup_irq(irq, &orion_timer_irq);
         orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
diff --git a/arch/arm/plat-s5p/dev-uart.c b/arch/arm/plat-s5p/dev-uart.c
index 6a734288617..afaf87fdb93 100644
--- a/arch/arm/plat-s5p/dev-uart.c
+++ b/arch/arm/plat-s5p/dev-uart.c
@@ -28,7 +28,7 @@
 static struct resource s5p_uart0_resource[] = {
         [0] = {
                 .start  = S5P_PA_UART0,
-                .end    = S5P_PA_UART0 + S5P_SZ_UART,
+                .end    = S5P_PA_UART0 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -51,7 +51,7 @@ static struct resource s5p_uart0_resource[] = {
 static struct resource s5p_uart1_resource[] = {
         [0] = {
                 .start  = S5P_PA_UART1,
-                .end    = S5P_PA_UART1 + S5P_SZ_UART,
+                .end    = S5P_PA_UART1 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -74,7 +74,7 @@ static struct resource s5p_uart1_resource[] = {
 static struct resource s5p_uart2_resource[] = {
         [0] = {
                 .start  = S5P_PA_UART2,
-                .end    = S5P_PA_UART2 + S5P_SZ_UART,
+                .end    = S5P_PA_UART2 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -98,7 +98,7 @@ static struct resource s5p_uart3_resource[] = {
 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
         [0] = {
                 .start  = S5P_PA_UART3,
-                .end    = S5P_PA_UART3 + S5P_SZ_UART,
+                .end    = S5P_PA_UART3 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -123,7 +123,7 @@ static struct resource s5p_uart4_resource[] = {
 #if CONFIG_SERIAL_SAMSUNG_UARTS > 4
         [0] = {
                 .start  = S5P_PA_UART4,
-                .end    = S5P_PA_UART4 + S5P_SZ_UART,
+                .end    = S5P_PA_UART4 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
@@ -148,7 +148,7 @@ static struct resource s5p_uart5_resource[] = {
 #if CONFIG_SERIAL_SAMSUNG_UARTS > 5
         [0] = {
                 .start  = S5P_PA_UART5,
-                .end    = S5P_PA_UART5 + S5P_SZ_UART,
+                .end    = S5P_PA_UART5 + S5P_SZ_UART - 1,
                 .flags  = IORESOURCE_MEM,
         },
         [1] = {
diff --git a/arch/arm/plat-samsung/dev-ts.c b/arch/arm/plat-samsung/dev-ts.c
index 236ef8427d7..3e4bd8147bf 100644
--- a/arch/arm/plat-samsung/dev-ts.c
+++ b/arch/arm/plat-samsung/dev-ts.c
@@ -58,4 +58,3 @@ void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
 
         s3c_device_ts.dev.platform_data = npd;
 }
-EXPORT_SYMBOL(s3c24xx_ts_set_platdata);
diff --git a/arch/arm/plat-spear/include/plat/uncompress.h b/arch/arm/plat-spear/include/plat/uncompress.h
index 99ba6789cc9..6dd455bafdf 100644
--- a/arch/arm/plat-spear/include/plat/uncompress.h
+++ b/arch/arm/plat-spear/include/plat/uncompress.h
@@ -24,10 +24,10 @@ static inline void putc(int c)
 {
         void __iomem *base = (void __iomem *)SPEAR_DBG_UART_BASE;
 
-        while (readl(base + UART01x_FR) & UART01x_FR_TXFF)
+        while (readl_relaxed(base + UART01x_FR) & UART01x_FR_TXFF)
                 barrier();
 
-        writel(c, base + UART01x_DR);
+        writel_relaxed(c, base + UART01x_DR);
 }
 
 static inline void flush(void)
diff --git a/arch/arm/plat-spear/include/plat/vmalloc.h b/arch/arm/plat-spear/include/plat/vmalloc.h
index 09e9372aea2..8c8b24d0704 100644
--- a/arch/arm/plat-spear/include/plat/vmalloc.h
+++ b/arch/arm/plat-spear/include/plat/vmalloc.h
@@ -14,6 +14,6 @@
 #ifndef __PLAT_VMALLOC_H
 #define __PLAT_VMALLOC_H
 
-#define VMALLOC_END             0xF0000000
+#define VMALLOC_END             0xF0000000UL
 
 #endif /* __PLAT_VMALLOC_H */
diff --git a/arch/s390/boot/compressed/misc.c b/arch/s390/boot/compressed/misc.c
index 0851eb1e919..2751b3a8a66 100644
--- a/arch/s390/boot/compressed/misc.c
+++ b/arch/s390/boot/compressed/misc.c
@@ -133,11 +133,12 @@ unsigned long decompress_kernel(void)
         unsigned long output_addr;
         unsigned char *output;
 
-        check_ipl_parmblock((void *) 0, (unsigned long) output + SZ__bss_start);
+        output_addr = ((unsigned long) &_end + HEAP_SIZE + 4095UL) & -4096UL;
+        check_ipl_parmblock((void *) 0, output_addr + SZ__bss_start);
         memset(&_bss, 0, &_ebss - &_bss);
         free_mem_ptr = (unsigned long)&_end;
         free_mem_end_ptr = free_mem_ptr + HEAP_SIZE;
-        output = (unsigned char *) ((free_mem_end_ptr + 4095UL) & -4096UL);
+        output = (unsigned char *) output_addr;
 
 #ifdef CONFIG_BLK_DEV_INITRD
         /*
diff --git a/arch/s390/include/asm/atomic.h b/arch/s390/include/asm/atomic.h
index 76daea11718..5c5ba10384c 100644
--- a/arch/s390/include/asm/atomic.h
+++ b/arch/s390/include/asm/atomic.h
@@ -36,14 +36,19 @@
 
 static inline int atomic_read(const atomic_t *v)
 {
-        barrier();
-        return v->counter;
+        int c;
+
+        asm volatile(
+                "       l       %0,%1\n"
+                : "=d" (c) : "Q" (v->counter));
+        return c;
 }
 
 static inline void atomic_set(atomic_t *v, int i)
 {
-        v->counter = i;
-        barrier();
+        asm volatile(
+                "       st      %1,%0\n"
+                : "=Q" (v->counter) : "d" (i));
 }
 
 static inline int atomic_add_return(int i, atomic_t *v)
@@ -128,14 +133,19 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
 
 static inline long long atomic64_read(const atomic64_t *v)
 {
-        barrier();
-        return v->counter;
+        long long c;
+
+        asm volatile(
+                "       lg      %0,%1\n"
+                : "=d" (c) : "Q" (v->counter));
+        return c;
 }
 
 static inline void atomic64_set(atomic64_t *v, long long i)
 {
-        v->counter = i;
-        barrier();
+        asm volatile(
+                "       stg     %1,%0\n"
+                : "=Q" (v->counter) : "d" (i));
 }
 
 static inline long long atomic64_add_return(long long i, atomic64_t *v)
diff --git a/arch/s390/include/asm/cache.h b/arch/s390/include/asm/cache.h
index 24aafa68b64..2a30d5ac066 100644
--- a/arch/s390/include/asm/cache.h
+++ b/arch/s390/include/asm/cache.h
@@ -13,6 +13,7 @@
 
 #define L1_CACHE_BYTES     256
 #define L1_CACHE_SHIFT     8
+#define NET_SKB_PAD        32
 
 #define __read_mostly __attribute__((__section__(".data..read_mostly")))
 
diff --git a/drivers/char/tpm/tpm.c b/drivers/char/tpm/tpm.c
index faf5a2c6592..36e0fa161c2 100644
--- a/drivers/char/tpm/tpm.c
+++ b/drivers/char/tpm/tpm.c
@@ -577,11 +577,9 @@ duration:
         if (rc)
                 return;
 
-        if (be32_to_cpu(tpm_cmd.header.out.return_code) != 0 ||
-            be32_to_cpu(tpm_cmd.header.out.length)
-            != sizeof(tpm_cmd.header.out) + sizeof(u32) + 3 * sizeof(u32))
+        if (be32_to_cpu(tpm_cmd.header.out.return_code)
+            != 3 * sizeof(u32))
                 return;
-
         duration_cap = &tpm_cmd.params.getcap_out.cap.duration;
         chip->vendor.duration[TPM_SHORT] =
             usecs_to_jiffies(be32_to_cpu(duration_cap->tpm_short));
@@ -941,18 +939,6 @@ ssize_t tpm_show_caps_1_2(struct device * dev,
 }
 EXPORT_SYMBOL_GPL(tpm_show_caps_1_2);
 
-ssize_t tpm_show_timeouts(struct device *dev, struct device_attribute *attr,
-                          char *buf)
-{
-        struct tpm_chip *chip = dev_get_drvdata(dev);
-
-        return sprintf(buf, "%d %d %d\n",
-                       jiffies_to_usecs(chip->vendor.duration[TPM_SHORT]),
-                       jiffies_to_usecs(chip->vendor.duration[TPM_MEDIUM]),
-                       jiffies_to_usecs(chip->vendor.duration[TPM_LONG]));
-}
-EXPORT_SYMBOL_GPL(tpm_show_timeouts);
-
 ssize_t tpm_store_cancel(struct device *dev, struct device_attribute *attr,
                         const char *buf, size_t count)
 {
diff --git a/drivers/char/tpm/tpm.h b/drivers/char/tpm/tpm.h
index d84ff772c26..72ddb031b69 100644
--- a/drivers/char/tpm/tpm.h
+++ b/drivers/char/tpm/tpm.h
@@ -56,8 +56,6 @@ extern ssize_t tpm_show_owned(struct device *, struct device_attribute *attr,
                                 char *);
 extern ssize_t tpm_show_temp_deactivated(struct device *,
                                          struct device_attribute *attr, char *);
-extern ssize_t tpm_show_timeouts(struct device *,
-                                 struct device_attribute *attr, char *);
 
 struct tpm_chip;
 
diff --git a/drivers/char/tpm/tpm_tis.c b/drivers/char/tpm/tpm_tis.c
index 0d1d38e5f26..dd21df55689 100644
--- a/drivers/char/tpm/tpm_tis.c
+++ b/drivers/char/tpm/tpm_tis.c
@@ -376,7 +376,6 @@ static DEVICE_ATTR(temp_deactivated, S_IRUGO, tpm_show_temp_deactivated,
                    NULL);
 static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps_1_2, NULL);
 static DEVICE_ATTR(cancel, S_IWUSR | S_IWGRP, NULL, tpm_store_cancel);
-static DEVICE_ATTR(timeouts, S_IRUGO, tpm_show_timeouts, NULL);
 
 static struct attribute *tis_attrs[] = {
         &dev_attr_pubek.attr,
@@ -386,8 +385,7 @@ static struct attribute *tis_attrs[] = {
         &dev_attr_owned.attr,
         &dev_attr_temp_deactivated.attr,
         &dev_attr_caps.attr,
-        &dev_attr_cancel.attr,
-        &dev_attr_timeouts.attr, NULL,
+        &dev_attr_cancel.attr, NULL,
 };
 
 static struct attribute_group tis_attr_grp = {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 15d94c63918..729d4233b76 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1553,17 +1553,7 @@
 
 /* Backlight control */
 #define BLC_PWM_CTL             0x61254
-#define   BACKLIGHT_MODULATION_FREQ_SHIFT               (17)
 #define BLC_PWM_CTL2            0x61250 /* 965+ only */
-#define   BLM_COMBINATION_MODE (1 << 30)
-/*
- * This is the most significant 15 bits of the number of backlight cycles in a
- * complete cycle of the modulated backlight control.
- *
- * The actual value is this field multiplied by two.
- */
-#define   BACKLIGHT_MODULATION_FREQ_MASK                (0x7fff << 17)
-#define   BLM_LEGACY_MODE                               (1 << 16)
 /*
  * This is the number of cycles out of the backlight modulation cycle for which
  * the backlight is on.
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index c65992df458..d860abeda70 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -30,8 +30,6 @@
 
 #include "intel_drv.h"
 
-#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
-
 void
 intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
                        struct drm_display_mode *adjusted_mode)
@@ -112,19 +110,6 @@ done:
         dev_priv->pch_pf_size = (width << 16) | height;
 }
 
-static int is_backlight_combination_mode(struct drm_device *dev)
-{
-        struct drm_i915_private *dev_priv = dev->dev_private;
-
-        if (INTEL_INFO(dev)->gen >= 4)
-                return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
-
-        if (IS_GEN2(dev))
-                return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
-
-        return 0;
-}
-
 static u32 i915_read_blc_pwm_ctl(struct drm_i915_private *dev_priv)
 {
         u32 val;
@@ -181,9 +166,6 @@ u32 intel_panel_get_max_backlight(struct drm_device *dev)
                         if (INTEL_INFO(dev)->gen < 4)
                                 max &= ~1;
                 }
-
-                if (is_backlight_combination_mode(dev))
-                        max *= 0xff;
         }
 
         DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
@@ -201,15 +183,6 @@ u32 intel_panel_get_backlight(struct drm_device *dev)
                 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
                 if (IS_PINEVIEW(dev))
                         val >>= 1;
-
-                if (is_backlight_combination_mode(dev)){
-                        u8 lbpc;
-
-                        val &= ~1;
-                        pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
-                        val *= lbpc;
-                        val >>= 1;
-                }
         }
 
         DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
@@ -232,16 +205,6 @@ void intel_panel_set_backlight(struct drm_device *dev, u32 level)
 
         if (HAS_PCH_SPLIT(dev))
                 return intel_pch_panel_set_backlight(dev, level);
-
-        if (is_backlight_combination_mode(dev)){
-                u32 max = intel_panel_get_max_backlight(dev);
-                u8 lpbc;
-
-                lpbc = level * 0xfe / max + 1;
-                level /= lpbc;
-                pci_write_config_byte(dev->pdev, PCI_LBPC, lpbc);
-        }
-
         tmp = I915_READ(BLC_PWM_CTL);
         if (IS_PINEVIEW(dev)) {
                 tmp &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 773e484f164..297bc9a7d6e 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -238,13 +238,13 @@ config SENSORS_K8TEMP
           will be called k8temp.
 
 config SENSORS_K10TEMP
-        tristate "AMD Phenom/Sempron/Turion/Opteron temperature sensor"
+        tristate "AMD Family 10h/11h/12h/14h temperature sensor"
         depends on X86 && PCI
         help
           If you say yes here you get support for the temperature
           sensor(s) inside your CPU. Supported are later revisions of
-          the AMD Family 10h and all revisions of the AMD Family 11h
-          microarchitectures.
+          the AMD Family 10h and all revisions of the AMD Family 11h,
+          12h (Llano), and 14h (Brazos) microarchitectures.
 
           This driver can also be built as a module.  If so, the module
           will be called k10temp.
@@ -455,13 +455,14 @@ config SENSORS_JZ4740
           called jz4740-hwmon.
 
 config SENSORS_JC42
-        tristate "JEDEC JC42.4 compliant temperature sensors"
+        tristate "JEDEC JC42.4 compliant memory module temperature sensors"
         depends on I2C
         help
-          If you say yes here you get support for Jedec JC42.4 compliant
-          temperature sensors. Support will include, but not be limited to,
-          ADT7408, CAT34TS02,, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243,
-          MCP9843, SE97, SE98, STTS424, TSE2002B3, and TS3000B3.
+          If you say yes here, you get support for JEDEC JC42.4 compliant
+          temperature sensors, which are used on many DDR3 memory modules for
+          mobile devices and servers.  Support will include, but not be limited
+          to, ADT7408, CAT34TS02, CAT6095, MAX6604, MCP9805, MCP98242, MCP98243,
+          MCP9843, SE97, SE98, STTS424(E), TSE2002B3, and TS3000B3.
 
           This driver can also be built as a module.  If so, the module
           will be called jc42.
@@ -574,7 +575,7 @@ config SENSORS_LM85
         help
           If you say yes here you get support for National Semiconductor LM85
           sensor chips and clones: ADM1027, ADT7463, ADT7468, EMC6D100,
-          EMC6D101 and EMC6D102.
+          EMC6D101, EMC6D102, and EMC6D103.
 
           This driver can also be built as a module.  If so, the module
           will be called lm85.
diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c
index 340fc78c8dd..93499123706 100644
--- a/drivers/hwmon/jc42.c
+++ b/drivers/hwmon/jc42.c
@@ -53,6 +53,8 @@ static const unsigned short normal_i2c[] = {
 
 /* Configuration register defines */
 #define JC42_CFG_CRIT_ONLY      (1 << 2)
+#define JC42_CFG_TCRIT_LOCK     (1 << 6)
+#define JC42_CFG_EVENT_LOCK     (1 << 7)
 #define JC42_CFG_SHUTDOWN       (1 << 8)
 #define JC42_CFG_HYST_SHIFT     9
 #define JC42_CFG_HYST_MASK      0x03
@@ -332,7 +334,7 @@ static ssize_t set_temp_crit_hyst(struct device *dev,
 {
         struct i2c_client *client = to_i2c_client(dev);
         struct jc42_data *data = i2c_get_clientdata(client);
-        long val;
+        unsigned long val;
         int diff, hyst;
         int err;
         int ret = count;
@@ -380,14 +382,14 @@ static ssize_t show_alarm(struct device *dev,
 
 static DEVICE_ATTR(temp1_input, S_IRUGO,
                    show_temp_input, NULL);
-static DEVICE_ATTR(temp1_crit, S_IWUSR | S_IRUGO,
+static DEVICE_ATTR(temp1_crit, S_IRUGO,
                    show_temp_crit, set_temp_crit);
-static DEVICE_ATTR(temp1_min, S_IWUSR | S_IRUGO,
+static DEVICE_ATTR(temp1_min, S_IRUGO,
                    show_temp_min, set_temp_min);
-static DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO,
+static DEVICE_ATTR(temp1_max, S_IRUGO,
                    show_temp_max, set_temp_max);
 
-static DEVICE_ATTR(temp1_crit_hyst, S_IWUSR | S_IRUGO,
+static DEVICE_ATTR(temp1_crit_hyst, S_IRUGO,
                    show_temp_crit_hyst, set_temp_crit_hyst);
 static DEVICE_ATTR(temp1_max_hyst, S_IRUGO,
                    show_temp_max_hyst, NULL);
@@ -412,8 +414,31 @@ static struct attribute *jc42_attributes[] = {
         NULL
 };
 
+static mode_t jc42_attribute_mode(struct kobject *kobj,
+                                  struct attribute *attr, int index)
+{
+        struct device *dev = container_of(kobj, struct device, kobj);
+        struct i2c_client *client = to_i2c_client(dev);
+        struct jc42_data *data = i2c_get_clientdata(client);
+        unsigned int config = data->config;
+        bool readonly;
+
+        if (attr == &dev_attr_temp1_crit.attr)
+                readonly = config & JC42_CFG_TCRIT_LOCK;
+        else if (attr == &dev_attr_temp1_min.attr ||
+                 attr == &dev_attr_temp1_max.attr)
+                readonly = config & JC42_CFG_EVENT_LOCK;
+        else if (attr == &dev_attr_temp1_crit_hyst.attr)
+                readonly = config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK);
+        else
+                readonly = true;
+
+        return S_IRUGO | (readonly ? 0 : S_IWUSR);
+}
+
 static const struct attribute_group jc42_group = {
         .attrs = jc42_attributes,
+        .is_visible = jc42_attribute_mode,
 };
 
 /* Return 0 if detection is successful, -ENODEV otherwise */
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index da5a2404cd3..82bf65aa296 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -1,5 +1,5 @@
 /*
- * k10temp.c - AMD Family 10h/11h processor hardware monitoring
+ * k10temp.c - AMD Family 10h/11h/12h/14h processor hardware monitoring
  *
  * Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
  *
@@ -25,7 +25,7 @@
 #include <linux/pci.h>
 #include <asm/processor.h>
 
-MODULE_DESCRIPTION("AMD Family 10h/11h CPU core temperature monitor");
+MODULE_DESCRIPTION("AMD Family 10h/11h/12h/14h CPU core temperature monitor");
 MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
 MODULE_LICENSE("GPL");
 
@@ -208,6 +208,7 @@ static void __devexit k10temp_remove(struct pci_dev *pdev)
 static const struct pci_device_id k10temp_id_table[] = {
         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
+        { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
         {}
 };
 MODULE_DEVICE_TABLE(pci, k10temp_id_table);
diff --git a/drivers/hwmon/lm85.c b/drivers/hwmon/lm85.c
index 1e229847f37..d2cc2866081 100644
--- a/drivers/hwmon/lm85.c
+++ b/drivers/hwmon/lm85.c
@@ -41,7 +41,7 @@ static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END };
 enum chips {
         any_chip, lm85b, lm85c,
         adm1027, adt7463, adt7468,
-        emc6d100, emc6d102
+        emc6d100, emc6d102, emc6d103
 };
 
 /* The LM85 registers */
@@ -90,6 +90,9 @@ enum chips {
 #define LM85_VERSTEP_EMC6D100_A0        0x60
 #define LM85_VERSTEP_EMC6D100_A1        0x61
 #define LM85_VERSTEP_EMC6D102           0x65
+#define LM85_VERSTEP_EMC6D103_A0        0x68
+#define LM85_VERSTEP_EMC6D103_A1        0x69
+#define LM85_VERSTEP_EMC6D103S          0x6A    /* Also known as EMC6D103:A2 */
 
 #define LM85_REG_CONFIG                 0x40
 
@@ -348,6 +351,7 @@ static const struct i2c_device_id lm85_id[] = {
         { "emc6d100", emc6d100 },
         { "emc6d101", emc6d100 },
         { "emc6d102", emc6d102 },
+        { "emc6d103", emc6d103 },
         { }
 };
 MODULE_DEVICE_TABLE(i2c, lm85_id);
@@ -1250,6 +1254,20 @@ static int lm85_detect(struct i2c_client *client, struct i2c_board_info *info)
                 case LM85_VERSTEP_EMC6D102:
                         type_name = "emc6d102";
                         break;
+                case LM85_VERSTEP_EMC6D103_A0:
+                case LM85_VERSTEP_EMC6D103_A1:
+                        type_name = "emc6d103";
+                        break;
+                /*
+                 * Registers apparently missing in EMC6D103S/EMC6D103:A2
+                 * compared to EMC6D103:A0, EMC6D103:A1, and EMC6D102
+                 * (according to the data sheets), but used unconditionally
+                 * in the driver: 62[5:7], 6D[0:7], and 6E[0:7].
+                 * So skip EMC6D103S for now.
+                case LM85_VERSTEP_EMC6D103S:
+                        type_name = "emc6d103s";
+                        break;
+                 */
                 }
         } else {
                 dev_dbg(&adapter->dev,
@@ -1283,6 +1301,7 @@ static int lm85_probe(struct i2c_client *client,
         case adt7468:
         case emc6d100:
         case emc6d102:
+        case emc6d103:
                 data->freq_map = adm1027_freq_map;
                 break;
         default:
@@ -1468,7 +1487,7 @@ static struct lm85_data *lm85_update_device(struct device *dev)
                         /* More alarm bits */
                         data->alarms |= lm85_read_value(client,
                                                 EMC6D100_REG_ALARM3) << 16;
-                } else if (data->type == emc6d102) {
+                } else if (data->type == emc6d102 || data->type == emc6d103) {
                         /* Have to read LSB bits after the MSB ones because
                            the reading of the MSB bits has frozen the
                            LSBs (backward from the ADM1027).
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index d163bc2e2b9..a59af5b24f0 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -227,7 +227,7 @@ config SONYPI_COMPAT
 config IDEAPAD_LAPTOP
         tristate "Lenovo IdeaPad Laptop Extras"
         depends on ACPI
-        depends on RFKILL
+        depends on RFKILL && INPUT
         select INPUT_SPARSEKMAP
         help
           This is a driver for the rfkill switches on Lenovo IdeaPad netbooks.
diff --git a/drivers/platform/x86/acer-wmi.c b/drivers/platform/x86/acer-wmi.c
index c5c4b8c32eb..38b34a73866 100644
--- a/drivers/platform/x86/acer-wmi.c
+++ b/drivers/platform/x86/acer-wmi.c
@@ -84,7 +84,7 @@ MODULE_LICENSE("GPL");
  */
 #define AMW0_GUID1              "67C3371D-95A3-4C37-BB61-DD47B491DAAB"
 #define AMW0_GUID2              "431F16ED-0C2B-444C-B267-27DEB140CF9C"
-#define WMID_GUID1              "6AF4F258-B401-42fd-BE91-3D4AC2D7C0D3"
+#define WMID_GUID1              "6AF4F258-B401-42FD-BE91-3D4AC2D7C0D3"
 #define WMID_GUID2              "95764E09-FB56-4e83-B31A-37761F60994A"
 #define WMID_GUID3              "61EF69EA-865C-4BC3-A502-A0DEBA0CB531"
 
@@ -1280,7 +1280,7 @@ static ssize_t set_bool_threeg(struct device *dev,
                         return -EINVAL;
         return count;
 }
-static DEVICE_ATTR(threeg, S_IWUGO | S_IRUGO | S_IWUSR, show_bool_threeg,
+static DEVICE_ATTR(threeg, S_IRUGO | S_IWUSR, show_bool_threeg,
         set_bool_threeg);
 
 static ssize_t show_interface(struct device *dev, struct device_attribute *attr,
diff --git a/drivers/platform/x86/asus_acpi.c b/drivers/platform/x86/asus_acpi.c
index 4633fd8532c..fe495939c30 100644
--- a/drivers/platform/x86/asus_acpi.c
+++ b/drivers/platform/x86/asus_acpi.c
@@ -1081,14 +1081,8 @@ static int asus_hotk_add_fs(struct acpi_device *device)
         struct proc_dir_entry *proc;
         mode_t mode;
 
-        /*
-         * If parameter uid or gid is not changed, keep the default setting for
-         * our proc entries (-rw-rw-rw-) else, it means we care about security,
-         * and then set to -rw-rw----
-         */
-
         if ((asus_uid == 0) && (asus_gid == 0)) {
-                mode = S_IFREG | S_IRUGO | S_IWUGO;
+                mode = S_IFREG | S_IRUGO | S_IWUSR | S_IWGRP;
         } else {
                 mode = S_IFREG | S_IRUSR | S_IRGRP | S_IWUSR | S_IWGRP;
                 printk(KERN_WARNING "  asus_uid and asus_gid parameters are "
diff --git a/drivers/platform/x86/dell-laptop.c b/drivers/platform/x86/dell-laptop.c
index 34657f96b5a..ad24ef36f9f 100644
--- a/drivers/platform/x86/dell-laptop.c
+++ b/drivers/platform/x86/dell-laptop.c
@@ -290,9 +290,12 @@ static int dell_rfkill_set(void *data, bool blocked)
         dell_send_request(buffer, 17, 11);
 
         /* If the hardware switch controls this radio, and the hardware
-           switch is disabled, don't allow changing the software state */
+           switch is disabled, don't allow changing the software state.
+           If the hardware switch is reported as not supported, always
+           fire the SMI to toggle the killswitch. */
         if ((hwswitch_state & BIT(hwswitch_bit)) &&
-            !(buffer->output[1] & BIT(16))) {
+            !(buffer->output[1] & BIT(16)) &&
+            (buffer->output[1] & BIT(0))) {
                 ret = -EINVAL;
                 goto out;
         }
@@ -398,6 +401,23 @@ static const struct file_operations dell_debugfs_fops = {
 
 static void dell_update_rfkill(struct work_struct *ignored)
 {
+        int status;
+
+        get_buffer();
+        dell_send_request(buffer, 17, 11);
+        status = buffer->output[1];
+        release_buffer();
+
+        /* if hardware rfkill is not supported, set it explicitly */
+        if (!(status & BIT(0))) {
+                if (wifi_rfkill)
+                        dell_rfkill_set((void *)1, !((status & BIT(17)) >> 17));
+                if (bluetooth_rfkill)
+                        dell_rfkill_set((void *)2, !((status & BIT(18)) >> 18));
+                if (wwan_rfkill)
+                        dell_rfkill_set((void *)3, !((status & BIT(19)) >> 19));
+        }
+
         if (wifi_rfkill)
                 dell_rfkill_query(wifi_rfkill, (void *)1);
         if (bluetooth_rfkill)
diff --git a/drivers/platform/x86/intel_pmic_gpio.c b/drivers/platform/x86/intel_pmic_gpio.c
index 930e6276236..61433d49286 100644
--- a/drivers/platform/x86/intel_pmic_gpio.c
+++ b/drivers/platform/x86/intel_pmic_gpio.c
@@ -60,69 +60,20 @@ enum pmic_gpio_register {
 #define GPOSW_DOU 0x08
 #define GPOSW_RDRV 0x30
 
+#define GPIO_UPDATE_TYPE        0x80000000
 
 #define NUM_GPIO 24
 
-struct pmic_gpio_irq {
-        spinlock_t lock;
-        u32 trigger[NUM_GPIO];
-        u32 dirty;
-        struct work_struct work;
-};
-
-
 struct pmic_gpio {
+        struct mutex            buslock;
         struct gpio_chip        chip;
-        struct pmic_gpio_irq    irqtypes;
         void                    *gpiointr;
         int                     irq;
         unsigned                irq_base;
+        unsigned int            update_type;
+        u32                     trigger_type;
 };
 
-static void pmic_program_irqtype(int gpio, int type)
-{
-        if (type & IRQ_TYPE_EDGE_RISING)
-                intel_scu_ipc_update_register(GPIO0 + gpio, 0x20, 0x20);
-        else
-                intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x20);
-
-        if (type & IRQ_TYPE_EDGE_FALLING)
-                intel_scu_ipc_update_register(GPIO0 + gpio, 0x10, 0x10);
-        else
-                intel_scu_ipc_update_register(GPIO0 + gpio, 0x00, 0x10);
-};
-
-static void pmic_irqtype_work(struct work_struct *work)
-{
-        struct pmic_gpio_irq *t =
-                container_of(work, struct pmic_gpio_irq, work);
-        unsigned long flags;
-        int i;
-        u16 type;
-
-        spin_lock_irqsave(&t->lock, flags);
-        /* As we drop the lock, we may need multiple scans if we race the
-           pmic_irq_type function */
-        while (t->dirty) {
-                /*
-                 *      For each pin that has the dirty bit set send an IPC
-                 *      message to configure the hardware via the PMIC
-                 */
-                for (i = 0; i < NUM_GPIO; i++) {
-                        if (!(t->dirty & (1 << i)))
-                                continue;
-                        t->dirty &= ~(1 << i);
-                        /* We can't trust the array entry or dirty
-                           once the lock is dropped */
-                        type = t->trigger[i];
-                        spin_unlock_irqrestore(&t->lock, flags);
-                        pmic_program_irqtype(i, type);
-                        spin_lock_irqsave(&t->lock, flags);
-                }
-        }
-        spin_unlock_irqrestore(&t->lock, flags);
-}
-
 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         if (offset > 8) {
@@ -190,25 +141,24 @@ static void pmic_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
                         1 << (offset - 16));
 }
 
-static int pmic_irq_type(unsigned irq, unsigned type)
+/*
+ * This is called from genirq with pg->buslock locked and
+ * irq_desc->lock held. We can not access the scu bus here, so we
+ * store the change and update in the bus_sync_unlock() function below
+ */
+static int pmic_irq_type(struct irq_data *data, unsigned type)
 {
-        struct pmic_gpio *pg = get_irq_chip_data(irq);
-        u32 gpio = irq - pg->irq_base;
-        unsigned long flags;
+        struct pmic_gpio *pg = irq_data_get_irq_chip_data(data);
+        u32 gpio = data->irq - pg->irq_base;
 
         if (gpio >= pg->chip.ngpio)
                 return -EINVAL;
 
-        spin_lock_irqsave(&pg->irqtypes.lock, flags);
-        pg->irqtypes.trigger[gpio] = type;
-        pg->irqtypes.dirty |=  (1 << gpio);
-        spin_unlock_irqrestore(&pg->irqtypes.lock, flags);
-        schedule_work(&pg->irqtypes.work);
+        pg->trigger_type = type;
+        pg->update_type = gpio | GPIO_UPDATE_TYPE;
         return 0;
 }
 
-
-
 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 {
         struct pmic_gpio *pg = container_of(chip, struct pmic_gpio, chip);
@@ -217,38 +167,32 @@ static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
 }
 
 /* the gpiointr register is read-clear, so just do nothing. */
-static void pmic_irq_unmask(unsigned irq)
-{
-};
+static void pmic_irq_unmask(struct irq_data *data) { }
 
-static void pmic_irq_mask(unsigned irq)
-{
-};
+static void pmic_irq_mask(struct irq_data *data) { }
 
 static struct irq_chip pmic_irqchip = {
         .name           = "PMIC-GPIO",
-        .mask           = pmic_irq_mask,
-        .unmask         = pmic_irq_unmask,
-        .set_type       = pmic_irq_type,
+        .irq_mask       = pmic_irq_mask,
+        .irq_unmask     = pmic_irq_unmask,
+        .irq_set_type   = pmic_irq_type,
 };
 
-static void pmic_irq_handler(unsigned irq, struct irq_desc *desc)
+static irqreturn_t pmic_irq_handler(int irq, void *data)
 {
-        struct pmic_gpio *pg = (struct pmic_gpio *)get_irq_data(irq);
+        struct pmic_gpio *pg = data;
         u8 intsts = *((u8 *)pg->gpiointr + 4);
         int gpio;
+        irqreturn_t ret = IRQ_NONE;
 
         for (gpio = 0; gpio < 8; gpio++) {
                 if (intsts & (1 << gpio)) {
                         pr_debug("pmic pin %d triggered\n", gpio);
                         generic_handle_irq(pg->irq_base + gpio);
+                        ret = IRQ_HANDLED;
                 }
         }
-
-        if (desc->chip->irq_eoi)
-                desc->chip->irq_eoi(irq_get_irq_data(irq));
-        else
-                dev_warn(pg->chip.dev, "missing EOI handler for irq %d\n", irq);
+        return ret;
 }
 
 static int __devinit platform_pmic_gpio_probe(struct platform_device *pdev)
@@ -297,8 +241,7 @@ static int __devinit platform_pmic_gpio_probe(struct platform_device *pdev)
         pg->chip.can_sleep = 1;
         pg->chip.dev = dev;
 
-        INIT_WORK(&pg->irqtypes.work, pmic_irqtype_work);
-        spin_lock_init(&pg->irqtypes.lock);
+        mutex_init(&pg->buslock);
 
         pg->chip.dev = dev;
         retval = gpiochip_add(&pg->chip);
@@ -306,8 +249,13 @@ static int __devinit platform_pmic_gpio_probe(struct platform_device *pdev)
                 printk(KERN_ERR "%s: Can not add pmic gpio chip.\n", __func__);
                 goto err;
         }
-        set_irq_data(pg->irq, pg);
-        set_irq_chained_handler(pg->irq, pmic_irq_handler);
+
+        retval = request_irq(pg->irq, pmic_irq_handler, 0, "pmic", pg);
+        if (retval) {
+                printk(KERN_WARNING "pmic: Interrupt request failed\n");
+                goto err;
+        }
+
         for (i = 0; i < 8; i++) {
                 set_irq_chip_and_handler_name(i + pg->irq_base, &pmic_irqchip,
                                         handle_simple_irq, "demux");
diff --git a/drivers/platform/x86/tc1100-wmi.c b/drivers/platform/x86/tc1100-wmi.c
index 1fe0f1feff7..865ef78d6f1 100644
--- a/drivers/platform/x86/tc1100-wmi.c
+++ b/drivers/platform/x86/tc1100-wmi.c
@@ -162,7 +162,7 @@ set_bool_##value(struct device *dev, struct device_attribute *attr, \
                         return -EINVAL; \
         return count; \
 } \
-static DEVICE_ATTR(value, S_IWUGO | S_IRUGO | S_IWUSR, \
+static DEVICE_ATTR(value, S_IRUGO | S_IWUSR, \
         show_bool_##value, set_bool_##value);
 
 show_set_bool(wireless, TC1100_INSTANCE_WIRELESS);
diff --git a/drivers/platform/x86/thinkpad_acpi.c b/drivers/platform/x86/thinkpad_acpi.c
index dd599585c6a..eb9922385ef 100644
--- a/drivers/platform/x86/thinkpad_acpi.c
+++ b/drivers/platform/x86/thinkpad_acpi.c
@@ -2275,16 +2275,12 @@ static void tpacpi_input_send_key(const unsigned int scancode)
         if (keycode != KEY_RESERVED) {
                 mutex_lock(&tpacpi_inputdev_send_mutex);
 
+                input_event(tpacpi_inputdev, EV_MSC, MSC_SCAN, scancode);
                 input_report_key(tpacpi_inputdev, keycode, 1);
-                if (keycode == KEY_UNKNOWN)
-                        input_event(tpacpi_inputdev, EV_MSC, MSC_SCAN,
-                                    scancode);
                 input_sync(tpacpi_inputdev);
 
+                input_event(tpacpi_inputdev, EV_MSC, MSC_SCAN, scancode);
                 input_report_key(tpacpi_inputdev, keycode, 0);
-                if (keycode == KEY_UNKNOWN)
-                        input_event(tpacpi_inputdev, EV_MSC, MSC_SCAN,
-                                    scancode);
                 input_sync(tpacpi_inputdev);
 
                 mutex_unlock(&tpacpi_inputdev_send_mutex);
diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c
index 318672d0556..a9fe23d5bd0 100644
--- a/drivers/s390/block/dasd_eckd.c
+++ b/drivers/s390/block/dasd_eckd.c
@@ -72,7 +72,7 @@ static struct dasd_discipline dasd_eckd_discipline;
 static struct ccw_device_id dasd_eckd_ids[] = {
         { CCW_DEVICE_DEVTYPE (0x3990, 0, 0x3390, 0), .driver_info = 0x1},
         { CCW_DEVICE_DEVTYPE (0x2105, 0, 0x3390, 0), .driver_info = 0x2},
-        { CCW_DEVICE_DEVTYPE (0x3880, 0, 0x3390, 0), .driver_info = 0x3},
+        { CCW_DEVICE_DEVTYPE (0x3880, 0, 0x3380, 0), .driver_info = 0x3},
         { CCW_DEVICE_DEVTYPE (0x3990, 0, 0x3380, 0), .driver_info = 0x4},
         { CCW_DEVICE_DEVTYPE (0x2105, 0, 0x3380, 0), .driver_info = 0x5},
         { CCW_DEVICE_DEVTYPE (0x9343, 0, 0x9345, 0), .driver_info = 0x6},
diff --git a/fs/ceph/dir.c b/fs/ceph/dir.c
index 0bc68de8edd..f0aef787a10 100644
--- a/fs/ceph/dir.c
+++ b/fs/ceph/dir.c
@@ -60,6 +60,7 @@ int ceph_init_dentry(struct dentry *dentry)
         }
         di->dentry = dentry;
         di->lease_session = NULL;
+        di->parent_inode = igrab(dentry->d_parent->d_inode);
         dentry->d_fsdata = di;
         dentry->d_time = jiffies;
         ceph_dentry_lru_add(dentry);
@@ -1033,7 +1034,7 @@ static void ceph_dentry_release(struct dentry *dentry)
         u64 snapid = CEPH_NOSNAP;
 
         if (!IS_ROOT(dentry)) {
-                parent_inode = dentry->d_parent->d_inode;
+                parent_inode = di->parent_inode;
                 if (parent_inode)
                         snapid = ceph_snap(parent_inode);
         }
@@ -1058,6 +1059,8 @@ static void ceph_dentry_release(struct dentry *dentry)
                 kmem_cache_free(ceph_dentry_cachep, di);
                 dentry->d_fsdata = NULL;
         }
+        if (parent_inode)
+                iput(parent_inode);
 }
 
 static int ceph_snapdir_d_revalidate(struct dentry *dentry,
diff --git a/fs/ceph/snap.c b/fs/ceph/snap.c
index 39c243acd06..f40b9139e43 100644
--- a/fs/ceph/snap.c
+++ b/fs/ceph/snap.c
@@ -584,10 +584,14 @@ static void queue_realm_cap_snaps(struct ceph_snap_realm *realm)
         if (lastinode)
                 iput(lastinode);
 
-        dout("queue_realm_cap_snaps %p %llx children\n", realm, realm->ino);
-        list_for_each_entry(child, &realm->children, child_item)
-                queue_realm_cap_snaps(child);
+        list_for_each_entry(child, &realm->children, child_item) {
+                dout("queue_realm_cap_snaps %p %llx queue child %p %llx\n",
+                     realm, realm->ino, child, child->ino);
+                list_del_init(&child->dirty_item);
+                list_add(&child->dirty_item, &realm->dirty_item);
+        }
 
+        list_del_init(&realm->dirty_item);
         dout("queue_realm_cap_snaps %p %llx done\n", realm, realm->ino);
 }
 
@@ -683,7 +687,9 @@ more:
          * queue cap snaps _after_ we've built the new snap contexts,
          * so that i_head_snapc can be set appropriately.
          */
-        list_for_each_entry(realm, &dirty_realms, dirty_item) {
+        while (!list_empty(&dirty_realms)) {
+                realm = list_first_entry(&dirty_realms, struct ceph_snap_realm,
+                                         dirty_item);
                 queue_realm_cap_snaps(realm);
         }
 
diff --git a/fs/ceph/super.h b/fs/ceph/super.h
index 20b907d76ae..88fcaa21b80 100644
--- a/fs/ceph/super.h
+++ b/fs/ceph/super.h
@@ -207,6 +207,7 @@ struct ceph_dentry_info {
         struct dentry *dentry;
         u64 time;
         u64 offset;
+        struct inode *parent_inode;
 };
 
 struct ceph_inode_xattrs_info {
diff --git a/fs/cifs/cifsfs.h b/fs/cifs/cifsfs.h
index 4a3330235d5..a9371b6578c 100644
--- a/fs/cifs/cifsfs.h
+++ b/fs/cifs/cifsfs.h
@@ -127,5 +127,5 @@ extern long cifs_ioctl(struct file *filep, unsigned int cmd, unsigned long arg);
 extern const struct export_operations cifs_export_ops;
 #endif /* EXPERIMENTAL */
 
-#define CIFS_VERSION   "1.70"
+#define CIFS_VERSION   "1.71"
 #endif                          /* _CIFSFS_H */
diff --git a/fs/cifs/netmisc.c b/fs/cifs/netmisc.c
index 8d9189f6447..79f641eeda3 100644
--- a/fs/cifs/netmisc.c
+++ b/fs/cifs/netmisc.c
@@ -170,7 +170,7 @@ cifs_convert_address(struct sockaddr *dst, const char *src, int len)
 {
         int rc, alen, slen;
         const char *pct;
-        char *endp, scope_id[13];
+        char scope_id[13];
         struct sockaddr_in *s4 = (struct sockaddr_in *) dst;
         struct sockaddr_in6 *s6 = (struct sockaddr_in6 *) dst;
 
@@ -197,9 +197,9 @@ cifs_convert_address(struct sockaddr *dst, const char *src, int len)
                 memcpy(scope_id, pct + 1, slen);
                 scope_id[slen] = '\0';
 
-                s6->sin6_scope_id = (u32) simple_strtoul(pct, &endp, 0);
-                if (endp != scope_id + slen)
-                        return 0;
+                rc = strict_strtoul(scope_id, 0,
+                                        (unsigned long *)&s6->sin6_scope_id);
+                rc = (rc == 0) ? 1 : 0;
         }
 
         return rc;
diff --git a/fs/cifs/sess.c b/fs/cifs/sess.c
index 1adc9625a34..16765703131 100644
--- a/fs/cifs/sess.c
+++ b/fs/cifs/sess.c
@@ -656,13 +656,13 @@ ssetup_ntlmssp_authenticate:
 
         if (type == LANMAN) {
 #ifdef CONFIG_CIFS_WEAK_PW_HASH
-                char lnm_session_key[CIFS_SESS_KEY_SIZE];
+                char lnm_session_key[CIFS_AUTH_RESP_SIZE];
 
                 pSMB->req.hdr.Flags2 &= ~SMBFLG2_UNICODE;
 
                 /* no capabilities flags in old lanman negotiation */
 
-                pSMB->old_req.PasswordLength = cpu_to_le16(CIFS_SESS_KEY_SIZE);
+                pSMB->old_req.PasswordLength = cpu_to_le16(CIFS_AUTH_RESP_SIZE);
 
                 /* Calculate hash with password and copy into bcc_ptr.
                  * Encryption Key (stored as in cryptkey) gets used if the
@@ -675,8 +675,8 @@ ssetup_ntlmssp_authenticate:
                                         true : false, lnm_session_key);
 
                 ses->flags |= CIFS_SES_LANMAN;
-                memcpy(bcc_ptr, (char *)lnm_session_key, CIFS_SESS_KEY_SIZE);
-                bcc_ptr += CIFS_SESS_KEY_SIZE;
+                memcpy(bcc_ptr, (char *)lnm_session_key, CIFS_AUTH_RESP_SIZE);
+                bcc_ptr += CIFS_AUTH_RESP_SIZE;
 
                 /* can not sign if LANMAN negotiated so no need
                 to calculate signing key? but what if server
diff --git a/fs/ecryptfs/dentry.c b/fs/ecryptfs/dentry.c
index 6fc4f319b55..534c1d46e69 100644
--- a/fs/ecryptfs/dentry.c
+++ b/fs/ecryptfs/dentry.c
@@ -46,24 +46,28 @@ static int ecryptfs_d_revalidate(struct dentry *dentry, struct nameidata *nd)
 {
         struct dentry *lower_dentry;
         struct vfsmount *lower_mnt;
-        struct dentry *dentry_save;
-        struct vfsmount *vfsmount_save;
+        struct dentry *dentry_save = NULL;
+        struct vfsmount *vfsmount_save = NULL;
         int rc = 1;
 
-        if (nd->flags & LOOKUP_RCU)
+        if (nd && nd->flags & LOOKUP_RCU)
                 return -ECHILD;
 
         lower_dentry = ecryptfs_dentry_to_lower(dentry);
         lower_mnt = ecryptfs_dentry_to_lower_mnt(dentry);
         if (!lower_dentry->d_op || !lower_dentry->d_op->d_revalidate)
                 goto out;
-        dentry_save = nd->path.dentry;
-        vfsmount_save = nd->path.mnt;
-        nd->path.dentry = lower_dentry;
-        nd->path.mnt = lower_mnt;
+        if (nd) {
+                dentry_save = nd->path.dentry;
+                vfsmount_save = nd->path.mnt;
+                nd->path.dentry = lower_dentry;
+                nd->path.mnt = lower_mnt;
+        }
         rc = lower_dentry->d_op->d_revalidate(lower_dentry, nd);
-        nd->path.dentry = dentry_save;
-        nd->path.mnt = vfsmount_save;
+        if (nd) {
+                nd->path.dentry = dentry_save;
+                nd->path.mnt = vfsmount_save;
+        }
         if (dentry->d_inode) {
                 struct inode *lower_inode =
                         ecryptfs_inode_to_lower(dentry->d_inode);
diff --git a/fs/ecryptfs/ecryptfs_kernel.h b/fs/ecryptfs/ecryptfs_kernel.h
index dbc84ed9633..e00753496e3 100644
--- a/fs/ecryptfs/ecryptfs_kernel.h
+++ b/fs/ecryptfs/ecryptfs_kernel.h
@@ -632,8 +632,7 @@ int ecryptfs_interpose(struct dentry *hidden_dentry,
                        u32 flags);
 int ecryptfs_lookup_and_interpose_lower(struct dentry *ecryptfs_dentry,
                                         struct dentry *lower_dentry,
-                                        struct inode *ecryptfs_dir_inode,
-                                        struct nameidata *ecryptfs_nd);
+                                        struct inode *ecryptfs_dir_inode);
 int ecryptfs_decode_and_decrypt_filename(char **decrypted_name,
                                          size_t *decrypted_name_size,
                                          struct dentry *ecryptfs_dentry,
diff --git a/fs/ecryptfs/file.c b/fs/ecryptfs/file.c
index 81e10e6a944..7d1050e254f 100644
--- a/fs/ecryptfs/file.c
+++ b/fs/ecryptfs/file.c
@@ -317,6 +317,7 @@ ecryptfs_compat_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
 
 const struct file_operations ecryptfs_dir_fops = {
         .readdir = ecryptfs_readdir,
+        .read = generic_read_dir,
         .unlocked_ioctl = ecryptfs_unlocked_ioctl,
 #ifdef CONFIG_COMPAT
         .compat_ioctl = ecryptfs_compat_ioctl,
diff --git a/fs/ecryptfs/inode.c b/fs/ecryptfs/inode.c
index bd33f87a190..b592938a84b 100644
--- a/fs/ecryptfs/inode.c
+++ b/fs/ecryptfs/inode.c
@@ -74,16 +74,20 @@ ecryptfs_create_underlying_file(struct inode *lower_dir_inode,
         unsigned int flags_save;
         int rc;
 
-        dentry_save = nd->path.dentry;
-        vfsmount_save = nd->path.mnt;
-        flags_save = nd->flags;
-        nd->path.dentry = lower_dentry;
-        nd->path.mnt = lower_mnt;
-        nd->flags &= ~LOOKUP_OPEN;
+        if (nd) {
+                dentry_save = nd->path.dentry;
+                vfsmount_save = nd->path.mnt;
+                flags_save = nd->flags;
+                nd->path.dentry = lower_dentry;
+                nd->path.mnt = lower_mnt;
+                nd->flags &= ~LOOKUP_OPEN;
+        }
         rc = vfs_create(lower_dir_inode, lower_dentry, mode, nd);
-        nd->path.dentry = dentry_save;
-        nd->path.mnt = vfsmount_save;
-        nd->flags = flags_save;
+        if (nd) {
+                nd->path.dentry = dentry_save;
+                nd->path.mnt = vfsmount_save;
+                nd->flags = flags_save;
+        }
         return rc;
 }
 
@@ -241,8 +245,7 @@ out:
  */
 int ecryptfs_lookup_and_interpose_lower(struct dentry *ecryptfs_dentry,
                                         struct dentry *lower_dentry,
-                                        struct inode *ecryptfs_dir_inode,
-                                        struct nameidata *ecryptfs_nd)
+                                        struct inode *ecryptfs_dir_inode)
 {
         struct dentry *lower_dir_dentry;
         struct vfsmount *lower_mnt;
@@ -290,8 +293,6 @@ int ecryptfs_lookup_and_interpose_lower(struct dentry *ecryptfs_dentry,
                 goto out;
         if (special_file(lower_inode->i_mode))
                 goto out;
-        if (!ecryptfs_nd)
-                goto out;
         /* Released in this function */
         page_virt = kmem_cache_zalloc(ecryptfs_header_cache_2, GFP_USER);
         if (!page_virt) {
@@ -349,75 +350,6 @@ out:
 }
 
 /**
- * ecryptfs_new_lower_dentry
- * @name: The name of the new dentry.
- * @lower_dir_dentry: Parent directory of the new dentry.
- * @nd: nameidata from last lookup.
- *
- * Create a new dentry or get it from lower parent dir.
- */
-static struct dentry *
-ecryptfs_new_lower_dentry(struct qstr *name, struct dentry *lower_dir_dentry,
-                          struct nameidata *nd)
-{
-        struct dentry *new_dentry;
-        struct dentry *tmp;
-        struct inode *lower_dir_inode;
-
-        lower_dir_inode = lower_dir_dentry->d_inode;
-
-        tmp = d_alloc(lower_dir_dentry, name);
-        if (!tmp)
-                return ERR_PTR(-ENOMEM);
-
-        mutex_lock(&lower_dir_inode->i_mutex);
-        new_dentry = lower_dir_inode->i_op->lookup(lower_dir_inode, tmp, nd);
-        mutex_unlock(&lower_dir_inode->i_mutex);
-
-        if (!new_dentry)
-                new_dentry = tmp;
-        else
-                dput(tmp);
-
-        return new_dentry;
-}
-
-
-/**
- * ecryptfs_lookup_one_lower
- * @ecryptfs_dentry: The eCryptfs dentry that we are looking up
- * @lower_dir_dentry: lower parent directory
- * @name: lower file name
- *
- * Get the lower dentry from vfs. If lower dentry does not exist yet,
- * create it.
- */
-static struct dentry *
-ecryptfs_lookup_one_lower(struct dentry *ecryptfs_dentry,
-                          struct dentry *lower_dir_dentry, struct qstr *name)
-{
-        struct nameidata nd;
-        struct vfsmount *lower_mnt;
-        int err;
-
-        lower_mnt = mntget(ecryptfs_dentry_to_lower_mnt(
-                                    ecryptfs_dentry->d_parent));
-        err = vfs_path_lookup(lower_dir_dentry, lower_mnt, name->name , 0, &nd);
-        mntput(lower_mnt);
-
-        if (!err) {
-                /* we dont need the mount */
-                mntput(nd.path.mnt);
-                return nd.path.dentry;
-        }
-        if (err != -ENOENT)
-                return ERR_PTR(err);
-
-        /* create a new lower dentry */
-        return ecryptfs_new_lower_dentry(name, lower_dir_dentry, &nd);
-}
-
-/**
  * ecryptfs_lookup
  * @ecryptfs_dir_inode: The eCryptfs directory inode
  * @ecryptfs_dentry: The eCryptfs dentry that we are looking up
@@ -434,7 +366,6 @@ static struct dentry *ecryptfs_lookup(struct inode *ecryptfs_dir_inode,
         size_t encrypted_and_encoded_name_size;
         struct ecryptfs_mount_crypt_stat *mount_crypt_stat = NULL;
         struct dentry *lower_dir_dentry, *lower_dentry;
-        struct qstr lower_name;
         int rc = 0;
 
         if ((ecryptfs_dentry->d_name.len == 1
@@ -444,20 +375,14 @@ static struct dentry *ecryptfs_lookup(struct inode *ecryptfs_dir_inode,
                 goto out_d_drop;
         }
         lower_dir_dentry = ecryptfs_dentry_to_lower(ecryptfs_dentry->d_parent);
-        lower_name.name = ecryptfs_dentry->d_name.name;
-        lower_name.len = ecryptfs_dentry->d_name.len;
-        lower_name.hash = ecryptfs_dentry->d_name.hash;
-        if (lower_dir_dentry->d_op && lower_dir_dentry->d_op->d_hash) {
-                rc = lower_dir_dentry->d_op->d_hash(lower_dir_dentry,
-                                lower_dir_dentry->d_inode, &lower_name);
-                if (rc < 0)
-                        goto out_d_drop;
-        }
-        lower_dentry = ecryptfs_lookup_one_lower(ecryptfs_dentry,
-                                                 lower_dir_dentry, &lower_name);
+        mutex_lock(&lower_dir_dentry->d_inode->i_mutex);
+        lower_dentry = lookup_one_len(ecryptfs_dentry->d_name.name,
+                                      lower_dir_dentry,
+                                      ecryptfs_dentry->d_name.len);
+        mutex_unlock(&lower_dir_dentry->d_inode->i_mutex);
         if (IS_ERR(lower_dentry)) {
                 rc = PTR_ERR(lower_dentry);
-                ecryptfs_printk(KERN_DEBUG, "%s: lookup_one_lower() returned "
+                ecryptfs_printk(KERN_DEBUG, "%s: lookup_one_len() returned "
                                 "[%d] on lower_dentry = [%s]\n", __func__, rc,
                                 encrypted_and_encoded_name);
                 goto out_d_drop;
@@ -479,28 +404,21 @@ static struct dentry *ecryptfs_lookup(struct inode *ecryptfs_dir_inode,
                        "filename; rc = [%d]\n", __func__, rc);
                 goto out_d_drop;
         }
-        lower_name.name = encrypted_and_encoded_name;
-        lower_name.len = encrypted_and_encoded_name_size;
-        lower_name.hash = full_name_hash(lower_name.name, lower_name.len);
-        if (lower_dir_dentry->d_op && lower_dir_dentry->d_op->d_hash) {
-                rc = lower_dir_dentry->d_op->d_hash(lower_dir_dentry,
-                                lower_dir_dentry->d_inode, &lower_name);
-                if (rc < 0)
-                        goto out_d_drop;
-        }
-        lower_dentry = ecryptfs_lookup_one_lower(ecryptfs_dentry,
-                                                 lower_dir_dentry, &lower_name);
+        mutex_lock(&lower_dir_dentry->d_inode->i_mutex);
+        lower_dentry = lookup_one_len(encrypted_and_encoded_name,
+                                      lower_dir_dentry,
+                                      encrypted_and_encoded_name_size);
+        mutex_unlock(&lower_dir_dentry->d_inode->i_mutex);
         if (IS_ERR(lower_dentry)) {
                 rc = PTR_ERR(lower_dentry);
-                ecryptfs_printk(KERN_DEBUG, "%s: lookup_one_lower() returned "
+                ecryptfs_printk(KERN_DEBUG, "%s: lookup_one_len() returned "
                                 "[%d] on lower_dentry = [%s]\n", __func__, rc,
                                 encrypted_and_encoded_name);
                 goto out_d_drop;
         }
 lookup_and_interpose:
         rc = ecryptfs_lookup_and_interpose_lower(ecryptfs_dentry, lower_dentry,
-                                                 ecryptfs_dir_inode,
-                                                 ecryptfs_nd);
+                                                 ecryptfs_dir_inode);
         goto out;
 out_d_drop:
         d_drop(ecryptfs_dentry);
@@ -1092,6 +1010,8 @@ int ecryptfs_getattr(struct vfsmount *mnt, struct dentry *dentry,
         rc = vfs_getattr(ecryptfs_dentry_to_lower_mnt(dentry),
                          ecryptfs_dentry_to_lower(dentry), &lower_stat);
         if (!rc) {
+                fsstack_copy_attr_all(dentry->d_inode,
+                                      ecryptfs_inode_to_lower(dentry->d_inode));
                 generic_fillattr(dentry->d_inode, stat);
                 stat->blocks = lower_stat.blocks;
         }
diff --git a/fs/eventfd.c b/fs/eventfd.c
index e0194b3e14d..d9a59177391 100644
--- a/fs/eventfd.c
+++ b/fs/eventfd.c
@@ -99,7 +99,7 @@ EXPORT_SYMBOL_GPL(eventfd_ctx_get);
  * @ctx: [in] Pointer to eventfd context.
  *
  * The eventfd context reference must have been previously acquired either
- * with eventfd_ctx_get() or eventfd_ctx_fdget()).
+ * with eventfd_ctx_get() or eventfd_ctx_fdget().
  */
 void eventfd_ctx_put(struct eventfd_ctx *ctx)
 {
@@ -146,9 +146,9 @@ static void eventfd_ctx_do_read(struct eventfd_ctx *ctx, __u64 *cnt)
  * eventfd_ctx_remove_wait_queue - Read the current counter and removes wait queue.
  * @ctx: [in] Pointer to eventfd context.
  * @wait: [in] Wait queue to be removed.
- * @cnt: [out] Pointer to the 64bit conter value.
+ * @cnt: [out] Pointer to the 64-bit counter value.
  *
- * Returns zero if successful, or the following error codes:
+ * Returns %0 if successful, or the following error codes:
  *
  * -EAGAIN      : The operation would have blocked.
  *
@@ -175,11 +175,11 @@ EXPORT_SYMBOL_GPL(eventfd_ctx_remove_wait_queue);
  * eventfd_ctx_read - Reads the eventfd counter or wait if it is zero.
  * @ctx: [in] Pointer to eventfd context.
  * @no_wait: [in] Different from zero if the operation should not block.
- * @cnt: [out] Pointer to the 64bit conter value.
+ * @cnt: [out] Pointer to the 64-bit counter value.
  *
- * Returns zero if successful, or the following error codes:
+ * Returns %0 if successful, or the following error codes:
  *
- * -EAGAIN      : The operation would have blocked but @no_wait was nonzero.
+ * -EAGAIN      : The operation would have blocked but @no_wait was non-zero.
  * -ERESTARTSYS : A signal interrupted the wait operation.
  *
  * If @no_wait is zero, the function might sleep until the eventfd internal
diff --git a/include/linux/module.h b/include/linux/module.h
index 9bdf27c7615..5de42043dff 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -62,7 +62,7 @@ struct module_version_attribute {
         struct module_attribute mattr;
         const char *module_name;
         const char *version;
-};
+} __attribute__ ((__aligned__(sizeof(void *))));
 
 struct module_kobject
 {
diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c
index dff633d62e5..35b36b86d76 100644
--- a/net/ceph/messenger.c
+++ b/net/ceph/messenger.c
@@ -252,8 +252,12 @@ static int ceph_tcp_recvmsg(struct socket *sock, void *buf, size_t len)
 {
         struct kvec iov = {buf, len};
         struct msghdr msg = { .msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL };
+        int r;
 
-        return kernel_recvmsg(sock, &msg, &iov, 1, len, msg.msg_flags);
+        r = kernel_recvmsg(sock, &msg, &iov, 1, len, msg.msg_flags);
+        if (r == -EAGAIN)
+                r = 0;
+        return r;
 }
 
 /*
@@ -264,13 +268,17 @@ static int ceph_tcp_sendmsg(struct socket *sock, struct kvec *iov,
                      size_t kvlen, size_t len, int more)
 {
         struct msghdr msg = { .msg_flags = MSG_DONTWAIT | MSG_NOSIGNAL };
+        int r;
 
         if (more)
                 msg.msg_flags |= MSG_MORE;
         else
                 msg.msg_flags |= MSG_EOR;  /* superfluous, but what the hell */
 
-        return kernel_sendmsg(sock, &msg, iov, kvlen, len);
+        r = kernel_sendmsg(sock, &msg, iov, kvlen, len);
+        if (r == -EAGAIN)
+                r = 0;
+        return r;
 }
 
 
@@ -847,6 +855,8 @@ static int write_partial_msg_pages(struct ceph_connection *con)
                     (msg->pages || msg->pagelist || msg->bio || in_trail))
                         kunmap(page);
 
+                if (ret == -EAGAIN)
+                        ret = 0;
                 if (ret <= 0)
                         goto out;
 
@@ -1737,16 +1747,12 @@ more_kvec:
         if (con->out_skip) {
                 ret = write_partial_skip(con);
                 if (ret <= 0)
-                        goto done;
-                if (ret < 0) {
-                        dout("try_write write_partial_skip err %d\n", ret);
-                        goto done;
-                }
+                        goto out;
         }
         if (con->out_kvec_left) {
                 ret = write_partial_kvec(con);
                 if (ret <= 0)
-                        goto done;
+                        goto out;
         }
 
         /* msg pages? */
@@ -1761,11 +1767,11 @@ more_kvec:
                 if (ret == 1)
                         goto more_kvec;  /* we need to send the footer, too! */
                 if (ret == 0)
-                        goto done;
+                        goto out;
                 if (ret < 0) {
                         dout("try_write write_partial_msg_pages err %d\n",
                              ret);
-                        goto done;
+                        goto out;
                 }
         }
 
@@ -1789,10 +1795,9 @@ do_next:
         /* Nothing to do! */
         clear_bit(WRITE_PENDING, &con->state);
         dout("try_write nothing else to write.\n");
-done:
         ret = 0;
 out:
-        dout("try_write done on %p\n", con);
+        dout("try_write done on %p ret %d\n", con, ret);
         return ret;
 }
 
@@ -1821,19 +1826,17 @@ more:
                         dout("try_read connecting\n");
                         ret = read_partial_banner(con);
                         if (ret <= 0)
-                                goto done;
-                        if (process_banner(con) < 0) {
-                                ret = -1;
                                 goto out;
-                        }
+                        ret = process_banner(con);
+                        if (ret < 0)
+                                goto out;
                 }
                 ret = read_partial_connect(con);
                 if (ret <= 0)
-                        goto done;
-                if (process_connect(con) < 0) {
-                        ret = -1;
                         goto out;
-                }
+                ret = process_connect(con);
+                if (ret < 0)
+                        goto out;
                 goto more;
         }
 
@@ -1848,7 +1851,7 @@ more:
                 dout("skipping %d / %d bytes\n", skip, -con->in_base_pos);
                 ret = ceph_tcp_recvmsg(con->sock, buf, skip);
                 if (ret <= 0)
-                        goto done;
+                        goto out;
                 con->in_base_pos += ret;
                 if (con->in_base_pos)
                         goto more;
@@ -1859,7 +1862,7 @@ more:
                  */
                 ret = ceph_tcp_recvmsg(con->sock, &con->in_tag, 1);
                 if (ret <= 0)
-                        goto done;
+                        goto out;
                 dout("try_read got tag %d\n", (int)con->in_tag);
                 switch (con->in_tag) {
                 case CEPH_MSGR_TAG_MSG:
@@ -1870,7 +1873,7 @@ more:
                         break;
                 case CEPH_MSGR_TAG_CLOSE:
                         set_bit(CLOSED, &con->state);   /* fixme */
-                        goto done;
+                        goto out;
                 default:
                         goto bad_tag;
                 }
@@ -1882,13 +1885,12 @@ more:
                         case -EBADMSG:
                                 con->error_msg = "bad crc";
                                 ret = -EIO;
-                                goto out;
+                                break;
                         case -EIO:
                                 con->error_msg = "io error";
-                                goto out;
-                        default:
-                                goto done;
+                                break;
                         }
+                        goto out;
                 }
                 if (con->in_tag == CEPH_MSGR_TAG_READY)
                         goto more;
@@ -1898,15 +1900,13 @@ more:
         if (con->in_tag == CEPH_MSGR_TAG_ACK) {
                 ret = read_partial_ack(con);
                 if (ret <= 0)
-                        goto done;
+                        goto out;
                 process_ack(con);
                 goto more;
         }
 
-done:
-        ret = 0;
 out:
-        dout("try_read done on %p\n", con);
+        dout("try_read done on %p ret %d\n", con, ret);
         return ret;
 
 bad_tag:
diff --git a/scripts/basic/fixdep.c b/scripts/basic/fixdep.c
index c9a16abacab..6c94c6ce292 100644
--- a/scripts/basic/fixdep.c
+++ b/scripts/basic/fixdep.c
@@ -315,6 +315,7 @@ static void parse_dep_file(void *map, size_t len)
         char *end = m + len;
         char *p;
         char s[PATH_MAX];
+        int first;
 
         p = strchr(m, ':');
         if (!p) {
@@ -327,6 +328,7 @@ static void parse_dep_file(void *map, size_t len)
 
         clear_config();
 
+        first = 1;
         while (m < end) {
                 while (m < end && (*m == ' ' || *m == '\\' || *m == '\n'))
                         m++;
@@ -340,9 +342,17 @@ static void parse_dep_file(void *map, size_t len)
                 if (strrcmp(s, "include/generated/autoconf.h") &&
                     strrcmp(s, "arch/um/include/uml-config.h") &&
                     strrcmp(s, ".ver")) {
-                        printf("  %s \\\n", s);
+                        /*
+                         * Do not output the first dependency (the
+                         * source file), so that kbuild is not confused
+                         * if a .c file is rewritten into .S or vice
+                         * versa.
+                         */
+                        if (!first)
+                                printf("  %s \\\n", s);
                         do_config_file(s);
                 }
+                first = 0;
                 m = p + 1;
         }
         printf("\n%s: $(deps_%s)\n\n", target, target);
diff --git a/sound/pci/au88x0/au88x0_core.c b/sound/pci/au88x0/au88x0_core.c
index 23f49f356e0..16c0bdfbb16 100644
--- a/sound/pci/au88x0/au88x0_core.c
+++ b/sound/pci/au88x0/au88x0_core.c
@@ -1252,11 +1252,19 @@ static void vortex_adbdma_resetup(vortex_t *vortex, int adbdma) {
 static int inline vortex_adbdma_getlinearpos(vortex_t * vortex, int adbdma)
 {
         stream_t *dma = &vortex->dma_adb[adbdma];
-        int temp;
+        int temp, page, delta;
 
         temp = hwread(vortex->mmio, VORTEX_ADBDMA_STAT + (adbdma << 2));
-        temp = (dma->period_virt * dma->period_bytes) + (temp & (dma->period_bytes - 1));
-        return temp;
+        page = (temp & ADB_SUBBUF_MASK) >> ADB_SUBBUF_SHIFT;
+        if (dma->nr_periods >= 4)
+                delta = (page - dma->period_real) & 3;
+        else {
+                delta = (page - dma->period_real);
+                if (delta < 0)
+                        delta += dma->nr_periods;
+        }
+        return (dma->period_virt + delta) * dma->period_bytes
+                + (temp & (dma->period_bytes - 1));
 }
 
 static void vortex_adbdma_startfifo(vortex_t * vortex, int adbdma)
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 0baffcdee8f..fcedad9a5fe 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -2308,6 +2308,7 @@ static struct snd_pci_quirk position_fix_list[] __devinitdata = {
         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
+        SND_PCI_QUIRK(0x1043, 0x8410, "ASUS", POS_FIX_LPIB),
         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
         SND_PCI_QUIRK(0x1179, 0xff10, "Toshiba A100-259", POS_FIX_LPIB),
diff --git a/sound/pci/hda/patch_conexant.c b/sound/pci/hda/patch_conexant.c
index fbe97d32140..dd7c5c12225 100644
--- a/sound/pci/hda/patch_conexant.c
+++ b/sound/pci/hda/patch_conexant.c
@@ -3410,7 +3410,7 @@ static void cx_auto_parse_output(struct hda_codec *codec)
                 }
         }
         spec->multiout.dac_nids = spec->private_dac_nids;
-        spec->multiout.max_channels = nums * 2;
+        spec->multiout.max_channels = spec->multiout.num_dacs * 2;
 
         if (cfg->hp_outs > 0)
                 spec->auto_mute = 1;
@@ -3729,9 +3729,9 @@ static int cx_auto_init(struct hda_codec *codec)
         return 0;
 }
 
-static int cx_auto_add_volume(struct hda_codec *codec, const char *basename,
+static int cx_auto_add_volume_idx(struct hda_codec *codec, const char *basename,
                               const char *dir, int cidx,
-                              hda_nid_t nid, int hda_dir)
+                              hda_nid_t nid, int hda_dir, int amp_idx)
 {
         static char name[32];
         static struct snd_kcontrol_new knew[] = {
@@ -3743,7 +3743,8 @@ static int cx_auto_add_volume(struct hda_codec *codec, const char *basename,
 
         for (i = 0; i < 2; i++) {
                 struct snd_kcontrol *kctl;
-                knew[i].private_value = HDA_COMPOSE_AMP_VAL(nid, 3, 0, hda_dir);
+                knew[i].private_value = HDA_COMPOSE_AMP_VAL(nid, 3, amp_idx,
+                                                            hda_dir);
                 knew[i].subdevice = HDA_SUBDEV_AMP_FLAG;
                 knew[i].index = cidx;
                 snprintf(name, sizeof(name), "%s%s %s", basename, dir, sfx[i]);
@@ -3759,6 +3760,9 @@ static int cx_auto_add_volume(struct hda_codec *codec, const char *basename,
         return 0;
 }
 
+#define cx_auto_add_volume(codec, str, dir, cidx, nid, hda_dir)         \
+        cx_auto_add_volume_idx(codec, str, dir, cidx, nid, hda_dir, 0)
+
 #define cx_auto_add_pb_volume(codec, nid, str, idx)                     \
         cx_auto_add_volume(codec, str, " Playback", idx, nid, HDA_OUTPUT)
 
@@ -3808,29 +3812,60 @@ static int cx_auto_build_input_controls(struct hda_codec *codec)
         struct conexant_spec *spec = codec->spec;
         struct auto_pin_cfg *cfg = &spec->autocfg;
         static const char *prev_label;
-        int i, err, cidx;
+        int i, err, cidx, conn_len;
+        hda_nid_t conn[HDA_MAX_CONNECTIONS];
+
+        int multi_adc_volume = 0; /* If the ADC nid has several input volumes */
+        int adc_nid = spec->adc_nids[0];
+
+        conn_len = snd_hda_get_connections(codec, adc_nid, conn,
+                                           HDA_MAX_CONNECTIONS);
+        if (conn_len < 0)
+                return conn_len;
+
+        multi_adc_volume = cfg->num_inputs > 1 && conn_len > 1;
+        if (!multi_adc_volume) {
+                err = cx_auto_add_volume(codec, "Capture", "", 0, adc_nid,
+                                         HDA_INPUT);
+                if (err < 0)
+                        return err;
+        }
 
-        err = cx_auto_add_volume(codec, "Capture", "", 0, spec->adc_nids[0],
-                                 HDA_INPUT);
-        if (err < 0)
-                return err;
         prev_label = NULL;
         cidx = 0;
         for (i = 0; i < cfg->num_inputs; i++) {
                 hda_nid_t nid = cfg->inputs[i].pin;
                 const char *label;
-                if (!(get_wcaps(codec, nid) & AC_WCAP_IN_AMP))
+                int j;
+                int pin_amp = get_wcaps(codec, nid) & AC_WCAP_IN_AMP;
+                if (!pin_amp && !multi_adc_volume)
                         continue;
+
                 label = hda_get_autocfg_input_label(codec, cfg, i);
                 if (label == prev_label)
                         cidx++;
                 else
                         cidx = 0;
                 prev_label = label;
-                err = cx_auto_add_volume(codec, label, " Capture", cidx,
-                                         nid, HDA_INPUT);
-                if (err < 0)
-                        return err;
+
+                if (pin_amp) {
+                        err = cx_auto_add_volume(codec, label, " Boost", cidx,
+                                                 nid, HDA_INPUT);
+                        if (err < 0)
+                                return err;
+                }
+
+                if (!multi_adc_volume)
+                        continue;
+                for (j = 0; j < conn_len; j++) {
+                        if (conn[j] == nid) {
+                                err = cx_auto_add_volume_idx(codec, label,
+                                    " Capture", cidx, adc_nid, HDA_INPUT, j);
+                                if (err < 0)
+                                        return err;
+                                break;
+                        }
+                }
         }
         return 0;
 }
diff --git a/sound/usb/caiaq/audio.c b/sound/usb/caiaq/audio.c
index 68b97477577..66eabafb1c2 100644
--- a/sound/usb/caiaq/audio.c
+++ b/sound/usb/caiaq/audio.c
@@ -785,7 +785,7 @@ int snd_usb_caiaq_audio_init(struct snd_usb_caiaqdev *dev)
         }
 
         dev->pcm->private_data = dev;
-        strcpy(dev->pcm->name, dev->product_name);
+        strlcpy(dev->pcm->name, dev->product_name, sizeof(dev->pcm->name));
 
         memset(dev->sub_playback, 0, sizeof(dev->sub_playback));
         memset(dev->sub_capture, 0, sizeof(dev->sub_capture));
diff --git a/sound/usb/caiaq/midi.c b/sound/usb/caiaq/midi.c
index 2f218c77fff..a1a47088fd0 100644
--- a/sound/usb/caiaq/midi.c
+++ b/sound/usb/caiaq/midi.c
@@ -136,7 +136,7 @@ int snd_usb_caiaq_midi_init(struct snd_usb_caiaqdev *device)
         if (ret < 0)
                 return ret;
 
-        strcpy(rmidi->name, device->product_name);
+        strlcpy(rmidi->name, device->product_name, sizeof(rmidi->name));
 
         rmidi->info_flags = SNDRV_RAWMIDI_INFO_DUPLEX;
         rmidi->private_data = device;