[media] s5h1432: Add new s5h1432 driver

Introduce a new driver for the s5h1432 Signed-off-by: Palash Bandyopadhyay <palash.bandyopadhyay@conexant.com> Signed-off-by: Devin Heitmueller <dheitmueller@hauppauge.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
author: Palash Bandyopadhyay <palash.bandyopadhyay@conexant.com> 2010-07-06 15:40:58 -0400
committer: Mauro Carvalho Chehab <mchehab@redhat.com> 2010-10-20 23:17:09 -0400
commit: 47b75ec14653f12f9fd6fd76bfd5891ba35e1e79 (patch)
tree: 02c5c4c170aaec16c99a2ed99da98b28b6b77b85
parent: e4115bb2841019aa19cc5bcf0f1aa24789d05ccf (diff)
4 files changed, 544 insertions, 0 deletions
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index d83632c0687..35cb8c5c947 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -257,6 +257,13 @@ config DVB_CX22702
        help
          A DVB-T tuner module. Say Y when you want to support this frontend.
+config DVB_S5H1432
+        tristate "Samsung s5h1432 demodulator (OFDM)"
+        depends on DVB_CORE && I2C
+        default m if DVB_FE_CUSTOMISE
+        help
+          A DVB-T tuner module. Say Y when you want to support this frontend.
 config DVB_DRX397XD
        tristate "Micronas DRX3975D/DRX3977D based"
        depends on DVB_CORE && I2C
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index 9b59e411d5b..63cf3d0986b 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_DVB_STB0899) += stb0899.o
 obj-$(CONFIG_DVB_STB6100) += stb6100.o
 obj-$(CONFIG_DVB_SP8870) += sp8870.o
 obj-$(CONFIG_DVB_CX22700) += cx22700.o
+obj-$(CONFIG_DVB_S5H1432) += s5h1432.o
 obj-$(CONFIG_DVB_CX24110) += cx24110.o
 obj-$(CONFIG_DVB_TDA8083) += tda8083.o
 obj-$(CONFIG_DVB_L64781) += l64781.o
diff --git a/drivers/media/dvb/frontends/s5h1432.c b/drivers/media/dvb/frontends/s5h1432.c
new file mode 100644
index 00000000000..cff164c812e
--- /dev/null
+++ b/drivers/media/dvb/frontends/s5h1432.c
@@ -0,0 +1,440 @@
+/*
+    Samsung s5h1432 DVB-T demodulator driver
+    Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include "dvb_frontend.h"
+#include "s5h1432.h"
+struct s5h1432_state {
+        struct i2c_adapter *i2c;
+        /* configuration settings */
+        const struct s5h1432_config *config;
+        struct dvb_frontend frontend;
+        fe_modulation_t current_modulation;
+        unsigned int first_tune:1;
+        u32 current_frequency;
+        int if_freq;
+        u8 inversion;
+};
+static int debug;
+#define dprintk(arg...) do {    \
+        if (debug)              \
+                printk(arg);    \
+        } while (0)
+static int s5h1432_writereg(struct s5h1432_state *state,
+        u8 addr, u8 reg, u8 data)
+{
+        int ret;
+        u8 buf[] = { reg, data };
+        struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 2 };
+        ret = i2c_transfer(state->i2c, &msg, 1);
+        if (ret != 1)
+                printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, "
+                       "ret == %i)\n", __func__, addr, reg, data, ret);
+        return (ret != 1) ? -1 : 0;
+}
+static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
+{
+        int ret;
+        u8 b0[] = { reg };
+        u8 b1[] = { 0 };
+        struct i2c_msg msg[] = {
+                { .addr = addr, .flags = 0, .buf = b0, .len = 1 },
+                { .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
+        ret = i2c_transfer(state->i2c, msg, 2);
+        if (ret != 2)
+                printk(KERN_ERR "%s: readreg error (ret == %i)\n",
+                        __func__, ret);
+        return b1[0];
+}
+static int s5h1432_sleep(struct dvb_frontend *fe)
+{
+        return 0;
+}
+static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
+{
+        struct s5h1432_state *state = fe->demodulator_priv;
+        u8 reg = 0;
+    /* Register        [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2*/
+        reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
+        reg &= ~(0x0C);
+        switch (bandwidth) {
+        case 6:
+                reg |= 0x08;
+                break;
+        case 7:
+                reg |= 0x04;
+                break;
+        case 8:
+                reg |= 0x00;
+                break;
+        default:
+        return 0;
+        }
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
+    return 1;
+}
+static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
+{
+        struct s5h1432_state *state = fe->demodulator_priv;
+        switch (ifFreqHz) {
+        case TAIWAN_HI_IF_FREQ_44_MHZ:
+                {
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x15);
+                    break;
+                }
+        case EUROPE_HI_IF_FREQ_36_MHZ:
+                {
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x40);
+                    break;
+                }
+        case IF_FREQ_6_MHZ:
+                {
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xe0);
+                    break;
+                }
+        case IF_FREQ_3point3_MHZ:
+                {
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
+                    break;
+                }
+        case IF_FREQ_3point5_MHZ:
+                {
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xED);
+                    break;
+                }
+        case IF_FREQ_4_MHZ:
+                {
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0xAA);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0xAA);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEA);
+                    break;
+                }
+        default:
+                {
+                u32 value = 0;
+                value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
+                                 (u32) 32768) / (48 * 1000));
+                printk(KERN_INFO "Default IFFreq %d :reg value = 0x%x \n",
+                                 ifFreqHz, value);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 ,
+                                 (u8) value & 0xFF);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 ,
+                                 (u8)(value>>8) & 0xFF);
+                    s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 ,
+                                 (u8)(value>>16) & 0xFF);
+                    break;
+        }
+        }
+    return 1;
+}
+/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
+static int s5h1432_set_frontend(struct dvb_frontend *fe,
+        struct dvb_frontend_parameters *p)
+{
+        u32 dvb_bandwidth = 8;
+        struct s5h1432_state *state = fe->demodulator_priv;
+        if (p->frequency == state->current_frequency) {
+                /*current_frequency = p->frequency;*/
+                /*state->current_frequency = p->frequency;*/
+        } else {
+                fe->ops.tuner_ops.set_params(fe, p); msleep(300);
+                s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
+                switch (p->u.ofdm.bandwidth) {
+                case BANDWIDTH_6_MHZ:
+                                dvb_bandwidth = 6;
+                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                                break;
+                case BANDWIDTH_7_MHZ:
+                                dvb_bandwidth = 7;
+                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                                break;
+                case BANDWIDTH_8_MHZ:
+                                dvb_bandwidth = 8;
+                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                                break;
+                default:
+                                return 0;
+                        }
+                /*fe->ops.tuner_ops.set_params(fe, p);*/
+/*Soft Reset chip*/
+        msleep(30);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1a);
+        msleep(30);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1b);
+                s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
+                switch (p->u.ofdm.bandwidth) {
+                case BANDWIDTH_6_MHZ:
+                                dvb_bandwidth = 6;
+                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                                break;
+                case BANDWIDTH_7_MHZ:
+                                dvb_bandwidth = 7;
+                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                                break;
+                case BANDWIDTH_8_MHZ:
+                                dvb_bandwidth = 8;
+                                s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
+                                break;
+                default:
+                                return 0;
+                        }
+                /*fe->ops.tuner_ops.set_params(fe,p);*/
+/*Soft Reset chip*/
+        msleep(30);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1a);
+        msleep(30);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1b);
+        }
+        state->current_frequency = p->frequency;
+        return 0;
+}
+static int s5h1432_init(struct dvb_frontend *fe)
+{
+        struct s5h1432_state *state = fe->demodulator_priv;
+        u8 reg = 0;
+        state->current_frequency = 0;
+        printk(KERN_INFO " s5h1432_init().\n");
+    /*Set VSB mode as default, this also does a soft reset*/
+    /*Initialize registers*/
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04,     0xa8);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05,     0x01);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07,     0x70);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19,     0x80);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b,     0x9D);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c,     0x30);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d,     0x20);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e,     0x1B);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e,     0x40);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42,     0x84);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50,     0x5a);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a,     0xd3);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68,     0x50);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8,     0x3c);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4,     0x10);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc,     0x9c);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA,     0x00);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1,     0x94);
+/*      s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4,     0xa1);*/
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9,     0x00);
+/*For NXP tuner*/
+    /*Set 3.3MHz as default IF frequency*/
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
+    /* Set reg 0x1E to get the full dynamic range */
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e,     0x31);
+/*Mode setting in demod*/
+        reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
+        reg |= 0x80;
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
+        /*Serial mode*/
+/*Soft Reset chip*/
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1a);
+        msleep(30);
+        s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09,     0x1b);
+        return 0;
+}
+static int s5h1432_read_status(struct dvb_frontend *fe, fe_status_t *status)
+{
+        return 0;
+}
+static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
+        u16 *signal_strength)
+{
+        return 0;
+}
+static int s5h1432_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+        return 0;
+}
+static int s5h1432_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+        return 0;
+}
+static int s5h1432_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+        return 0;
+}
+static int s5h1432_get_frontend(struct dvb_frontend *fe,
+                                struct dvb_frontend_parameters *p)
+{
+        return 0;
+}
+static int s5h1432_get_tune_settings(struct dvb_frontend *fe,
+                                     struct dvb_frontend_tune_settings *tune)
+{
+        return 0;
+}
+static void s5h1432_release(struct dvb_frontend *fe)
+{
+        struct s5h1432_state *state = fe->demodulator_priv;
+        kfree(state);
+}
+static struct dvb_frontend_ops s5h1432_ops;
+struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
+                                    struct i2c_adapter *i2c)
+{
+        struct s5h1432_state *state = NULL;
+        printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
+        /* allocate memory for the internal state */
+        state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
+        if (state == NULL)
+                goto error;
+        /* setup the state */
+        state->config = config;
+        state->i2c = i2c;
+        state->current_modulation = QAM_16;
+        state->inversion = state->config->inversion;
+        /* create dvb_frontend */
+        memcpy(&state->frontend.ops, &s5h1432_ops,
+               sizeof(struct dvb_frontend_ops));
+        state->frontend.demodulator_priv = state;
+        return &state->frontend;
+error:
+        kfree(state);
+        return NULL;
+}
+EXPORT_SYMBOL(s5h1432_attach);
+static struct dvb_frontend_ops s5h1432_ops = {
+        .info = {
+                .name                   = "Samsung s5h1432 DVB-T Frontend",
+                .type                   = FE_OFDM,
+                .frequency_min          = 177000000,
+                .frequency_max          = 858000000,
+                .frequency_stepsize     = 166666,
+                .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+                FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+                FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
+                FE_CAN_HIERARCHY_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
+                FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER
+        },
+        .init                 = s5h1432_init,
+        .sleep                = s5h1432_sleep,
+        .set_frontend         = s5h1432_set_frontend,
+        .get_frontend         = s5h1432_get_frontend,
+        .get_tune_settings    = s5h1432_get_tune_settings,
+        .read_status          = s5h1432_read_status,
+        .read_ber             = s5h1432_read_ber,
+        .read_signal_strength = s5h1432_read_signal_strength,
+        .read_snr             = s5h1432_read_snr,
+        .read_ucblocks        = s5h1432_read_ucblocks,
+        .release              = s5h1432_release,
+};
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Enable verbose debug messages");
+MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver");
+MODULE_AUTHOR("Bill Liu");
+MODULE_LICENSE("GPL");
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ */
diff --git a/drivers/media/dvb/frontends/s5h1432.h b/drivers/media/dvb/frontends/s5h1432.h
new file mode 100644
index 00000000000..241a9044d86
--- /dev/null
+++ b/drivers/media/dvb/frontends/s5h1432.h
@@ -0,0 +1,96 @@
+/*
+    Samsung s5h1432 VSB/QAM demodulator driver
+    Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
+    This program is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+    You should have received a copy of the GNU General Public License
+    along with this program; if not, write to the Free Software
+    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+*/
+#ifndef __S5H1432_H__
+#define __S5H1432_H__
+#include <linux/dvb/frontend.h>
+#define S5H1432_I2C_TOP_ADDR (0x02 >> 1)
+#define TAIWAN_HI_IF_FREQ_44_MHZ 44000000
+#define EUROPE_HI_IF_FREQ_36_MHZ 36000000
+#define IF_FREQ_6_MHZ             6000000
+#define IF_FREQ_3point3_MHZ       3300000
+#define IF_FREQ_3point5_MHZ       3500000
+#define IF_FREQ_4_MHZ             4000000
+struct s5h1432_config {
+        /* serial/parallel output */
+#define S5H1432_PARALLEL_OUTPUT 0
+#define S5H1432_SERIAL_OUTPUT   1
+        u8 output_mode;
+        /* GPIO Setting */
+#define S5H1432_GPIO_OFF 0
+#define S5H1432_GPIO_ON  1
+        u8 gpio;
+        /* MPEG signal timing */
+#define S5H1432_MPEGTIMING_CONTINOUS_INVERTING_CLOCK       0
+#define S5H1432_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK    1
+#define S5H1432_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK    2
+#define S5H1432_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK 3
+        u16 mpeg_timing;
+        /* IF Freq for QAM and VSB in KHz */
+#define S5H1432_IF_3250  3250
+#define S5H1432_IF_3500  3500
+#define S5H1432_IF_4000  4000
+#define S5H1432_IF_5380  5380
+#define S5H1432_IF_44000 44000
+#define S5H1432_VSB_IF_DEFAULT s5h1432_IF_44000
+#define S5H1432_QAM_IF_DEFAULT s5h1432_IF_44000
+        u16 qam_if;
+        u16 vsb_if;
+        /* Spectral Inversion */
+#define S5H1432_INVERSION_OFF 0
+#define S5H1432_INVERSION_ON  1
+        u8 inversion;
+        /* Return lock status based on tuner lock, or demod lock */
+#define S5H1432_TUNERLOCKING 0
+#define S5H1432_DEMODLOCKING 1
+        u8 status_mode;
+};
+#if defined(CONFIG_DVB_S5H1432) || \
+        (defined(CONFIG_DVB_S5H1432_MODULE) && defined(MODULE))
+extern struct dvb_frontend *s5h1432_attach(const struct s5h1432_config *config,
+                                           struct i2c_adapter *i2c);
+#else
+static inline struct dvb_frontend *s5h1432_attach(
+        const struct s5h1432_config *config,
+        struct i2c_adapter *i2c)
+{
+        printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+        return NULL;
+}
+#endif /* CONFIG_DVB_s5h1432 */
+#endif /* __s5h1432_H__ */
+/*
+ * Local variables:
+ * c-basic-offset: 8
+ */
author	Palash Bandyopadhyay <palash.bandyopadhyay@conexant.com>	2010-07-06 15:40:58 -0400
committer	Mauro Carvalho Chehab <mchehab@redhat.com>	2010-10-20 23:17:09 -0400
commit	47b75ec14653f12f9fd6fd76bfd5891ba35e1e79 (patch)
tree	02c5c4c170aaec16c99a2ed99da98b28b6b77b85
parent	e4115bb2841019aa19cc5bcf0f1aa24789d05ccf (diff)

diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig index d83632c0687..35cb8c5c947 100644 --- a/drivers/media/dvb/frontends/Kconfig +++ b/drivers/media/dvb/frontends/Kconfig
@@ -257,6 +257,13 @@ config DVB_CX22702
257	help	257	help
258	A DVB-T tuner module. Say Y when you want to support this frontend.	258	A DVB-T tuner module. Say Y when you want to support this frontend.
259		259
		260	config DVB_S5H1432
		261	tristate "Samsung s5h1432 demodulator (OFDM)"
		262	depends on DVB_CORE && I2C
		263	default m if DVB_FE_CUSTOMISE
		264	help
		265	A DVB-T tuner module. Say Y when you want to support this frontend.
		266
260	config DVB_DRX397XD	267	config DVB_DRX397XD
261	tristate "Micronas DRX3975D/DRX3977D based"	268	tristate "Micronas DRX3975D/DRX3977D based"
262	depends on DVB_CORE && I2C	269	depends on DVB_CORE && I2C


diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile index 9b59e411d5b..63cf3d0986b 100644 --- a/drivers/media/dvb/frontends/Makefile +++ b/drivers/media/dvb/frontends/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_DVB_STB0899) += stb0899.o
16	obj-$(CONFIG_DVB_STB6100) += stb6100.o	16	obj-$(CONFIG_DVB_STB6100) += stb6100.o
17	obj-$(CONFIG_DVB_SP8870) += sp8870.o	17	obj-$(CONFIG_DVB_SP8870) += sp8870.o
18	obj-$(CONFIG_DVB_CX22700) += cx22700.o	18	obj-$(CONFIG_DVB_CX22700) += cx22700.o
		19	obj-$(CONFIG_DVB_S5H1432) += s5h1432.o
19	obj-$(CONFIG_DVB_CX24110) += cx24110.o	20	obj-$(CONFIG_DVB_CX24110) += cx24110.o
20	obj-$(CONFIG_DVB_TDA8083) += tda8083.o	21	obj-$(CONFIG_DVB_TDA8083) += tda8083.o
21	obj-$(CONFIG_DVB_L64781) += l64781.o	22	obj-$(CONFIG_DVB_L64781) += l64781.o


diff --git a/drivers/media/dvb/frontends/s5h1432.c b/drivers/media/dvb/frontends/s5h1432.c new file mode 100644 index 00000000000..cff164c812e --- /dev/null +++ b/drivers/media/dvb/frontends/s5h1432.c
@@ -0,0 +1,440 @@
		1	/*
		2	Samsung s5h1432 DVB-T demodulator driver
		3
		4	Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
		5
		6	This program is free software; you can redistribute it and/or modify
		7	it under the terms of the GNU General Public License as published by
		8	the Free Software Foundation; either version 2 of the License, or
		9	(at your option) any later version.
		10
		11	This program is distributed in the hope that it will be useful,
		12	but WITHOUT ANY WARRANTY; without even the implied warranty of
		13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		14	GNU General Public License for more details.
		15
		16	You should have received a copy of the GNU General Public License
		17	along with this program; if not, write to the Free Software
		18	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
		19
		20	*/
		21
		22	#include <linux/kernel.h>
		23	#include <linux/init.h>
		24	#include <linux/module.h>
		25	#include <linux/string.h>
		26	#include <linux/slab.h>
		27	#include <linux/delay.h>
		28	#include "dvb_frontend.h"
		29	#include "s5h1432.h"
		30
		31	struct s5h1432_state {
		32
		33	struct i2c_adapter *i2c;
		34
		35	/* configuration settings */
		36	const struct s5h1432_config *config;
		37
		38	struct dvb_frontend frontend;
		39
		40	fe_modulation_t current_modulation;
		41	unsigned int first_tune:1;
		42
		43	u32 current_frequency;
		44	int if_freq;
		45
		46	u8 inversion;
		47	};
		48
		49	static int debug;
		50
		51	#define dprintk(arg...) do { \
		52	if (debug) \
		53	printk(arg); \
		54	} while (0)
		55
		56
		57	static int s5h1432_writereg(struct s5h1432_state *state,
		58	u8 addr, u8 reg, u8 data)
		59	{
		60	int ret;
		61	u8 buf[] = { reg, data };
		62
		63	struct i2c_msg msg = { .addr = addr, .flags = 0, .buf = buf, .len = 2 };
		64
		65	ret = i2c_transfer(state->i2c, &msg, 1);
		66
		67	if (ret != 1)
		68	printk(KERN_ERR "%s: writereg error 0x%02x 0x%02x 0x%04x, "
		69	"ret == %i)\n", __func__, addr, reg, data, ret);
		70
		71	return (ret != 1) ? -1 : 0;
		72	}
		73
		74	static u8 s5h1432_readreg(struct s5h1432_state *state, u8 addr, u8 reg)
		75	{
		76	int ret;
		77	u8 b0[] = { reg };
		78	u8 b1[] = { 0 };
		79
		80	struct i2c_msg msg[] = {
		81	{ .addr = addr, .flags = 0, .buf = b0, .len = 1 },
		82	{ .addr = addr, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
		83
		84	ret = i2c_transfer(state->i2c, msg, 2);
		85
		86	if (ret != 2)
		87	printk(KERN_ERR "%s: readreg error (ret == %i)\n",
		88	__func__, ret);
		89	return b1[0];
		90	}
		91
		92	static int s5h1432_sleep(struct dvb_frontend *fe)
		93	{
		94	return 0;
		95	}
		96
		97	static int s5h1432_set_channel_bandwidth(struct dvb_frontend *fe, u32 bandwidth)
		98	{
		99
		100	struct s5h1432_state *state = fe->demodulator_priv;
		101
		102	u8 reg = 0;
		103
		104
		105	/* Register [0x2E] bit 3:2 : 8MHz = 0; 7MHz = 1; 6MHz = 2*/
		106	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x2E);
		107	reg &= ~(0x0C);
		108	switch (bandwidth) {
		109	case 6:
		110	reg \|= 0x08;
		111	break;
		112	case 7:
		113	reg \|= 0x04;
		114	break;
		115	case 8:
		116	reg \|= 0x00;
		117	break;
		118	default:
		119	return 0;
		120	}
		121	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2E, reg);
		122	return 1;
		123	}
		124
		125	static int s5h1432_set_IF(struct dvb_frontend *fe, u32 ifFreqHz)
		126	{
		127
		128	struct s5h1432_state *state = fe->demodulator_priv;
		129
		130	switch (ifFreqHz) {
		131	case TAIWAN_HI_IF_FREQ_44_MHZ:
		132	{
		133	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
		134	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
		135	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x15);
		136	break;
		137	}
		138	case EUROPE_HI_IF_FREQ_36_MHZ:
		139	{
		140	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
		141	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
		142	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0x40);
		143	break;
		144	}
		145	case IF_FREQ_6_MHZ:
		146	{
		147	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x00);
		148	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x00);
		149	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xe0);
		150	break;
		151	}
		152	case IF_FREQ_3point3_MHZ:
		153	{
		154	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
		155	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
		156	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
		157	break;
		158	}
		159	case IF_FREQ_3point5_MHZ:
		160	{
		161	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x55);
		162	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x55);
		163	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xED);
		164	break;
		165	}
		166	case IF_FREQ_4_MHZ:
		167	{
		168	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0xAA);
		169	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0xAA);
		170	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEA);
		171	break;
		172	}
		173	default:
		174	{
		175	u32 value = 0;
		176	value = (u32) (((48000 - (ifFreqHz / 1000)) * 512 *
		177	(u32) 32768) / (48 * 1000));
		178	printk(KERN_INFO "Default IFFreq %d :reg value = 0x%x \n",
		179	ifFreqHz, value);
		180	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 ,
		181	(u8) value & 0xFF);
		182	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 ,
		183	(u8)(value>>8) & 0xFF);
		184	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 ,
		185	(u8)(value>>16) & 0xFF);
		186	break;
		187	}
		188
		189	}
		190
		191	return 1;
		192	}
		193
		194	/* Talk to the demod, set the FEC, GUARD, QAM settings etc */
		195	static int s5h1432_set_frontend(struct dvb_frontend *fe,
		196	struct dvb_frontend_parameters *p)
		197	{
		198	u32 dvb_bandwidth = 8;
		199	struct s5h1432_state *state = fe->demodulator_priv;
		200
		201	if (p->frequency == state->current_frequency) {
		202	/current_frequency = p->frequency;/
		203	/state->current_frequency = p->frequency;/
		204	} else {
		205	fe->ops.tuner_ops.set_params(fe, p); msleep(300);
		206	s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
		207	switch (p->u.ofdm.bandwidth) {
		208	case BANDWIDTH_6_MHZ:
		209	dvb_bandwidth = 6;
		210	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
		211	break;
		212	case BANDWIDTH_7_MHZ:
		213	dvb_bandwidth = 7;
		214	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
		215	break;
		216	case BANDWIDTH_8_MHZ:
		217	dvb_bandwidth = 8;
		218	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
		219	break;
		220	default:
		221	return 0;
		222	}
		223	/fe->ops.tuner_ops.set_params(fe, p);/
		224	/Soft Reset chip/
		225	msleep(30);
		226	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
		227	msleep(30);
		228	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
		229
		230
		231	s5h1432_set_channel_bandwidth(fe, dvb_bandwidth);
		232	switch (p->u.ofdm.bandwidth) {
		233	case BANDWIDTH_6_MHZ:
		234	dvb_bandwidth = 6;
		235	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
		236	break;
		237	case BANDWIDTH_7_MHZ:
		238	dvb_bandwidth = 7;
		239	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
		240	break;
		241	case BANDWIDTH_8_MHZ:
		242	dvb_bandwidth = 8;
		243	s5h1432_set_IF(fe, IF_FREQ_4_MHZ);
		244	break;
		245	default:
		246	return 0;
		247	}
		248	/fe->ops.tuner_ops.set_params(fe,p);/
		249	/Soft Reset chip/
		250	msleep(30);
		251	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
		252	msleep(30);
		253	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
		254
		255	}
		256
		257	state->current_frequency = p->frequency;
		258
		259	return 0;
		260	}
		261
		262
		263	static int s5h1432_init(struct dvb_frontend *fe)
		264	{
		265	struct s5h1432_state *state = fe->demodulator_priv;
		266
		267	u8 reg = 0;
		268	state->current_frequency = 0;
		269	printk(KERN_INFO " s5h1432_init().\n");
		270
		271
		272	/Set VSB mode as default, this also does a soft reset/
		273	/Initialize registers/
		274
		275	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x04, 0xa8);
		276	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x05, 0x01);
		277	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x07, 0x70);
		278	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x19, 0x80);
		279	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1b, 0x9D);
		280	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1c, 0x30);
		281	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1d, 0x20);
		282	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x1B);
		283	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x2e, 0x40);
		284	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, 0x84);
		285	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x50, 0x5a);
		286	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x5a, 0xd3);
		287	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x68, 0x50);
		288	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xb8, 0x3c);
		289	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xc4, 0x10);
		290	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xcc, 0x9c);
		291	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xDA, 0x00);
		292	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe1, 0x94);
		293	/* s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf4, 0xa1);*/
		294	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xf9, 0x00);
		295
		296	/For NXP tuner/
		297
		298	/Set 3.3MHz as default IF frequency/
		299	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe4 , 0x66);
		300	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe5 , 0x66);
		301	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0xe7 , 0xEE);
		302	/* Set reg 0x1E to get the full dynamic range */
		303	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x1e, 0x31);
		304
		305	/Mode setting in demod/
		306	reg = s5h1432_readreg(state, S5H1432_I2C_TOP_ADDR, 0x42);
		307	reg \|= 0x80;
		308	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x42, reg);
		309	/Serial mode/
		310
		311	/Soft Reset chip/
		312
		313	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1a);
		314	msleep(30);
		315	s5h1432_writereg(state, S5H1432_I2C_TOP_ADDR, 0x09, 0x1b);
		316
		317
		318	return 0;
		319	}
		320
		321
		322	static int s5h1432_read_status(struct dvb_frontend fe, fe_status_t status)
		323	{
		324	return 0;
		325	}
		326
		327
		328
		329	static int s5h1432_read_signal_strength(struct dvb_frontend *fe,
		330	u16 *signal_strength)
		331	{
		332	return 0;
		333	}
		334
		335	static int s5h1432_read_snr(struct dvb_frontend fe, u16 snr)
		336	{
		337	return 0;
		338	}
		339
		340	static int s5h1432_read_ucblocks(struct dvb_frontend fe, u32 ucblocks)
		341	{
		342
		343	return 0;
		344	}
		345
		346	static int s5h1432_read_ber(struct dvb_frontend fe, u32 ber)
		347	{
		348	return 0;
		349	}
		350
		351	static int s5h1432_get_frontend(struct dvb_frontend *fe,
		352	struct dvb_frontend_parameters *p)
		353	{
		354	return 0;
		355	}
		356
		357	static int s5h1432_get_tune_settings(struct dvb_frontend *fe,
		358	struct dvb_frontend_tune_settings *tune)
		359	{
		360	return 0;
		361	}
		362
		363	static void s5h1432_release(struct dvb_frontend *fe)
		364	{
		365	struct s5h1432_state *state = fe->demodulator_priv;
		366	kfree(state);
		367	}
		368
		369	static struct dvb_frontend_ops s5h1432_ops;
		370
		371	struct dvb_frontend s5h1432_attach(const struct s5h1432_config config,
		372	struct i2c_adapter *i2c)
		373	{
		374	struct s5h1432_state *state = NULL;
		375
		376	printk(KERN_INFO " Enter s5h1432_attach(). attach success!\n");
		377	/* allocate memory for the internal state */
		378	state = kmalloc(sizeof(struct s5h1432_state), GFP_KERNEL);
		379	if (state == NULL)
		380	goto error;
		381
		382	/* setup the state */
		383	state->config = config;
		384	state->i2c = i2c;
		385	state->current_modulation = QAM_16;
		386	state->inversion = state->config->inversion;
		387
		388	/* create dvb_frontend */
		389	memcpy(&state->frontend.ops, &s5h1432_ops,
		390	sizeof(struct dvb_frontend_ops));
		391
		392	state->frontend.demodulator_priv = state;
		393
		394	return &state->frontend;
		395
		396	error:
		397	kfree(state);
		398	return NULL;
		399	}
		400	EXPORT_SYMBOL(s5h1432_attach);
		401
		402	static struct dvb_frontend_ops s5h1432_ops = {
		403
		404	.info = {
		405	.name = "Samsung s5h1432 DVB-T Frontend",
		406	.type = FE_OFDM,
		407	.frequency_min = 177000000,
		408	.frequency_max = 858000000,
		409	.frequency_stepsize = 166666,
		410	.caps = FE_CAN_FEC_1_2 \| FE_CAN_FEC_2_3 \| FE_CAN_FEC_3_4 \|
		411	FE_CAN_FEC_5_6 \| FE_CAN_FEC_7_8 \| FE_CAN_FEC_AUTO \|
		412	FE_CAN_QPSK \| FE_CAN_QAM_16 \| FE_CAN_QAM_64 \| FE_CAN_QAM_AUTO \|
		413	FE_CAN_HIERARCHY_AUTO \| FE_CAN_GUARD_INTERVAL_AUTO \|
		414	FE_CAN_TRANSMISSION_MODE_AUTO \| FE_CAN_RECOVER
		415	},
		416
		417	.init = s5h1432_init,
		418	.sleep = s5h1432_sleep,
		419	.set_frontend = s5h1432_set_frontend,
		420	.get_frontend = s5h1432_get_frontend,
		421	.get_tune_settings = s5h1432_get_tune_settings,
		422	.read_status = s5h1432_read_status,
		423	.read_ber = s5h1432_read_ber,
		424	.read_signal_strength = s5h1432_read_signal_strength,
		425	.read_snr = s5h1432_read_snr,
		426	.read_ucblocks = s5h1432_read_ucblocks,
		427	.release = s5h1432_release,
		428	};
		429
		430	module_param(debug, int, 0644);
		431	MODULE_PARM_DESC(debug, "Enable verbose debug messages");
		432
		433	MODULE_DESCRIPTION("Samsung s5h1432 DVB-T Demodulator driver");
		434	MODULE_AUTHOR("Bill Liu");
		435	MODULE_LICENSE("GPL");
		436
		437	/*
		438	* Local variables:
		439	* c-basic-offset: 8
		440	*/


diff --git a/drivers/media/dvb/frontends/s5h1432.h b/drivers/media/dvb/frontends/s5h1432.h new file mode 100644 index 00000000000..241a9044d86 --- /dev/null +++ b/drivers/media/dvb/frontends/s5h1432.h
@@ -0,0 +1,96 @@
		1	/*
		2	Samsung s5h1432 VSB/QAM demodulator driver
		3
		4	Copyright (C) 2009 Bill Liu <Bill.Liu@Conexant.com>
		5
		6	This program is free software; you can redistribute it and/or modify
		7	it under the terms of the GNU General Public License as published by
		8	the Free Software Foundation; either version 2 of the License, or
		9	(at your option) any later version.
		10
		11	This program is distributed in the hope that it will be useful,
		12	but WITHOUT ANY WARRANTY; without even the implied warranty of
		13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
		14	GNU General Public License for more details.
		15
		16	You should have received a copy of the GNU General Public License
		17	along with this program; if not, write to the Free Software
		18	Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
		19
		20	*/
		21
		22	#ifndef __S5H1432_H__
		23	#define __S5H1432_H__
		24
		25	#include <linux/dvb/frontend.h>
		26
		27	#define S5H1432_I2C_TOP_ADDR (0x02 >> 1)
		28
		29	#define TAIWAN_HI_IF_FREQ_44_MHZ 44000000
		30	#define EUROPE_HI_IF_FREQ_36_MHZ 36000000
		31	#define IF_FREQ_6_MHZ 6000000
		32	#define IF_FREQ_3point3_MHZ 3300000
		33	#define IF_FREQ_3point5_MHZ 3500000
		34	#define IF_FREQ_4_MHZ 4000000
		35
		36	struct s5h1432_config {
		37
		38	/* serial/parallel output */
		39	#define S5H1432_PARALLEL_OUTPUT 0
		40	#define S5H1432_SERIAL_OUTPUT 1
		41	u8 output_mode;
		42
		43	/* GPIO Setting */
		44	#define S5H1432_GPIO_OFF 0
		45	#define S5H1432_GPIO_ON 1
		46	u8 gpio;
		47
		48	/* MPEG signal timing */
		49	#define S5H1432_MPEGTIMING_CONTINOUS_INVERTING_CLOCK 0
		50	#define S5H1432_MPEGTIMING_CONTINOUS_NONINVERTING_CLOCK 1
		51	#define S5H1432_MPEGTIMING_NONCONTINOUS_INVERTING_CLOCK 2
		52	#define S5H1432_MPEGTIMING_NONCONTINOUS_NONINVERTING_CLOCK 3
		53	u16 mpeg_timing;
		54
		55	/* IF Freq for QAM and VSB in KHz */
		56	#define S5H1432_IF_3250 3250
		57	#define S5H1432_IF_3500 3500
		58	#define S5H1432_IF_4000 4000
		59	#define S5H1432_IF_5380 5380
		60	#define S5H1432_IF_44000 44000
		61	#define S5H1432_VSB_IF_DEFAULT s5h1432_IF_44000
		62	#define S5H1432_QAM_IF_DEFAULT s5h1432_IF_44000
		63	u16 qam_if;
		64	u16 vsb_if;
		65
		66	/* Spectral Inversion */
		67	#define S5H1432_INVERSION_OFF 0
		68	#define S5H1432_INVERSION_ON 1
		69	u8 inversion;
		70
		71	/* Return lock status based on tuner lock, or demod lock */
		72	#define S5H1432_TUNERLOCKING 0
		73	#define S5H1432_DEMODLOCKING 1
		74	u8 status_mode;
		75	};
		76
		77	#if defined(CONFIG_DVB_S5H1432) \|\| \
		78	(defined(CONFIG_DVB_S5H1432_MODULE) && defined(MODULE))
		79	extern struct dvb_frontend s5h1432_attach(const struct s5h1432_config config,
		80	struct i2c_adapter *i2c);
		81	#else
		82	static inline struct dvb_frontend *s5h1432_attach(
		83	const struct s5h1432_config *config,
		84	struct i2c_adapter *i2c)
		85	{
		86	printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
		87	return NULL;
		88	}
		89	#endif /* CONFIG_DVB_s5h1432 */
		90
		91	#endif /* __s5h1432_H__ */
		92
		93	/*
		94	* Local variables:
		95	* c-basic-offset: 8
		96	*/