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authorMohammed Shafi Shajakhan <mohammed@qca.qualcomm.com>2012-06-18 03:43:30 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2012-07-16 11:47:39 -0400
commit3a3ca923be330c3a8b0f391d8e92040f4987eb21 (patch)
tree0febffa93e6bc72b63548cc2220481200ee062ad
parentde39eed0da6d7afcf2d758dc0e99811988a3bd06 (diff)
ath9k_hw: avoid possible infinite loop in ar9003_get_pll_sqsum_dvc
commit f18e3c6b67f448ec47b3a5b242789bd3d5644879 upstream. "ath9k: Fix softlockup in AR9485" with commit id 64bc1239c790e051ff677e023435d770d2ffa174 fixed the reported issue, yet its better to avoid the possible infinite loop in ar9003_get_pll_sqsum_dvc by having a timeout as suggested by ath9k maintainers. http://www.spinics.net/lists/linux-wireless/msg92126.html. Based on my testing PLL's locking measurement is done in ~200us (2 iterations). Cc: Rolf Offermanns <rolf.offermanns@gmx.net> Cc: Sujith Manoharan <c_manoha@qca.qualcomm.com> Cc: Senthil Balasubramanian <senthilb@qca.qualcomm.com> Signed-off-by: Mohammed Shafi Shajakhan <mohammed@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 7c2f06ed7a1..05320b9888b 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -682,13 +682,25 @@ static void ath9k_hw_init_qos(struct ath_hw *ah)
682 682
683u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah) 683u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
684{ 684{
685 struct ath_common *common = ath9k_hw_common(ah);
686 int i = 0;
687
685 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 688 REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
686 udelay(100); 689 udelay(100);
687 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); 690 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
688 691
689 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) 692 while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
693
690 udelay(100); 694 udelay(100);
691 695
696 if (WARN_ON_ONCE(i >= 100)) {
697 ath_err(common, "PLL4 meaurement not done\n");
698 break;
699 }
700
701 i++;
702 }
703
692 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3; 704 return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
693} 705}
694EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc); 706EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);