aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorPaul Mundt <lethal@linux-sh.org>2010-01-21 02:05:25 -0500
committerPaul Mundt <lethal@linux-sh.org>2010-01-21 02:05:25 -0500
commit2dc2f8e0c46864e2a3722c84eaa96513d4cf8b2f (patch)
tree8464625ad2cf3f5a7e567d37493a15ec3596a98b
parent3125ee72dca25fc2157dcddd07e2d740db921fc4 (diff)
sh: Kill off the special uncached section and fixmap.
Now that cached_to_uncached works as advertized in 32-bit mode and we're never going to be able to map < 16MB anyways, there's no need for the special uncached section. Kill it off. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/include/asm/fixmap.h4
-rw-r--r--arch/sh/include/asm/system_32.h3
-rw-r--r--arch/sh/include/asm/system_64.h2
-rw-r--r--arch/sh/kernel/cpu/init.c4
-rw-r--r--arch/sh/kernel/cpu/sh3/probe.c2
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7723.c3
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7724.c3
-rw-r--r--arch/sh/kernel/vmlinux.lds.S12
-rw-r--r--arch/sh/mm/cache-debugfs.c3
-rw-r--r--arch/sh/mm/cache-sh4.c4
-rw-r--r--arch/sh/mm/cache-sh7705.c4
-rw-r--r--arch/sh/mm/init.c3
-rw-r--r--arch/sh/mm/pmb.c6
-rw-r--r--arch/sh/mm/tlb-pteaex.c3
-rw-r--r--arch/sh/mm/tlb-sh4.c3
15 files changed, 20 insertions, 39 deletions
diff --git a/arch/sh/include/asm/fixmap.h b/arch/sh/include/asm/fixmap.h
index 38a1de86687..17b22b6c100 100644
--- a/arch/sh/include/asm/fixmap.h
+++ b/arch/sh/include/asm/fixmap.h
@@ -55,11 +55,12 @@ enum fixed_addresses {
55#define FIX_N_COLOURS 8 55#define FIX_N_COLOURS 8
56 FIX_CMAP_BEGIN, 56 FIX_CMAP_BEGIN,
57 FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS) - 1, 57 FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS) - 1,
58 FIX_UNCACHED, 58
59#ifdef CONFIG_HIGHMEM 59#ifdef CONFIG_HIGHMEM
60 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */ 60 FIX_KMAP_BEGIN, /* reserved pte's for temporary kernel mappings */
61 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1, 61 FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
62#endif 62#endif
63
63 /* 64 /*
64 * FIX_IOREMAP entries are useful for mapping physical address 65 * FIX_IOREMAP entries are useful for mapping physical address
65 * space before ioremap() is useable, e.g. really early in boot 66 * space before ioremap() is useable, e.g. really early in boot
@@ -68,6 +69,7 @@ enum fixed_addresses {
68#define FIX_N_IOREMAPS 32 69#define FIX_N_IOREMAPS 32
69 FIX_IOREMAP_BEGIN, 70 FIX_IOREMAP_BEGIN,
70 FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS, 71 FIX_IOREMAP_END = FIX_IOREMAP_BEGIN + FIX_N_IOREMAPS,
72
71 __end_of_fixed_addresses 73 __end_of_fixed_addresses
72}; 74};
73 75
diff --git a/arch/sh/include/asm/system_32.h b/arch/sh/include/asm/system_32.h
index 34bd2bac9a5..51296b36770 100644
--- a/arch/sh/include/asm/system_32.h
+++ b/arch/sh/include/asm/system_32.h
@@ -145,9 +145,6 @@ do { \
145 __restore_dsp(prev); \ 145 __restore_dsp(prev); \
146} while (0) 146} while (0)
147 147
148#define __uses_jump_to_uncached \
149 noinline __attribute__ ((__section__ (".uncached.text")))
150
151/* 148/*
152 * Jump to uncached area. 149 * Jump to uncached area.
153 * When handling TLB or caches, we need to do it from an uncached area. 150 * When handling TLB or caches, we need to do it from an uncached area.
diff --git a/arch/sh/include/asm/system_64.h b/arch/sh/include/asm/system_64.h
index 604ba7802cc..3391bb6b21d 100644
--- a/arch/sh/include/asm/system_64.h
+++ b/arch/sh/include/asm/system_64.h
@@ -33,8 +33,6 @@ do { \
33 &next->thread); \ 33 &next->thread); \
34} while (0) 34} while (0)
35 35
36#define __uses_jump_to_uncached
37
38#define jump_to_uncached() do { } while (0) 36#define jump_to_uncached() do { } while (0)
39#define back_to_cached() do { } while (0) 37#define back_to_cached() do { } while (0)
40 38
diff --git a/arch/sh/kernel/cpu/init.c b/arch/sh/kernel/cpu/init.c
index a5bb0550bbf..05a7d2a373b 100644
--- a/arch/sh/kernel/cpu/init.c
+++ b/arch/sh/kernel/cpu/init.c
@@ -98,7 +98,7 @@ static void __init expmask_init(void)
98#endif 98#endif
99 99
100/* 2nd-level cache init */ 100/* 2nd-level cache init */
101void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void) 101void __attribute__ ((weak)) l2_cache_init(void)
102{ 102{
103} 103}
104 104
@@ -106,7 +106,7 @@ void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
106 * Generic first-level cache init 106 * Generic first-level cache init
107 */ 107 */
108#ifdef CONFIG_SUPERH32 108#ifdef CONFIG_SUPERH32
109static void __uses_jump_to_uncached cache_init(void) 109static void cache_init(void)
110{ 110{
111 unsigned long ccr, flags; 111 unsigned long ccr, flags;
112 112
diff --git a/arch/sh/kernel/cpu/sh3/probe.c b/arch/sh/kernel/cpu/sh3/probe.c
index f9c7df64eb0..c2db65719f4 100644
--- a/arch/sh/kernel/cpu/sh3/probe.c
+++ b/arch/sh/kernel/cpu/sh3/probe.c
@@ -16,7 +16,7 @@
16#include <asm/cache.h> 16#include <asm/cache.h>
17#include <asm/io.h> 17#include <asm/io.h>
18 18
19int __uses_jump_to_uncached detect_cpu_and_cache_system(void) 19int detect_cpu_and_cache_system(void)
20{ 20{
21 unsigned long addr0, addr1, data0, data1, data2, data3; 21 unsigned long addr0, addr1, data0, data1, data2, data3;
22 22
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
index 772b9265d0e..9d426258aa0 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7723.c
@@ -592,7 +592,8 @@ void __init plat_early_device_setup(void)
592#define RAMCR_CACHE_L2FC 0x0002 592#define RAMCR_CACHE_L2FC 0x0002
593#define RAMCR_CACHE_L2E 0x0001 593#define RAMCR_CACHE_L2E 0x0001
594#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 594#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
595void __uses_jump_to_uncached l2_cache_init(void) 595
596void l2_cache_init(void)
596{ 597{
597 /* Enable L2 cache */ 598 /* Enable L2 cache */
598 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 599 ctrl_outl(L2_CACHE_ENABLE, RAMCR);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
index d32f96c1cc1..578e9f80271 100644
--- a/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7724.c
@@ -714,7 +714,8 @@ void __init plat_early_device_setup(void)
714#define RAMCR_CACHE_L2FC 0x0002 714#define RAMCR_CACHE_L2FC 0x0002
715#define RAMCR_CACHE_L2E 0x0001 715#define RAMCR_CACHE_L2E 0x0001
716#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC) 716#define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
717void __uses_jump_to_uncached l2_cache_init(void) 717
718void l2_cache_init(void)
718{ 719{
719 /* Enable L2 cache */ 720 /* Enable L2 cache */
720 ctrl_outl(L2_CACHE_ENABLE, RAMCR); 721 ctrl_outl(L2_CACHE_ENABLE, RAMCR);
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index 9e5a5878eea..93e9b25a181 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -53,18 +53,6 @@ SECTIONS
53 53
54 NOTES 54 NOTES
55 RO_DATA(PAGE_SIZE) 55 RO_DATA(PAGE_SIZE)
56
57 /*
58 * Code which must be executed uncached and the associated data
59 */
60 . = ALIGN(PAGE_SIZE);
61 .uncached : AT(ADDR(.uncached) - LOAD_OFFSET) {
62 __uncached_start = .;
63 *(.uncached.text)
64 *(.uncached.data)
65 __uncached_end = .;
66 }
67
68 RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE) 56 RW_DATA_SECTION(L1_CACHE_BYTES, PAGE_SIZE, THREAD_SIZE)
69 57
70 _edata = .; /* End of data section */ 58 _edata = .; /* End of data section */
diff --git a/arch/sh/mm/cache-debugfs.c b/arch/sh/mm/cache-debugfs.c
index 5ba067b2659..48ce82ee9fd 100644
--- a/arch/sh/mm/cache-debugfs.c
+++ b/arch/sh/mm/cache-debugfs.c
@@ -22,8 +22,7 @@ enum cache_type {
22 CACHE_TYPE_UNIFIED, 22 CACHE_TYPE_UNIFIED,
23}; 23};
24 24
25static int __uses_jump_to_uncached cache_seq_show(struct seq_file *file, 25static int cache_seq_show(struct seq_file *file, void *iter)
26 void *iter)
27{ 26{
28 unsigned int cache_type = (unsigned int)file->private; 27 unsigned int cache_type = (unsigned int)file->private;
29 struct cache_info *cache; 28 struct cache_info *cache;
diff --git a/arch/sh/mm/cache-sh4.c b/arch/sh/mm/cache-sh4.c
index a2301daeefa..87115b3ee70 100644
--- a/arch/sh/mm/cache-sh4.c
+++ b/arch/sh/mm/cache-sh4.c
@@ -36,7 +36,7 @@ static void __flush_cache_one(unsigned long addr, unsigned long phys,
36 * Called from kernel/module.c:sys_init_module and routine for a.out format, 36 * Called from kernel/module.c:sys_init_module and routine for a.out format,
37 * signal handler code and kprobes code 37 * signal handler code and kprobes code
38 */ 38 */
39static void __uses_jump_to_uncached sh4_flush_icache_range(void *args) 39static void sh4_flush_icache_range(void *args)
40{ 40{
41 struct flusher_data *data = args; 41 struct flusher_data *data = args;
42 unsigned long start, end; 42 unsigned long start, end;
@@ -124,7 +124,7 @@ static void sh4_flush_dcache_page(void *arg)
124} 124}
125 125
126/* TODO: Selective icache invalidation through IC address array.. */ 126/* TODO: Selective icache invalidation through IC address array.. */
127static void __uses_jump_to_uncached flush_icache_all(void) 127static void flush_icache_all(void)
128{ 128{
129 unsigned long flags, ccr; 129 unsigned long flags, ccr;
130 130
diff --git a/arch/sh/mm/cache-sh7705.c b/arch/sh/mm/cache-sh7705.c
index f527fb70fce..870293ee539 100644
--- a/arch/sh/mm/cache-sh7705.c
+++ b/arch/sh/mm/cache-sh7705.c
@@ -78,7 +78,7 @@ static void sh7705_flush_icache_range(void *args)
78/* 78/*
79 * Writeback&Invalidate the D-cache of the page 79 * Writeback&Invalidate the D-cache of the page
80 */ 80 */
81static void __uses_jump_to_uncached __flush_dcache_page(unsigned long phys) 81static void __flush_dcache_page(unsigned long phys)
82{ 82{
83 unsigned long ways, waysize, addrstart; 83 unsigned long ways, waysize, addrstart;
84 unsigned long flags; 84 unsigned long flags;
@@ -144,7 +144,7 @@ static void sh7705_flush_dcache_page(void *arg)
144 __flush_dcache_page(__pa(page_address(page))); 144 __flush_dcache_page(__pa(page_address(page)));
145} 145}
146 146
147static void __uses_jump_to_uncached sh7705_flush_cache_all(void *args) 147static void sh7705_flush_cache_all(void *args)
148{ 148{
149 unsigned long flags; 149 unsigned long flags;
150 150
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index a28ff63c17a..dffa6c74948 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -211,9 +211,6 @@ void __init paging_init(void)
211 } 211 }
212 212
213 free_area_init_nodes(max_zone_pfns); 213 free_area_init_nodes(max_zone_pfns);
214
215 /* Set up the uncached fixmap */
216 set_fixmap_nocache(FIX_UNCACHED, __pa(&__uncached_start));
217} 214}
218 215
219/* 216/*
diff --git a/arch/sh/mm/pmb.c b/arch/sh/mm/pmb.c
index d318fa6caff..3d5eece7e6d 100644
--- a/arch/sh/mm/pmb.c
+++ b/arch/sh/mm/pmb.c
@@ -127,14 +127,14 @@ static void __set_pmb_entry(unsigned long vpn, unsigned long ppn,
127 ctrl_outl(ppn | flags | PMB_V, mk_pmb_data(pos)); 127 ctrl_outl(ppn | flags | PMB_V, mk_pmb_data(pos));
128} 128}
129 129
130static void __uses_jump_to_uncached set_pmb_entry(struct pmb_entry *pmbe) 130static void set_pmb_entry(struct pmb_entry *pmbe)
131{ 131{
132 jump_to_uncached(); 132 jump_to_uncached();
133 __set_pmb_entry(pmbe->vpn, pmbe->ppn, pmbe->flags, pmbe->entry); 133 __set_pmb_entry(pmbe->vpn, pmbe->ppn, pmbe->flags, pmbe->entry);
134 back_to_cached(); 134 back_to_cached();
135} 135}
136 136
137static void __uses_jump_to_uncached clear_pmb_entry(struct pmb_entry *pmbe) 137static void clear_pmb_entry(struct pmb_entry *pmbe)
138{ 138{
139 unsigned int entry = pmbe->entry; 139 unsigned int entry = pmbe->entry;
140 unsigned long addr; 140 unsigned long addr;
@@ -364,7 +364,7 @@ static inline int pmb_apply_legacy_mappings(void)
364} 364}
365#endif 365#endif
366 366
367int __uses_jump_to_uncached pmb_init(void) 367int pmb_init(void)
368{ 368{
369 int i; 369 int i;
370 unsigned long addr, data; 370 unsigned long addr, data;
diff --git a/arch/sh/mm/tlb-pteaex.c b/arch/sh/mm/tlb-pteaex.c
index 409b7c2b4b9..32dc674c550 100644
--- a/arch/sh/mm/tlb-pteaex.c
+++ b/arch/sh/mm/tlb-pteaex.c
@@ -68,8 +68,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
68 * in extended mode, the legacy 8-bit ASID field in address array 1 has 68 * in extended mode, the legacy 8-bit ASID field in address array 1 has
69 * undefined behaviour. 69 * undefined behaviour.
70 */ 70 */
71void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid, 71void local_flush_tlb_one(unsigned long asid, unsigned long page)
72 unsigned long page)
73{ 72{
74 jump_to_uncached(); 73 jump_to_uncached();
75 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT); 74 __raw_writel(page, MMU_UTLB_ADDRESS_ARRAY | MMU_PAGE_ASSOC_BIT);
diff --git a/arch/sh/mm/tlb-sh4.c b/arch/sh/mm/tlb-sh4.c
index 8cf550e2570..624c1daa9f3 100644
--- a/arch/sh/mm/tlb-sh4.c
+++ b/arch/sh/mm/tlb-sh4.c
@@ -64,8 +64,7 @@ void __update_tlb(struct vm_area_struct *vma, unsigned long address, pte_t pte)
64 local_irq_restore(flags); 64 local_irq_restore(flags);
65} 65}
66 66
67void __uses_jump_to_uncached local_flush_tlb_one(unsigned long asid, 67void local_flush_tlb_one(unsigned long asid, unsigned long page)
68 unsigned long page)
69{ 68{
70 unsigned long addr, data; 69 unsigned long addr, data;
71 70