diff options
author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-21 12:20:47 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-21 12:20:47 -0500 |
commit | 28c006c1f09ea92d4f2585a087a188955ce3f64c (patch) | |
tree | 2615749653cd3ba4852d2f5ed22f21eec0cd5712 | |
parent | cbe037b46f564188045937e6006c5c1d6093618a (diff) | |
parent | 7abe53155b77c31028a7158883bc9aac705790da (diff) |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] Fix cosmetic typo in asm/irq.h
[ARM] 3367/1: CLCD mode no longer supported on the RealView boards
[ARM] 3366/1: Allow the 16bpp mode configuration in the CLCD control register
-rw-r--r-- | arch/arm/mach-realview/core.c | 28 | ||||
-rw-r--r-- | include/asm-arm/irq.h | 2 | ||||
-rw-r--r-- | include/linux/amba/clcd.h | 12 |
3 files changed, 14 insertions, 28 deletions
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 4303d988c4b..d13270c5d7c 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
@@ -202,11 +202,6 @@ struct clk realview_clcd_clk = { | |||
202 | /* | 202 | /* |
203 | * CLCD support. | 203 | * CLCD support. |
204 | */ | 204 | */ |
205 | #define SYS_CLCD_MODE_MASK (3 << 0) | ||
206 | #define SYS_CLCD_MODE_888 (0 << 0) | ||
207 | #define SYS_CLCD_MODE_5551 (1 << 0) | ||
208 | #define SYS_CLCD_MODE_565_RLSB (2 << 0) | ||
209 | #define SYS_CLCD_MODE_565_BLSB (3 << 0) | ||
210 | #define SYS_CLCD_NLCDIOON (1 << 2) | 205 | #define SYS_CLCD_NLCDIOON (1 << 2) |
211 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) | 206 | #define SYS_CLCD_VDDPOSSWITCH (1 << 3) |
212 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) | 207 | #define SYS_CLCD_PWR3V5SWITCH (1 << 4) |
@@ -360,29 +355,10 @@ static void realview_clcd_enable(struct clcd_fb *fb) | |||
360 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; | 355 | void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; |
361 | u32 val; | 356 | u32 val; |
362 | 357 | ||
363 | val = readl(sys_clcd); | ||
364 | val &= ~SYS_CLCD_MODE_MASK; | ||
365 | |||
366 | switch (fb->fb.var.green.length) { | ||
367 | case 5: | ||
368 | val |= SYS_CLCD_MODE_5551; | ||
369 | break; | ||
370 | case 6: | ||
371 | val |= SYS_CLCD_MODE_565_RLSB; | ||
372 | break; | ||
373 | case 8: | ||
374 | val |= SYS_CLCD_MODE_888; | ||
375 | break; | ||
376 | } | ||
377 | |||
378 | /* | ||
379 | * Set the MUX | ||
380 | */ | ||
381 | writel(val, sys_clcd); | ||
382 | |||
383 | /* | 358 | /* |
384 | * And now enable the PSUs | 359 | * Enable the PSUs |
385 | */ | 360 | */ |
361 | val = readl(sys_clcd); | ||
386 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; | 362 | val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; |
387 | writel(val, sys_clcd); | 363 | writel(val, sys_clcd); |
388 | } | 364 | } |
diff --git a/include/asm-arm/irq.h b/include/asm-arm/irq.h index 7772432d3fd..60b5105c9c9 100644 --- a/include/asm-arm/irq.h +++ b/include/asm-arm/irq.h | |||
@@ -27,7 +27,7 @@ extern void enable_irq(unsigned int); | |||
27 | 27 | ||
28 | /* | 28 | /* |
29 | * These correspond with the SA_TRIGGER_* defines, and therefore the | 29 | * These correspond with the SA_TRIGGER_* defines, and therefore the |
30 | * IRQRESOURCE_IRQ_* defines. | 30 | * IORESOURCE_IRQ_* defines. |
31 | */ | 31 | */ |
32 | #define __IRQT_RISEDGE (1 << 0) | 32 | #define __IRQT_RISEDGE (1 << 0) |
33 | #define __IRQT_FALEDGE (1 << 1) | 33 | #define __IRQT_FALEDGE (1 << 1) |
diff --git a/include/linux/amba/clcd.h b/include/linux/amba/clcd.h index 6b8d73dc1ab..9cf64b1b688 100644 --- a/include/linux/amba/clcd.h +++ b/include/linux/amba/clcd.h | |||
@@ -54,6 +54,7 @@ | |||
54 | #define CNTL_LCDBPP4 (2 << 1) | 54 | #define CNTL_LCDBPP4 (2 << 1) |
55 | #define CNTL_LCDBPP8 (3 << 1) | 55 | #define CNTL_LCDBPP8 (3 << 1) |
56 | #define CNTL_LCDBPP16 (4 << 1) | 56 | #define CNTL_LCDBPP16 (4 << 1) |
57 | #define CNTL_LCDBPP16_565 (6 << 1) | ||
57 | #define CNTL_LCDBPP24 (5 << 1) | 58 | #define CNTL_LCDBPP24 (5 << 1) |
58 | #define CNTL_LCDBW (1 << 4) | 59 | #define CNTL_LCDBW (1 << 4) |
59 | #define CNTL_LCDTFT (1 << 5) | 60 | #define CNTL_LCDTFT (1 << 5) |
@@ -209,7 +210,16 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs) | |||
209 | val |= CNTL_LCDBPP8; | 210 | val |= CNTL_LCDBPP8; |
210 | break; | 211 | break; |
211 | case 16: | 212 | case 16: |
212 | val |= CNTL_LCDBPP16; | 213 | /* |
214 | * PL110 cannot choose between 5551 and 565 modes in | ||
215 | * its control register | ||
216 | */ | ||
217 | if ((fb->dev->periphid & 0x000fffff) == 0x00041110) | ||
218 | val |= CNTL_LCDBPP16; | ||
219 | else if (fb->fb.var.green.length == 5) | ||
220 | val |= CNTL_LCDBPP16; | ||
221 | else | ||
222 | val |= CNTL_LCDBPP16_565; | ||
213 | break; | 223 | break; |
214 | case 32: | 224 | case 32: |
215 | val |= CNTL_LCDBPP24; | 225 | val |= CNTL_LCDBPP24; |