diff options
author | Magnus Damm <damm@igel.co.jp> | 2009-07-31 03:01:36 -0400 |
---|---|---|
committer | Paul Mundt <lethal@linux-sh.org> | 2009-08-04 01:40:58 -0400 |
commit | 133b170f08d6c20578f25b1ae71f80a5e638ccb6 (patch) | |
tree | ef9ffba4f24f413e1e67ba732b684c75b7d84da8 | |
parent | 6ba4a8f0f542e791e4158c91a844234b142578dc (diff) |
sh: clean up MSTPCRn register definitions
This patch removes the unused MSTPCRn register definitions
from the SuperH Mobile code for sh7722, sh7723 and sh7724.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7722.c | 3 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7723.c | 3 | ||||
-rw-r--r-- | arch/sh/kernel/cpu/sh4a/clock-sh7724.c | 3 |
3 files changed, 0 insertions, 9 deletions
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c index 1fa9e1dd1cc..5b1bbbe63b1 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7722.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7722.c | |||
@@ -32,9 +32,6 @@ | |||
32 | #define SCLKBCR 0xa415000c | 32 | #define SCLKBCR 0xa415000c |
33 | #define IRDACLKCR 0xa4150018 | 33 | #define IRDACLKCR 0xa4150018 |
34 | #define PLLCR 0xa4150024 | 34 | #define PLLCR 0xa4150024 |
35 | #define MSTPCR0 0xa4150030 | ||
36 | #define MSTPCR1 0xa4150034 | ||
37 | #define MSTPCR2 0xa4150038 | ||
38 | #define DLLFRQ 0xa4150050 | 35 | #define DLLFRQ 0xa4150050 |
39 | 36 | ||
40 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | 37 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c index bf64c78eee3..e5c63911403 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7723.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7723.c | |||
@@ -32,9 +32,6 @@ | |||
32 | #define SCLKBCR 0xa415000c | 32 | #define SCLKBCR 0xa415000c |
33 | #define IRDACLKCR 0xa4150018 | 33 | #define IRDACLKCR 0xa4150018 |
34 | #define PLLCR 0xa4150024 | 34 | #define PLLCR 0xa4150024 |
35 | #define MSTPCR0 0xa4150030 | ||
36 | #define MSTPCR1 0xa4150034 | ||
37 | #define MSTPCR2 0xa4150038 | ||
38 | #define DLLFRQ 0xa4150050 | 35 | #define DLLFRQ 0xa4150050 |
39 | 36 | ||
40 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ | 37 | /* Fixed 32 KHz root clock for RTC and Power Management purposes */ |
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c index ba24e38c9fc..34611d97378 100644 --- a/arch/sh/kernel/cpu/sh4a/clock-sh7724.c +++ b/arch/sh/kernel/cpu/sh4a/clock-sh7724.c | |||
@@ -33,9 +33,6 @@ | |||
33 | #define FCLKBCR 0xa415000c | 33 | #define FCLKBCR 0xa415000c |
34 | #define IRDACLKCR 0xa4150018 | 34 | #define IRDACLKCR 0xa4150018 |
35 | #define PLLCR 0xa4150024 | 35 | #define PLLCR 0xa4150024 |
36 | #define MSTPCR0 0xa4150030 | ||
37 | #define MSTPCR1 0xa4150034 | ||
38 | #define MSTPCR2 0xa4150038 | ||
39 | #define SPUCLKCR 0xa415003c | 36 | #define SPUCLKCR 0xa415003c |
40 | #define FLLFRQ 0xa4150050 | 37 | #define FLLFRQ 0xa4150050 |
41 | #define LSTATS 0xa4150060 | 38 | #define LSTATS 0xa4150060 |