aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@linux-foundation.org>2011-06-07 22:09:17 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-06-07 22:09:17 -0400
commit12871a0bd67dd4db4418e1daafcd46e9d329ef10 (patch)
treefaf782dd816040d6cdaaccd7113956d8d29cd0e5
parentecff4fcc7bbaf060646d2160123f8dc02605a047 (diff)
parentf3aeceac61b6e2f3167717ea1793472108e47564 (diff)
Merge branch 'drm-radeon-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-radeon-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: drm/radeon/kms/atom: fix PHY init drm/radeon/kms: add missing Evergreen texture formats to the CS parser drm/radeon/kms: viewport height has to be even drm/radeon/kms: remove duplicate reg from r600 safe regs drm/radeon/kms: add support for Llano Fusion APUs drm/radeon/kms: add llano pci ids drm/radeon/kms: fill in asic struct for llano drm/radeon/kms: add family ids for llano APUs drm/radeon: fix oops in ttm reserve when pageflipping (v2) drm/radeon/kms: clean up the radeon kms Kconfig drm/radeon/kms: fix thermal sensor reading on juniper drm/radeon/kms: add missing case for cayman thermal sensor drm/radeon/kms: add blit support for cayman (v2) drm/radeon/kms/blit: workaround some hw issues on evergreen+
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/Kconfig9
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c12
-rw-r--r--drivers/gpu/drm/radeon/cayman_blit_shaders.c326
-rw-r--r--drivers/gpu/drm/radeon/cayman_blit_shaders.h3
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c104
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c561
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h8
-rw-r--r--drivers/gpu/drm/radeon/ni.c13
-rw-r--r--drivers/gpu/drm/radeon/r600.c12
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c28
-rw-r--r--drivers/gpu/drm/radeon/r600d.h3
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c8
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_display.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c17
-rw-r--r--drivers/gpu/drm/radeon/radeon_family.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c1
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r6001
-rw-r--r--include/drm/drm_pciids.h11
19 files changed, 830 insertions, 304 deletions
diff --git a/drivers/gpu/drm/radeon/Kconfig b/drivers/gpu/drm/radeon/Kconfig
index 9746fee59f5..ea92bbe3ed3 100644
--- a/drivers/gpu/drm/radeon/Kconfig
+++ b/drivers/gpu/drm/radeon/Kconfig
@@ -28,11 +28,4 @@ config DRM_RADEON_KMS
28 The kernel will also perform security check on command stream 28 The kernel will also perform security check on command stream
29 provided by the user, we want to catch and forbid any illegal use 29 provided by the user, we want to catch and forbid any illegal use
30 of the GPU such as DMA into random system memory or into memory 30 of the GPU such as DMA into random system memory or into memory
31 not owned by the process supplying the command stream. This part 31 not owned by the process supplying the command stream.
32 of the code is still incomplete and this why we propose that patch
33 as a staging driver addition, future security might forbid current
34 experimental userspace to run.
35
36 This code support the following hardware : R1XX,R2XX,R3XX,R4XX,R5XX
37 (radeon up to X1950). Works is underway to provide support for R6XX,
38 R7XX and newer hardware (radeon from HD2XXX to HD4XXX).
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index ec848787d7d..84a69e7fa11 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1045,7 +1045,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1045 uint64_t fb_location; 1045 uint64_t fb_location;
1046 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1046 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1047 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE); 1047 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1048 u32 tmp; 1048 u32 tmp, viewport_w, viewport_h;
1049 int r; 1049 int r;
1050 1050
1051 /* no fb bound */ 1051 /* no fb bound */
@@ -1171,8 +1171,10 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1171 y &= ~1; 1171 y &= ~1;
1172 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset, 1172 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1173 (x << 16) | y); 1173 (x << 16) | y);
1174 viewport_w = crtc->mode.hdisplay;
1175 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1174 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1176 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1175 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 1177 (viewport_w << 16) | viewport_h);
1176 1178
1177 /* pageflip setup */ 1179 /* pageflip setup */
1178 /* make sure flip is at vb rather than hb */ 1180 /* make sure flip is at vb rather than hb */
@@ -1213,7 +1215,7 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1213 uint64_t fb_location; 1215 uint64_t fb_location;
1214 uint32_t fb_format, fb_pitch_pixels, tiling_flags; 1216 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1215 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; 1217 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1216 u32 tmp; 1218 u32 tmp, viewport_w, viewport_h;
1217 int r; 1219 int r;
1218 1220
1219 /* no fb bound */ 1221 /* no fb bound */
@@ -1338,8 +1340,10 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1338 y &= ~1; 1340 y &= ~1;
1339 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, 1341 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1340 (x << 16) | y); 1342 (x << 16) | y);
1343 viewport_w = crtc->mode.hdisplay;
1344 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1341 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, 1345 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1342 (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); 1346 (viewport_w << 16) | viewport_h);
1343 1347
1344 /* pageflip setup */ 1348 /* pageflip setup */
1345 /* make sure flip is at vb rather than hb */ 1349 /* make sure flip is at vb rather than hb */
diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.c b/drivers/gpu/drm/radeon/cayman_blit_shaders.c
index e148ab04b80..7b4eeb7b4a8 100644
--- a/drivers/gpu/drm/radeon/cayman_blit_shaders.c
+++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.c
@@ -39,17 +39,335 @@
39 39
40const u32 cayman_default_state[] = 40const u32 cayman_default_state[] =
41{ 41{
42 /* XXX fill in additional blit state */ 42 0xc0066900,
43 0x00000000,
44 0x00000060, /* DB_RENDER_CONTROL */
45 0x00000000, /* DB_COUNT_CONTROL */
46 0x00000000, /* DB_DEPTH_VIEW */
47 0x0000002a, /* DB_RENDER_OVERRIDE */
48 0x00000000, /* DB_RENDER_OVERRIDE2 */
49 0x00000000, /* DB_HTILE_DATA_BASE */
43 50
44 0xc0026900, 51 0xc0026900,
45 0x00000316, 52 0x0000000a,
46 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 53 0x00000000, /* DB_STENCIL_CLEAR */
47 0x00000010, /* */ 54 0x00000000, /* DB_DEPTH_CLEAR */
55
56 0xc0036900,
57 0x0000000f,
58 0x00000000, /* DB_DEPTH_INFO */
59 0x00000000, /* DB_Z_INFO */
60 0x00000000, /* DB_STENCIL_INFO */
61
62 0xc0016900,
63 0x00000080,
64 0x00000000, /* PA_SC_WINDOW_OFFSET */
65
66 0xc00d6900,
67 0x00000083,
68 0x0000ffff, /* PA_SC_CLIPRECT_RULE */
69 0x00000000, /* PA_SC_CLIPRECT_0_TL */
70 0x20002000, /* PA_SC_CLIPRECT_0_BR */
71 0x00000000,
72 0x20002000,
73 0x00000000,
74 0x20002000,
75 0x00000000,
76 0x20002000,
77 0xaaaaaaaa, /* PA_SC_EDGERULE */
78 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
79 0x0000000f, /* CB_TARGET_MASK */
80 0x0000000f, /* CB_SHADER_MASK */
81
82 0xc0226900,
83 0x00000094,
84 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
85 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
86 0x80000000,
87 0x20002000,
88 0x80000000,
89 0x20002000,
90 0x80000000,
91 0x20002000,
92 0x80000000,
93 0x20002000,
94 0x80000000,
95 0x20002000,
96 0x80000000,
97 0x20002000,
98 0x80000000,
99 0x20002000,
100 0x80000000,
101 0x20002000,
102 0x80000000,
103 0x20002000,
104 0x80000000,
105 0x20002000,
106 0x80000000,
107 0x20002000,
108 0x80000000,
109 0x20002000,
110 0x80000000,
111 0x20002000,
112 0x80000000,
113 0x20002000,
114 0x80000000,
115 0x20002000,
116 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
117 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
118
119 0xc0016900,
120 0x000000d4,
121 0x00000000, /* SX_MISC */
48 122
49 0xc0026900, 123 0xc0026900,
50 0x000000d9, 124 0x000000d9,
51 0x00000000, /* CP_RINGID */ 125 0x00000000, /* CP_RINGID */
52 0x00000000, /* CP_VMID */ 126 0x00000000, /* CP_VMID */
127
128 0xc0096900,
129 0x00000100,
130 0x00ffffff, /* VGT_MAX_VTX_INDX */
131 0x00000000, /* VGT_MIN_VTX_INDX */
132 0x00000000, /* VGT_INDX_OFFSET */
133 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
134 0x00000000, /* SX_ALPHA_TEST_CONTROL */
135 0x00000000, /* CB_BLEND_RED */
136 0x00000000, /* CB_BLEND_GREEN */
137 0x00000000, /* CB_BLEND_BLUE */
138 0x00000000, /* CB_BLEND_ALPHA */
139
140 0xc0016900,
141 0x00000187,
142 0x00000100, /* SPI_VS_OUT_ID_0 */
143
144 0xc0026900,
145 0x00000191,
146 0x00000100, /* SPI_PS_INPUT_CNTL_0 */
147 0x00000101, /* SPI_PS_INPUT_CNTL_1 */
148
149 0xc0016900,
150 0x000001b1,
151 0x00000000, /* SPI_VS_OUT_CONFIG */
152
153 0xc0106900,
154 0x000001b3,
155 0x20000001, /* SPI_PS_IN_CONTROL_0 */
156 0x00000000, /* SPI_PS_IN_CONTROL_1 */
157 0x00000000, /* SPI_INTERP_CONTROL_0 */
158 0x00000000, /* SPI_INPUT_Z */
159 0x00000000, /* SPI_FOG_CNTL */
160 0x00100000, /* SPI_BARYC_CNTL */
161 0x00000000, /* SPI_PS_IN_CONTROL_2 */
162 0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
163 0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
164 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
165 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
166 0x00000000, /* SPI_GPR_MGMT */
167 0x00000000, /* SPI_LDS_MGMT */
168 0x00000000, /* SPI_STACK_MGMT */
169 0x00000000, /* SPI_WAVE_MGMT_1 */
170 0x00000000, /* SPI_WAVE_MGMT_2 */
171
172 0xc0016900,
173 0x000001e0,
174 0x00000000, /* CB_BLEND0_CONTROL */
175
176 0xc00e6900,
177 0x00000200,
178 0x00000000, /* DB_DEPTH_CONTROL */
179 0x00000000, /* DB_EQAA */
180 0x00cc0010, /* CB_COLOR_CONTROL */
181 0x00000210, /* DB_SHADER_CONTROL */
182 0x00010000, /* PA_CL_CLIP_CNTL */
183 0x00000004, /* PA_SU_SC_MODE_CNTL */
184 0x00000100, /* PA_CL_VTE_CNTL */
185 0x00000000, /* PA_CL_VS_OUT_CNTL */
186 0x00000000, /* PA_CL_NANINF_CNTL */
187 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
188 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
189 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
190 0x00000000, /* */
191 0x00000000, /* */
192
193 0xc0026900,
194 0x00000229,
195 0x00000000, /* SQ_PGM_START_FS */
196 0x00000000,
197
198 0xc0016900,
199 0x0000023b,
200 0x00000000, /* SQ_LDS_ALLOC_PS */
201
202 0xc0066900,
203 0x00000240,
204 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
205 0x00000000,
206 0x00000000,
207 0x00000000,
208 0x00000000,
209 0x00000000,
210
211 0xc0046900,
212 0x00000247,
213 0x00000000, /* SQ_GS_VERT_ITEMSIZE */
214 0x00000000,
215 0x00000000,
216 0x00000000,
217
218 0xc0116900,
219 0x00000280,
220 0x00000000, /* PA_SU_POINT_SIZE */
221 0x00000000, /* PA_SU_POINT_MINMAX */
222 0x00000008, /* PA_SU_LINE_CNTL */
223 0x00000000, /* PA_SC_LINE_STIPPLE */
224 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
225 0x00000000, /* VGT_HOS_CNTL */
226 0x00000000,
227 0x00000000,
228 0x00000000,
229 0x00000000,
230 0x00000000,
231 0x00000000,
232 0x00000000,
233 0x00000000,
234 0x00000000,
235 0x00000000,
236 0x00000000, /* VGT_GS_MODE */
237
238 0xc0026900,
239 0x00000292,
240 0x00000000, /* PA_SC_MODE_CNTL_0 */
241 0x00000000, /* PA_SC_MODE_CNTL_1 */
242
243 0xc0016900,
244 0x000002a1,
245 0x00000000, /* VGT_PRIMITIVEID_EN */
246
247 0xc0016900,
248 0x000002a5,
249 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
250
251 0xc0026900,
252 0x000002a8,
253 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
254 0x00000000,
255
256 0xc0026900,
257 0x000002ad,
258 0x00000000, /* VGT_REUSE_OFF */
259 0x00000000,
260
261 0xc0016900,
262 0x000002d5,
263 0x00000000, /* VGT_SHADER_STAGES_EN */
264
265 0xc0016900,
266 0x000002dc,
267 0x0000aa00, /* DB_ALPHA_TO_MASK */
268
269 0xc0066900,
270 0x000002de,
271 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
272 0x00000000,
273 0x00000000,
274 0x00000000,
275 0x00000000,
276 0x00000000,
277
278 0xc0026900,
279 0x000002e5,
280 0x00000000, /* VGT_STRMOUT_CONFIG */
281 0x00000000,
282
283 0xc01b6900,
284 0x000002f5,
285 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
286 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
287 0x00000000, /* PA_SC_LINE_CNTL */
288 0x00000000, /* PA_SC_AA_CONFIG */
289 0x00000005, /* PA_SU_VTX_CNTL */
290 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
291 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
292 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
293 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
294 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
295 0x00000000,
296 0x00000000,
297 0x00000000,
298 0x00000000,
299 0x00000000,
300 0x00000000,
301 0x00000000,
302 0x00000000,
303 0x00000000,
304 0x00000000,
305 0x00000000,
306 0x00000000,
307 0x00000000,
308 0x00000000,
309 0x00000000,
310 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
311 0xffffffff,
312
313 0xc0026900,
314 0x00000316,
315 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
316 0x00000010, /* */
317};
318
319const u32 cayman_vs[] =
320{
321 0x00000004,
322 0x80400400,
323 0x0000a03c,
324 0x95000688,
325 0x00004000,
326 0x15000688,
327 0x00000000,
328 0x88000000,
329 0x04000000,
330 0x67961001,
331#ifdef __BIG_ENDIAN
332 0x00020000,
333#else
334 0x00000000,
335#endif
336 0x00000000,
337 0x04000000,
338 0x67961000,
339#ifdef __BIG_ENDIAN
340 0x00020008,
341#else
342 0x00000008,
343#endif
344 0x00000000,
345};
346
347const u32 cayman_ps[] =
348{
349 0x00000004,
350 0xa00c0000,
351 0x00000008,
352 0x80400000,
353 0x00000000,
354 0x95000688,
355 0x00000000,
356 0x88000000,
357 0x00380400,
358 0x00146b10,
359 0x00380000,
360 0x20146b10,
361 0x00380400,
362 0x40146b00,
363 0x80380000,
364 0x60146b00,
365 0x00000010,
366 0x000d1000,
367 0xb0800000,
368 0x00000000,
53}; 369};
54 370
371const u32 cayman_ps_size = ARRAY_SIZE(cayman_ps);
372const u32 cayman_vs_size = ARRAY_SIZE(cayman_vs);
55const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state); 373const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.h b/drivers/gpu/drm/radeon/cayman_blit_shaders.h
index 33b75e5d0fa..f5d0e9a6026 100644
--- a/drivers/gpu/drm/radeon/cayman_blit_shaders.h
+++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.h
@@ -25,8 +25,11 @@
25#ifndef CAYMAN_BLIT_SHADERS_H 25#ifndef CAYMAN_BLIT_SHADERS_H
26#define CAYMAN_BLIT_SHADERS_H 26#define CAYMAN_BLIT_SHADERS_H
27 27
28extern const u32 cayman_ps[];
29extern const u32 cayman_vs[];
28extern const u32 cayman_default_state[]; 30extern const u32 cayman_default_state[];
29 31
32extern const u32 cayman_ps_size, cayman_vs_size;
30extern const u32 cayman_default_size; 33extern const u32 cayman_default_size;
31 34
32#endif 35#endif
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 7c37638095f..98ea597bc76 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -88,21 +88,39 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
88/* get temperature in millidegrees */ 88/* get temperature in millidegrees */
89int evergreen_get_temp(struct radeon_device *rdev) 89int evergreen_get_temp(struct radeon_device *rdev)
90{ 90{
91 u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >> 91 u32 temp, toffset, actual_temp = 0;
92 ASIC_T_SHIFT; 92
93 u32 actual_temp = 0; 93 if (rdev->family == CHIP_JUNIPER) {
94 94 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
95 if (temp & 0x400) 95 TOFFSET_SHIFT;
96 actual_temp = -256; 96 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
97 else if (temp & 0x200) 97 TS0_ADC_DOUT_SHIFT;
98 actual_temp = 255; 98
99 else if (temp & 0x100) { 99 if (toffset & 0x100)
100 actual_temp = temp & 0x1ff; 100 actual_temp = temp / 2 - (0x200 - toffset);
101 actual_temp |= ~0x1ff; 101 else
102 } else 102 actual_temp = temp / 2 + toffset;
103 actual_temp = temp & 0xff; 103
104 actual_temp = actual_temp * 1000;
105
106 } else {
107 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
108 ASIC_T_SHIFT;
104 109
105 return (actual_temp * 1000) / 2; 110 if (temp & 0x400)
111 actual_temp = -256;
112 else if (temp & 0x200)
113 actual_temp = 255;
114 else if (temp & 0x100) {
115 actual_temp = temp & 0x1ff;
116 actual_temp |= ~0x1ff;
117 } else
118 actual_temp = temp & 0xff;
119
120 actual_temp = (actual_temp * 1000) / 2;
121 }
122
123 return actual_temp;
106} 124}
107 125
108int sumo_get_temp(struct radeon_device *rdev) 126int sumo_get_temp(struct radeon_device *rdev)
@@ -1415,6 +1433,8 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1415 case CHIP_CEDAR: 1433 case CHIP_CEDAR:
1416 case CHIP_REDWOOD: 1434 case CHIP_REDWOOD:
1417 case CHIP_PALM: 1435 case CHIP_PALM:
1436 case CHIP_SUMO:
1437 case CHIP_SUMO2:
1418 case CHIP_TURKS: 1438 case CHIP_TURKS:
1419 case CHIP_CAICOS: 1439 case CHIP_CAICOS:
1420 force_no_swizzle = false; 1440 force_no_swizzle = false;
@@ -1544,6 +1564,8 @@ static void evergreen_program_channel_remap(struct radeon_device *rdev)
1544 case CHIP_REDWOOD: 1564 case CHIP_REDWOOD:
1545 case CHIP_CEDAR: 1565 case CHIP_CEDAR:
1546 case CHIP_PALM: 1566 case CHIP_PALM:
1567 case CHIP_SUMO:
1568 case CHIP_SUMO2:
1547 case CHIP_TURKS: 1569 case CHIP_TURKS:
1548 case CHIP_CAICOS: 1570 case CHIP_CAICOS:
1549 default: 1571 default:
@@ -1689,6 +1711,54 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1689 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1711 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1690 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1712 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1691 break; 1713 break;
1714 case CHIP_SUMO:
1715 rdev->config.evergreen.num_ses = 1;
1716 rdev->config.evergreen.max_pipes = 4;
1717 rdev->config.evergreen.max_tile_pipes = 2;
1718 if (rdev->pdev->device == 0x9648)
1719 rdev->config.evergreen.max_simds = 3;
1720 else if ((rdev->pdev->device == 0x9647) ||
1721 (rdev->pdev->device == 0x964a))
1722 rdev->config.evergreen.max_simds = 4;
1723 else
1724 rdev->config.evergreen.max_simds = 5;
1725 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1726 rdev->config.evergreen.max_gprs = 256;
1727 rdev->config.evergreen.max_threads = 248;
1728 rdev->config.evergreen.max_gs_threads = 32;
1729 rdev->config.evergreen.max_stack_entries = 256;
1730 rdev->config.evergreen.sx_num_of_sets = 4;
1731 rdev->config.evergreen.sx_max_export_size = 256;
1732 rdev->config.evergreen.sx_max_export_pos_size = 64;
1733 rdev->config.evergreen.sx_max_export_smx_size = 192;
1734 rdev->config.evergreen.max_hw_contexts = 8;
1735 rdev->config.evergreen.sq_num_cf_insts = 2;
1736
1737 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1738 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1739 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1740 break;
1741 case CHIP_SUMO2:
1742 rdev->config.evergreen.num_ses = 1;
1743 rdev->config.evergreen.max_pipes = 4;
1744 rdev->config.evergreen.max_tile_pipes = 4;
1745 rdev->config.evergreen.max_simds = 2;
1746 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1747 rdev->config.evergreen.max_gprs = 256;
1748 rdev->config.evergreen.max_threads = 248;
1749 rdev->config.evergreen.max_gs_threads = 32;
1750 rdev->config.evergreen.max_stack_entries = 512;
1751 rdev->config.evergreen.sx_num_of_sets = 4;
1752 rdev->config.evergreen.sx_max_export_size = 256;
1753 rdev->config.evergreen.sx_max_export_pos_size = 64;
1754 rdev->config.evergreen.sx_max_export_smx_size = 192;
1755 rdev->config.evergreen.max_hw_contexts = 8;
1756 rdev->config.evergreen.sq_num_cf_insts = 2;
1757
1758 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1759 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1760 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1761 break;
1692 case CHIP_BARTS: 1762 case CHIP_BARTS:
1693 rdev->config.evergreen.num_ses = 2; 1763 rdev->config.evergreen.num_ses = 2;
1694 rdev->config.evergreen.max_pipes = 4; 1764 rdev->config.evergreen.max_pipes = 4;
@@ -2039,6 +2109,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2039 switch (rdev->family) { 2109 switch (rdev->family) {
2040 case CHIP_CEDAR: 2110 case CHIP_CEDAR:
2041 case CHIP_PALM: 2111 case CHIP_PALM:
2112 case CHIP_SUMO:
2113 case CHIP_SUMO2:
2042 case CHIP_CAICOS: 2114 case CHIP_CAICOS:
2043 /* no vertex cache */ 2115 /* no vertex cache */
2044 sq_config &= ~VC_ENABLE; 2116 sq_config &= ~VC_ENABLE;
@@ -2060,6 +2132,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2060 switch (rdev->family) { 2132 switch (rdev->family) {
2061 case CHIP_CEDAR: 2133 case CHIP_CEDAR:
2062 case CHIP_PALM: 2134 case CHIP_PALM:
2135 case CHIP_SUMO:
2136 case CHIP_SUMO2:
2063 ps_thread_count = 96; 2137 ps_thread_count = 96;
2064 break; 2138 break;
2065 default: 2139 default:
@@ -2099,6 +2173,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
2099 switch (rdev->family) { 2173 switch (rdev->family) {
2100 case CHIP_CEDAR: 2174 case CHIP_CEDAR:
2101 case CHIP_PALM: 2175 case CHIP_PALM:
2176 case CHIP_SUMO:
2177 case CHIP_SUMO2:
2102 case CHIP_CAICOS: 2178 case CHIP_CAICOS:
2103 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); 2179 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2104 break; 2180 break;
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index ba06a69c6de..57f3bc17b87 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -31,6 +31,7 @@
31 31
32#include "evergreend.h" 32#include "evergreend.h"
33#include "evergreen_blit_shaders.h" 33#include "evergreen_blit_shaders.h"
34#include "cayman_blit_shaders.h"
34 35
35#define DI_PT_RECTLIST 0x11 36#define DI_PT_RECTLIST 0x11
36#define DI_INDEX_SIZE_16_BIT 0x0 37#define DI_INDEX_SIZE_16_BIT 0x0
@@ -152,6 +153,8 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
152 153
153 if ((rdev->family == CHIP_CEDAR) || 154 if ((rdev->family == CHIP_CEDAR) ||
154 (rdev->family == CHIP_PALM) || 155 (rdev->family == CHIP_PALM) ||
156 (rdev->family == CHIP_SUMO) ||
157 (rdev->family == CHIP_SUMO2) ||
155 (rdev->family == CHIP_CAICOS)) 158 (rdev->family == CHIP_CAICOS))
156 cp_set_surface_sync(rdev, 159 cp_set_surface_sync(rdev,
157 PACKET3_TC_ACTION_ENA, 48, gpu_addr); 160 PACKET3_TC_ACTION_ENA, 48, gpu_addr);
@@ -199,6 +202,16 @@ static void
199set_scissors(struct radeon_device *rdev, int x1, int y1, 202set_scissors(struct radeon_device *rdev, int x1, int y1,
200 int x2, int y2) 203 int x2, int y2)
201{ 204{
205 /* workaround some hw bugs */
206 if (x2 == 0)
207 x1 = 1;
208 if (y2 == 0)
209 y1 = 1;
210 if (rdev->family == CHIP_CAYMAN) {
211 if ((x2 == 1) && (y2 == 1))
212 x2 = 2;
213 }
214
202 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 215 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
203 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); 216 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
204 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); 217 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
@@ -255,238 +268,284 @@ set_default_state(struct radeon_device *rdev)
255 u64 gpu_addr; 268 u64 gpu_addr;
256 int dwords; 269 int dwords;
257 270
258 switch (rdev->family) {
259 case CHIP_CEDAR:
260 default:
261 num_ps_gprs = 93;
262 num_vs_gprs = 46;
263 num_temp_gprs = 4;
264 num_gs_gprs = 31;
265 num_es_gprs = 31;
266 num_hs_gprs = 23;
267 num_ls_gprs = 23;
268 num_ps_threads = 96;
269 num_vs_threads = 16;
270 num_gs_threads = 16;
271 num_es_threads = 16;
272 num_hs_threads = 16;
273 num_ls_threads = 16;
274 num_ps_stack_entries = 42;
275 num_vs_stack_entries = 42;
276 num_gs_stack_entries = 42;
277 num_es_stack_entries = 42;
278 num_hs_stack_entries = 42;
279 num_ls_stack_entries = 42;
280 break;
281 case CHIP_REDWOOD:
282 num_ps_gprs = 93;
283 num_vs_gprs = 46;
284 num_temp_gprs = 4;
285 num_gs_gprs = 31;
286 num_es_gprs = 31;
287 num_hs_gprs = 23;
288 num_ls_gprs = 23;
289 num_ps_threads = 128;
290 num_vs_threads = 20;
291 num_gs_threads = 20;
292 num_es_threads = 20;
293 num_hs_threads = 20;
294 num_ls_threads = 20;
295 num_ps_stack_entries = 42;
296 num_vs_stack_entries = 42;
297 num_gs_stack_entries = 42;
298 num_es_stack_entries = 42;
299 num_hs_stack_entries = 42;
300 num_ls_stack_entries = 42;
301 break;
302 case CHIP_JUNIPER:
303 num_ps_gprs = 93;
304 num_vs_gprs = 46;
305 num_temp_gprs = 4;
306 num_gs_gprs = 31;
307 num_es_gprs = 31;
308 num_hs_gprs = 23;
309 num_ls_gprs = 23;
310 num_ps_threads = 128;
311 num_vs_threads = 20;
312 num_gs_threads = 20;
313 num_es_threads = 20;
314 num_hs_threads = 20;
315 num_ls_threads = 20;
316 num_ps_stack_entries = 85;
317 num_vs_stack_entries = 85;
318 num_gs_stack_entries = 85;
319 num_es_stack_entries = 85;
320 num_hs_stack_entries = 85;
321 num_ls_stack_entries = 85;
322 break;
323 case CHIP_CYPRESS:
324 case CHIP_HEMLOCK:
325 num_ps_gprs = 93;
326 num_vs_gprs = 46;
327 num_temp_gprs = 4;
328 num_gs_gprs = 31;
329 num_es_gprs = 31;
330 num_hs_gprs = 23;
331 num_ls_gprs = 23;
332 num_ps_threads = 128;
333 num_vs_threads = 20;
334 num_gs_threads = 20;
335 num_es_threads = 20;
336 num_hs_threads = 20;
337 num_ls_threads = 20;
338 num_ps_stack_entries = 85;
339 num_vs_stack_entries = 85;
340 num_gs_stack_entries = 85;
341 num_es_stack_entries = 85;
342 num_hs_stack_entries = 85;
343 num_ls_stack_entries = 85;
344 break;
345 case CHIP_PALM:
346 num_ps_gprs = 93;
347 num_vs_gprs = 46;
348 num_temp_gprs = 4;
349 num_gs_gprs = 31;
350 num_es_gprs = 31;
351 num_hs_gprs = 23;
352 num_ls_gprs = 23;
353 num_ps_threads = 96;
354 num_vs_threads = 16;
355 num_gs_threads = 16;
356 num_es_threads = 16;
357 num_hs_threads = 16;
358 num_ls_threads = 16;
359 num_ps_stack_entries = 42;
360 num_vs_stack_entries = 42;
361 num_gs_stack_entries = 42;
362 num_es_stack_entries = 42;
363 num_hs_stack_entries = 42;
364 num_ls_stack_entries = 42;
365 break;
366 case CHIP_BARTS:
367 num_ps_gprs = 93;
368 num_vs_gprs = 46;
369 num_temp_gprs = 4;
370 num_gs_gprs = 31;
371 num_es_gprs = 31;
372 num_hs_gprs = 23;
373 num_ls_gprs = 23;
374 num_ps_threads = 128;
375 num_vs_threads = 20;
376 num_gs_threads = 20;
377 num_es_threads = 20;
378 num_hs_threads = 20;
379 num_ls_threads = 20;
380 num_ps_stack_entries = 85;
381 num_vs_stack_entries = 85;
382 num_gs_stack_entries = 85;
383 num_es_stack_entries = 85;
384 num_hs_stack_entries = 85;
385 num_ls_stack_entries = 85;
386 break;
387 case CHIP_TURKS:
388 num_ps_gprs = 93;
389 num_vs_gprs = 46;
390 num_temp_gprs = 4;
391 num_gs_gprs = 31;
392 num_es_gprs = 31;
393 num_hs_gprs = 23;
394 num_ls_gprs = 23;
395 num_ps_threads = 128;
396 num_vs_threads = 20;
397 num_gs_threads = 20;
398 num_es_threads = 20;
399 num_hs_threads = 20;
400 num_ls_threads = 20;
401 num_ps_stack_entries = 42;
402 num_vs_stack_entries = 42;
403 num_gs_stack_entries = 42;
404 num_es_stack_entries = 42;
405 num_hs_stack_entries = 42;
406 num_ls_stack_entries = 42;
407 break;
408 case CHIP_CAICOS:
409 num_ps_gprs = 93;
410 num_vs_gprs = 46;
411 num_temp_gprs = 4;
412 num_gs_gprs = 31;
413 num_es_gprs = 31;
414 num_hs_gprs = 23;
415 num_ls_gprs = 23;
416 num_ps_threads = 128;
417 num_vs_threads = 10;
418 num_gs_threads = 10;
419 num_es_threads = 10;
420 num_hs_threads = 10;
421 num_ls_threads = 10;
422 num_ps_stack_entries = 42;
423 num_vs_stack_entries = 42;
424 num_gs_stack_entries = 42;
425 num_es_stack_entries = 42;
426 num_hs_stack_entries = 42;
427 num_ls_stack_entries = 42;
428 break;
429 }
430
431 if ((rdev->family == CHIP_CEDAR) ||
432 (rdev->family == CHIP_PALM) ||
433 (rdev->family == CHIP_CAICOS))
434 sq_config = 0;
435 else
436 sq_config = VC_ENABLE;
437
438 sq_config |= (EXPORT_SRC_C |
439 CS_PRIO(0) |
440 LS_PRIO(0) |
441 HS_PRIO(0) |
442 PS_PRIO(0) |
443 VS_PRIO(1) |
444 GS_PRIO(2) |
445 ES_PRIO(3));
446
447 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
448 NUM_VS_GPRS(num_vs_gprs) |
449 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
450 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
451 NUM_ES_GPRS(num_es_gprs));
452 sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
453 NUM_LS_GPRS(num_ls_gprs));
454 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
455 NUM_VS_THREADS(num_vs_threads) |
456 NUM_GS_THREADS(num_gs_threads) |
457 NUM_ES_THREADS(num_es_threads));
458 sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
459 NUM_LS_THREADS(num_ls_threads));
460 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
461 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
462 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
463 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
464 sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
465 NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
466
467 /* set clear context state */ 271 /* set clear context state */
468 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); 272 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
469 radeon_ring_write(rdev, 0); 273 radeon_ring_write(rdev, 0);
470 274
471 /* disable dyn gprs */ 275 if (rdev->family < CHIP_CAYMAN) {
472 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 276 switch (rdev->family) {
473 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); 277 case CHIP_CEDAR:
474 radeon_ring_write(rdev, 0); 278 default:
279 num_ps_gprs = 93;
280 num_vs_gprs = 46;
281 num_temp_gprs = 4;
282 num_gs_gprs = 31;
283 num_es_gprs = 31;
284 num_hs_gprs = 23;
285 num_ls_gprs = 23;
286 num_ps_threads = 96;
287 num_vs_threads = 16;
288 num_gs_threads = 16;
289 num_es_threads = 16;
290 num_hs_threads = 16;
291 num_ls_threads = 16;
292 num_ps_stack_entries = 42;
293 num_vs_stack_entries = 42;
294 num_gs_stack_entries = 42;
295 num_es_stack_entries = 42;
296 num_hs_stack_entries = 42;
297 num_ls_stack_entries = 42;
298 break;
299 case CHIP_REDWOOD:
300 num_ps_gprs = 93;
301 num_vs_gprs = 46;
302 num_temp_gprs = 4;
303 num_gs_gprs = 31;
304 num_es_gprs = 31;
305 num_hs_gprs = 23;
306 num_ls_gprs = 23;
307 num_ps_threads = 128;
308 num_vs_threads = 20;
309 num_gs_threads = 20;
310 num_es_threads = 20;
311 num_hs_threads = 20;
312 num_ls_threads = 20;
313 num_ps_stack_entries = 42;
314 num_vs_stack_entries = 42;
315 num_gs_stack_entries = 42;
316 num_es_stack_entries = 42;
317 num_hs_stack_entries = 42;
318 num_ls_stack_entries = 42;
319 break;
320 case CHIP_JUNIPER:
321 num_ps_gprs = 93;
322 num_vs_gprs = 46;
323 num_temp_gprs = 4;
324 num_gs_gprs = 31;
325 num_es_gprs = 31;
326 num_hs_gprs = 23;
327 num_ls_gprs = 23;
328 num_ps_threads = 128;
329 num_vs_threads = 20;
330 num_gs_threads = 20;
331 num_es_threads = 20;
332 num_hs_threads = 20;
333 num_ls_threads = 20;
334 num_ps_stack_entries = 85;
335 num_vs_stack_entries = 85;
336 num_gs_stack_entries = 85;
337 num_es_stack_entries = 85;
338 num_hs_stack_entries = 85;
339 num_ls_stack_entries = 85;
340 break;
341 case CHIP_CYPRESS:
342 case CHIP_HEMLOCK:
343 num_ps_gprs = 93;
344 num_vs_gprs = 46;
345 num_temp_gprs = 4;
346 num_gs_gprs = 31;
347 num_es_gprs = 31;
348 num_hs_gprs = 23;
349 num_ls_gprs = 23;
350 num_ps_threads = 128;
351 num_vs_threads = 20;
352 num_gs_threads = 20;
353 num_es_threads = 20;
354 num_hs_threads = 20;
355 num_ls_threads = 20;
356 num_ps_stack_entries = 85;
357 num_vs_stack_entries = 85;
358 num_gs_stack_entries = 85;
359 num_es_stack_entries = 85;
360 num_hs_stack_entries = 85;
361 num_ls_stack_entries = 85;
362 break;
363 case CHIP_PALM:
364 num_ps_gprs = 93;
365 num_vs_gprs = 46;
366 num_temp_gprs = 4;
367 num_gs_gprs = 31;
368 num_es_gprs = 31;
369 num_hs_gprs = 23;
370 num_ls_gprs = 23;
371 num_ps_threads = 96;
372 num_vs_threads = 16;
373 num_gs_threads = 16;
374 num_es_threads = 16;
375 num_hs_threads = 16;
376 num_ls_threads = 16;
377 num_ps_stack_entries = 42;
378 num_vs_stack_entries = 42;
379 num_gs_stack_entries = 42;
380 num_es_stack_entries = 42;
381 num_hs_stack_entries = 42;
382 num_ls_stack_entries = 42;
383 break;
384 case CHIP_SUMO:
385 num_ps_gprs = 93;
386 num_vs_gprs = 46;
387 num_temp_gprs = 4;
388 num_gs_gprs = 31;
389 num_es_gprs = 31;
390 num_hs_gprs = 23;
391 num_ls_gprs = 23;
392 num_ps_threads = 96;
393 num_vs_threads = 25;
394 num_gs_threads = 25;
395 num_es_threads = 25;
396 num_hs_threads = 25;
397 num_ls_threads = 25;
398 num_ps_stack_entries = 42;
399 num_vs_stack_entries = 42;
400 num_gs_stack_entries = 42;
401 num_es_stack_entries = 42;
402 num_hs_stack_entries = 42;
403 num_ls_stack_entries = 42;
404 break;
405 case CHIP_SUMO2:
406 num_ps_gprs = 93;
407 num_vs_gprs = 46;
408 num_temp_gprs = 4;
409 num_gs_gprs = 31;
410 num_es_gprs = 31;
411 num_hs_gprs = 23;
412 num_ls_gprs = 23;
413 num_ps_threads = 96;
414 num_vs_threads = 25;
415 num_gs_threads = 25;
416 num_es_threads = 25;
417 num_hs_threads = 25;
418 num_ls_threads = 25;
419 num_ps_stack_entries = 85;
420 num_vs_stack_entries = 85;
421 num_gs_stack_entries = 85;
422 num_es_stack_entries = 85;
423 num_hs_stack_entries = 85;
424 num_ls_stack_entries = 85;
425 break;
426 case CHIP_BARTS:
427 num_ps_gprs = 93;
428 num_vs_gprs = 46;
429 num_temp_gprs = 4;
430 num_gs_gprs = 31;
431 num_es_gprs = 31;
432 num_hs_gprs = 23;
433 num_ls_gprs = 23;
434 num_ps_threads = 128;
435 num_vs_threads = 20;
436 num_gs_threads = 20;
437 num_es_threads = 20;
438 num_hs_threads = 20;
439 num_ls_threads = 20;
440 num_ps_stack_entries = 85;
441 num_vs_stack_entries = 85;
442 num_gs_stack_entries = 85;
443 num_es_stack_entries = 85;
444 num_hs_stack_entries = 85;
445 num_ls_stack_entries = 85;
446 break;
447 case CHIP_TURKS:
448 num_ps_gprs = 93;
449 num_vs_gprs = 46;
450 num_temp_gprs = 4;
451 num_gs_gprs = 31;
452 num_es_gprs = 31;
453 num_hs_gprs = 23;
454 num_ls_gprs = 23;
455 num_ps_threads = 128;
456 num_vs_threads = 20;
457 num_gs_threads = 20;
458 num_es_threads = 20;
459 num_hs_threads = 20;
460 num_ls_threads = 20;
461 num_ps_stack_entries = 42;
462 num_vs_stack_entries = 42;
463 num_gs_stack_entries = 42;
464 num_es_stack_entries = 42;
465 num_hs_stack_entries = 42;
466 num_ls_stack_entries = 42;
467 break;
468 case CHIP_CAICOS:
469 num_ps_gprs = 93;
470 num_vs_gprs = 46;
471 num_temp_gprs = 4;
472 num_gs_gprs = 31;
473 num_es_gprs = 31;
474 num_hs_gprs = 23;
475 num_ls_gprs = 23;
476 num_ps_threads = 128;
477 num_vs_threads = 10;
478 num_gs_threads = 10;
479 num_es_threads = 10;
480 num_hs_threads = 10;
481 num_ls_threads = 10;
482 num_ps_stack_entries = 42;
483 num_vs_stack_entries = 42;
484 num_gs_stack_entries = 42;
485 num_es_stack_entries = 42;
486 num_hs_stack_entries = 42;
487 num_ls_stack_entries = 42;
488 break;
489 }
475 490
476 /* SQ config */ 491 if ((rdev->family == CHIP_CEDAR) ||
477 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); 492 (rdev->family == CHIP_PALM) ||
478 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); 493 (rdev->family == CHIP_SUMO) ||
479 radeon_ring_write(rdev, sq_config); 494 (rdev->family == CHIP_SUMO2) ||
480 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); 495 (rdev->family == CHIP_CAICOS))
481 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); 496 sq_config = 0;
482 radeon_ring_write(rdev, sq_gpr_resource_mgmt_3); 497 else
483 radeon_ring_write(rdev, 0); 498 sq_config = VC_ENABLE;
484 radeon_ring_write(rdev, 0); 499
485 radeon_ring_write(rdev, sq_thread_resource_mgmt); 500 sq_config |= (EXPORT_SRC_C |
486 radeon_ring_write(rdev, sq_thread_resource_mgmt_2); 501 CS_PRIO(0) |
487 radeon_ring_write(rdev, sq_stack_resource_mgmt_1); 502 LS_PRIO(0) |
488 radeon_ring_write(rdev, sq_stack_resource_mgmt_2); 503 HS_PRIO(0) |
489 radeon_ring_write(rdev, sq_stack_resource_mgmt_3); 504 PS_PRIO(0) |
505 VS_PRIO(1) |
506 GS_PRIO(2) |
507 ES_PRIO(3));
508
509 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
510 NUM_VS_GPRS(num_vs_gprs) |
511 NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
512 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
513 NUM_ES_GPRS(num_es_gprs));
514 sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
515 NUM_LS_GPRS(num_ls_gprs));
516 sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
517 NUM_VS_THREADS(num_vs_threads) |
518 NUM_GS_THREADS(num_gs_threads) |
519 NUM_ES_THREADS(num_es_threads));
520 sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
521 NUM_LS_THREADS(num_ls_threads));
522 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
523 NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
524 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
525 NUM_ES_STACK_ENTRIES(num_es_stack_entries));
526 sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
527 NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
528
529 /* disable dyn gprs */
530 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
531 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
532 radeon_ring_write(rdev, 0);
533
534 /* SQ config */
535 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
536 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
537 radeon_ring_write(rdev, sq_config);
538 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
539 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
540 radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
541 radeon_ring_write(rdev, 0);
542 radeon_ring_write(rdev, 0);
543 radeon_ring_write(rdev, sq_thread_resource_mgmt);
544 radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
545 radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
546 radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
547 radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
548 }
490 549
491 /* CONTEXT_CONTROL */ 550 /* CONTEXT_CONTROL */
492 radeon_ring_write(rdev, 0xc0012800); 551 radeon_ring_write(rdev, 0xc0012800);
@@ -560,7 +619,10 @@ int evergreen_blit_init(struct radeon_device *rdev)
560 mutex_init(&rdev->r600_blit.mutex); 619 mutex_init(&rdev->r600_blit.mutex);
561 rdev->r600_blit.state_offset = 0; 620 rdev->r600_blit.state_offset = 0;
562 621
563 rdev->r600_blit.state_len = evergreen_default_size; 622 if (rdev->family < CHIP_CAYMAN)
623 rdev->r600_blit.state_len = evergreen_default_size;
624 else
625 rdev->r600_blit.state_len = cayman_default_size;
564 626
565 dwords = rdev->r600_blit.state_len; 627 dwords = rdev->r600_blit.state_len;
566 while (dwords & 0xf) { 628 while (dwords & 0xf) {
@@ -572,11 +634,17 @@ int evergreen_blit_init(struct radeon_device *rdev)
572 obj_size = ALIGN(obj_size, 256); 634 obj_size = ALIGN(obj_size, 256);
573 635
574 rdev->r600_blit.vs_offset = obj_size; 636 rdev->r600_blit.vs_offset = obj_size;
575 obj_size += evergreen_vs_size * 4; 637 if (rdev->family < CHIP_CAYMAN)
638 obj_size += evergreen_vs_size * 4;
639 else
640 obj_size += cayman_vs_size * 4;
576 obj_size = ALIGN(obj_size, 256); 641 obj_size = ALIGN(obj_size, 256);
577 642
578 rdev->r600_blit.ps_offset = obj_size; 643 rdev->r600_blit.ps_offset = obj_size;
579 obj_size += evergreen_ps_size * 4; 644 if (rdev->family < CHIP_CAYMAN)
645 obj_size += evergreen_ps_size * 4;
646 else
647 obj_size += cayman_ps_size * 4;
580 obj_size = ALIGN(obj_size, 256); 648 obj_size = ALIGN(obj_size, 256);
581 649
582 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, 650 r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
@@ -599,16 +667,29 @@ int evergreen_blit_init(struct radeon_device *rdev)
599 return r; 667 return r;
600 } 668 }
601 669
602 memcpy_toio(ptr + rdev->r600_blit.state_offset, 670 if (rdev->family < CHIP_CAYMAN) {
603 evergreen_default_state, rdev->r600_blit.state_len * 4); 671 memcpy_toio(ptr + rdev->r600_blit.state_offset,
604 672 evergreen_default_state, rdev->r600_blit.state_len * 4);
605 if (num_packet2s) 673
606 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), 674 if (num_packet2s)
607 packet2s, num_packet2s * 4); 675 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
608 for (i = 0; i < evergreen_vs_size; i++) 676 packet2s, num_packet2s * 4);
609 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]); 677 for (i = 0; i < evergreen_vs_size; i++)
610 for (i = 0; i < evergreen_ps_size; i++) 678 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
611 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]); 679 for (i = 0; i < evergreen_ps_size; i++)
680 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
681 } else {
682 memcpy_toio(ptr + rdev->r600_blit.state_offset,
683 cayman_default_state, rdev->r600_blit.state_len * 4);
684
685 if (num_packet2s)
686 memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
687 packet2s, num_packet2s * 4);
688 for (i = 0; i < cayman_vs_size; i++)
689 *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
690 for (i = 0; i < cayman_ps_size; i++)
691 *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
692 }
612 radeon_bo_kunmap(rdev->r600_blit.shader_obj); 693 radeon_bo_kunmap(rdev->r600_blit.shader_obj);
613 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 694 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
614 695
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index f37e91ee8a1..1636e344982 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -168,10 +168,16 @@
168#define SE_DB_BUSY (1 << 30) 168#define SE_DB_BUSY (1 << 30)
169#define SE_CB_BUSY (1 << 31) 169#define SE_CB_BUSY (1 << 31)
170/* evergreen */ 170/* evergreen */
171#define CG_THERMAL_CTRL 0x72c
172#define TOFFSET_MASK 0x00003FE0
173#define TOFFSET_SHIFT 5
171#define CG_MULT_THERMAL_STATUS 0x740 174#define CG_MULT_THERMAL_STATUS 0x740
172#define ASIC_T(x) ((x) << 16) 175#define ASIC_T(x) ((x) << 16)
173#define ASIC_T_MASK 0x7FF0000 176#define ASIC_T_MASK 0x07FF0000
174#define ASIC_T_SHIFT 16 177#define ASIC_T_SHIFT 16
178#define CG_TS0_STATUS 0x760
179#define TS0_ADC_DOUT_MASK 0x000003FF
180#define TS0_ADC_DOUT_SHIFT 0
175/* APU */ 181/* APU */
176#define CG_THERMAL_STATUS 0x678 182#define CG_THERMAL_STATUS 0x678
177 183
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index b205ba1cdd8..16caafeadf5 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1387,14 +1387,12 @@ static int cayman_startup(struct radeon_device *rdev)
1387 return r; 1387 return r;
1388 cayman_gpu_init(rdev); 1388 cayman_gpu_init(rdev);
1389 1389
1390#if 0 1390 r = evergreen_blit_init(rdev);
1391 r = cayman_blit_init(rdev);
1392 if (r) { 1391 if (r) {
1393 cayman_blit_fini(rdev); 1392 evergreen_blit_fini(rdev);
1394 rdev->asic->copy = NULL; 1393 rdev->asic->copy = NULL;
1395 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 1394 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1396 } 1395 }
1397#endif
1398 1396
1399 /* allocate wb buffer */ 1397 /* allocate wb buffer */
1400 r = radeon_wb_init(rdev); 1398 r = radeon_wb_init(rdev);
@@ -1452,7 +1450,7 @@ int cayman_resume(struct radeon_device *rdev)
1452 1450
1453int cayman_suspend(struct radeon_device *rdev) 1451int cayman_suspend(struct radeon_device *rdev)
1454{ 1452{
1455 /* int r; */ 1453 int r;
1456 1454
1457 /* FIXME: we should wait for ring to be empty */ 1455 /* FIXME: we should wait for ring to be empty */
1458 cayman_cp_enable(rdev, false); 1456 cayman_cp_enable(rdev, false);
@@ -1461,14 +1459,13 @@ int cayman_suspend(struct radeon_device *rdev)
1461 radeon_wb_disable(rdev); 1459 radeon_wb_disable(rdev);
1462 cayman_pcie_gart_disable(rdev); 1460 cayman_pcie_gart_disable(rdev);
1463 1461
1464#if 0
1465 /* unpin shaders bo */ 1462 /* unpin shaders bo */
1466 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); 1463 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1467 if (likely(r == 0)) { 1464 if (likely(r == 0)) {
1468 radeon_bo_unpin(rdev->r600_blit.shader_obj); 1465 radeon_bo_unpin(rdev->r600_blit.shader_obj);
1469 radeon_bo_unreserve(rdev->r600_blit.shader_obj); 1466 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1470 } 1467 }
1471#endif 1468
1472 return 0; 1469 return 0;
1473} 1470}
1474 1471
@@ -1580,7 +1577,7 @@ int cayman_init(struct radeon_device *rdev)
1580 1577
1581void cayman_fini(struct radeon_device *rdev) 1578void cayman_fini(struct radeon_device *rdev)
1582{ 1579{
1583 /* cayman_blit_fini(rdev); */ 1580 evergreen_blit_fini(rdev);
1584 cayman_cp_fini(rdev); 1581 cayman_cp_fini(rdev);
1585 r600_irq_fini(rdev); 1582 r600_irq_fini(rdev);
1586 radeon_wb_fini(rdev); 1583 radeon_wb_fini(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 6f27593901c..d74d4d71437 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -87,6 +87,10 @@ MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
87MODULE_FIRMWARE("radeon/PALM_pfp.bin"); 87MODULE_FIRMWARE("radeon/PALM_pfp.bin");
88MODULE_FIRMWARE("radeon/PALM_me.bin"); 88MODULE_FIRMWARE("radeon/PALM_me.bin");
89MODULE_FIRMWARE("radeon/SUMO_rlc.bin"); 89MODULE_FIRMWARE("radeon/SUMO_rlc.bin");
90MODULE_FIRMWARE("radeon/SUMO_pfp.bin");
91MODULE_FIRMWARE("radeon/SUMO_me.bin");
92MODULE_FIRMWARE("radeon/SUMO2_pfp.bin");
93MODULE_FIRMWARE("radeon/SUMO2_me.bin");
90 94
91int r600_debugfs_mc_info_init(struct radeon_device *rdev); 95int r600_debugfs_mc_info_init(struct radeon_device *rdev);
92 96
@@ -2024,6 +2028,14 @@ int r600_init_microcode(struct radeon_device *rdev)
2024 chip_name = "PALM"; 2028 chip_name = "PALM";
2025 rlc_chip_name = "SUMO"; 2029 rlc_chip_name = "SUMO";
2026 break; 2030 break;
2031 case CHIP_SUMO:
2032 chip_name = "SUMO";
2033 rlc_chip_name = "SUMO";
2034 break;
2035 case CHIP_SUMO2:
2036 chip_name = "SUMO2";
2037 rlc_chip_name = "SUMO";
2038 break;
2027 default: BUG(); 2039 default: BUG();
2028 } 2040 }
2029 2041
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index fd18be9871a..909bda8dd55 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -71,20 +71,21 @@ struct r600_cs_track {
71 u64 db_bo_mc; 71 u64 db_bo_mc;
72}; 72};
73 73
74#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc } 74#define FMT_8_BIT(fmt, vc) [fmt] = { 1, 1, 1, vc, CHIP_R600 }
75#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc } 75#define FMT_16_BIT(fmt, vc) [fmt] = { 1, 1, 2, vc, CHIP_R600 }
76#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0 } 76#define FMT_24_BIT(fmt) [fmt] = { 1, 1, 3, 0, CHIP_R600 }
77#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc } 77#define FMT_32_BIT(fmt, vc) [fmt] = { 1, 1, 4, vc, CHIP_R600 }
78#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0 } 78#define FMT_48_BIT(fmt) [fmt] = { 1, 1, 6, 0, CHIP_R600 }
79#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc } 79#define FMT_64_BIT(fmt, vc) [fmt] = { 1, 1, 8, vc, CHIP_R600 }
80#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0 } 80#define FMT_96_BIT(fmt) [fmt] = { 1, 1, 12, 0, CHIP_R600 }
81#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16, vc } 81#define FMT_128_BIT(fmt, vc) [fmt] = { 1, 1, 16,vc, CHIP_R600 }
82 82
83struct gpu_formats { 83struct gpu_formats {
84 unsigned blockwidth; 84 unsigned blockwidth;
85 unsigned blockheight; 85 unsigned blockheight;
86 unsigned blocksize; 86 unsigned blocksize;
87 unsigned valid_color; 87 unsigned valid_color;
88 enum radeon_family min_family;
88}; 89};
89 90
90static const struct gpu_formats color_formats_table[] = { 91static const struct gpu_formats color_formats_table[] = {
@@ -154,7 +155,11 @@ static const struct gpu_formats color_formats_table[] = {
154 [V_038004_FMT_BC3] = { 4, 4, 16, 0 }, 155 [V_038004_FMT_BC3] = { 4, 4, 16, 0 },
155 [V_038004_FMT_BC4] = { 4, 4, 8, 0 }, 156 [V_038004_FMT_BC4] = { 4, 4, 8, 0 },
156 [V_038004_FMT_BC5] = { 4, 4, 16, 0}, 157 [V_038004_FMT_BC5] = { 4, 4, 16, 0},
158 [V_038004_FMT_BC6] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
159 [V_038004_FMT_BC7] = { 4, 4, 16, 0, CHIP_CEDAR}, /* Evergreen-only */
157 160
161 /* The other Evergreen formats */
162 [V_038004_FMT_32_AS_32_32_32_32] = { 1, 1, 4, 0, CHIP_CEDAR},
158}; 163};
159 164
160static inline bool fmt_is_valid_color(u32 format) 165static inline bool fmt_is_valid_color(u32 format)
@@ -168,11 +173,14 @@ static inline bool fmt_is_valid_color(u32 format)
168 return false; 173 return false;
169} 174}
170 175
171static inline bool fmt_is_valid_texture(u32 format) 176static inline bool fmt_is_valid_texture(u32 format, enum radeon_family family)
172{ 177{
173 if (format >= ARRAY_SIZE(color_formats_table)) 178 if (format >= ARRAY_SIZE(color_formats_table))
174 return false; 179 return false;
175 180
181 if (family < color_formats_table[format].min_family)
182 return false;
183
176 if (color_formats_table[format].blockwidth > 0) 184 if (color_formats_table[format].blockwidth > 0)
177 return true; 185 return true;
178 186
@@ -1325,7 +1333,7 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i
1325 return -EINVAL; 1333 return -EINVAL;
1326 } 1334 }
1327 format = G_038004_DATA_FORMAT(word1); 1335 format = G_038004_DATA_FORMAT(word1);
1328 if (!fmt_is_valid_texture(format)) { 1336 if (!fmt_is_valid_texture(format, p->family)) {
1329 dev_warn(p->dev, "%s:%d texture invalid format %d\n", 1337 dev_warn(p->dev, "%s:%d texture invalid format %d\n",
1330 __func__, __LINE__, format); 1338 __func__, __LINE__, format);
1331 return -EINVAL; 1339 return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index b2b944bcd05..f140a0d5cb5 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -1309,6 +1309,9 @@
1309#define V_038004_FMT_BC3 0x00000033 1309#define V_038004_FMT_BC3 0x00000033
1310#define V_038004_FMT_BC4 0x00000034 1310#define V_038004_FMT_BC4 0x00000034
1311#define V_038004_FMT_BC5 0x00000035 1311#define V_038004_FMT_BC5 0x00000035
1312#define V_038004_FMT_BC6 0x00000036
1313#define V_038004_FMT_BC7 0x00000037
1314#define V_038004_FMT_32_AS_32_32_32_32 0x00000038
1312#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 1315#define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010
1313#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1316#define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0)
1314#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1317#define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index d948265db87..9bd162fc9b0 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -906,9 +906,9 @@ static struct radeon_asic cayman_asic = {
906 .get_vblank_counter = &evergreen_get_vblank_counter, 906 .get_vblank_counter = &evergreen_get_vblank_counter,
907 .fence_ring_emit = &r600_fence_ring_emit, 907 .fence_ring_emit = &r600_fence_ring_emit,
908 .cs_parse = &evergreen_cs_parse, 908 .cs_parse = &evergreen_cs_parse,
909 .copy_blit = NULL, 909 .copy_blit = &evergreen_copy_blit,
910 .copy_dma = NULL, 910 .copy_dma = &evergreen_copy_blit,
911 .copy = NULL, 911 .copy = &evergreen_copy_blit,
912 .get_engine_clock = &radeon_atom_get_engine_clock, 912 .get_engine_clock = &radeon_atom_get_engine_clock,
913 .set_engine_clock = &radeon_atom_set_engine_clock, 913 .set_engine_clock = &radeon_atom_set_engine_clock,
914 .get_memory_clock = &radeon_atom_get_memory_clock, 914 .get_memory_clock = &radeon_atom_get_memory_clock,
@@ -1020,6 +1020,8 @@ int radeon_asic_init(struct radeon_device *rdev)
1020 rdev->asic = &evergreen_asic; 1020 rdev->asic = &evergreen_asic;
1021 break; 1021 break;
1022 case CHIP_PALM: 1022 case CHIP_PALM:
1023 case CHIP_SUMO:
1024 case CHIP_SUMO2:
1023 rdev->asic = &sumo_asic; 1025 rdev->asic = &sumo_asic;
1024 break; 1026 break;
1025 case CHIP_BARTS: 1027 case CHIP_BARTS:
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 5b61364e31f..d77ede3e67c 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -82,6 +82,8 @@ static const char radeon_family_name[][16] = {
82 "CYPRESS", 82 "CYPRESS",
83 "HEMLOCK", 83 "HEMLOCK",
84 "PALM", 84 "PALM",
85 "SUMO",
86 "SUMO2",
85 "BARTS", 87 "BARTS",
86 "TURKS", 88 "TURKS",
87 "CAICOS", 89 "CAICOS",
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index ae247eec87c..292f73f0ddb 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -264,6 +264,8 @@ static void radeon_unpin_work_func(struct work_struct *__work)
264 radeon_bo_unreserve(work->old_rbo); 264 radeon_bo_unreserve(work->old_rbo);
265 } else 265 } else
266 DRM_ERROR("failed to reserve buffer after flip\n"); 266 DRM_ERROR("failed to reserve buffer after flip\n");
267
268 drm_gem_object_unreference_unlocked(&work->old_rbo->gem_base);
267 kfree(work); 269 kfree(work);
268} 270}
269 271
@@ -371,6 +373,8 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
371 new_radeon_fb = to_radeon_framebuffer(fb); 373 new_radeon_fb = to_radeon_framebuffer(fb);
372 /* schedule unpin of the old buffer */ 374 /* schedule unpin of the old buffer */
373 obj = old_radeon_fb->obj; 375 obj = old_radeon_fb->obj;
376 /* take a reference to the old object */
377 drm_gem_object_reference(obj);
374 rbo = gem_to_radeon_bo(obj); 378 rbo = gem_to_radeon_bo(obj);
375 work->old_rbo = rbo; 379 work->old_rbo = rbo;
376 INIT_WORK(&work->work, radeon_unpin_work_func); 380 INIT_WORK(&work->work, radeon_unpin_work_func);
@@ -378,12 +382,9 @@ static int radeon_crtc_page_flip(struct drm_crtc *crtc,
378 /* We borrow the event spin lock for protecting unpin_work */ 382 /* We borrow the event spin lock for protecting unpin_work */
379 spin_lock_irqsave(&dev->event_lock, flags); 383 spin_lock_irqsave(&dev->event_lock, flags);
380 if (radeon_crtc->unpin_work) { 384 if (radeon_crtc->unpin_work) {
381 spin_unlock_irqrestore(&dev->event_lock, flags);
382 kfree(work);
383 radeon_fence_unref(&fence);
384
385 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); 385 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
386 return -EBUSY; 386 r = -EBUSY;
387 goto unlock_free;
387 } 388 }
388 radeon_crtc->unpin_work = work; 389 radeon_crtc->unpin_work = work;
389 radeon_crtc->deferred_flip_completion = 0; 390 radeon_crtc->deferred_flip_completion = 0;
@@ -497,6 +498,8 @@ pflip_cleanup1:
497pflip_cleanup: 498pflip_cleanup:
498 spin_lock_irqsave(&dev->event_lock, flags); 499 spin_lock_irqsave(&dev->event_lock, flags);
499 radeon_crtc->unpin_work = NULL; 500 radeon_crtc->unpin_work = NULL;
501unlock_free:
502 drm_gem_object_unreference_unlocked(old_radeon_fb->obj);
500 spin_unlock_irqrestore(&dev->event_lock, flags); 503 spin_unlock_irqrestore(&dev->event_lock, flags);
501 radeon_fence_unref(&fence); 504 radeon_fence_unref(&fence);
502 kfree(work); 505 kfree(work);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 1b557554696..03f124d626c 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -954,10 +954,15 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
954 int dp_lane_count = 0; 954 int dp_lane_count = 0;
955 int connector_object_id = 0; 955 int connector_object_id = 0;
956 int igp_lane_info = 0; 956 int igp_lane_info = 0;
957 int dig_encoder = dig->dig_encoder;
957 958
958 if (action == ATOM_TRANSMITTER_ACTION_INIT) 959 if (action == ATOM_TRANSMITTER_ACTION_INIT) {
959 connector = radeon_get_connector_for_encoder_init(encoder); 960 connector = radeon_get_connector_for_encoder_init(encoder);
960 else 961 /* just needed to avoid bailing in the encoder check. the encoder
962 * isn't used for init
963 */
964 dig_encoder = 0;
965 } else
961 connector = radeon_get_connector_for_encoder(encoder); 966 connector = radeon_get_connector_for_encoder(encoder);
962 967
963 if (connector) { 968 if (connector) {
@@ -973,7 +978,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
973 } 978 }
974 979
975 /* no dig encoder assigned */ 980 /* no dig encoder assigned */
976 if (dig->dig_encoder == -1) 981 if (dig_encoder == -1)
977 return; 982 return;
978 983
979 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) 984 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
@@ -1023,7 +1028,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
1023 1028
1024 if (dig->linkb) 1029 if (dig->linkb)
1025 args.v3.acConfig.ucLinkSel = 1; 1030 args.v3.acConfig.ucLinkSel = 1;
1026 if (dig->dig_encoder & 1) 1031 if (dig_encoder & 1)
1027 args.v3.acConfig.ucEncoderSel = 1; 1032 args.v3.acConfig.ucEncoderSel = 1;
1028 1033
1029 /* Select the PLL for the PHY 1034 /* Select the PLL for the PHY
@@ -1073,7 +1078,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
1073 args.v3.acConfig.fDualLinkConnector = 1; 1078 args.v3.acConfig.fDualLinkConnector = 1;
1074 } 1079 }
1075 } else if (ASIC_IS_DCE32(rdev)) { 1080 } else if (ASIC_IS_DCE32(rdev)) {
1076 args.v2.acConfig.ucEncoderSel = dig->dig_encoder; 1081 args.v2.acConfig.ucEncoderSel = dig_encoder;
1077 if (dig->linkb) 1082 if (dig->linkb)
1078 args.v2.acConfig.ucLinkSel = 1; 1083 args.v2.acConfig.ucLinkSel = 1;
1079 1084
@@ -1100,7 +1105,7 @@ atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t
1100 } else { 1105 } else {
1101 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL; 1106 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1102 1107
1103 if (dig->dig_encoder) 1108 if (dig_encoder)
1104 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER; 1109 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1105 else 1110 else
1106 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER; 1111 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
diff --git a/drivers/gpu/drm/radeon/radeon_family.h b/drivers/gpu/drm/radeon/radeon_family.h
index 6f1d9e563e7..ec2f1ea84f8 100644
--- a/drivers/gpu/drm/radeon/radeon_family.h
+++ b/drivers/gpu/drm/radeon/radeon_family.h
@@ -81,6 +81,8 @@ enum radeon_family {
81 CHIP_CYPRESS, 81 CHIP_CYPRESS,
82 CHIP_HEMLOCK, 82 CHIP_HEMLOCK,
83 CHIP_PALM, 83 CHIP_PALM,
84 CHIP_SUMO,
85 CHIP_SUMO2,
84 CHIP_BARTS, 86 CHIP_BARTS,
85 CHIP_TURKS, 87 CHIP_TURKS,
86 CHIP_CAICOS, 88 CHIP_CAICOS,
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 86eda1ea94d..aaa19dc418a 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -487,6 +487,7 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
487 case THERMAL_TYPE_RV6XX: 487 case THERMAL_TYPE_RV6XX:
488 case THERMAL_TYPE_RV770: 488 case THERMAL_TYPE_RV770:
489 case THERMAL_TYPE_EVERGREEN: 489 case THERMAL_TYPE_EVERGREEN:
490 case THERMAL_TYPE_NI:
490 case THERMAL_TYPE_SUMO: 491 case THERMAL_TYPE_SUMO:
491 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev); 492 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
492 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 493 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index 92f1900dc7c..ea49752ee99 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -758,6 +758,5 @@ r600 0x9400
7580x00009714 VC_ENHANCE 7580x00009714 VC_ENHANCE
7590x00009830 DB_DEBUG 7590x00009830 DB_DEBUG
7600x00009838 DB_WATERMARKS 7600x00009838 DB_WATERMARKS
7610x00028D28 DB_SRESULTS_COMPARE_STATE0
7620x00028D44 DB_ALPHA_TO_MASK 7610x00028D44 DB_ALPHA_TO_MASK
7630x00009700 VC_CNTL 7620x00009700 VC_CNTL
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index f04b2a3b0f4..e08f344c6cf 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -467,6 +467,17 @@
467 {0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 467 {0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
468 {0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 468 {0x1002, 0x9615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
469 {0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 469 {0x1002, 0x9616, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
470 {0x1002, 0x9640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
471 {0x1002, 0x9641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
472 {0x1002, 0x9642, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
473 {0x1002, 0x9643, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
474 {0x1002, 0x9644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
475 {0x1002, 0x9645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO2|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
476 {0x1002, 0x9647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
477 {0x1002, 0x9648, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
478 {0x1002, 0x964a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
479 {0x1002, 0x964e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
480 {0x1002, 0x964f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SUMO|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP},\
470 {0x1002, 0x9710, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 481 {0x1002, 0x9710, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
471 {0x1002, 0x9711, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 482 {0x1002, 0x9711, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
472 {0x1002, 0x9712, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \ 483 {0x1002, 0x9712, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS880|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-05 09:49:17 -0500