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It should use STC_SYSCLK_DIV_OFFSET. Thus fix it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 6ae6698276ca36f37afc2ad38054092021519ad4)
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The current clock selecting mechanism would choose a clock and set its rate
later when using it. It might be feasible for other clock sources but not
for sysclk -- ipg clock. Changing ipg clock rate in specific driver would
be a dangerous operation, so we here ingore the sysclk and will restore it
after we accomplish a better mechanism.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <b42378@freescale.com>
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This patch implements a device-tree-only CPU DAI driver for Freescale
S/PDIF controller that supports stereo playback and record feature.
Signed-off-by: Nicolin Chen <b42378@freescale.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
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