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path: root/sound/mips/au1x00.c
Commit message (Expand)AuthorAge
* ALSA: mips: remove __dev* attributesBill Pemberton2012-12-07
* sound: Add module.h to the previously silent sound usersPaul Gortmaker2011-10-31
* sound: irq: Remove IRQF_DISABLEDYong Zhang2011-09-22
* sound: Add missing spin_unlockJulia Lawall2010-05-27
* Merge branch 'topic/misc' into for-linusTakashi Iwai2009-03-23
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| * ALSA: Add missing KERN_* prefix to printk in other sound/*Takashi Iwai2009-02-05
* | ALSA: Convert to snd_card_create() in other sound/*Takashi Iwai2009-01-12
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* ALSA: Kill snd_assert() in other placesTakashi Iwai2008-08-13
* removed unused #include <linux/version.h>'sAdrian Bunk2008-08-23
* [ALSA] Remove sound/driver.hTakashi Iwai2008-01-31
* Fix misspellings of "system", "controller", "interrupt" and "necessary".Robert P. J. Day2007-10-19
* IRQ: Maintain regs pointer globally rather than passing to IRQ handlersDavid Howells2006-10-05
* [PATCH] sound/mips/au1x00: Use ARRAY_SIZE macroTobias Klauser2006-09-29
* [PATCH] irq-flags: sound: Use the new IRQF_ constantsThomas Gleixner2006-07-02
* [ALSA] AMD Au1x00: AC'97 controller is memory mappedSergei Shtylyov2006-03-22
* [ALSA] AMD Au1x00: fix DMA init/cleanupSergei Shtylyov2006-03-22
* [ALSA] AMD Au1x00: make driver build after cleanupSergei Shtylylov2006-03-22
* [ALSA] Remove snd_card_generic_dev()Takashi Iwai2006-01-03
* [ALSA] Remove xxx_t typedefs: MIPS AU1x00Takashi Iwai2006-01-03
* [ALSA] au1x00 - Code clean upTakashi Iwai2006-01-03
* [ALSA] AMD Au1x00 driver: buggy spinlocksKonstantin Baydarov2005-11-04
* [ALSA] Remove obsolete chip_tTakashi Iwai2005-11-04
* [ALSA] Remove vmalloc wrapper, kfree_nocheck()Takashi Iwai2005-11-04
* [ALSA] Add snd_card_set_generic_dev() callTakashi Iwai2005-09-12
* Linux-2.6.12-rc2Linus Torvalds2005-04-16
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 00:57:13 -0400
span> * DEALINGS IN THE SOFTWARE. */ #ifndef NVGPU_ACR_H #define NVGPU_ACR_H #include <nvgpu/falcon.h> #include "gk20a/mm_gk20a.h" #include "acr_lsfm.h" #include "acr_flcnbl.h" #include "acr_objlsfm.h" #include "acr_objflcn.h" struct nvgpu_firmware; struct gk20a; struct hs_acr_ops; struct hs_acr; struct nvgpu_acr; #define HSBIN_ACR_BL_UCODE_IMAGE "pmu_bl.bin" #define GM20B_HSBIN_ACR_PROD_UCODE "nv_acr_ucode_prod.bin" #define GM20B_HSBIN_ACR_DBG_UCODE "nv_acr_ucode_dbg.bin" #define HSBIN_ACR_UCODE_IMAGE "acr_ucode.bin" #define HSBIN_ACR_PROD_UCODE "acr_ucode_prod.bin" #define HSBIN_ACR_DBG_UCODE "acr_ucode_dbg.bin" #define HSBIN_ACR_AHESASC_PROD_UCODE "acr_ahesasc_prod_ucode.bin" #define HSBIN_ACR_ASB_PROD_UCODE "acr_asb_prod_ucode.bin" #define HSBIN_ACR_AHESASC_DBG_UCODE "acr_ahesasc_dbg_ucode.bin" #define HSBIN_ACR_ASB_DBG_UCODE "acr_asb_dbg_ucode.bin" #define LSF_SEC2_UCODE_IMAGE_BIN "sec2_ucode_image.bin" #define LSF_SEC2_UCODE_DESC_BIN "sec2_ucode_desc.bin" #define LSF_SEC2_UCODE_SIG_BIN "sec2_sig.bin" #define MAX_SUPPORTED_LSFM 3 /*PMU, FECS, GPCCS*/ #define ACR_COMPLETION_TIMEOUT_MS 10000 /*in msec */ #define PMU_SECURE_MODE (0x1) #define PMU_LSFM_MANAGED (0x2) struct bin_hdr { /* 0x10de */ u32 bin_magic; /* versioning of bin format */ u32 bin_ver; /* Entire image size including this header */ u32 bin_size; /* * Header offset of executable binary metadata, * start @ offset- 0x100 * */ u32 header_offset; /* * Start of executable binary data, start @ * offset- 0x200 */ u32 data_offset; /* Size of executable binary */ u32 data_size; }; struct acr_fw_header { u32 sig_dbg_offset; u32 sig_dbg_size; u32 sig_prod_offset; u32 sig_prod_size; u32 patch_loc; u32 patch_sig; u32 hdr_offset; /* This header points to acr_ucode_header_t210_load */ u32 hdr_size; /* Size of above header */ }; struct wpr_carveout_info { u64 wpr_base; u64 nonwpr_base; u64 size; }; /* ACR interfaces */ struct hs_flcn_bl { char *bl_fw_name; struct nvgpu_firmware *hs_bl_fw; struct hsflcn_bl_desc *hs_bl_desc; struct bin_hdr *hs_bl_bin_hdr; struct nvgpu_mem hs_bl_ucode; }; struct hs_acr { u32 acr_type; /* HS bootloader to validate & load ACR ucode */ struct hs_flcn_bl acr_hs_bl; /* ACR ucode */ char *acr_fw_name; struct nvgpu_firmware *acr_fw; struct nvgpu_mem acr_ucode; union { struct flcn_bl_dmem_desc bl_dmem_desc; struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; }; void *ptr_bl_dmem_desc; u32 bl_dmem_desc_size; union{ struct flcn_acr_desc *acr_dmem_desc; struct flcn_acr_desc_v1 *acr_dmem_desc_v1; }; /* Falcon used to execute ACR ucode */ struct nvgpu_falcon *acr_flcn; int (*acr_flcn_setup_hw_and_bl_bootstrap)(struct gk20a *g, struct hs_acr *acr_desc, struct nvgpu_falcon_bl_info *bl_info); }; #define ACR_DEFAULT 0U #define ACR_AHESASC 1U #define ACR_ASB 2U struct nvgpu_acr { struct gk20a *g; u32 bootstrap_owner; u32 max_supported_lsfm; u32 capabilities; /* * non-wpr space to hold LSF ucodes, * ACR does copy ucode from non-wpr to wpr */ struct nvgpu_mem ucode_blob; /* * Even though this mem_desc wouldn't be used, * the wpr region needs to be reserved in the * allocator in dGPU case. */ struct nvgpu_mem wpr_dummy; /* ACR member for different types of ucode */ /* For older dgpu/tegra ACR cuode */ struct hs_acr acr; /* ACR load split feature support */ struct hs_acr acr_ahesasc; struct hs_acr acr_asb; u32 pmu_args; struct nvgpu_firmware *pmu_fw; struct nvgpu_firmware *pmu_desc; int (*prepare_ucode_blob)(struct gk20a *g, struct nvgpu_acr *acr); void (*get_wpr_info)(struct gk20a *g, struct wpr_carveout_info *inf); int (*alloc_blob_space)(struct gk20a *g, size_t size, struct nvgpu_mem *mem); int (*patch_wpr_info_to_ucode)(struct gk20a *g, struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery); int (*acr_fill_bl_dmem_desc)(struct gk20a *g, struct nvgpu_acr *acr, struct hs_acr *acr_desc, u32 *acr_ucode_header); int (*bootstrap_hs_acr)(struct gk20a *g, struct nvgpu_acr *acr, struct hs_acr *acr_desc); void (*remove_support)(struct nvgpu_acr *acr); }; #endif /* NVGPU_ACR_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-18 00:57:12 -0400