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* ENGR00322272-1: ARM: imx6sx: hide the buggy ldb_di_sel mux from clk APIShawn Guo2014-07-11
| | | | | | | | | | | | | | | | This is a smilar change for imx6sx clock tree as what we did for imx6q with commit 0bec46131d88 (ENGR00318063-8: ARM: imx6q: hide buggy ldb_di_sel from clk API). As the valid procedure of switching ldb_di_sel on imx6sx is not available yet, we hide this buggy mux by looking at the parent selection done by bootloader and register it statically to clock framework, so that switching this buggy mux becomes impossible. Also, since the bit width of ldb_di_sels is 3, we add two "dummy" entries for ldb_di_sels to avoid out-of-bounds error. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00318063-3: ARM: imx6sx: fix ocram_sels mux settingShawn Guo2014-06-25
| | | | | | | | | | | | | | | The current imx6sx clock driver combines two mux clocks ocram_alt_sel and ocram_sel into one, while ocram_alt_sel is a glitchy mux and ocram_sel is a glitchless one. Fix it to match the clock tree in Reference Manual. One thing clk API clients need to take care is that clk_set_parent() can be called on glitchy ocram_alt_sel only when ocram_sel selects the other path, i.e. periph. Otherwise, a glitch could be generated on ocram_alt_sel and get propagated into the divider ocram_podf. In that case, ocram_podf gets locked up and ocram clock has no output. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ENGR00310878-1 Asoc: fsl: refine clock tree for ESAIShengjiu Wang2014-04-29
| | | | | | | There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Make the clock for ESAI more clear. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00309977-3 ARM: imx6sx: Drop useless IMX6SX_CLK_AUDIO_GATENicolin Chen2014-04-23
| | | | | | | | Since we've fixed the clock's shared-gate issue, we no longer need this gate clock. Thus drop it. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00306442-1 ARM: imx6sx: Merge SPDIF and AUDIO clocks into one gate clockNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On Solo X, SPDIF and AUDIO clocks shares one single gate to switch two entirely different clock routes: SPDIF <-- <---- SPDIF_PODF ----.... \ / gate1 / \ AUDIO <-- <---- AUDIO_PODF ----.... The two audio modules would easily cause conflict during clock operations if running in the same time: SPDIF <-- gate1 <---- SPDIF_PODF ----.... AUDIO <-- gate1 <---- AUDIO_PODF ----.... To keep them safe, we here have to merge them into one gate clock and limit their rates and parent identical: <---- SPDIF_PODF ----.... / SPDIF, AUDIO <-- gate1 \ <---- AUDIO_PODF ----.... [ The only disadvantage of this modification is that we can not separately set a different clock rates and clock sources to SPDIF and AUDIO clock. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00305648-2 ARM: imx6sx: Add SAI ipg clock to the clock treeNicolin Chen2014-04-16
| | | | | | | There's one clock for SAI memory access missing in the clock tree. Thus add it. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00303122-3 ARM: imx6sx: fix ASRC related clocks in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | | | | | | According to imx6sx RM, there are three clock providers for ASRC: Module clock Clock root Gate asrck_clock_d spdif0_clk_root N/A ipg_clk ahb_clk_root asrc_clk_enable mem_clk ahb_clk_root asrc_clk_enable while the current clock tree describes a clock named 'ASRC' that only describes the asrc_clk_enable function. Thus this patch first adds the other missing clocks to ASRC. [ Since we don't have the gate for asrck_clock_d, we can pass spdif0_clk to ASRC in the devicetree directly. ] Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00302235-2 arm: enable pcie on imx6sxRichard Zhu2014-04-16
| | | | | | | | | - add mandatory pcie related clks in imx6sx clks tree - add pcie dts in imx6sx dts - add pcie kconfig option in imx6sx soc config - add pcie regulate into dts Signed-off-by: Richard Zhu <r65037@freescale.com>
* ENGR00301552-1 ARM: imx6sx: Correct audio_clk in the clock treeNicolin Chen2014-04-16
| | | | | | | | | | | | | We currently has asrc_* clocks in the imx6sx clock tree while actually, according to the Reference Manual, all of them should be named after the audio_clk that controls the external MCLK output from MCLK pad of AUDMUX. Thus fix it along with its gate clock missing in the current clock tree. Meanwhile, this patch also configures a default clock rate for it -- 24MHz. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00299323-11 ARM: imx: Add i.mx6sx enet clk supportFugang Duan2014-04-16
| | | | | | | | | Add i.mx6sx enet clk support: - Add enet2 refrence clock. - Add PTP clock. - Set enet system AHB clock to 200Mh. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00298524-2 ARM: imx: Add MSL support for i.mx6sxAnson Huang2014-04-16
| | | | | | | | | | | | | | It adds initial MSL support for i.mx6sx, including below features: 1. add cpu type check; 2. add system timer support; 3. add clock tree support; 4. add machine layer init support; Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com> Acked-by: Jason Liu
* ENGR00289643-1 arm: imx6sl: add missing spba clock to clock treeNicolin Chen2014-04-16
| | | | | | | | We are missing spba clock in imx6sl's clock tree, thus add it. Acked-by: Wang Shengjiu <b02247@freescale.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00281769 [iMX6SL] Allow uart to be sourced from 24MHz XTALRanjani Vaidyanathan2014-04-16
| | | | | | | | | | In order to optmize low power IDLE numbers all PLLs should be in bypass. On imx6sl, UART can be sourced directly from the 24MHz XTAL. Its frequency is limited to 4MHz due to an internal divide by 6 divider. For customer who don't require higher uart speeds add "uart_at_4M" to the kernel command line. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00281789-01 imx6sl: add missing enet clock for imx6slFugang Duan2014-04-16
| | | | | | There's a enet clock gate missing in clock tree, thus add it. Signed-off-by: Fugang Duan <B38611@freescale.com>
* ENGR00280101-1 [iMX6SL] Add busfreq supportRanjani Vaidyanathan2014-04-16
| | | | | | | Add support to scale the DDR frequency between 400MHz and 24MHz. Add support to scale AHB between 132MHz and 24MHz. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00277715-6 ARM: clk: Add missing pll4_audio_div for imx6slNicolin Chen2014-04-16
| | | | | | | There's a dividor for pll4_audio clock missing in clock tree, thus add it. Acked-by: Shawn Guo <shawn.guo@freescale.com> Signed-off-by: Nicolin Chen <b42378@freescale.com>
* ENGR00274009 ARM: imx: gpt clk on i.mx6sl can NOT source from OSCAnson Huang2014-04-16
| | | | | | | | | | | There is no OSC clock source option for gpt on i.mx6sl, it can only source from perclk, and perclk can be from OSC. As perclk is clock source of many low speed devices, set it to be from OSC, this can avoid freq varying when bus clk(ipg) is scaled. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00273512-2 ARM: imx: Change GPT clock source to OSCAnson Huang2014-04-16
| | | | | | | | | | GPT clock is system clock source, need to avoid freq varying, as system bus clock(ipg) may be changed, for i.mx6 series SOCs, all of them except i.mx6q TO1.0 support sourcing GPT clk from OSC directly, so switch gpt clock to OSC if the SOCs support this feature, as OSC freq is constant. Signed-off-by: Anson Huang <b20788@freescale.com>
* ARM: imx: fix vf610 enet module clock selectionShawn Guo2014-04-16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fec/enet driver calculates MDC rate with the formula below. ref_freq / ((MII_SPEED + 1) x 2) The ref_freq here is the fec internal module clock, which is missing from clk-vf610 clock driver right now. And clk-vf610 driver mistakenly supplies RMII clock (50 MHz) as the source to fec. This results in the situation that fec driver gets ref_freq as 50 MHz, while physically it runs at 66 MHz (fec module clock physically sources from ipg which runs at 66 MHz). That's why software expects MDC runs at 2.5 MHz, while the measurement tells it runs at 3.3 MHz. And this causes the PHY KSZ8041 keeps swithing between Full and Half mode as below. libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half libphy: 400d0000.etherne:00 - Link is Up - 100/Full libphy: 400d0000.etherne:00 - Link is Up - 100/Half Add the missing module clock for ENET0 and ENET1, and correct the clock supplying in device tree to fix above issue. Thanks to Alison Wang <b18965@freescale.com> for debugging the issue. Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add VF610 clock supportJingchang Lu2014-04-16
| | | | | | | | | | | | Commit 1f2c5fd5f0486566f73aa0149577d5f69df90bcc upstream. Add clock support for Vybrid VF610. It uses dtc macro support to define all clock IDs in vf610-clock.h to keep clock IDs coherence between kernel and DT. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
* ARM: imx: add clock support for imx6slShawn Guo2014-04-16
Commit 45fe6810347b0a83561a13d9ee656c899a309fc0 upstream. Add clock support for i.MX6 SoloLite. It uses the dtc marco support to define all clock IDs in imx6sl-clock.h, which will be included by both clock driver and device tree sources, so that the data will stay sync all the time between kernel and DT. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
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