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* ENGR00322215 EPDC: kernel dump when do EPDC framebuffer unit testFancy Fang2014-07-17
| | | | | | | | | | | | | | [<80013b00>] (unwind_backtrace+0x0/0xf4) from [<80011524>] (show_stack+0x10/0x14) [<80011524>] (show_stack+0x10/0x14) from [<8026bc4c>] (Ldiv0+0x8/0x10) [<8026bc4c>] (Ldiv0+0x8/0x10) from [<802c1144>] (pxp_dispatch_thread+0xd74/0x11f8) [<802c1144>] (pxp_dispatch_thread+0xd74/0x11f8) from [<80046a90>] (kthread+0xb4/0xb8) [<80046a90>] (kthread+0xb4/0xb8) from [<8000e118>] (ret_from_fork+0x14/0x3c) This is caused by div by 0 in some corner cases. So add the check before doing the division. Signed-off-by: Fancy Fang <chen.fang@freescale.com> (cherry picked from commit 2a5dfad5ff763d4eb8b33628ea96291ad4b95d5e)
* ENGR00319406-3 PXP: refine rotation feature to support more cases for ↵Fancy Fang2014-06-26
| | | | | | | | | | | multimedia usage After dropping the output offset calculating step, the rotation coordinates should be calculated to make it work properly. Signed-off-by: Fancy Fang <chen.fang@freescale.com> (cherry picked from commit cf975a339015797707fc471b0526b4089631943a)
* ENGR00319406-2 PXP: remove the rot_pos=1 support temporarilyFancy Fang2014-06-26
| | | | | | | | | Remove the rotation operation support before composite, since this function has several big limitations and it is almost useless in the real applcations. Signed-off-by: Fancy Fang <chen.fang@freescale.com> (cherry picked from commit 18cbd7c5f12ff0be2b75634dfeb2af7827b6811b)
* ENGR00319406-1 PXP: don't need to calculate the offset for output bufferFancy Fang2014-06-26
| | | | | | | | | The original copy operation done by PXP can be replaced by alpha blending + colorkey. And this is more reasonable in the view of PXP hardware. Signed-off-by: Fancy Fang <chen.fang@freescale.com> (cherry picked from commit e8c0cd431108ae9cac2af33f99e4aeae900984a4)
* ENGR00319473: dma: imx-sdma: support sdma restore from mega/fast power down ↵Robin Gong2014-06-25
| | | | | | | | | status Support sdma suspend and resume interface to restore from mega/fast power down. Signed-off-by: Robin Gong <b38343@freescale.com> (cherry picked from commit 9489283e164f16355baf15bf917238e33375485c)
* ENGR00318965 dma: sdma: swap LWML and HWML of INFO if LWML > HWMLRobin Gong2014-06-19
| | | | | | | | Correct r0, r1 and INFO parames if LWML > HWML in DEV_TO_DEV case. Below link raise up the issue: https://community.freescale.com/message/410174?et=watches.email.thread#410174 Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00318995 V4L2_PXP: no overlay can be seen in the pxp_v4l2 test caseFancy Fang2014-06-18
| | | | | | | The "layer_nr" field in struct pxp_config_data is modified by the memset unconsciously. So this field should not reset. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00313660 PXP: fix a build warning brought in by a previous patchFancy Fang2014-05-14
| | | | | | Fix a build warning brought in by a previous patch in PXP driver. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00313080 ARM: imx6sl: fix the incorrect out_lrc settings of PXP when ↵Fancy Fang2014-05-12
| | | | | | | | | | rot_pos==1 This is a typing error by mistake in a previous patch. Obviously, the out_lrc settings should not be the same between rot_pos == 0 and rot_pos == 1. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00313072 dma: sdma: sdma can't work for p2p in some case.Shengjiu Wang2014-05-12
| | | | | | | | | | | | | | | | | | | sdma can't work for p2p when "dma_request0 < 31, dma_request1 > 31". The context parameter for p_2_p script is described in RM A.3.2.5.1 r0: LWML event mask, combined with bit28 of INFO r1: HWML event mask, combined with bit29 of INFO r7: INFO: bit 28: LWML Event (0 - LWE in EVENTS, 1 - LWE in EVENTS2); bit 29: HWML event (0 - HWE in EVENTS, 1 - HWE in EVENTS2); In sdma_load_context(), we set r0 = event_mask1, r1 = event_mask0. which means the event_mask1 is LWML event mask, event_mask0 is HWML event mask. In sdma_config_channel() Event_id0 set the bit 28, which means event_id0 is corresponding to event_mask1, event_id1 is corresponding to event_mask0. So here we need to correct the wrong setting in sdma_config_channel(), for some setting didn't follow this principle. Signed-off-by: Shengjiu Wang <b02247@freescale.com>
* ENGR00312702-2 PXP: Reset channel state before pxp channel configurationSandor Yu2014-05-12
| | | | | | | Reset struct of pxp_conf_state to zero before pxp channel configuration, in case some application miss configuration struct ol_param. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00310844 [IMX6SX_SDB/IMX6SL_EVK]Video Display: All the videos have a ↵Fancy Fang2014-05-11
| | | | | | | | | | | | green line at the bottom when play with 'gplay' and 'gplay-1.0' This issue is due to the incorrect settings for PXP_SCALE register. On the previous settings, when the PXP need to do interpolation operation in SCALE engine, it has out-of-range image access. So we need to adjust the scaling settings to make this issue not happen through sacrifising some unnoticed image precise. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00308770-2 : dma: sdma: add new sdma scripts for qspi/canfdRobin Gong2014-04-17
| | | | | | update sdma script and the script number. Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00307014-01 dma: pxp: Add YUV444 csc supportSandor Yu2014-04-17
| | | | | | Add YUV444 csc support in pxp driver. Signed-off-by: Sandor Yu <R01008@freescale.com>
* ENGR00308001 dma: imx-sdma: add support for sdma memory copyRobin Gong2014-04-16
| | | | | | | | | | | This patch use more common dma interface , including "device_prep_dma_memcpy" and "device_prep_dma_sg". The way in v3.0.35 reuse "device_prep_slave_sg" and need call twice to tell dest dma address in one memory copy(ENGR00233569). It looks tricky something, so give up the original patch. In this patch,"device_prep_dma_memcpy" support memory copy by buffer and "device_prep_dma_sg" support memory copy by scatter-list. You can get the example code from 'linux-test/module_test/mxc_sdma_memcopy_test.' Signed-off-by: Robin Gong <b38343@freescale.com>
* ENGR00307635-2 dmaengine: imx-sdma: Add imx6sx platform supportNicolin Chen2014-04-16
| | | | | | | | | | | | | | The new Solo X has more requirements for SDMA events. So it creates a event mux to remap most of event numbers in GPR (General Purpose Register). If we want to use SDMA support for those module who do not get the even number as default, we need to configure GPR first. Thus this patch adds this support of GPR event remapping configuration to the SDMA driver. Acked-by: Robin Gong <b38343@freescale.com> Acked-by: Huang Shijie <b32955@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00304418 [V4l2][PXP] Add some rotation cases support for V4L app.Fancy Fang2014-04-16
| | | | | | | | Some V4L2 apps require that playing rotated fullscreen video on the screen. In recent PXP driver, this is not supported yet. So this patch adds it on through combining rotation and resize together. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* dma: of: Remove restriction that #dma-cells can't be 0Lars-Peter Clausen2014-04-16
| | | | | | | | | | | | | | | | | | There is no sensible reason why #dma-cells shouldn't be allowed to be 0. It is completely up to the DMA controller how many additional parameters, besides the phandle, it needs to identify a channel. E.g. for DMA controller with only one channel or for DMA controllers which don't have a restriction on which channel can be used for which peripheral it completely legitimate to not require any additional parameters. Also fixes the following warning: drivers/dma/of-dma.c: In function 'of_dma_controller_register': drivers/dma/of-dma.c:67:7: warning: 'nbcells' may be used uninitialized in this function Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com> (cherry picked from commit ff0e0f4f568e8d7593e0035c0c58067bcaf4ab07)
* ENGR00305648-8 dma: imx-sdma: Add SAI script supportNicolin Chen2014-04-16
| | | | | | | This patch adds SAI script support to imx-sdma. Acked-by: Wang Shengjiu <b02247@freescale.com> Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
* ENGR00304574-2 dma: mxs-dma: add the dependency for SOC_IMX6SXHuang Shijie2014-04-16
| | | | | | Add the dependency for imx6sx. Signed-off-by: Huang Shijie <b32955@freescale.com>
* ENGR00299748-1 imx: pxp: add display_axi_clock handling for imx6sxRobby Cai2014-04-16
| | | | | | | | The display axi clock is a clock gating newly added on imx6sx. It need to be enabled for lcdif/pxp/csi/pcie to work. It should be set as a placeholder on other SoCs. Signed-off-by: Robby Cai <R63905@freescale.com>
* ENGR00298631 PXP: remove pxp_hw_init() when do pxp probeFancy Fang2014-04-16
| | | | | | | | Since the pxp registers have been already set to default values after hardware reset, it is not necessary to re-initialize them again. And this can accelerate the system booting procedure. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00298338 PXP: fix hang issue due to read pxp reg when clk disabledFancy Fang2014-04-16
| | | | | | | | The function dump_pxp_reg() may be called when the pxp clock is disabled. So this will cause system hang issue. Now add clock enable/disable pair to this function call. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00298315 PXP: PXP registers should be reset to default after each task ↵Fancy Fang2014-04-16
| | | | | | | | | | finished The PXP registers should be cleared to its default values after each task done to avoid affecting the other later tasks status. And PXP CTRL register provide a SFTRST bit to do this on hardware level. Signed-off-by: Fancy Fang <chen.fang@freescale.com>
* ENGR00294115 PXP: correct the pxp_dispatch thread exit logicFancy Fang2014-04-16
| | | | | | | We should add thread stop checking before handle pxp task, since the wait condition includes this check. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00294114 PXP: correct the PS U/V buffer settings when format is YVU420PFancy Fang2014-04-16
| | | | | | | | The PXP itself doesn't support YVU420P default. But we can get the U and V address according to the format when we try to set PS_UBUF and PS_VBUF registers. So the YVU420P can be supported indirectly. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293898 PXP: set the pxp_dispatch kernel thread to be freezable to ↵Fancy Fang2014-04-16
| | | | | | | | | | | | | avoid hang By default, the kernel thread cannot be freezed during pm suspend. So during pm suspend, the pxp_dipatch thread is still handling pxp task and setting pxp registers. And in some time, this pxp register setting may happen after the pxp_suspend done. So the hang issue happens. This patch set the thread to be freezable to freeze it before pxp_suspend called to avoid this hang issue. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293323 PXP: add WC and cacheable dma buffer support for PXP deviceFancy Fang2014-04-16
| | | | | | | | | This change add support for new dma buffer type(writecombine and cacheable) which allows user application has more choices for the buffer type. And if the dma buffer is cacheable, then add flush interfaces to make it cache coherent when necessary. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293292 PXP: enhance channel and buffer reclaim for PXP deviceFancy Fang2014-04-16
| | | | | | | | Enhance channel and buffer reclaim to make sure that all the allocated resources which are not freed yet to be freed when the device file descriptor release() function called. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293234 PXP: let irq_pending variable to be atomicFancy Fang2014-04-16
| | | | | | | Change irq_pending field in struct pxp_irq_info to a atomic type. So the spin lock in pxp_irq_info is unnecessary. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293211 PXP: bind allocated DMA channels to opened device file descriptorFancy Fang2014-04-16
| | | | | | | | | | | The allocated DMA channels via some opened file descriptor is better to be bound to this descriptor. Since this can avoid some application to fake a channel id which may be requested by other applications to request PXP service. And also, this make it easier to release the dma channel when application exists abnormally or forgets to release it explicitly. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293170 PXP: remove cpu_addr field from struct pxp_mem_descFancy Fang2014-04-16
| | | | | | | | | | The cpu_addr field in struct pxp_mem_desc cannot be used by user application, so it is not necessary to pass this field data to user. Now the similar field 'virtual' in struct pxp_buf_obj is used to store the kernel space virtual addr for allocated dma buffer. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00293119 PXP: change the dma buffer lists management for PXP deviceFancy Fang2014-04-16
| | | | | | | | | Create pxp_info struct data for each opened device file descriptor. And bind all the allocated dma buffers to this struct for each opened file. This makes the dma buffer lists management safer, more effective and more flexible. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00292816 PXP: move two struct definitions to pxp_device.hFancy Fang2014-04-16
| | | | | | | | Move two struct definitions defined in pxp_device.c to pxp_device.h. Now the pxp_device.h has been created for PXP device driver. So all the type definition should stay in header file not c source file. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00292607 PXP: define a static dma_chan array to record channel statusFancy Fang2014-04-16
| | | | | | | Since the number of dma channels is constant, it is more efficient to use an array to record all the channels alloc/free status. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00292562 PXP: move the definitions used only by PXP device to a new ↵Fancy Fang2014-04-16
| | | | | | | | | | header file Some definitions used only by PXP device driver should not stay in pxp_dma.h which is shared by PXP, EPDC and V4L2. So the patch creates a new header file pxp_device.h to hold these definitions. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00292398 PXP: refine two spin locks usage in PXP dma driverFancy Fang2014-04-16
| | | | | | | | | | | | This patch provides the following refinements: 1. For pxp channel lock, use spin_lock() instead of spin_lock_irqsave(). Since this lock is not used in any ISR. Moreover, this can increase the driver's concurrency with no local irq disabled. 2. Narrow down the pxp lock's locking range in pxp_issue_pending(). Since this lock is also used in PXP ISR, so its hold time should be as few as possible to reduce the time when local irq disabled. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00292369 PXP: remove unnecessary head list empty checkFancy Fang2014-04-16
| | | | | | | | | The head list empty check in function pxpdma_dostart_work() is meaningless, since this function only can be called when there is some pxp task in the head list, that is to say head list is not empty. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00292129 PXP: remove some unnecessary code from PXP dma driverFancy Fang2014-04-16
| | | | | | | There is no need to use spin lock in pxp_prep_slave_sg() after dynamic descriptors allocation enabled. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00291731 PXP: move pxp_irq_info definition from PXP dma to PXP deviceFancy Fang2014-04-16
| | | | | | | | struct pxp_irq_info is only used by PXP device driver, so it is unreasonable to define it in pxp_dma.h which will be included by EPDC, V4L2 PXP and PXP device driver. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00291729 PXP: remove a mutex lock from pxp channelFancy Fang2014-04-16
| | | | | | | | | This mutex lock is no longer necessary in PXP dma driver. After the commit "ENGR00291400 PXP: Organize PXP task queue to be FIFO", protection fields can be protected by the spin lock in PXP channel now. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00291658 PXP: allow PXP device users to submit multiple tasks before ↵Fancy Fang2014-04-16
| | | | | | | | | | | | start PXP After the commit "ffcad666548417ef21937e0a755d85ab922313a9" pushed, adding this support in PXP device driver is also necessary. This change allows users to submit more than one PXP tasks followd by only one wait for finished ioctl. It means that users can wait for more than one tasks done by calling one PXP_IOC_WAIT4CMPLT ioctl. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00291400 PXP: Organize PXP task queue to be FIFOFancy Fang2014-04-16
| | | | | | | | | | | | The requested PXP tasks were handled based on channel unit. All the tasks in one channel were handled one by one, and the tasks in another channel only can get chance after all the tasks in previous channel were finished. So this may allow some channel occupies PXP hardware exclusively all the time, and other channels may never get PXP services. So this change makes the PXP task queue to be a FIFO to avoid this kind of unfair usage for PXP. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00290664 PXP: allocate DMA TX descriptors on demand instead of in PXP ↵Fancy Fang2014-04-16
| | | | | | | | | | | | | initialization In previous PXP driver, the number of tx descriptors allocated for each channel is a constant 16 and they can only be allocated during PXP initialization. But since the driver allows users to queue more than one PXP tasks for each channel before issuing pending tasks, so in this case the descriptors may be not enough for some cases. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00290613 PXP: add asynchronous multi instances support for PXPFancy Fang2014-04-16
| | | | | | | | | Move PXP registers setting from pxp_issue_pending() to a seperate kernel thread. This change will avoid the multi instances hang issues solved in previous commits. And also the pxp users won't be blocked when it call dma_async_issue_pending() function. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00290236 PXP: Correct PXP settings when s0 format is PXP_PIX_FMT_YUV422PFancy Fang2014-04-16
| | | | | | | When the s0 format is PXP_PIX_FMT_YUV422P, the s0 pitch and U/V buffer address cannot be set correctly. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00289859 PXP: fix that multi users may access PXP hardware simultaneouslyFancy Fang2014-04-16
| | | | | | | | | After the patch 6320ada11093ef0a4ded9065d6ae284a9129f7d6, there still exists some cases that more than one user would set PXP hardware registers before the previous task done. Now use another mutex lock to make sure that registers settings can only happen when PXP hardware is idle. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00289237 PXP: fix a multiple instances hang issueFancy Fang2014-04-16
| | | | | | | | | | In pxp_issue_pending(), the wait for pxp done processes will be woken up together in PXP ISR. So there will be some situations that one process will set PXP hardware registers after another process's setting but before the first PXP task done. So the PXP hardware may be corrupted and hang maybe happen. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00285283 PXP: make pxp driver compatible for G2DFancy Fang2014-04-16
| | | | | | | | Use stride to set AS and PS pitch by default, if stride is 0, then use width to set AS and PS pitch instead. This will make PXP driver both work for PXP kernel users and G2D applications. Signed-off-by: Fancy Fang <B47543@freescale.com>
* ENGR00284411-1 PXP: Enhance YUV, alpha blend and rotationFancy Fang2014-04-16
| | | | | | | | Support YUV formats like: I420, NV12, NV21, UYVY, YUYV, VYUY, YVYU, NV16, NV61 and YV12. Support rotation in both stages before and after alpha blending. Signed-off-by: Fancy Fang <B47543@freescale.com>
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