| Commit message (Collapse) | Author | Age |
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Support sdma suspend and resume interface to restore from mega/fast power down.
Signed-off-by: Robin Gong <b38343@freescale.com>
(cherry picked from commit 9489283e164f16355baf15bf917238e33375485c)
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The usdhc could also be wakeup source, thus add it into the mege_fast
wakeup source list.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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After adding mega fast support, the default enabled usdhc wakeup will block
M/F to gate off power domain.
To avoid this issue, we only claim wakeup capability and reply on user to enable
it via sysfs according to real needs.
The drawback of such change is that for SDIO WiFi Wakeup On Wireless feature,
User has to enable both uSDHC and WiFi WoW wakeup mannually to make
WoW work well.
BTW, due to the wakeup feature is controller itself, so we do not need to reply
on WiFi PM flags to enable it.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Date: Jun 16, 2014
Signed-off-by: Loren Huang <b02279@freescale.com>
Acked-by: Shawn Guo
(cherry picked from commit a6f5349968e494d67f9da339dad433b528ce52fe)
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The reason is that PRRC and PCRC isn't cleared in restore_reg(), then
update_bits for PCRC and PRRC will fail for cache is not updated.
In other side, remove the store_reg() and restore_reg for adding regcache,
and use regcache_sync to restore the registers.
Signed-off-by: Shengjiu Wang <b02247@freescale.com>
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The mmc core will reserve the mmc index for the specific controller
by add mmc alias in device tree.
There's an eMMC chip on sabresd board on uSDHC slot 4.
We want it be fixed to mmc0 to be used for finding rootfs persistently.
So adding Alias mmc0 to usdhc4 in device tree.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
(cherry picked from commit 4cd99820322abca9c9d2b82ee2513aa9d096c02b)
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As with gpio, uart and others, allow specifying the name_idx via the
aliases-node in the devicetree.
On embedded devices, there is often a combination of removable (e.g.
SD card) and non-removable mmc devices (e.g. eMMC).
Therefore the name_idx might change depending on
- host of removable device
- removable card present or not
This makes it difficult to hard code the root device, if it is on the
non-removable device. E.g. if SD card is present eMMC will be mmcblk1,
if SD card is not present at boot, eMMC will be mmcblk0.
If the aliases-node is not found, the driver will act as before.
The original patch is from here:
https://www.mail-archive.com/linux-mmc@vger.kernel.org/msg26472.html
The patch requires additional alias_id fix or it won't work.
Because according to function definition the max_idx parameter of idx_alloc
is exclusive, so need add 1 or it will be unable to find the proper idx
within an invalid range.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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of_alias_max_index will return the maximum number for which an
alias of a given stem exists. This is useful for frameworks
whishing to reserve a number of device slots from dynamic
allocation.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
(cherry picked from commit 18ae7362e9822993436c1a544e49cfd58fa175b2)
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Since i.MX6SX doesn't supports MLB150 , it is not strictly explicit to
name driver module as mxc_mlb150.ko. Rename it to mxc_mlb.ko.It would be
more common.
Signed-off-by: Luwei Zhou <b45643@freescale.com>
(cherry picked from commit dbe1a350e2f61e827501fd322951b9ea255461a5)
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There are about 0.02% percentage on some imx6q/dl/solo
hw boards, random pcie link down when warm-reset is used.
Make sure to clear the ref_ssp_en bit16 of gpr1 before
warm-rst, and set ref_ssp_en after the pcie clks are
stable to workaround it.
rootcause:
* gpr regisers wouldn't be reset by warm-rst, while the
ref_ssp_en is required to be reset by pcie.
(work-around in u-boot)
* ref_ssp_en should be set after pcie clks are stable.
(work-around in kernel)
Signed-off-by: Richard Zhu <r65037@freescale.com>
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add suspend/resume functions and reset qspi controller when resume.
Signed-off-by: Allen Xu <b45815@freescale.com>
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For imx6sx 17x17/19x19 arm2 board, add enet as mege_fast wakeup source.
For imx6sx sdb board, it don't support wake on lan, so it cannot support
enet as mega_fast wake up source.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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To support DSM with M/F mix off, driver need to call phy_stop before
suspend, call phy_start after resume.
Signed-off-by: Fugang Duan <B38611@freescale.com>
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enable canfd by default.
The defconfig is generated by make ARCH=arm savedefconfig
which got the uneeded CONFIG_USB_PHY removed.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Introduce a new dtb imx6sx-sdb-canfd.dtb due to pin conflict with flexcan.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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Switch on the transceiver by default for board with canfd enabled
since canfd driver does not handle it.
Two CAN instances share the same switch.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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The patch adds the basic CAN TX/RX function support for Bosch M_CAN controller.
For TX, only one dedicated tx buffer is used for sending data.
For RX, RXFIFO 0 is used for receiving data to avoid overflow.
Rx FIFO 1 and Rx Buffers are not used currently, as well as Tx Event FIFO.
Due to the message ram can be shared by multi m_can instances
and the fifo element is configurable which is SoC dependant,
the design is to parse the message ram related configuration data from device
tree rather than hardcode define it in driver which can make the message
ram using fully transparently to M_CAN controller driver,
then we can gain better driver maintainability and future features upgrade.
M_CAN also supports CANFD protocol features like data payload up to 64 bytes
and bitrate switch at runtime, however, this patch still does not add the
support for these features.
Signed-off-by: Dong Aisheng <b29396@freescale.com>
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The commit 96c50caa5148 (net: fec: Enable IP header hardware checksum)
enable HW IP header checksum for IPV4 and IPV6, which causes IPV6 TCP/UDP
cannot work. (The issue is reported by Russell King)
For FEC IP header checksum function: Insert IP header checksum. This "IINS"
bit is written by the user. If set, IP accelerator calculates the IP header
checksum and overwrites the IINS corresponding header field with the calculated
value. The checksum field must be cleared by user, otherwise the checksum
always is 0xFFFF.
So the previous patch clear IP header checksum field regardless of IP frame
type.
In fact, IP HW detect the packet as IPV6 type, even if the "IINS" bit is set,
the IP accelerator is not triggered to calculates IPV6 header checksum because
IPV6 frame format don't have checksum.
So this results in the IPV6 frame being corrupted.
The patch just add software detect the current packet type, if it is IPV6
frame, it don't clear IP header checksum field.
Cc: Russell King <linux@arm.linux.org.uk>
Reported-and-tested-by: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Test i2c device Maxim max44009, datasheet is located at:
http://www.maximintegrated.com/datasheet/index.mvp/id/7175
The max44009 support repeat operation like:
read -> repeat restart -> read/write
The current i2c imx host controller driver don't support this
operation that causes i2c bus hang due to "MTX" is cleared in
.i2c_imx_read(). If "read" is the last message there have no problem,
so the current driver supports all SMbus operation like:
write -> repeat restart -> read/write
IMX i2c controller for master receiver has some limitation:
- If it is the last byte for one operation, it must generate STOP
signal before read I2DR to prevent controller from generating another
clock cycle.
- If it is the last byte in the read, and then do repeat restart, it must
set "MTX" before read I2DR to prevent controller from generating another
extra clock cycle.
The patch is to fix the issue.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
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The clock sources from ASRC, ESAI and MLB are not actually from CCM but
outside PAD inputs. So we these clock sources over here are totally wrong
and should be fixed.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, AUDMUX needs to
save all the values of registers before the system suspend and restore them
after the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SSI needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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MEGA Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SPDIF needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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Fast
For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, ESAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, SAI needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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STOP
The SDMA driver doesn't support DMA_PAUSE and DMA_RESUME commands.
So this patch use TRIGGER_START for TRIGGER_RESUME and TRIGGER_SUSPEND
for TRIGGER_STOP as a work around so that Audio can normally stop
and restart its corresponding DMA channels.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
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For i.MX6 SoloX, there is a mode of the SoC to shutdown all power source of
modules during system suspend and resume procedure. Thus, ASRC needs to save
all the values of registers before the system suspend and restore them after
the system resume.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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We actually do nothing to process input buffer. Thus simplify it.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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wait_for_compeltion code
After dropping the extra task for last period buffer fetching, we have a total
symmetrical wait_for_compeltion here so it's better to abstract a function to
make the driver neat.
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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period data
The original design:
-> Input DMA task -> complete()
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-> Output DMA task -> complete()
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| -> Last period polling work thread -> complete()
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Main thread --------------> wait_for_completion() of Input and last period
It's too complicated and worthless to use an extra work thread for last period data.
So this patch just switches the flow into a simpler approach:
-> Input DMA task -> complete()
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-> Output DMA task -> complete()
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Main thread --------------> wait_for_completion() of In/Output -> Last period polling
Acked-by: Wang Shengjiu <b02247@freescale.com>
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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regcache_sync_block_raw_flush takes the address of the base register
and the address of one past the last register to write to. "count" is
the number of registers in the range, not the number of bytes, it
should be (end addr - start addr) / stride. Without accounting for
strides greater than one, registers past the end might be synced or
the writeable_reg callback at the beginning of _regmap_raw_write will
fail and nothing will be written.
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 78ba73eecd2256790926859849801c0446766c0a)
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
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The regular state before we execute SNDRV_PCM_TRIGGER_SUSPEND should be
SNDRV_PCM_TRIGGER_START, not SNDRV_PCM_TRIGGER_STOP. Thus fix it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Mark Brown <broonie@linaro.org>
(cherry picked from commit 868a6ca84ee7e547ae01a5e04e232e4a392c50b8)
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ldo-bypass mode
In case ldo-bypass mode, we will use 'pureg_dummy' in stead of 'vddpu'.The
voltage setting is 0x1f(ldo-mode) and the non-zero value means 'vddpu' enabled
status. Regulator common framwork will turn off the unused regulator which keep
enabled status. That will set the PU mode from ldo-bypass to power off, and may make
gpu/vpu driver hang etc. You can also see the below abnormal message during boot:
[ 3.000182] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4
[ 3.010577] VGEN3: disabling
[ 3.015116] VGEN2: disabling
[ 3.019659] VGEN1: disabling
[ 3.023598] vddpu: disabling
Signed-off-by: Robin Gong <b38343@freescale.com>
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Correct r0, r1 and INFO parames if LWML > HWML in
DEV_TO_DEV case. Below link raise up the issue:
https://community.freescale.com/message/410174?et=watches.email.thread#410174
Signed-off-by: Robin Gong <b38343@freescale.com>
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code
Remove useless code for release interrupt enabled, because we check status by
timer rather than release interrupt. Remove the code which may disable depress
interrupt. Also make sure enable depress interrupt in suspend function.
Signed-off-by: Robin Gong <b38343@freescale.com>
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There is a small window after system suspend but timer scan function
didn't finish timely, in this case, system enter suspend without kpp
interrupt enabled and failed to resume back if key depressed.We add
pm_stay_awake and pm_relax to make sure system suspend flow abort in
this case.
Signed-off-by: Robin Gong <b38343@freescale.com>
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The "layer_nr" field in struct pxp_config_data is modified by the
memset unconsciously. So this field should not reset.
Signed-off-by: Fancy Fang <chen.fang@freescale.com>
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this patch adds the support for kernel cmdline "no_console_suspend".
Signed-off-by: Huang Shijie <b32955@freescale.com>
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The wait_event() makes the application hang for ever in the following case:
[1] the hardware flow control is enabled.
[2] the other end (or the remote end) is terminated, and the TX is still
waiting for the hardware flow control signal to become asserted.
This patch fixes it by changing the wait_event to wait_event_interruptible.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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When the uart port is suspending, the RX data is useless.
So in this case, we can terminate the RX DMA right now.
Signed-off-by: Huang Shijie <b32955@freescale.com>
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When Mega/Fast mix is off, UART controller will lost power,
so need to add save/restore to make it work after resume.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
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Add mega fast domain power off feature in DSM, it can save about
0.72mW power;
If there is any module in Mega/Fast domain enabled as wakeup source,
then Mega/Fast domain's power will be kept on in DSM.
Signed-off-by: Anson Huang <b20788@freescale.com>
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Add Mega/Fast domain's wakeup source info for kernel, if there
is wakeup source in Mega/Fast domain enabled, then this domain's
power can NOT be disabled in DSM.
Signed-off-by: Anson Huang <b20788@freescale.com>
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suspend/resume
This patch ensures that the SCU and certain A9 CP15 registers state are maintained across
a suspend/resume cycle:
1. Need to ensure that SCU standby bit is set again after suspend/resume cycle, else
the system will never WAIT mode after a suspend/resume cycle. This bit should be enabled
on all SMP systems immaterial of whether CPUIDLE is enabled or not.
2. Several A9 errata workarounds involve setting bits in the ARM diagnostic register.
Save/restore this register across a suspend/resume cycle.
3. Save and restore the A9 power control register also.
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>
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Remove register setting that not define in specification.
Signed-off-by: Sandor Yu <R01008@freescale.com>
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Add software TSO support for FEC.
This feature allows to improve outbound throughput performance.
Tested on imx6dl sabresd board, running iperf tcp tests shows:
- 16.2% improvement comparing with FEC SG patch
- 82% improvement comparing with NO SG & TSO patch
$ ethtool -K eth0 tso on
$ iperf -c 10.192.242.167 -t 3 &
[ 3] local 10.192.242.108 port 35388 connected with 10.192.242.167 port 5001
[ ID] Interval Transfer Bandwidth
[ 3] 0.0- 3.0 sec 181 MBytes 506 Mbits/sec
During the testing, CPU loading is 30%.
Since imx6dl FEC Bandwidth is limited to SOC system bus bandwidth, the
performance with SW TSO is a milestone.
CC: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
CC: Eric Dumazet <eric.dumazet@gmail.com>
CC: David Laight <David.Laight@ACULAB.COM>
CC: Li Frank <B20596@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry-pick and merge from linux-net:79f339125ea31)
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Add Scatter/gather support for FEC.
This feature allows to improve outbound throughput performance.
Tested on imx6dl sabresd board:
Running iperf tests shows a 55.4% improvement.
$ ethtool -K eth0 sg off
$ iperf -c 10.192.242.167 -t 3 &
[ 3] local 10.192.242.108 port 52618 connected with 10.192.242.167 port 5001
[ ID] Interval Transfer Bandwidth
[ 3] 0.0- 3.0 sec 99.5 MBytes 278 Mbits/sec
$ ethtool -K eth0 sg on
$ iperf -c 10.192.242.167 -t 3 &
[ 3] local 10.192.242.108 port 52617 connected with 10.192.242.167 port 5001
[ ID] Interval Transfer Bandwidth
[ 3] 0.0- 3.0 sec 154 MBytes 432 Mbits/sec
CC: Li Frank <B20596@freescale.com>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry-pick and merge form linux-net: 6e909283cb3)
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IP header checksum is calcalated by network layer in default.
To support software TSO, it is better to use HW calculate the
IP header checksum.
FEC hw checksum feature request the checksum field in frame
is zero, otherwise the calculative CRC is not correct.
For segmentated TCP packet, HW calculate the IP header checksum again,
it doesn't bring any impact. For SW TSO, HW calculated checksum bring
better performance.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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In order to enhance the code readable, let's factorize the
feature list.
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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Make the code more readable and easy to support other features like
SG, TSO, moving the common transmit function to one api.
And the patch also factorize the getting BD index to it own function.
CC: David Laight <David.Laight@ACULAB.COM>
Signed-off-by: Fugang Duan <B38611@freescale.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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