diff options
author | Sandor Yu <R01008@freescale.com> | 2014-06-03 04:02:50 -0400 |
---|---|---|
committer | Sandor Yu <R01008@freescale.com> | 2014-06-13 10:41:00 -0400 |
commit | d5ca6cfc5aa134ea974dd16dd9783fa8d1e36634 (patch) | |
tree | 366b0663fd9f8ab01143537f4f4fa2cd833a6c1f | |
parent | 2391741646c77916c6224095120d70208ca2dfe9 (diff) |
ENGR00316536 vadc: Remove register setting that not define in specification
Remove register setting that not define in specification.
Signed-off-by: Sandor Yu <R01008@freescale.com>
-rw-r--r-- | drivers/media/platform/mxc/capture/mxc_vadc.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/drivers/media/platform/mxc/capture/mxc_vadc.c b/drivers/media/platform/mxc/capture/mxc_vadc.c index 05b2708d44b8..bb114e1f9994 100644 --- a/drivers/media/platform/mxc/capture/mxc_vadc.c +++ b/drivers/media/platform/mxc/capture/mxc_vadc.c | |||
@@ -306,14 +306,6 @@ static void vdec_init(struct vadc_data *vadc) | |||
306 | reg32_write(VDEC_BASE + (0x3a*4), 0x80); | 306 | reg32_write(VDEC_BASE + (0x3a*4), 0x80); |
307 | reg32_write(VDEC_SHPIMP, 0x00); | 307 | reg32_write(VDEC_SHPIMP, 0x00); |
308 | 308 | ||
309 | /* enable div by 4 on out for 10 bit output | ||
310 | * enable vga progressive output. */ | ||
311 | reg32_write(VDEC_BASE + (0xf3*4), 0x0c); | ||
312 | |||
313 | /* set for 11 bit intput | ||
314 | * also enable dc offset integrator to go on every clock. */ | ||
315 | reg32_write(VDEC_BASE + (0xf4*4), 0x10); | ||
316 | |||
317 | /* setup the vsync block */ | 309 | /* setup the vsync block */ |
318 | reg32_write(VDEC_VSCON1, 0x87); | 310 | reg32_write(VDEC_VSCON1, 0x87); |
319 | 311 | ||
@@ -324,9 +316,6 @@ static void vdec_init(struct vadc_data *vadc) | |||
324 | /* set length for min hphase filter (or saturate limit if saturate is chosen) */ | 316 | /* set length for min hphase filter (or saturate limit if saturate is chosen) */ |
325 | reg32_write(VDEC_BASE + (0x45*4), 0x40); | 317 | reg32_write(VDEC_BASE + (0x45*4), 0x40); |
326 | 318 | ||
327 | /* choose the internal 66Mhz clock */ | ||
328 | reg32_write(VDEC_BASE + (0xf8*4), 0x01); | ||
329 | |||
330 | /* enable the internal resampler, | 319 | /* enable the internal resampler, |
331 | * select min filter not saturate for hphase noise filter for vcr detect. | 320 | * select min filter not saturate for hphase noise filter for vcr detect. |
332 | * enable vcr pause mode different field lengths */ | 321 | * enable vcr pause mode different field lengths */ |