diff options
Diffstat (limited to 'include/linux')
| -rw-r--r-- | include/linux/fec.h | 3 | ||||
| -rw-r--r-- | include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 3 |
2 files changed, 5 insertions, 1 deletions
diff --git a/include/linux/fec.h b/include/linux/fec.h index bcff455d1d53..ef3c72ca6a66 100644 --- a/include/linux/fec.h +++ b/include/linux/fec.h | |||
| @@ -3,7 +3,7 @@ | |||
| 3 | * Copyright (c) 2009 Orex Computed Radiography | 3 | * Copyright (c) 2009 Orex Computed Radiography |
| 4 | * Baruch Siach <baruch@tkos.co.il> | 4 | * Baruch Siach <baruch@tkos.co.il> |
| 5 | * | 5 | * |
| 6 | * Copyright (C) 2010 Freescale Semiconductor, Inc. | 6 | * Copyright (C) 2010-2014 Freescale Semiconductor, Inc. |
| 7 | * | 7 | * |
| 8 | * Header file for the FEC platform data | 8 | * Header file for the FEC platform data |
| 9 | * | 9 | * |
| @@ -19,6 +19,7 @@ | |||
| 19 | struct fec_platform_data { | 19 | struct fec_platform_data { |
| 20 | phy_interface_t phy; | 20 | phy_interface_t phy; |
| 21 | unsigned char mac[ETH_ALEN]; | 21 | unsigned char mac[ETH_ALEN]; |
| 22 | void (*sleep_mode_enable)(int enabled); | ||
| 22 | }; | 23 | }; |
| 23 | 24 | ||
| 24 | #endif | 25 | #endif |
diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h index c570e71471c4..dc7f6633768b 100644 --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | |||
| @@ -399,6 +399,9 @@ | |||
| 399 | #define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17) | 399 | #define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK (0x3 << 17) |
| 400 | #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13) | 400 | #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT (0x3 << 13) |
| 401 | 401 | ||
| 402 | #define IMX6SX_GPR4_FEC_ENET1_STOP_REQ (0x1 << 3) | ||
| 403 | #define IMX6SX_GPR4_FEC_ENET2_STOP_REQ (0x1 << 4) | ||
| 404 | |||
| 402 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3) | 405 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_MASK (0x1 << 3) |
| 403 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3) | 406 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF1 (0x0 << 3) |
| 404 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3) | 407 | #define IMX6SX_GPR5_DISP_MUX_LDB_CTRL_LCDIF2 (0x1 << 3) |
