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-rw-r--r--include/asm-blackfin/mach-bf537/anomaly.h249
-rw-r--r--include/asm-blackfin/mach-bf537/bf537.h158
-rw-r--r--include/asm-blackfin/mach-bf537/blackfin.h280
-rw-r--r--include/asm-blackfin/mach-bf537/cdefBF534.h4
-rw-r--r--include/asm-blackfin/mach-bf537/defBF534.h4
-rw-r--r--include/asm-blackfin/mach-bf537/irq.h2
-rw-r--r--include/asm-blackfin/mach-bf537/mem_map.h60
-rw-r--r--include/asm-blackfin/mach-bf537/portmux.h2
8 files changed, 173 insertions, 586 deletions
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
index 4453e614c3b1..2b66ecf489f7 100644
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -1,139 +1,144 @@
1
2/* 1/*
3 * File: include/asm-blackfin/mach-bf537/anomaly.h 2 * File: include/asm-blackfin/mach-bf537/anomaly.h
4 * Based on: 3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
5 * Author:
6 *
7 * Created:
8 * Description:
9 *
10 * Rev:
11 *
12 * Modified:
13 *
14 *
15 * Bugs: Enter bugs at http://blackfin.uclinux.org/
16 *
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2, or (at your option)
20 * any later version.
21 * 4 *
22 * This program is distributed in the hope that it will be useful, 5 * Copyright (C) 2004-2007 Analog Devices Inc.
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 6 * Licensed under the GPL-2 or later.
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; see the file COPYING.
29 * If not, write to the Free Software Foundation,
30 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 */ 7 */
32 8
33/* This file shoule be up to date with: 9/* This file shoule be up to date with:
34 * - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List 10 * - Revision M, March 13, 2007; ADSP-BF537 Blackfin Processor Anomaly List
35 * - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List 11 * - Revision L, March 13, 2007; ADSP-BF536 Blackfin Processor Anomaly List
36 * - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List 12 * - Revision M, March 13, 2007; ADSP-BF534 Blackfin Processor Anomaly List
37 */ 13 */
38 14
39#ifndef _MACH_ANOMALY_H_ 15#ifndef _MACH_ANOMALY_H_
40#define _MACH_ANOMALY_H_ 16#define _MACH_ANOMALY_H_
41 17
42/* We do not support 0.1 silicon - sorry */ 18/* We do not support 0.1 silicon - sorry */
43#if (defined(CONFIG_BF_REV_0_1)) 19#if __SILICON_REVISION__ < 2
44#error Kernel will not work on BF537/6/4 Version 0.1 20# error Kernel will not work on BF537 silicon version 0.0 or 0.1
45#endif 21#endif
46 22
47#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2)) 23#if defined(__ADSPBF534__)
48#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in 24# define ANOMALY_BF534 1
49 slot1 and store of a P register in slot 2 is not 25#else
50 supported */ 26# define ANOMALY_BF534 0
51#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
52 Channel DMA stops */
53#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
54 registers. */
55#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
56 upper bits*/
57#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
58 syncs */
59#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
60#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
61 Changed */
62#endif
63#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
64 SPORT external receive and transmit clocks. */
65#define ANOMALY_05000272 /* Certain data cache write through modes fail for
66 VDDint <=0.9V */
67#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
68#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
69 an edge is detected may clear interrupt */
70#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
71 not restored */
72#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
73 control */
74#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
75 killed in a particular stage*/
76#define ANOMALY_05000310 /* False hardware errors caused by fetches at the
77 * boundary of reserved memory */
78#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
79 registers are interrupted */
80#define ANOMALY_05000313 /* PPI is level sensitive on first transfer */
81#define ANOMALY_05000322 /* EMAC RMII mode at 10-Base-T speed: RX frames not
82 * received properly */
83#endif 27#endif
84 28#if defined(__ADSPBF536__)
85#if defined(CONFIG_BF_REV_0_2) 29# define ANOMALY_BF536 1
86#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or 30#else
87 IDLE around a Change of Control causes 31# define ANOMALY_BF536 0
88 unpredictable results */
89#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
90 (TDM) */
91#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
92#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
93#endif 32#endif
94#define ANOMALY_05000253 /* Maximum external clock speed for Timers */ 33#if defined(__ADSPBF537__)
95#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event 34# define ANOMALY_BF537 1
96 interrupt not functional */ 35#else
97#if (defined(CONFIG_BF537) || defined(CONFIG_BF536)) 36# define ANOMALY_BF537 0
98#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
99#endif 37#endif
100#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
101 loops may cause the instruction fetch unit to
102 malfunction */
103#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
104 the ICPLB Data registers differ */
105#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
106#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
107#define ANOMALY_05000262 /* Stores to data cache may be lost */
108#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
109#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
110 instruction will cause an infinite stall in the
111 second to last instruction in a hardware loop */
112#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
113 and non-zero DEB_TRAFFIC_PERIOD value */
114#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
115 internal voltage regulator (VDDint) to decrease */
116#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
117 an edge is detected may clear interrupt */
118#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
119 DMA system instability */
120#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
121 Atmel Dataflash devices */
122#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context
123 * is not restored */
124#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
125 * control */
126#define ANOMALY_05000283 /* System MMR Write Is Stalled Indefinitely When
127 * Killed in a Particular Stage */
128#define ANOMALY_05000285 /* New Feature: EMAC TX DMA Word Alignment
129 * (Not Available On Older Silicon) */
130#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
131#define ANOMALY_05000315 /* Killed System MMR Write Completes Erroneously
132 * On Next System MMR Access */
133#define ANOMALY_05000316 /* EMAC RMII mode: collisions occur in Full Duplex
134 * mode */
135#define ANOMALY_05000321 /* EMAC RMII mode: TX frames in half duplex fail with
136 * status No Carrier */
137#endif /* CONFIG_BF_REV_0_2 */
138 38
139#endif /* _MACH_ANOMALY_H_ */ 39/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
40#define ANOMALY_05000074 (1)
41/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
42#define ANOMALY_05000119 (1)
43/* Rx.H cannot be used to access 16-bit System MMR registers */
44#define ANOMALY_05000122 (1)
45/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
46#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
47/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
48#define ANOMALY_05000180 (1)
49/* Instruction Cache Is Not Functional */
50#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
51/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
52#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
53/* Spurious Hardware Error from an access in the shadow of a conditional branch */
54#define ANOMALY_05000245 (1)
55/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
56#define ANOMALY_05000247 (1)
57/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
58#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
59/* EMAC Tx DMA error after an early frame abort */
60#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
61/* Maximum external clock speed for Timers */
62#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
63/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
64#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
65/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
66#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
67/* EMAC MDIO input latched on wrong MDC edge */
68#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
69/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
70#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
71/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
72#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
73/* ICPLB_STATUS MMR register may be corrupted */
74#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
75/* DCPLB_FAULT_ADDR MMR register may be corrupted */
76#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
77/* Stores to data cache may be lost */
78#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
79/* Hardware loop corrupted when taking an ICPLB exception */
80#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
81/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
82#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
83/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
84#define ANOMALY_05000265 (1)
85/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
86#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
87/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
88#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
89/* Certain data cache write through modes fail for VDDint <=0.9V */
90#define ANOMALY_05000272 (1)
91/* Writes to Synchronous SDRAM memory may be lost */
92#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
93/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
94#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
95/* Disabling Peripherals with DMA running may cause DMA system instability */
96#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
97/* SPI Master boot mode does not work well with Atmel Data flash devices */
98#define ANOMALY_05000280 (1)
99/* False Hardware Error Exception when ISR context is not restored */
100#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
101/* Memory DMA corruption with 32-bit data and traffic control */
102#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
103/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
104#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
105/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
106#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
107/* SPORTs may receive bad data if FIFOs fill up */
108#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
109/* Memory to memory DMA source/destination descriptors must be in same memory space */
110#define ANOMALY_05000301 (1)
111/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
112#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
113/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
114#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
115/* SCKELOW Bit Does Not Maintain State Through Hibernate */
116#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
117/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
118#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
119/* False hardware errors caused by fetches at the boundary of reserved memory */
120#define ANOMALY_05000310 (1)
121/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
122#define ANOMALY_05000312 (1)
123/* PPI is level sensitive on first transfer */
124#define ANOMALY_05000313 (1)
125/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
126#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
127/* EMAC RMII mode: collisions occur in Full Duplex mode */
128#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
129/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
130#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
131/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
132#define ANOMALY_05000322 (1)
133
134/* Anomalies that don't exist on this proc */
135#define ANOMALY_05000125 (0)
136#define ANOMALY_05000158 (0)
137#define ANOMALY_05000183 (0)
138#define ANOMALY_05000198 (0)
139#define ANOMALY_05000230 (0)
140#define ANOMALY_05000266 (0)
141#define ANOMALY_05000311 (0)
142#define ANOMALY_05000323 (0)
143
144#endif
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
index b8924cd7730c..cfe2a221112e 100644
--- a/include/asm-blackfin/mach-bf537/bf537.h
+++ b/include/asm-blackfin/mach-bf537/bf537.h
@@ -62,12 +62,12 @@
62/***************************/ 62/***************************/
63 63
64 64
65#define BLKFIN_DSUBBANKS 4 65#define BFIN_DSUBBANKS 4
66#define BLKFIN_DWAYS 2 66#define BFIN_DWAYS 2
67#define BLKFIN_DLINES 64 67#define BFIN_DLINES 64
68#define BLKFIN_ISUBBANKS 4 68#define BFIN_ISUBBANKS 4
69#define BLKFIN_IWAYS 4 69#define BFIN_IWAYS 4
70#define BLKFIN_ILINES 32 70#define BFIN_ILINES 32
71 71
72#define WAY0_L 0x1 72#define WAY0_L 0x1
73#define WAY1_L 0x2 73#define WAY1_L 0x2
@@ -121,97 +121,6 @@
121 121
122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO) 122#define AMGCTLVAL (V_AMBEN | V_AMCKEN | V_CDPRIO)
123 123
124#define MAX_VC 650000000
125#define MIN_VC 50000000
126
127/********************************PLL Settings **************************************/
128#ifdef CONFIG_BFIN_KERNEL_CLOCK
129#if (CONFIG_VCO_MULT < 0)
130#error "VCO Multiplier is less than 0. Please select a different value"
131#endif
132
133#if (CONFIG_VCO_MULT == 0)
134#error "VCO Multiplier should be greater than 0. Please select a different value"
135#endif
136
137#if (CONFIG_VCO_MULT > 64)
138#error "VCO Multiplier is more than 64. Please select a different value"
139#endif
140
141#ifndef CONFIG_CLKIN_HALF
142#define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
143#else
144#define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
145#endif
146
147#ifndef CONFIG_PLL_BYPASS
148#define CONFIG_CCLK_HZ (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
149#define CONFIG_SCLK_HZ (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
150#else
151#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
152#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
153#endif
154
155#if (CONFIG_SCLK_DIV < 1)
156#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
157#endif
158
159#if (CONFIG_SCLK_DIV > 15)
160#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
161#endif
162
163#if (CONFIG_CCLK_DIV != 1)
164#if (CONFIG_CCLK_DIV != 2)
165#if (CONFIG_CCLK_DIV != 4)
166#if (CONFIG_CCLK_DIV != 8)
167#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
168#endif
169#endif
170#endif
171#endif
172
173#if (CONFIG_VCO_HZ > MAX_VC)
174#error "VCO selected is more than maximum value. Please change the VCO multipler"
175#endif
176
177#if (CONFIG_SCLK_HZ > 133000000)
178#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
179#endif
180
181#if (CONFIG_SCLK_HZ < 27000000)
182#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
183#endif
184
185#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
186#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
187#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
188#error "Please select sclk less than cclk"
189#endif
190#endif
191#endif
192
193#if (CONFIG_CCLK_DIV == 1)
194#define CONFIG_CCLK_ACT_DIV CCLK_DIV1
195#endif
196#if (CONFIG_CCLK_DIV == 2)
197#define CONFIG_CCLK_ACT_DIV CCLK_DIV2
198#endif
199#if (CONFIG_CCLK_DIV == 4)
200#define CONFIG_CCLK_ACT_DIV CCLK_DIV4
201#endif
202#if (CONFIG_CCLK_DIV == 8)
203#define CONFIG_CCLK_ACT_DIV CCLK_DIV8
204#endif
205#ifndef CONFIG_CCLK_ACT_DIV
206#define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
207#endif
208
209#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
210#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
211#endif
212
213#endif /* CONFIG_BFIN_KERNEL_CLOCK */
214
215#ifdef CONFIG_BF537 124#ifdef CONFIG_BF537
216#define CPU "BF537" 125#define CPU "BF537"
217#define CPUID 0x027c8000 126#define CPUID 0x027c8000
@@ -229,59 +138,4 @@
229#define CPUID 0x0 138#define CPUID 0x0
230#endif 139#endif
231 140
232#if (CONFIG_MEM_SIZE % 4)
233#error "SDRAM mem size must be multible of 4MB"
234#endif
235
236#define SDRAM_IGENERIC (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
237#define SDRAM_IKERNEL (SDRAM_IGENERIC | CPLB_LOCK)
238#define L1_IMEMORY ( CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
239#define SDRAM_INON_CHBL ( CPLB_USER_RD | CPLB_VALID)
240
241/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
242
243#define ANOMALY_05000158_WORKAROUND 0x200
244#ifdef CONFIG_BLKFIN_WB /*Write Back Policy */
245#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_DIRTY \
246 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
247#else /*Write Through */
248#define SDRAM_DGENERIC (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
249 | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
250#endif
251
252
253#define L1_DMEMORY (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
254#define SDRAM_DNON_CHBL (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
255#define SDRAM_EBIU (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
256#define SDRAM_OOPS (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
257
258#define SIZE_1K 0x00000400 /* 1K */
259#define SIZE_4K 0x00001000 /* 4K */
260#define SIZE_1M 0x00100000 /* 1M */
261#define SIZE_4M 0x00400000 /* 4M */
262
263#define MAX_CPLBS (16 * 2)
264
265/*
266* Number of required data CPLB switchtable entries
267* MEMSIZE / 4 (we mostly install 4M page size CPLBs
268* approx 16 for smaller 1MB page size CPLBs for allignment purposes
269* 1 for L1 Data Memory
270* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
271* 1 for ASYNC Memory
272*/
273
274
275#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
276
277/*
278* Number of required instruction CPLB switchtable entries
279* MEMSIZE / 4 (we mostly install 4M page size CPLBs
280* approx 12 for smaller 1MB page size CPLBs for allignment purposes
281* 1 for L1 Instruction Memory
282* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
283*/
284
285#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
286
287#endif /* __MACH_BF537_H__ */ 141#endif /* __MACH_BF537_H__ */
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
index bbd97051ec9c..53fcfa3408d0 100644
--- a/include/asm-blackfin/mach-bf537/blackfin.h
+++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -43,7 +43,7 @@
43#include "defBF537.h" 43#include "defBF537.h"
44#endif 44#endif
45 45
46#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY)) 46#if !defined(__ASSEMBLY__)
47#include "cdefBF534.h" 47#include "cdefBF534.h"
48 48
49/* UART 0*/ 49/* UART 0*/
@@ -143,284 +143,6 @@
143#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val) 143#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
144#define STOPCK_OFF STOPCK 144#define STOPCK_OFF STOPCK
145 145
146/* FIO USE PORT F*/
147#ifdef CONFIG_BF537_PORT_F
148#define bfin_read_PORT_FER() bfin_read_PORTF_FER()
149#define bfin_write_PORT_FER(val) bfin_write_PORTF_FER(val)
150#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
151#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
152#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
153#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
154#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
155#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
156#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
157#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
158#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
159#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
160#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
161#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
162#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
163#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
164#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
165#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
166#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
167#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
168#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
169#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
170#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
171#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
172#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
173#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
174#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
175#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
176#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
177#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
178#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
179#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
180#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
181#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
182#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
183#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
184
185#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
186#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
187#define FIO_FLAG_D PORTFIO
188#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
189#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
190#define FIO_FLAG_C PORTFIO_CLEAR
191#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
192#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
193#define FIO_FLAG_S PORTFIO_SET
194#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
195#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
196#define FIO_FLAG_T PORTFIO_TOGGLE
197#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
198#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
199#define FIO_MASKA_D PORTFIO_MASKA
200#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
201#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
202#define FIO_MASKA_C PORTFIO_MASKA_CLEAR
203#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
204#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
205#define FIO_MASKA_S PORTFIO_MASKA_SET
206#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
207#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
208#define FIO_MASKA_T PORTFIO_MASKA_TOGGLE
209#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
210#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
211#define FIO_MASKB_D PORTFIO_MASKB
212#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
213#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
214#define FIO_MASKB_C PORTFIO_MASKB_CLEAR
215#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
216#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
217#define FIO_MASKB_S PORTFIO_MASKB_SET
218#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
219#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
220#define FIO_MASKB_T PORTFIO_MASKB_TOGGLE
221#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
222#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
223#define FIO_DIR PORTFIO_DIR
224#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
225#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
226#define FIO_POLAR PORTFIO_POLAR
227#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
228#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
229#define FIO_EDGE PORTFIO_EDGE
230#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
231#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
232#define FIO_BOTH PORTFIO_BOTH
233#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
234#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
235#define FIO_INEN PORTFIO_INEN
236#endif
237
238/* FIO USE PORT G*/
239#ifdef CONFIG_BF537_PORT_G
240#define bfin_read_PORT_FER() bfin_read_PORTG_FER()
241#define bfin_write_PORT_FER(val) bfin_write_PORTG_FER(val)
242#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
243#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
244#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
245#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
246#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
247#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
248#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
249#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
250#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
251#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
252#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
253#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
254#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
255#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
256#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
257#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
258#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
259#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
260#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
261#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
262#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
263#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
264#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
265#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
266#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
267#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
268#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
269#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
270#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
271#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
272#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
273#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
274#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
275#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
276
277#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
278#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
279#define FIO_FLAG_D PORTGIO
280#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
281#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
282#define FIO_FLAG_C PORTGIO_CLEAR
283#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
284#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
285#define FIO_FLAG_S PORTGIO_SET
286#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
287#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
288#define FIO_FLAG_T PORTGIO_TOGGLE
289#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
290#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
291#define FIO_MASKA_D PORTGIO_MASKA
292#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
293#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
294#define FIO_MASKA_C PORTGIO_MASKA_CLEAR
295#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
296#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
297#define FIO_MASKA_S PORTGIO_MASKA_SET
298#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
299#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
300#define FIO_MASKA_T PORTGIO_MASKA_TOGGLE
301#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
302#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
303#define FIO_MASKB_D PORTGIO_MASKB
304#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
305#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
306#define FIO_MASKB_C PORTGIO_MASKB_CLEAR
307#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
308#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
309#define FIO_MASKB_S PORTGIO_MASKB_SET
310#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
311#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
312#define FIO_MASKB_T PORTGIO_MASKB_TOGGLE
313#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
314#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
315#define FIO_DIR PORTGIO_DIR
316#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
317#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
318#define FIO_POLAR PORTGIO_POLAR
319#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
320#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
321#define FIO_EDGE PORTGIO_EDGE
322#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
323#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
324#define FIO_BOTH PORTGIO_BOTH
325#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
326#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
327#define FIO_INEN PORTGIO_INEN
328
329#endif
330
331/* FIO USE PORT H*/
332#ifdef CONFIG_BF537_PORT_H
333#define bfin_read_PORT_FER() bfin_read_PORTH_FER()
334#define bfin_write_PORT_FER(val) bfin_write_PORTH_FER(val)
335#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
336#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
337#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
338#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
339#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
340#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
341#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
342#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
343#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
344#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
345#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
346#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
347#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
348#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
349#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
350#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
351#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
352#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
353#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
354#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
355#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
356#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
357#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
358#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
359#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
360#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
361#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
362#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
363#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
364#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
365#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
366#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
367#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
368#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
369
370#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
371#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
372#define FIO_FLAG_D PORTHIO
373#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
374#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
375#define FIO_FLAG_C PORTHIO_CLEAR
376#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
377#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
378#define FIO_FLAG_S PORTHIO_SET
379#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
380#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
381#define FIO_FLAG_T PORTHIO_TOGGLE
382#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
383#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
384#define FIO_MASKA_D PORTHIO_MASKA
385#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
386#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
387#define FIO_MASKA_C PORTHIO_MASKA_CLEAR
388#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
389#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
390#define FIO_MASKA_S PORTHIO_MASKA_SET
391#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
392#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
393#define FIO_MASKA_T PORTHIO_MASKA_TOGGLE
394#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
395#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
396#define FIO_MASKB_D PORTHIO_MASKB
397#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
398#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
399#define FIO_MASKB_C PORTHIO_MASKB_CLEAR
400#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
401#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
402#define FIO_MASKB_S PORTHIO_MASKB_SET
403#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
404#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
405#define FIO_MASKB_T PORTHIO_MASKB_TOGGLE
406#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
407#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
408#define FIO_DIR PORTHIO_DIR
409#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
410#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
411#define FIO_POLAR PORTHIO_POLAR
412#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
413#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
414#define FIO_EDGE PORTHIO_EDGE
415#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
416#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
417#define FIO_BOTH PORTHIO_BOTH
418#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
419#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
420#define FIO_INEN PORTHIO_INEN
421
422#endif
423
424/* PLL_DIV Masks */ 146/* PLL_DIV Masks */
425#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */ 147#define CCLK_DIV1 CSEL_DIV1 /* CCLK = VCO / 1 */
426#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */ 148#define CCLK_DIV2 CSEL_DIV2 /* CCLK = VCO / 2 */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
index 84e58fa73dce..78227bc855df 100644
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -32,6 +32,8 @@
32#ifndef _CDEF_BF534_H 32#ifndef _CDEF_BF534_H
33#define _CDEF_BF534_H 33#define _CDEF_BF534_H
34 34
35#include <asm/blackfin.h>
36
35/* Include all Core registers and bit definitions */ 37/* Include all Core registers and bit definitions */
36#include "defBF534.h" 38#include "defBF534.h"
37 39
@@ -57,7 +59,7 @@ static __inline__ void bfin_write_VR_CTL(unsigned int val)
57 bfin_write32(SIC_IWR, IWR_ENABLE(0)); 59 bfin_write32(SIC_IWR, IWR_ENABLE(0));
58 60
59 bfin_write16(VR_CTL, val); 61 bfin_write16(VR_CTL, val);
60 __builtin_bfin_ssync(); 62 SSYNC();
61 63
62 local_irq_save(flags); 64 local_irq_save(flags);
63 asm("IDLE;"); 65 asm("IDLE;");
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
index 1859f2fee5a7..d0d80d3152ba 100644
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -86,6 +86,7 @@
86#define UART0_GCTL 0xFFC00424 /* Global Control Register */ 86#define UART0_GCTL 0xFFC00424 /* Global Control Register */
87 87
88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */ 88/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
89#define SPI0_REGBASE 0xFFC00500
89#define SPI_CTL 0xFFC00500 /* SPI Control Register */ 90#define SPI_CTL 0xFFC00500 /* SPI Control Register */
90#define SPI_FLG 0xFFC00504 /* SPI Flag register */ 91#define SPI_FLG 0xFFC00504 /* SPI Flag register */
91#define SPI_STAT 0xFFC00508 /* SPI Status register */ 92#define SPI_STAT 0xFFC00508 /* SPI Status register */
@@ -456,6 +457,7 @@
456#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */ 457#define PPI_FRAME 0xFFC01010 /* PPI Frame Length Register */
457 458
458/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */ 459/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
460#define TWI0_REGBASE 0xFFC01400
459#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */ 461#define TWI_CLKDIV 0xFFC01400 /* Serial Clock Divider Register */
460#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */ 462#define TWI_CONTROL 0xFFC01404 /* TWI Control Register */
461#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */ 463#define TWI_SLAVE_CTL 0xFFC01408 /* Slave Mode Control Register */
@@ -1165,7 +1167,7 @@
1165#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */ 1167#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1166#define PSSE 0x0010 /* Slave-Select Input Enable */ 1168#define PSSE 0x0010 /* Slave-Select Input Enable */
1167#define EMISO 0x0020 /* Enable MISO As Output */ 1169#define EMISO 0x0020 /* Enable MISO As Output */
1168#define SPI_SIZE 0x0100 /* Size of Words (16/8* Bits) */ 1170#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1169#define LSBF 0x0200 /* LSB First */ 1171#define LSBF 0x0200 /* LSB First */
1170#define CPHA 0x0400 /* Clock Phase */ 1172#define CPHA 0x0400 /* Clock Phase */
1171#define CPOL 0x0800 /* Clock Polarity */ 1173#define CPOL 0x0800 /* Clock Polarity */
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
index 8af2a832ef6b..36c44bc1a917 100644
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -160,6 +160,8 @@ Core Emulation **
160#define IRQ_PH14 96 160#define IRQ_PH14 96
161#define IRQ_PH15 97 161#define IRQ_PH15 97
162 162
163#define GPIO_IRQ_BASE IRQ_PF0
164
163#ifdef CONFIG_IRQCHIP_DEMUX_GPIO 165#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
164#define NR_IRQS (IRQ_PH15+1) 166#define NR_IRQS (IRQ_PH15+1)
165#else 167#else
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
index 2a808c1202bf..18759e38eaae 100644
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -52,10 +52,10 @@
52 52
53/* Memory Map for ADSP-BF537 processors */ 53/* Memory Map for ADSP-BF537 processors */
54 54
55#ifdef CONFIG_BLKFIN_CACHE 55#ifdef CONFIG_BFIN_ICACHE
56#define BLKFIN_ICACHESIZE (16*1024) 56#define BFIN_ICACHESIZE (16*1024)
57#else 57#else
58#define BLKFIN_ICACHESIZE (0*1024) 58#define BFIN_ICACHESIZE (0*1024)
59#endif 59#endif
60 60
61 61
@@ -66,29 +66,29 @@
66 66
67#define L1_CODE_LENGTH 0xC000 67#define L1_CODE_LENGTH 0xC000
68 68
69#ifdef CONFIG_BLKFIN_DCACHE 69#ifdef CONFIG_BFIN_DCACHE
70 70
71#ifdef CONFIG_BLKFIN_DCACHE_BANKA 71#ifdef CONFIG_BFIN_DCACHE_BANKA
72#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 72#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
73#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 73#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
74#define L1_DATA_B_LENGTH 0x8000 74#define L1_DATA_B_LENGTH 0x8000
75#define BLKFIN_DCACHESIZE (16*1024) 75#define BFIN_DCACHESIZE (16*1024)
76#define BLKFIN_DSUPBANKS 1 76#define BFIN_DSUPBANKS 1
77#else 77#else
78#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 78#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
79#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 79#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
80#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 80#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
81#define BLKFIN_DCACHESIZE (32*1024) 81#define BFIN_DCACHESIZE (32*1024)
82#define BLKFIN_DSUPBANKS 2 82#define BFIN_DSUPBANKS 2
83#endif 83#endif
84 84
85#else 85#else
86#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 86#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
87#define L1_DATA_A_LENGTH 0x8000 87#define L1_DATA_A_LENGTH 0x8000
88#define L1_DATA_B_LENGTH 0x8000 88#define L1_DATA_B_LENGTH 0x8000
89#define BLKFIN_DCACHESIZE (0*1024) 89#define BFIN_DCACHESIZE (0*1024)
90#define BLKFIN_DSUPBANKS 0 90#define BFIN_DSUPBANKS 0
91#endif /*CONFIG_BLKFIN_DCACHE*/ 91#endif /*CONFIG_BFIN_DCACHE*/
92 92
93#endif /*CONFIG_BF537*/ 93#endif /*CONFIG_BF537*/
94 94
@@ -102,30 +102,30 @@
102#define L1_CODE_LENGTH 0xC000 102#define L1_CODE_LENGTH 0xC000
103 103
104 104
105#ifdef CONFIG_BLKFIN_DCACHE 105#ifdef CONFIG_BFIN_DCACHE
106 106
107#ifdef CONFIG_BLKFIN_DCACHE_BANKA 107#ifdef CONFIG_BFIN_DCACHE_BANKA
108#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 108#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
109#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 109#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
110#define L1_DATA_B_LENGTH 0x4000 110#define L1_DATA_B_LENGTH 0x4000
111#define BLKFIN_DCACHESIZE (16*1024) 111#define BFIN_DCACHESIZE (16*1024)
112#define BLKFIN_DSUPBANKS 1 112#define BFIN_DSUPBANKS 1
113 113
114#else 114#else
115#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 115#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
116#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 116#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
117#define L1_DATA_B_LENGTH (0x4000 - 0x4000) 117#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
118#define BLKFIN_DCACHESIZE (32*1024) 118#define BFIN_DCACHESIZE (32*1024)
119#define BLKFIN_DSUPBANKS 2 119#define BFIN_DSUPBANKS 2
120#endif 120#endif
121 121
122#else 122#else
123#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 123#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
124#define L1_DATA_A_LENGTH 0x4000 124#define L1_DATA_A_LENGTH 0x4000
125#define L1_DATA_B_LENGTH 0x4000 125#define L1_DATA_B_LENGTH 0x4000
126#define BLKFIN_DCACHESIZE (0*1024) 126#define BFIN_DCACHESIZE (0*1024)
127#define BLKFIN_DSUPBANKS 0 127#define BFIN_DSUPBANKS 0
128#endif /*CONFIG_BLKFIN_DCACHE*/ 128#endif /*CONFIG_BFIN_DCACHE*/
129 129
130#endif 130#endif
131 131
@@ -138,30 +138,30 @@
138 138
139#define L1_CODE_LENGTH 0xC000 139#define L1_CODE_LENGTH 0xC000
140 140
141#ifdef CONFIG_BLKFIN_DCACHE 141#ifdef CONFIG_BFIN_DCACHE
142 142
143#ifdef CONFIG_BLKFIN_DCACHE_BANKA 143#ifdef CONFIG_BFIN_DCACHE_BANKA
144#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 144#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
145#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 145#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
146#define L1_DATA_B_LENGTH 0x8000 146#define L1_DATA_B_LENGTH 0x8000
147#define BLKFIN_DCACHESIZE (16*1024) 147#define BFIN_DCACHESIZE (16*1024)
148#define BLKFIN_DSUPBANKS 1 148#define BFIN_DSUPBANKS 1
149 149
150#else 150#else
151#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 151#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
152#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 152#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
153#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 153#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
154#define BLKFIN_DCACHESIZE (32*1024) 154#define BFIN_DCACHESIZE (32*1024)
155#define BLKFIN_DSUPBANKS 2 155#define BFIN_DSUPBANKS 2
156#endif 156#endif
157 157
158#else 158#else
159#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 159#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
160#define L1_DATA_A_LENGTH 0x8000 160#define L1_DATA_A_LENGTH 0x8000
161#define L1_DATA_B_LENGTH 0x8000 161#define L1_DATA_B_LENGTH 0x8000
162#define BLKFIN_DCACHESIZE (0*1024) 162#define BFIN_DCACHESIZE (0*1024)
163#define BLKFIN_DSUPBANKS 0 163#define BFIN_DSUPBANKS 0
164#endif /*CONFIG_BLKFIN_DCACHE*/ 164#endif /*CONFIG_BFIN_DCACHE*/
165 165
166#endif 166#endif
167 167
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
index ae6c53b28452..5a3f7d3bf73d 100644
--- a/include/asm-blackfin/mach-bf537/portmux.h
+++ b/include/asm-blackfin/mach-bf537/portmux.h
@@ -99,7 +99,7 @@
99#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0)) 99#define P_SPORT0_DRPRI (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
100#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0)) 100#define P_SPORT0_TSCLK (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
101#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0)) 101#define P_SPORT0_TFS (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
102#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1)) 102#define P_SPORT0_DTPRI (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
103#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1)) 103#define P_CAN0_RX (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
104#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1)) 104#define P_CAN0_TX (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
105#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1)) 105#define P_SPI0_SSEL3 (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 11:15:08 -0500