aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-blackfin/mach-bf533/mem_map.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-blackfin/mach-bf533/mem_map.h')
-rw-r--r--include/asm-blackfin/mach-bf533/mem_map.h56
1 files changed, 28 insertions, 28 deletions
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
index e84baa3e939d..94d8c4062eb7 100644
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -51,10 +51,10 @@
51 51
52/* Level 1 Memory */ 52/* Level 1 Memory */
53 53
54#ifdef CONFIG_BLKFIN_CACHE 54#ifdef CONFIG_BFIN_ICACHE
55#define BLKFIN_ICACHESIZE (16*1024) 55#define BFIN_ICACHESIZE (16*1024)
56#else 56#else
57#define BLKFIN_ICACHESIZE (0*1024) 57#define BFIN_ICACHESIZE (0*1024)
58#endif 58#endif
59 59
60/* Memory Map for ADSP-BF533 processors */ 60/* Memory Map for ADSP-BF533 processors */
@@ -64,35 +64,35 @@
64#define L1_DATA_A_START 0xFF800000 64#define L1_DATA_A_START 0xFF800000
65#define L1_DATA_B_START 0xFF900000 65#define L1_DATA_B_START 0xFF900000
66 66
67#ifdef CONFIG_BLKFIN_CACHE 67#ifdef CONFIG_BFIN_ICACHE
68#define L1_CODE_LENGTH (0x14000 - 0x4000) 68#define L1_CODE_LENGTH (0x14000 - 0x4000)
69#else 69#else
70#define L1_CODE_LENGTH 0x14000 70#define L1_CODE_LENGTH 0x14000
71#endif 71#endif
72 72
73#ifdef CONFIG_BLKFIN_DCACHE 73#ifdef CONFIG_BFIN_DCACHE
74 74
75#ifdef CONFIG_BLKFIN_DCACHE_BANKA 75#ifdef CONFIG_BFIN_DCACHE_BANKA
76#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 76#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
77#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 77#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
78#define L1_DATA_B_LENGTH 0x8000 78#define L1_DATA_B_LENGTH 0x8000
79#define BLKFIN_DCACHESIZE (16*1024) 79#define BFIN_DCACHESIZE (16*1024)
80#define BLKFIN_DSUPBANKS 1 80#define BFIN_DSUPBANKS 1
81#else 81#else
82#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 82#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
83#define L1_DATA_A_LENGTH (0x8000 - 0x4000) 83#define L1_DATA_A_LENGTH (0x8000 - 0x4000)
84#define L1_DATA_B_LENGTH (0x8000 - 0x4000) 84#define L1_DATA_B_LENGTH (0x8000 - 0x4000)
85#define BLKFIN_DCACHESIZE (32*1024) 85#define BFIN_DCACHESIZE (32*1024)
86#define BLKFIN_DSUPBANKS 2 86#define BFIN_DSUPBANKS 2
87#endif 87#endif
88 88
89#else 89#else
90#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 90#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
91#define L1_DATA_A_LENGTH 0x8000 91#define L1_DATA_A_LENGTH 0x8000
92#define L1_DATA_B_LENGTH 0x8000 92#define L1_DATA_B_LENGTH 0x8000
93#define BLKFIN_DCACHESIZE (0*1024) 93#define BFIN_DCACHESIZE (0*1024)
94#define BLKFIN_DSUPBANKS 0 94#define BFIN_DSUPBANKS 0
95#endif /*CONFIG_BLKFIN_DCACHE*/ 95#endif /*CONFIG_BFIN_DCACHE*/
96#endif 96#endif
97 97
98/* Memory Map for ADSP-BF532 processors */ 98/* Memory Map for ADSP-BF532 processors */
@@ -102,36 +102,36 @@
102#define L1_DATA_A_START 0xFF804000 102#define L1_DATA_A_START 0xFF804000
103#define L1_DATA_B_START 0xFF904000 103#define L1_DATA_B_START 0xFF904000
104 104
105#ifdef CONFIG_BLKFIN_CACHE 105#ifdef CONFIG_BFIN_ICACHE
106#define L1_CODE_LENGTH (0xC000 - 0x4000) 106#define L1_CODE_LENGTH (0xC000 - 0x4000)
107#else 107#else
108#define L1_CODE_LENGTH 0xC000 108#define L1_CODE_LENGTH 0xC000
109#endif 109#endif
110 110
111#ifdef CONFIG_BLKFIN_DCACHE 111#ifdef CONFIG_BFIN_DCACHE
112 112
113#ifdef CONFIG_BLKFIN_DCACHE_BANKA 113#ifdef CONFIG_BFIN_DCACHE_BANKA
114#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 114#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
115#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 115#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
116#define L1_DATA_B_LENGTH 0x4000 116#define L1_DATA_B_LENGTH 0x4000
117#define BLKFIN_DCACHESIZE (16*1024) 117#define BFIN_DCACHESIZE (16*1024)
118#define BLKFIN_DSUPBANKS 1 118#define BFIN_DSUPBANKS 1
119 119
120#else 120#else
121#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0) 121#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
122#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 122#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
123#define L1_DATA_B_LENGTH (0x4000 - 0x4000) 123#define L1_DATA_B_LENGTH (0x4000 - 0x4000)
124#define BLKFIN_DCACHESIZE (32*1024) 124#define BFIN_DCACHESIZE (32*1024)
125#define BLKFIN_DSUPBANKS 2 125#define BFIN_DSUPBANKS 2
126#endif 126#endif
127 127
128#else 128#else
129#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 129#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
130#define L1_DATA_A_LENGTH 0x4000 130#define L1_DATA_A_LENGTH 0x4000
131#define L1_DATA_B_LENGTH 0x4000 131#define L1_DATA_B_LENGTH 0x4000
132#define BLKFIN_DCACHESIZE (0*1024) 132#define BFIN_DCACHESIZE (0*1024)
133#define BLKFIN_DSUPBANKS 0 133#define BFIN_DSUPBANKS 0
134#endif /*CONFIG_BLKFIN_DCACHE*/ 134#endif /*CONFIG_BFIN_DCACHE*/
135#endif 135#endif
136 136
137/* Memory Map for ADSP-BF531 processors */ 137/* Memory Map for ADSP-BF531 processors */
@@ -144,16 +144,16 @@
144#define L1_DATA_B_LENGTH 0x0000 144#define L1_DATA_B_LENGTH 0x0000
145 145
146 146
147#ifdef CONFIG_BLKFIN_DCACHE 147#ifdef CONFIG_BFIN_DCACHE
148#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0) 148#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
149#define L1_DATA_A_LENGTH (0x4000 - 0x4000) 149#define L1_DATA_A_LENGTH (0x4000 - 0x4000)
150#define BLKFIN_DCACHESIZE (16*1024) 150#define BFIN_DCACHESIZE (16*1024)
151#define BLKFIN_DSUPBANKS 1 151#define BFIN_DSUPBANKS 1
152#else 152#else
153#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0) 153#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
154#define L1_DATA_A_LENGTH 0x4000 154#define L1_DATA_A_LENGTH 0x4000
155#define BLKFIN_DCACHESIZE (0*1024) 155#define BFIN_DCACHESIZE (0*1024)
156#define BLKFIN_DSUPBANKS 0 156#define BFIN_DSUPBANKS 0
157#endif 157#endif
158 158
159#endif 159#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 12:59:56 -0500