diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/net/mv643xx_eth.h | 308 |
1 files changed, 307 insertions, 1 deletions
diff --git a/drivers/net/mv643xx_eth.h b/drivers/net/mv643xx_eth.h index be669eb23788..20acd2e52456 100644 --- a/drivers/net/mv643xx_eth.h +++ b/drivers/net/mv643xx_eth.h | |||
| @@ -7,7 +7,7 @@ | |||
| 7 | #include <linux/workqueue.h> | 7 | #include <linux/workqueue.h> |
| 8 | #include <linux/mii.h> | 8 | #include <linux/mii.h> |
| 9 | 9 | ||
| 10 | #include <linux/mv643xx.h> | 10 | #include <linux/mv643xx_eth.h> |
| 11 | 11 | ||
| 12 | #include <asm/dma-mapping.h> | 12 | #include <asm/dma-mapping.h> |
| 13 | 13 | ||
| @@ -51,6 +51,312 @@ | |||
| 51 | ETH_VLAN_HLEN + ETH_FCS_LEN) | 51 | ETH_VLAN_HLEN + ETH_FCS_LEN) |
| 52 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + dma_get_cache_alignment()) | 52 | #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + dma_get_cache_alignment()) |
| 53 | 53 | ||
| 54 | /****************************************/ | ||
| 55 | /* Ethernet Unit Registers */ | ||
| 56 | /****************************************/ | ||
| 57 | |||
| 58 | #define MV643XX_ETH_PHY_ADDR_REG 0x2000 | ||
| 59 | #define MV643XX_ETH_SMI_REG 0x2004 | ||
| 60 | #define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008 | ||
| 61 | #define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c | ||
| 62 | #define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080 | ||
| 63 | #define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084 | ||
| 64 | #define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc | ||
| 65 | #define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094 | ||
| 66 | #define MV643XX_ETH_BAR_0 0x2200 | ||
| 67 | #define MV643XX_ETH_BAR_1 0x2208 | ||
| 68 | #define MV643XX_ETH_BAR_2 0x2210 | ||
| 69 | #define MV643XX_ETH_BAR_3 0x2218 | ||
| 70 | #define MV643XX_ETH_BAR_4 0x2220 | ||
| 71 | #define MV643XX_ETH_BAR_5 0x2228 | ||
| 72 | #define MV643XX_ETH_SIZE_REG_0 0x2204 | ||
| 73 | #define MV643XX_ETH_SIZE_REG_1 0x220c | ||
| 74 | #define MV643XX_ETH_SIZE_REG_2 0x2214 | ||
| 75 | #define MV643XX_ETH_SIZE_REG_3 0x221c | ||
| 76 | #define MV643XX_ETH_SIZE_REG_4 0x2224 | ||
| 77 | #define MV643XX_ETH_SIZE_REG_5 0x222c | ||
| 78 | #define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230 | ||
| 79 | #define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234 | ||
| 80 | #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280 | ||
| 81 | #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284 | ||
| 82 | #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288 | ||
| 83 | #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c | ||
| 84 | #define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290 | ||
| 85 | #define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2)) | ||
| 86 | #define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7)) | ||
| 87 | #define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10)) | ||
| 88 | #define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10)) | ||
| 89 | #define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10)) | ||
| 90 | #define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10)) | ||
| 91 | #define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10)) | ||
| 92 | #define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10)) | ||
| 93 | #define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10)) | ||
| 94 | #define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10)) | ||
| 95 | #define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10)) | ||
| 96 | #define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10)) | ||
| 97 | #define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10)) | ||
| 98 | #define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10)) | ||
| 99 | #define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10)) | ||
| 100 | #define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10)) | ||
| 101 | #define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10)) | ||
| 102 | #define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10)) | ||
| 103 | #define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10)) | ||
| 104 | #define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10)) | ||
| 105 | #define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10)) | ||
| 106 | #define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10)) | ||
| 107 | #define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10)) | ||
| 108 | #define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10)) | ||
| 109 | #define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10)) | ||
| 110 | #define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10)) | ||
| 111 | #define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10)) | ||
| 112 | #define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10)) | ||
| 113 | #define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10)) | ||
| 114 | #define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10)) | ||
| 115 | #define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10)) | ||
| 116 | #define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10)) | ||
| 117 | #define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10)) | ||
| 118 | #define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10)) | ||
| 119 | #define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10)) | ||
| 120 | #define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10)) | ||
| 121 | #define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10)) | ||
| 122 | #define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10)) | ||
| 123 | #define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10)) | ||
| 124 | #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10)) | ||
| 125 | #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10)) | ||
| 126 | #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10)) | ||
| 127 | #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10)) | ||
| 128 | #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10)) | ||
| 129 | #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10)) | ||
| 130 | #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10)) | ||
| 131 | #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10)) | ||
| 132 | #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10)) | ||
| 133 | #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10)) | ||
| 134 | #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10)) | ||
| 135 | #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10)) | ||
| 136 | #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10)) | ||
| 137 | #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10)) | ||
| 138 | #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10)) | ||
| 139 | #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10)) | ||
| 140 | #define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10)) | ||
| 141 | #define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10)) | ||
| 142 | #define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10)) | ||
| 143 | #define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10)) | ||
| 144 | #define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10)) | ||
| 145 | #define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10)) | ||
| 146 | #define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10)) | ||
| 147 | #define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10)) | ||
| 148 | #define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10)) | ||
| 149 | #define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10)) | ||
| 150 | #define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10)) | ||
| 151 | #define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10)) | ||
| 152 | #define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10)) | ||
| 153 | #define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10)) | ||
| 154 | #define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10)) | ||
| 155 | #define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10)) | ||
| 156 | #define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10)) | ||
| 157 | #define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10)) | ||
| 158 | #define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10)) | ||
| 159 | #define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10)) | ||
| 160 | #define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10)) | ||
| 161 | #define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10)) | ||
| 162 | #define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10)) | ||
| 163 | #define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10)) | ||
| 164 | #define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10)) | ||
| 165 | #define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10)) | ||
| 166 | #define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10)) | ||
| 167 | #define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10)) | ||
| 168 | |||
| 169 | /* These macros describe Ethernet Port configuration reg (Px_cR) bits */ | ||
| 170 | #define MV643XX_ETH_UNICAST_NORMAL_MODE 0 | ||
| 171 | #define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0) | ||
| 172 | #define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0 | ||
| 173 | #define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1) | ||
| 174 | #define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2) | ||
| 175 | #define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1)) | ||
| 176 | #define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3) | ||
| 177 | #define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1)) | ||
| 178 | #define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2)) | ||
| 179 | #define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1)) | ||
| 180 | #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0 | ||
| 181 | #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4) | ||
| 182 | #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5) | ||
| 183 | #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4)) | ||
| 184 | #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6) | ||
| 185 | #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4)) | ||
| 186 | #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5)) | ||
| 187 | #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4)) | ||
| 188 | #define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0 | ||
| 189 | #define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7) | ||
| 190 | #define MV643XX_ETH_RECEIVE_BC_IF_IP 0 | ||
| 191 | #define MV643XX_ETH_REJECT_BC_IF_IP (1<<8) | ||
| 192 | #define MV643XX_ETH_RECEIVE_BC_IF_ARP 0 | ||
| 193 | #define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9) | ||
| 194 | #define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12) | ||
| 195 | #define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0 | ||
| 196 | #define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14) | ||
| 197 | #define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0 | ||
| 198 | #define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15) | ||
| 199 | #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0 | ||
| 200 | #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16) | ||
| 201 | #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17) | ||
| 202 | #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16)) | ||
| 203 | #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18) | ||
| 204 | #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16)) | ||
| 205 | #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17)) | ||
| 206 | #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16)) | ||
| 207 | #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0 | ||
| 208 | #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19) | ||
| 209 | #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20) | ||
| 210 | #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19)) | ||
| 211 | #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 (1<<21) | ||
| 212 | #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19)) | ||
| 213 | #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20)) | ||
| 214 | #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19)) | ||
| 215 | #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0 | ||
| 216 | #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22) | ||
| 217 | #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23) | ||
| 218 | #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22)) | ||
| 219 | #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24) | ||
| 220 | #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22)) | ||
| 221 | #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23)) | ||
| 222 | #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22)) | ||
| 223 | |||
| 224 | #define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \ | ||
| 225 | MV643XX_ETH_UNICAST_NORMAL_MODE | \ | ||
| 226 | MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \ | ||
| 227 | MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \ | ||
| 228 | MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \ | ||
| 229 | MV643XX_ETH_RECEIVE_BC_IF_IP | \ | ||
| 230 | MV643XX_ETH_RECEIVE_BC_IF_ARP | \ | ||
| 231 | MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \ | ||
| 232 | MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \ | ||
| 233 | MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \ | ||
| 234 | MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \ | ||
| 235 | MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 | ||
| 236 | |||
| 237 | /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/ | ||
| 238 | #define MV643XX_ETH_CLASSIFY_EN (1<<0) | ||
| 239 | #define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0 | ||
| 240 | #define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1) | ||
| 241 | #define MV643XX_ETH_PARTITION_DISABLE 0 | ||
| 242 | #define MV643XX_ETH_PARTITION_ENABLE (1<<2) | ||
| 243 | |||
| 244 | #define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \ | ||
| 245 | MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \ | ||
| 246 | MV643XX_ETH_PARTITION_DISABLE | ||
| 247 | |||
| 248 | /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */ | ||
| 249 | #define MV643XX_ETH_RIFB (1<<0) | ||
| 250 | #define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0 | ||
| 251 | #define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1) | ||
| 252 | #define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2) | ||
| 253 | #define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1)) | ||
| 254 | #define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3) | ||
| 255 | #define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4) | ||
| 256 | #define MV643XX_ETH_BLM_RX_BYTE_SWAP 0 | ||
| 257 | #define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5) | ||
| 258 | #define MV643XX_ETH_BLM_TX_BYTE_SWAP 0 | ||
| 259 | #define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6) | ||
| 260 | #define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0 | ||
| 261 | #define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0 | ||
| 262 | #define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22) | ||
| 263 | #define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23) | ||
| 264 | #define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22)) | ||
| 265 | #define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24) | ||
| 266 | |||
| 267 | #define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8) | ||
| 268 | |||
| 269 | #define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \ | ||
| 270 | MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \ | ||
| 271 | MV643XX_ETH_IPG_INT_RX(0) | \ | ||
| 272 | MV643XX_ETH_TX_BURST_SIZE_4_64BIT | ||
| 273 | |||
| 274 | /* These macros describe Ethernet Port serial control reg (PSCR) bits */ | ||
| 275 | #define MV643XX_ETH_SERIAL_PORT_DISABLE 0 | ||
| 276 | #define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0) | ||
| 277 | #define MV643XX_ETH_FORCE_LINK_PASS (1<<1) | ||
| 278 | #define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0 | ||
| 279 | #define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0 | ||
| 280 | #define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2) | ||
| 281 | #define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0 | ||
| 282 | #define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3) | ||
| 283 | #define MV643XX_ETH_ADV_NO_FLOW_CTRL 0 | ||
| 284 | #define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4) | ||
| 285 | #define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0 | ||
| 286 | #define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5) | ||
| 287 | #define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0 | ||
| 288 | #define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7) | ||
| 289 | #define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8) | ||
| 290 | #define MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED (1<<9) | ||
| 291 | #define MV643XX_ETH_FORCE_LINK_FAIL 0 | ||
| 292 | #define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10) | ||
| 293 | #define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0 | ||
| 294 | #define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11) | ||
| 295 | #define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13) | ||
| 296 | #define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0 | ||
| 297 | #define MV643XX_ETH_DTE_ADV_0 0 | ||
| 298 | #define MV643XX_ETH_DTE_ADV_1 (1<<14) | ||
| 299 | #define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0 | ||
| 300 | #define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15) | ||
| 301 | #define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0 | ||
| 302 | #define MV643XX_ETH_RESTART_AUTO_NEG (1<<16) | ||
| 303 | #define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0 | ||
| 304 | #define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17) | ||
| 305 | #define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18) | ||
| 306 | #define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17)) | ||
| 307 | #define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19) | ||
| 308 | #define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17)) | ||
| 309 | #define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20) | ||
| 310 | #define MV643XX_ETH_CLR_EXT_LOOPBACK 0 | ||
| 311 | #define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21) | ||
| 312 | #define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0 | ||
| 313 | #define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22) | ||
| 314 | #define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0 | ||
| 315 | #define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0 | ||
| 316 | #define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23) | ||
| 317 | #define MV643XX_ETH_SET_MII_SPEED_TO_10 0 | ||
| 318 | #define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24) | ||
| 319 | |||
| 320 | #define MV643XX_ETH_MAX_RX_PACKET_MASK (0x7<<17) | ||
| 321 | |||
| 322 | #define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \ | ||
| 323 | MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \ | ||
| 324 | MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \ | ||
| 325 | MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \ | ||
| 326 | MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \ | ||
| 327 | MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \ | ||
| 328 | MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \ | ||
| 329 | (1<<9) /* reserved */ | \ | ||
| 330 | MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \ | ||
| 331 | MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \ | ||
| 332 | MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \ | ||
| 333 | MV643XX_ETH_DTE_ADV_0 | \ | ||
| 334 | MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \ | ||
| 335 | MV643XX_ETH_AUTO_NEG_NO_CHANGE | \ | ||
| 336 | MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \ | ||
| 337 | MV643XX_ETH_CLR_EXT_LOOPBACK | \ | ||
| 338 | MV643XX_ETH_SET_FULL_DUPLEX_MODE | \ | ||
| 339 | MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX | ||
| 340 | |||
| 341 | /* These macros describe Ethernet Serial Status reg (PSR) bits */ | ||
| 342 | #define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0) | ||
| 343 | #define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1) | ||
| 344 | #define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2) | ||
| 345 | #define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3) | ||
| 346 | #define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4) | ||
| 347 | #define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5) | ||
| 348 | /* PSR bit 6 is undocumented */ | ||
| 349 | #define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7) | ||
| 350 | #define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8) | ||
| 351 | #define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9) | ||
| 352 | #define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10) | ||
| 353 | /* PSR bits 11-31 are reserved */ | ||
| 354 | |||
| 355 | #define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800 | ||
| 356 | #define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400 | ||
| 357 | |||
| 358 | #define MV643XX_ETH_DESC_SIZE 64 | ||
| 359 | |||
| 54 | #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ | 360 | #define ETH_RX_QUEUES_ENABLED (1 << 0) /* use only Q0 for receive */ |
| 55 | #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ | 361 | #define ETH_TX_QUEUES_ENABLED (1 << 0) /* use only Q0 for transmit */ |
| 56 | 362 | ||