diff options
Diffstat (limited to 'drivers/video/omap2/dss/dsi.c')
-rw-r--r-- | drivers/video/omap2/dss/dsi.c | 42 |
1 files changed, 29 insertions, 13 deletions
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c index df35aed828da..3ef94227bbe7 100644 --- a/drivers/video/omap2/dss/dsi.c +++ b/drivers/video/omap2/dss/dsi.c | |||
@@ -1022,10 +1022,14 @@ int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo) | |||
1022 | 1022 | ||
1023 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); | 1023 | DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4); |
1024 | 1024 | ||
1025 | DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n", | 1025 | DSSDBG("regm3 = %d, %s (%s) = %lu\n", cinfo->regm3, |
1026 | cinfo->regm3, cinfo->dsi1_pll_fclk); | 1026 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
1027 | DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n", | 1027 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), |
1028 | cinfo->regm4, cinfo->dsi2_pll_fclk); | 1028 | cinfo->dsi1_pll_fclk); |
1029 | DSSDBG("regm4 = %d, %s (%s) = %lu\n", cinfo->regm4, | ||
1030 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | ||
1031 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | ||
1032 | cinfo->dsi2_pll_fclk); | ||
1029 | 1033 | ||
1030 | REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ | 1034 | REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */ |
1031 | 1035 | ||
@@ -1169,6 +1173,10 @@ void dsi_dump_clocks(struct seq_file *s) | |||
1169 | { | 1173 | { |
1170 | int clksel; | 1174 | int clksel; |
1171 | struct dsi_clock_info *cinfo = &dsi.current_cinfo; | 1175 | struct dsi_clock_info *cinfo = &dsi.current_cinfo; |
1176 | enum dss_clk_source dispc_clk_src, dsi_clk_src; | ||
1177 | |||
1178 | dispc_clk_src = dss_get_dispc_clk_source(); | ||
1179 | dsi_clk_src = dss_get_dsi_clk_source(); | ||
1172 | 1180 | ||
1173 | enable_clocks(1); | 1181 | enable_clocks(1); |
1174 | 1182 | ||
@@ -1185,23 +1193,27 @@ void dsi_dump_clocks(struct seq_file *s) | |||
1185 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", | 1193 | seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n", |
1186 | cinfo->clkin4ddr, cinfo->regm); | 1194 | cinfo->clkin4ddr, cinfo->regm); |
1187 | 1195 | ||
1188 | seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n", | 1196 | seq_printf(s, "%s (%s)\t%-16luregm3 %u\t(%s)\n", |
1197 | dss_get_generic_clk_source_name(dispc_clk_src), | ||
1198 | dss_feat_get_clk_source_name(dispc_clk_src), | ||
1189 | cinfo->dsi1_pll_fclk, | 1199 | cinfo->dsi1_pll_fclk, |
1190 | cinfo->regm3, | 1200 | cinfo->regm3, |
1191 | dss_get_dispc_clk_source() == DSS_CLK_SRC_FCK ? | 1201 | dispc_clk_src == DSS_CLK_SRC_FCK ? |
1192 | "off" : "on"); | 1202 | "off" : "on"); |
1193 | 1203 | ||
1194 | seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n", | 1204 | seq_printf(s, "%s (%s)\t%-16luregm4 %u\t(%s)\n", |
1205 | dss_get_generic_clk_source_name(dsi_clk_src), | ||
1206 | dss_feat_get_clk_source_name(dsi_clk_src), | ||
1195 | cinfo->dsi2_pll_fclk, | 1207 | cinfo->dsi2_pll_fclk, |
1196 | cinfo->regm4, | 1208 | cinfo->regm4, |
1197 | dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ? | 1209 | dsi_clk_src == DSS_CLK_SRC_FCK ? |
1198 | "off" : "on"); | 1210 | "off" : "on"); |
1199 | 1211 | ||
1200 | seq_printf(s, "- DSI -\n"); | 1212 | seq_printf(s, "- DSI -\n"); |
1201 | 1213 | ||
1202 | seq_printf(s, "dsi fclk source = %s\n", | 1214 | seq_printf(s, "dsi fclk source = %s (%s)\n", |
1203 | dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK ? | 1215 | dss_get_generic_clk_source_name(dsi_clk_src), |
1204 | "dss1_alwon_fclk" : "dsi2_pll_fclk"); | 1216 | dss_feat_get_clk_source_name(dsi_clk_src)); |
1205 | 1217 | ||
1206 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); | 1218 | seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate()); |
1207 | 1219 | ||
@@ -3235,13 +3247,17 @@ int dsi_init_display(struct omap_dss_device *dssdev) | |||
3235 | void dsi_wait_dsi1_pll_active(void) | 3247 | void dsi_wait_dsi1_pll_active(void) |
3236 | { | 3248 | { |
3237 | if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) | 3249 | if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1) |
3238 | DSSERR("DSI1 PLL clock not active\n"); | 3250 | DSSERR("%s (%s) not active\n", |
3251 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC), | ||
3252 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)); | ||
3239 | } | 3253 | } |
3240 | 3254 | ||
3241 | void dsi_wait_dsi2_pll_active(void) | 3255 | void dsi_wait_dsi2_pll_active(void) |
3242 | { | 3256 | { |
3243 | if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) | 3257 | if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1) |
3244 | DSSERR("DSI2 PLL clock not active\n"); | 3258 | DSSERR("%s (%s) not active\n", |
3259 | dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI), | ||
3260 | dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)); | ||
3245 | } | 3261 | } |
3246 | 3262 | ||
3247 | static int dsi_init(struct platform_device *pdev) | 3263 | static int dsi_init(struct platform_device *pdev) |