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path: root/drivers/video/intelfb/intelfbhw.h
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Diffstat (limited to 'drivers/video/intelfb/intelfbhw.h')
-rw-r--r--drivers/video/intelfb/intelfbhw.h14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/video/intelfb/intelfbhw.h b/drivers/video/intelfb/intelfbhw.h
index cfcd53749484..1a4df251b540 100644
--- a/drivers/video/intelfb/intelfbhw.h
+++ b/drivers/video/intelfb/intelfbhw.h
@@ -83,7 +83,7 @@
83 */ 83 */
84#define RING_MIN_FREE 64 84#define RING_MIN_FREE 64
85 85
86#define IPEHR 0x2088 86#define IPEHR 0x2088
87 87
88#define INSTDONE 0x2090 88#define INSTDONE 0x2090
89#define PRI_RING_EMPTY 1 89#define PRI_RING_EMPTY 1
@@ -128,9 +128,9 @@
128 128
129#define GPIOA 0x5010 129#define GPIOA 0x5010
130#define GPIOB 0x5014 130#define GPIOB 0x5014
131#define GPIOC 0x5018 // this may be external DDC on i830 131#define GPIOC 0x5018 /* this may be external DDC on i830 */
132#define GPIOD 0x501C // this is DVO DDC 132#define GPIOD 0x501C /* this is DVO DDC */
133#define GPIOE 0x5020 // this is DVO i2C 133#define GPIOE 0x5020 /* this is DVO i2C */
134#define GPIOF 0x5024 134#define GPIOF 0x5024
135 135
136/* PLL registers */ 136/* PLL registers */
@@ -269,8 +269,8 @@
269#define PORT_ENABLE (1 << 31) 269#define PORT_ENABLE (1 << 31)
270#define PORT_PIPE_SELECT_SHIFT 30 270#define PORT_PIPE_SELECT_SHIFT 30
271#define PORT_TV_FLAGS_MASK 0xFF 271#define PORT_TV_FLAGS_MASK 0xFF
272#define PORT_TV_FLAGS 0xC4 // ripped from my BIOS 272#define PORT_TV_FLAGS 0xC4 /* ripped from my BIOS
273 // to understand and correct 273 to understand and correct */
274 274
275#define DVOA_SRCDIM 0x61124 275#define DVOA_SRCDIM 0x61124
276#define DVOB_SRCDIM 0x61144 276#define DVOB_SRCDIM 0x61144
@@ -369,7 +369,7 @@
369#define DISPPLANE_8BPP (0x2<<26) 369#define DISPPLANE_8BPP (0x2<<26)
370#define DISPPLANE_15_16BPP (0x4<<26) 370#define DISPPLANE_15_16BPP (0x4<<26)
371#define DISPPLANE_16BPP (0x5<<26) 371#define DISPPLANE_16BPP (0x5<<26)
372#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 372#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
373#define DISPPLANE_32BPP (0x7<<26) 373#define DISPPLANE_32BPP (0x7<<26)
374#define DISPPLANE_STEREO_ENABLE (1<<25) 374#define DISPPLANE_STEREO_ENABLE (1<<25)
375#define DISPPLANE_STEREO_DISABLE 0 375#define DISPPLANE_STEREO_DISABLE 0