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-rw-r--r--drivers/tty/serial/8250/8250.c3357
1 files changed, 3357 insertions, 0 deletions
diff --git a/drivers/tty/serial/8250/8250.c b/drivers/tty/serial/8250/8250.c
new file mode 100644
index 000000000000..9f50c4e3c2be
--- /dev/null
+++ b/drivers/tty/serial/8250/8250.c
@@ -0,0 +1,3357 @@
1/*
2 * Driver for 8250/16550-type serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Copyright (C) 2001 Russell King.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * A note about mapbase / membase
14 *
15 * mapbase is the physical address of the IO port.
16 * membase is an 'ioremapped' cookie.
17 */
18
19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/delay.h>
30#include <linux/platform_device.h>
31#include <linux/tty.h>
32#include <linux/ratelimit.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
38#include <linux/nmi.h>
39#include <linux/mutex.h>
40#include <linux/slab.h>
41
42#include <asm/io.h>
43#include <asm/irq.h>
44
45#include "8250.h"
46
47#ifdef CONFIG_SPARC
48#include "suncore.h"
49#endif
50
51/*
52 * Configuration:
53 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
54 * is unsafe when used on edge-triggered interrupts.
55 */
56static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57
58static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
59
60static struct uart_driver serial8250_reg;
61
62static int serial_index(struct uart_port *port)
63{
64 return (serial8250_reg.minor - 64) + port->line;
65}
66
67static unsigned int skip_txen_test; /* force skip of txen test at init time */
68
69/*
70 * Debugging.
71 */
72#if 0
73#define DEBUG_AUTOCONF(fmt...) printk(fmt)
74#else
75#define DEBUG_AUTOCONF(fmt...) do { } while (0)
76#endif
77
78#if 0
79#define DEBUG_INTR(fmt...) printk(fmt)
80#else
81#define DEBUG_INTR(fmt...) do { } while (0)
82#endif
83
84#define PASS_LIMIT 512
85
86#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
87
88
89/*
90 * We default to IRQ0 for the "no irq" hack. Some
91 * machine types want others as well - they're free
92 * to redefine this in their header file.
93 */
94#define is_real_interrupt(irq) ((irq) != 0)
95
96#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
97#define CONFIG_SERIAL_DETECT_IRQ 1
98#endif
99#ifdef CONFIG_SERIAL_8250_MANY_PORTS
100#define CONFIG_SERIAL_MANY_PORTS 1
101#endif
102
103/*
104 * HUB6 is always on. This will be removed once the header
105 * files have been cleaned.
106 */
107#define CONFIG_HUB6 1
108
109#include <asm/serial.h>
110/*
111 * SERIAL_PORT_DFNS tells us about built-in ports that have no
112 * standard enumeration mechanism. Platforms that can find all
113 * serial ports via mechanisms like ACPI or PCI need not supply it.
114 */
115#ifndef SERIAL_PORT_DFNS
116#define SERIAL_PORT_DFNS
117#endif
118
119static const struct old_serial_port old_serial_port[] = {
120 SERIAL_PORT_DFNS /* defined in asm/serial.h */
121};
122
123#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
124
125#ifdef CONFIG_SERIAL_8250_RSA
126
127#define PORT_RSA_MAX 4
128static unsigned long probe_rsa[PORT_RSA_MAX];
129static unsigned int probe_rsa_count;
130#endif /* CONFIG_SERIAL_8250_RSA */
131
132struct irq_info {
133 struct hlist_node node;
134 int irq;
135 spinlock_t lock; /* Protects list not the hash */
136 struct list_head *head;
137};
138
139#define NR_IRQ_HASH 32 /* Can be adjusted later */
140static struct hlist_head irq_lists[NR_IRQ_HASH];
141static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */
142
143/*
144 * Here we define the default xmit fifo size used for each type of UART.
145 */
146static const struct serial8250_config uart_config[] = {
147 [PORT_UNKNOWN] = {
148 .name = "unknown",
149 .fifo_size = 1,
150 .tx_loadsz = 1,
151 },
152 [PORT_8250] = {
153 .name = "8250",
154 .fifo_size = 1,
155 .tx_loadsz = 1,
156 },
157 [PORT_16450] = {
158 .name = "16450",
159 .fifo_size = 1,
160 .tx_loadsz = 1,
161 },
162 [PORT_16550] = {
163 .name = "16550",
164 .fifo_size = 1,
165 .tx_loadsz = 1,
166 },
167 [PORT_16550A] = {
168 .name = "16550A",
169 .fifo_size = 16,
170 .tx_loadsz = 16,
171 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
172 .flags = UART_CAP_FIFO,
173 },
174 [PORT_CIRRUS] = {
175 .name = "Cirrus",
176 .fifo_size = 1,
177 .tx_loadsz = 1,
178 },
179 [PORT_16650] = {
180 .name = "ST16650",
181 .fifo_size = 1,
182 .tx_loadsz = 1,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16650V2] = {
186 .name = "ST16650V2",
187 .fifo_size = 32,
188 .tx_loadsz = 16,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
190 UART_FCR_T_TRIG_00,
191 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
192 },
193 [PORT_16750] = {
194 .name = "TI16750",
195 .fifo_size = 64,
196 .tx_loadsz = 64,
197 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
198 UART_FCR7_64BYTE,
199 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
200 },
201 [PORT_STARTECH] = {
202 .name = "Startech",
203 .fifo_size = 1,
204 .tx_loadsz = 1,
205 },
206 [PORT_16C950] = {
207 .name = "16C950/954",
208 .fifo_size = 128,
209 .tx_loadsz = 128,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
211 /* UART_CAP_EFR breaks billionon CF bluetooth card. */
212 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
213 },
214 [PORT_16654] = {
215 .name = "ST16654",
216 .fifo_size = 64,
217 .tx_loadsz = 32,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
219 UART_FCR_T_TRIG_10,
220 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
221 },
222 [PORT_16850] = {
223 .name = "XR16850",
224 .fifo_size = 128,
225 .tx_loadsz = 128,
226 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
227 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
228 },
229 [PORT_RSA] = {
230 .name = "RSA",
231 .fifo_size = 2048,
232 .tx_loadsz = 2048,
233 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
234 .flags = UART_CAP_FIFO,
235 },
236 [PORT_NS16550A] = {
237 .name = "NS16550A",
238 .fifo_size = 16,
239 .tx_loadsz = 16,
240 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
241 .flags = UART_CAP_FIFO | UART_NATSEMI,
242 },
243 [PORT_XSCALE] = {
244 .name = "XScale",
245 .fifo_size = 32,
246 .tx_loadsz = 32,
247 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
248 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
249 },
250 [PORT_RM9000] = {
251 .name = "RM9000",
252 .fifo_size = 16,
253 .tx_loadsz = 16,
254 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
255 .flags = UART_CAP_FIFO,
256 },
257 [PORT_OCTEON] = {
258 .name = "OCTEON",
259 .fifo_size = 64,
260 .tx_loadsz = 64,
261 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
262 .flags = UART_CAP_FIFO,
263 },
264 [PORT_AR7] = {
265 .name = "AR7",
266 .fifo_size = 16,
267 .tx_loadsz = 16,
268 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
269 .flags = UART_CAP_FIFO | UART_CAP_AFE,
270 },
271 [PORT_U6_16550A] = {
272 .name = "U6_16550A",
273 .fifo_size = 64,
274 .tx_loadsz = 64,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_AFE,
277 },
278 [PORT_TEGRA] = {
279 .name = "Tegra",
280 .fifo_size = 32,
281 .tx_loadsz = 8,
282 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
283 UART_FCR_T_TRIG_01,
284 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
285 },
286 [PORT_XR17D15X] = {
287 .name = "XR17D15X",
288 .fifo_size = 64,
289 .tx_loadsz = 64,
290 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
291 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR,
292 },
293};
294
295#if defined(CONFIG_MIPS_ALCHEMY)
296
297/* Au1x00 UART hardware has a weird register layout */
298static const u8 au_io_in_map[] = {
299 [UART_RX] = 0,
300 [UART_IER] = 2,
301 [UART_IIR] = 3,
302 [UART_LCR] = 5,
303 [UART_MCR] = 6,
304 [UART_LSR] = 7,
305 [UART_MSR] = 8,
306};
307
308static const u8 au_io_out_map[] = {
309 [UART_TX] = 1,
310 [UART_IER] = 2,
311 [UART_FCR] = 4,
312 [UART_LCR] = 5,
313 [UART_MCR] = 6,
314};
315
316/* sane hardware needs no mapping */
317static inline int map_8250_in_reg(struct uart_port *p, int offset)
318{
319 if (p->iotype != UPIO_AU)
320 return offset;
321 return au_io_in_map[offset];
322}
323
324static inline int map_8250_out_reg(struct uart_port *p, int offset)
325{
326 if (p->iotype != UPIO_AU)
327 return offset;
328 return au_io_out_map[offset];
329}
330
331#elif defined(CONFIG_SERIAL_8250_RM9K)
332
333static const u8
334 regmap_in[8] = {
335 [UART_RX] = 0x00,
336 [UART_IER] = 0x0c,
337 [UART_IIR] = 0x14,
338 [UART_LCR] = 0x1c,
339 [UART_MCR] = 0x20,
340 [UART_LSR] = 0x24,
341 [UART_MSR] = 0x28,
342 [UART_SCR] = 0x2c
343 },
344 regmap_out[8] = {
345 [UART_TX] = 0x04,
346 [UART_IER] = 0x0c,
347 [UART_FCR] = 0x18,
348 [UART_LCR] = 0x1c,
349 [UART_MCR] = 0x20,
350 [UART_LSR] = 0x24,
351 [UART_MSR] = 0x28,
352 [UART_SCR] = 0x2c
353 };
354
355static inline int map_8250_in_reg(struct uart_port *p, int offset)
356{
357 if (p->iotype != UPIO_RM9000)
358 return offset;
359 return regmap_in[offset];
360}
361
362static inline int map_8250_out_reg(struct uart_port *p, int offset)
363{
364 if (p->iotype != UPIO_RM9000)
365 return offset;
366 return regmap_out[offset];
367}
368
369#else
370
371/* sane hardware needs no mapping */
372#define map_8250_in_reg(up, offset) (offset)
373#define map_8250_out_reg(up, offset) (offset)
374
375#endif
376
377static unsigned int hub6_serial_in(struct uart_port *p, int offset)
378{
379 offset = map_8250_in_reg(p, offset) << p->regshift;
380 outb(p->hub6 - 1 + offset, p->iobase);
381 return inb(p->iobase + 1);
382}
383
384static void hub6_serial_out(struct uart_port *p, int offset, int value)
385{
386 offset = map_8250_out_reg(p, offset) << p->regshift;
387 outb(p->hub6 - 1 + offset, p->iobase);
388 outb(value, p->iobase + 1);
389}
390
391static unsigned int mem_serial_in(struct uart_port *p, int offset)
392{
393 offset = map_8250_in_reg(p, offset) << p->regshift;
394 return readb(p->membase + offset);
395}
396
397static void mem_serial_out(struct uart_port *p, int offset, int value)
398{
399 offset = map_8250_out_reg(p, offset) << p->regshift;
400 writeb(value, p->membase + offset);
401}
402
403static void mem32_serial_out(struct uart_port *p, int offset, int value)
404{
405 offset = map_8250_out_reg(p, offset) << p->regshift;
406 writel(value, p->membase + offset);
407}
408
409static unsigned int mem32_serial_in(struct uart_port *p, int offset)
410{
411 offset = map_8250_in_reg(p, offset) << p->regshift;
412 return readl(p->membase + offset);
413}
414
415static unsigned int au_serial_in(struct uart_port *p, int offset)
416{
417 offset = map_8250_in_reg(p, offset) << p->regshift;
418 return __raw_readl(p->membase + offset);
419}
420
421static void au_serial_out(struct uart_port *p, int offset, int value)
422{
423 offset = map_8250_out_reg(p, offset) << p->regshift;
424 __raw_writel(value, p->membase + offset);
425}
426
427static unsigned int io_serial_in(struct uart_port *p, int offset)
428{
429 offset = map_8250_in_reg(p, offset) << p->regshift;
430 return inb(p->iobase + offset);
431}
432
433static void io_serial_out(struct uart_port *p, int offset, int value)
434{
435 offset = map_8250_out_reg(p, offset) << p->regshift;
436 outb(value, p->iobase + offset);
437}
438
439static int serial8250_default_handle_irq(struct uart_port *port);
440
441static void set_io_from_upio(struct uart_port *p)
442{
443 struct uart_8250_port *up =
444 container_of(p, struct uart_8250_port, port);
445 switch (p->iotype) {
446 case UPIO_HUB6:
447 p->serial_in = hub6_serial_in;
448 p->serial_out = hub6_serial_out;
449 break;
450
451 case UPIO_MEM:
452 p->serial_in = mem_serial_in;
453 p->serial_out = mem_serial_out;
454 break;
455
456 case UPIO_RM9000:
457 case UPIO_MEM32:
458 p->serial_in = mem32_serial_in;
459 p->serial_out = mem32_serial_out;
460 break;
461
462 case UPIO_AU:
463 p->serial_in = au_serial_in;
464 p->serial_out = au_serial_out;
465 break;
466
467 default:
468 p->serial_in = io_serial_in;
469 p->serial_out = io_serial_out;
470 break;
471 }
472 /* Remember loaded iotype */
473 up->cur_iotype = p->iotype;
474 p->handle_irq = serial8250_default_handle_irq;
475}
476
477static void
478serial_out_sync(struct uart_8250_port *up, int offset, int value)
479{
480 struct uart_port *p = &up->port;
481 switch (p->iotype) {
482 case UPIO_MEM:
483 case UPIO_MEM32:
484 case UPIO_AU:
485 p->serial_out(p, offset, value);
486 p->serial_in(p, UART_LCR); /* safe, no side-effects */
487 break;
488 default:
489 p->serial_out(p, offset, value);
490 }
491}
492
493#define serial_in(up, offset) \
494 (up->port.serial_in(&(up)->port, (offset)))
495#define serial_out(up, offset, value) \
496 (up->port.serial_out(&(up)->port, (offset), (value)))
497/*
498 * We used to support using pause I/O for certain machines. We
499 * haven't supported this for a while, but just in case it's badly
500 * needed for certain old 386 machines, I've left these #define's
501 * in....
502 */
503#define serial_inp(up, offset) serial_in(up, offset)
504#define serial_outp(up, offset, value) serial_out(up, offset, value)
505
506/* Uart divisor latch read */
507static inline int _serial_dl_read(struct uart_8250_port *up)
508{
509 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
510}
511
512/* Uart divisor latch write */
513static inline void _serial_dl_write(struct uart_8250_port *up, int value)
514{
515 serial_outp(up, UART_DLL, value & 0xff);
516 serial_outp(up, UART_DLM, value >> 8 & 0xff);
517}
518
519#if defined(CONFIG_MIPS_ALCHEMY)
520/* Au1x00 haven't got a standard divisor latch */
521static int serial_dl_read(struct uart_8250_port *up)
522{
523 if (up->port.iotype == UPIO_AU)
524 return __raw_readl(up->port.membase + 0x28);
525 else
526 return _serial_dl_read(up);
527}
528
529static void serial_dl_write(struct uart_8250_port *up, int value)
530{
531 if (up->port.iotype == UPIO_AU)
532 __raw_writel(value, up->port.membase + 0x28);
533 else
534 _serial_dl_write(up, value);
535}
536#elif defined(CONFIG_SERIAL_8250_RM9K)
537static int serial_dl_read(struct uart_8250_port *up)
538{
539 return (up->port.iotype == UPIO_RM9000) ?
540 (((__raw_readl(up->port.membase + 0x10) << 8) |
541 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
542 _serial_dl_read(up);
543}
544
545static void serial_dl_write(struct uart_8250_port *up, int value)
546{
547 if (up->port.iotype == UPIO_RM9000) {
548 __raw_writel(value, up->port.membase + 0x08);
549 __raw_writel(value >> 8, up->port.membase + 0x10);
550 } else {
551 _serial_dl_write(up, value);
552 }
553}
554#else
555#define serial_dl_read(up) _serial_dl_read(up)
556#define serial_dl_write(up, value) _serial_dl_write(up, value)
557#endif
558
559/*
560 * For the 16C950
561 */
562static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
563{
564 serial_out(up, UART_SCR, offset);
565 serial_out(up, UART_ICR, value);
566}
567
568static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
569{
570 unsigned int value;
571
572 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
573 serial_out(up, UART_SCR, offset);
574 value = serial_in(up, UART_ICR);
575 serial_icr_write(up, UART_ACR, up->acr);
576
577 return value;
578}
579
580/*
581 * FIFO support.
582 */
583static void serial8250_clear_fifos(struct uart_8250_port *p)
584{
585 if (p->capabilities & UART_CAP_FIFO) {
586 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
587 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
588 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
589 serial_outp(p, UART_FCR, 0);
590 }
591}
592
593/*
594 * IER sleep support. UARTs which have EFRs need the "extended
595 * capability" bit enabled. Note that on XR16C850s, we need to
596 * reset LCR to write to IER.
597 */
598static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
599{
600 if (p->capabilities & UART_CAP_SLEEP) {
601 if (p->capabilities & UART_CAP_EFR) {
602 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
603 serial_outp(p, UART_EFR, UART_EFR_ECB);
604 serial_outp(p, UART_LCR, 0);
605 }
606 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
607 if (p->capabilities & UART_CAP_EFR) {
608 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_B);
609 serial_outp(p, UART_EFR, 0);
610 serial_outp(p, UART_LCR, 0);
611 }
612 }
613}
614
615#ifdef CONFIG_SERIAL_8250_RSA
616/*
617 * Attempts to turn on the RSA FIFO. Returns zero on failure.
618 * We set the port uart clock rate if we succeed.
619 */
620static int __enable_rsa(struct uart_8250_port *up)
621{
622 unsigned char mode;
623 int result;
624
625 mode = serial_inp(up, UART_RSA_MSR);
626 result = mode & UART_RSA_MSR_FIFO;
627
628 if (!result) {
629 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
630 mode = serial_inp(up, UART_RSA_MSR);
631 result = mode & UART_RSA_MSR_FIFO;
632 }
633
634 if (result)
635 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
636
637 return result;
638}
639
640static void enable_rsa(struct uart_8250_port *up)
641{
642 if (up->port.type == PORT_RSA) {
643 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
644 spin_lock_irq(&up->port.lock);
645 __enable_rsa(up);
646 spin_unlock_irq(&up->port.lock);
647 }
648 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
649 serial_outp(up, UART_RSA_FRR, 0);
650 }
651}
652
653/*
654 * Attempts to turn off the RSA FIFO. Returns zero on failure.
655 * It is unknown why interrupts were disabled in here. However,
656 * the caller is expected to preserve this behaviour by grabbing
657 * the spinlock before calling this function.
658 */
659static void disable_rsa(struct uart_8250_port *up)
660{
661 unsigned char mode;
662 int result;
663
664 if (up->port.type == PORT_RSA &&
665 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
666 spin_lock_irq(&up->port.lock);
667
668 mode = serial_inp(up, UART_RSA_MSR);
669 result = !(mode & UART_RSA_MSR_FIFO);
670
671 if (!result) {
672 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
673 mode = serial_inp(up, UART_RSA_MSR);
674 result = !(mode & UART_RSA_MSR_FIFO);
675 }
676
677 if (result)
678 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
679 spin_unlock_irq(&up->port.lock);
680 }
681}
682#endif /* CONFIG_SERIAL_8250_RSA */
683
684/*
685 * This is a quickie test to see how big the FIFO is.
686 * It doesn't work at all the time, more's the pity.
687 */
688static int size_fifo(struct uart_8250_port *up)
689{
690 unsigned char old_fcr, old_mcr, old_lcr;
691 unsigned short old_dl;
692 int count;
693
694 old_lcr = serial_inp(up, UART_LCR);
695 serial_outp(up, UART_LCR, 0);
696 old_fcr = serial_inp(up, UART_FCR);
697 old_mcr = serial_inp(up, UART_MCR);
698 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
699 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
700 serial_outp(up, UART_MCR, UART_MCR_LOOP);
701 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
702 old_dl = serial_dl_read(up);
703 serial_dl_write(up, 0x0001);
704 serial_outp(up, UART_LCR, 0x03);
705 for (count = 0; count < 256; count++)
706 serial_outp(up, UART_TX, count);
707 mdelay(20);/* FIXME - schedule_timeout */
708 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
709 (count < 256); count++)
710 serial_inp(up, UART_RX);
711 serial_outp(up, UART_FCR, old_fcr);
712 serial_outp(up, UART_MCR, old_mcr);
713 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
714 serial_dl_write(up, old_dl);
715 serial_outp(up, UART_LCR, old_lcr);
716
717 return count;
718}
719
720/*
721 * Read UART ID using the divisor method - set DLL and DLM to zero
722 * and the revision will be in DLL and device type in DLM. We
723 * preserve the device state across this.
724 */
725static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
726{
727 unsigned char old_dll, old_dlm, old_lcr;
728 unsigned int id;
729
730 old_lcr = serial_inp(p, UART_LCR);
731 serial_outp(p, UART_LCR, UART_LCR_CONF_MODE_A);
732
733 old_dll = serial_inp(p, UART_DLL);
734 old_dlm = serial_inp(p, UART_DLM);
735
736 serial_outp(p, UART_DLL, 0);
737 serial_outp(p, UART_DLM, 0);
738
739 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
740
741 serial_outp(p, UART_DLL, old_dll);
742 serial_outp(p, UART_DLM, old_dlm);
743 serial_outp(p, UART_LCR, old_lcr);
744
745 return id;
746}
747
748/*
749 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
750 * When this function is called we know it is at least a StarTech
751 * 16650 V2, but it might be one of several StarTech UARTs, or one of
752 * its clones. (We treat the broken original StarTech 16650 V1 as a
753 * 16550, and why not? Startech doesn't seem to even acknowledge its
754 * existence.)
755 *
756 * What evil have men's minds wrought...
757 */
758static void autoconfig_has_efr(struct uart_8250_port *up)
759{
760 unsigned int id1, id2, id3, rev;
761
762 /*
763 * Everything with an EFR has SLEEP
764 */
765 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
766
767 /*
768 * First we check to see if it's an Oxford Semiconductor UART.
769 *
770 * If we have to do this here because some non-National
771 * Semiconductor clone chips lock up if you try writing to the
772 * LSR register (which serial_icr_read does)
773 */
774
775 /*
776 * Check for Oxford Semiconductor 16C950.
777 *
778 * EFR [4] must be set else this test fails.
779 *
780 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
781 * claims that it's needed for 952 dual UART's (which are not
782 * recommended for new designs).
783 */
784 up->acr = 0;
785 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
786 serial_out(up, UART_EFR, UART_EFR_ECB);
787 serial_out(up, UART_LCR, 0x00);
788 id1 = serial_icr_read(up, UART_ID1);
789 id2 = serial_icr_read(up, UART_ID2);
790 id3 = serial_icr_read(up, UART_ID3);
791 rev = serial_icr_read(up, UART_REV);
792
793 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
794
795 if (id1 == 0x16 && id2 == 0xC9 &&
796 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
797 up->port.type = PORT_16C950;
798
799 /*
800 * Enable work around for the Oxford Semiconductor 952 rev B
801 * chip which causes it to seriously miscalculate baud rates
802 * when DLL is 0.
803 */
804 if (id3 == 0x52 && rev == 0x01)
805 up->bugs |= UART_BUG_QUOT;
806 return;
807 }
808
809 /*
810 * We check for a XR16C850 by setting DLL and DLM to 0, and then
811 * reading back DLL and DLM. The chip type depends on the DLM
812 * value read back:
813 * 0x10 - XR16C850 and the DLL contains the chip revision.
814 * 0x12 - XR16C2850.
815 * 0x14 - XR16C854.
816 */
817 id1 = autoconfig_read_divisor_id(up);
818 DEBUG_AUTOCONF("850id=%04x ", id1);
819
820 id2 = id1 >> 8;
821 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
822 up->port.type = PORT_16850;
823 return;
824 }
825
826 /*
827 * It wasn't an XR16C850.
828 *
829 * We distinguish between the '654 and the '650 by counting
830 * how many bytes are in the FIFO. I'm using this for now,
831 * since that's the technique that was sent to me in the
832 * serial driver update, but I'm not convinced this works.
833 * I've had problems doing this in the past. -TYT
834 */
835 if (size_fifo(up) == 64)
836 up->port.type = PORT_16654;
837 else
838 up->port.type = PORT_16650V2;
839}
840
841/*
842 * We detected a chip without a FIFO. Only two fall into
843 * this category - the original 8250 and the 16450. The
844 * 16450 has a scratch register (accessible with LCR=0)
845 */
846static void autoconfig_8250(struct uart_8250_port *up)
847{
848 unsigned char scratch, status1, status2;
849
850 up->port.type = PORT_8250;
851
852 scratch = serial_in(up, UART_SCR);
853 serial_outp(up, UART_SCR, 0xa5);
854 status1 = serial_in(up, UART_SCR);
855 serial_outp(up, UART_SCR, 0x5a);
856 status2 = serial_in(up, UART_SCR);
857 serial_outp(up, UART_SCR, scratch);
858
859 if (status1 == 0xa5 && status2 == 0x5a)
860 up->port.type = PORT_16450;
861}
862
863static int broken_efr(struct uart_8250_port *up)
864{
865 /*
866 * Exar ST16C2550 "A2" devices incorrectly detect as
867 * having an EFR, and report an ID of 0x0201. See
868 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html
869 */
870 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
871 return 1;
872
873 return 0;
874}
875
876static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
877{
878 unsigned char status;
879
880 status = serial_in(up, 0x04); /* EXCR2 */
881#define PRESL(x) ((x) & 0x30)
882 if (PRESL(status) == 0x10) {
883 /* already in high speed mode */
884 return 0;
885 } else {
886 status &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
887 status |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
888 serial_outp(up, 0x04, status);
889 }
890 return 1;
891}
892
893/*
894 * We know that the chip has FIFOs. Does it have an EFR? The
895 * EFR is located in the same register position as the IIR and
896 * we know the top two bits of the IIR are currently set. The
897 * EFR should contain zero. Try to read the EFR.
898 */
899static void autoconfig_16550a(struct uart_8250_port *up)
900{
901 unsigned char status1, status2;
902 unsigned int iersave;
903
904 up->port.type = PORT_16550A;
905 up->capabilities |= UART_CAP_FIFO;
906
907 /*
908 * Check for presence of the EFR when DLAB is set.
909 * Only ST16C650V1 UARTs pass this test.
910 */
911 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
912 if (serial_in(up, UART_EFR) == 0) {
913 serial_outp(up, UART_EFR, 0xA8);
914 if (serial_in(up, UART_EFR) != 0) {
915 DEBUG_AUTOCONF("EFRv1 ");
916 up->port.type = PORT_16650;
917 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
918 } else {
919 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
920 }
921 serial_outp(up, UART_EFR, 0);
922 return;
923 }
924
925 /*
926 * Maybe it requires 0xbf to be written to the LCR.
927 * (other ST16C650V2 UARTs, TI16C752A, etc)
928 */
929 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
930 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
931 DEBUG_AUTOCONF("EFRv2 ");
932 autoconfig_has_efr(up);
933 return;
934 }
935
936 /*
937 * Check for a National Semiconductor SuperIO chip.
938 * Attempt to switch to bank 2, read the value of the LOOP bit
939 * from EXCR1. Switch back to bank 0, change it in MCR. Then
940 * switch back to bank 2, read it from EXCR1 again and check
941 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
942 */
943 serial_outp(up, UART_LCR, 0);
944 status1 = serial_in(up, UART_MCR);
945 serial_outp(up, UART_LCR, 0xE0);
946 status2 = serial_in(up, 0x02); /* EXCR1 */
947
948 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
949 serial_outp(up, UART_LCR, 0);
950 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
951 serial_outp(up, UART_LCR, 0xE0);
952 status2 = serial_in(up, 0x02); /* EXCR1 */
953 serial_outp(up, UART_LCR, 0);
954 serial_outp(up, UART_MCR, status1);
955
956 if ((status2 ^ status1) & UART_MCR_LOOP) {
957 unsigned short quot;
958
959 serial_outp(up, UART_LCR, 0xE0);
960
961 quot = serial_dl_read(up);
962 quot <<= 3;
963
964 if (ns16550a_goto_highspeed(up))
965 serial_dl_write(up, quot);
966
967 serial_outp(up, UART_LCR, 0);
968
969 up->port.uartclk = 921600*16;
970 up->port.type = PORT_NS16550A;
971 up->capabilities |= UART_NATSEMI;
972 return;
973 }
974 }
975
976 /*
977 * No EFR. Try to detect a TI16750, which only sets bit 5 of
978 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
979 * Try setting it with and without DLAB set. Cheap clones
980 * set bit 5 without DLAB set.
981 */
982 serial_outp(up, UART_LCR, 0);
983 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
984 status1 = serial_in(up, UART_IIR) >> 5;
985 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
986 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_A);
987 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
988 status2 = serial_in(up, UART_IIR) >> 5;
989 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
990 serial_outp(up, UART_LCR, 0);
991
992 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
993
994 if (status1 == 6 && status2 == 7) {
995 up->port.type = PORT_16750;
996 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
997 return;
998 }
999
1000 /*
1001 * Try writing and reading the UART_IER_UUE bit (b6).
1002 * If it works, this is probably one of the Xscale platform's
1003 * internal UARTs.
1004 * We're going to explicitly set the UUE bit to 0 before
1005 * trying to write and read a 1 just to make sure it's not
1006 * already a 1 and maybe locked there before we even start start.
1007 */
1008 iersave = serial_in(up, UART_IER);
1009 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
1010 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
1011 /*
1012 * OK it's in a known zero state, try writing and reading
1013 * without disturbing the current state of the other bits.
1014 */
1015 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
1016 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1017 /*
1018 * It's an Xscale.
1019 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
1020 */
1021 DEBUG_AUTOCONF("Xscale ");
1022 up->port.type = PORT_XSCALE;
1023 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1024 return;
1025 }
1026 } else {
1027 /*
1028 * If we got here we couldn't force the IER_UUE bit to 0.
1029 * Log it and continue.
1030 */
1031 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1032 }
1033 serial_outp(up, UART_IER, iersave);
1034
1035 /*
1036 * Exar uarts have EFR in a weird location
1037 */
1038 if (up->port.flags & UPF_EXAR_EFR) {
1039 up->port.type = PORT_XR17D15X;
1040 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR;
1041 }
1042
1043 /*
1044 * We distinguish between 16550A and U6 16550A by counting
1045 * how many bytes are in the FIFO.
1046 */
1047 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1048 up->port.type = PORT_U6_16550A;
1049 up->capabilities |= UART_CAP_AFE;
1050 }
1051}
1052
1053/*
1054 * This routine is called by rs_init() to initialize a specific serial
1055 * port. It determines what type of UART chip this serial port is
1056 * using: 8250, 16450, 16550, 16550A. The important question is
1057 * whether or not this UART is a 16550A or not, since this will
1058 * determine whether or not we can use its FIFO features or not.
1059 */
1060static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1061{
1062 unsigned char status1, scratch, scratch2, scratch3;
1063 unsigned char save_lcr, save_mcr;
1064 unsigned long flags;
1065
1066 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
1067 return;
1068
1069 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1070 serial_index(&up->port), up->port.iobase, up->port.membase);
1071
1072 /*
1073 * We really do need global IRQs disabled here - we're going to
1074 * be frobbing the chips IRQ enable register to see if it exists.
1075 */
1076 spin_lock_irqsave(&up->port.lock, flags);
1077
1078 up->capabilities = 0;
1079 up->bugs = 0;
1080
1081 if (!(up->port.flags & UPF_BUGGY_UART)) {
1082 /*
1083 * Do a simple existence test first; if we fail this,
1084 * there's no point trying anything else.
1085 *
1086 * 0x80 is used as a nonsense port to prevent against
1087 * false positives due to ISA bus float. The
1088 * assumption is that 0x80 is a non-existent port;
1089 * which should be safe since include/asm/io.h also
1090 * makes this assumption.
1091 *
1092 * Note: this is safe as long as MCR bit 4 is clear
1093 * and the device is in "PC" mode.
1094 */
1095 scratch = serial_inp(up, UART_IER);
1096 serial_outp(up, UART_IER, 0);
1097#ifdef __i386__
1098 outb(0xff, 0x080);
1099#endif
1100 /*
1101 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1102 * 16C754B) allow only to modify them if an EFR bit is set.
1103 */
1104 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1105 serial_outp(up, UART_IER, 0x0F);
1106#ifdef __i386__
1107 outb(0, 0x080);
1108#endif
1109 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1110 serial_outp(up, UART_IER, scratch);
1111 if (scratch2 != 0 || scratch3 != 0x0F) {
1112 /*
1113 * We failed; there's nothing here
1114 */
1115 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1116 scratch2, scratch3);
1117 goto out;
1118 }
1119 }
1120
1121 save_mcr = serial_in(up, UART_MCR);
1122 save_lcr = serial_in(up, UART_LCR);
1123
1124 /*
1125 * Check to see if a UART is really there. Certain broken
1126 * internal modems based on the Rockwell chipset fail this
1127 * test, because they apparently don't implement the loopback
1128 * test mode. So this test is skipped on the COM 1 through
1129 * COM 4 ports. This *should* be safe, since no board
1130 * manufacturer would be stupid enough to design a board
1131 * that conflicts with COM 1-4 --- we hope!
1132 */
1133 if (!(up->port.flags & UPF_SKIP_TEST)) {
1134 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1135 status1 = serial_inp(up, UART_MSR) & 0xF0;
1136 serial_outp(up, UART_MCR, save_mcr);
1137 if (status1 != 0x90) {
1138 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1139 status1);
1140 goto out;
1141 }
1142 }
1143
1144 /*
1145 * We're pretty sure there's a port here. Lets find out what
1146 * type of port it is. The IIR top two bits allows us to find
1147 * out if it's 8250 or 16450, 16550, 16550A or later. This
1148 * determines what we test for next.
1149 *
1150 * We also initialise the EFR (if any) to zero for later. The
1151 * EFR occupies the same register location as the FCR and IIR.
1152 */
1153 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1154 serial_outp(up, UART_EFR, 0);
1155 serial_outp(up, UART_LCR, 0);
1156
1157 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1158 scratch = serial_in(up, UART_IIR) >> 6;
1159
1160 DEBUG_AUTOCONF("iir=%d ", scratch);
1161
1162 switch (scratch) {
1163 case 0:
1164 autoconfig_8250(up);
1165 break;
1166 case 1:
1167 up->port.type = PORT_UNKNOWN;
1168 break;
1169 case 2:
1170 up->port.type = PORT_16550;
1171 break;
1172 case 3:
1173 autoconfig_16550a(up);
1174 break;
1175 }
1176
1177#ifdef CONFIG_SERIAL_8250_RSA
1178 /*
1179 * Only probe for RSA ports if we got the region.
1180 */
1181 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1182 int i;
1183
1184 for (i = 0 ; i < probe_rsa_count; ++i) {
1185 if (probe_rsa[i] == up->port.iobase &&
1186 __enable_rsa(up)) {
1187 up->port.type = PORT_RSA;
1188 break;
1189 }
1190 }
1191 }
1192#endif
1193
1194 serial_outp(up, UART_LCR, save_lcr);
1195
1196 if (up->capabilities != uart_config[up->port.type].flags) {
1197 printk(KERN_WARNING
1198 "ttyS%d: detected caps %08x should be %08x\n",
1199 serial_index(&up->port), up->capabilities,
1200 uart_config[up->port.type].flags);
1201 }
1202
1203 up->port.fifosize = uart_config[up->port.type].fifo_size;
1204 up->capabilities = uart_config[up->port.type].flags;
1205 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1206
1207 if (up->port.type == PORT_UNKNOWN)
1208 goto out;
1209
1210 /*
1211 * Reset the UART.
1212 */
1213#ifdef CONFIG_SERIAL_8250_RSA
1214 if (up->port.type == PORT_RSA)
1215 serial_outp(up, UART_RSA_FRR, 0);
1216#endif
1217 serial_outp(up, UART_MCR, save_mcr);
1218 serial8250_clear_fifos(up);
1219 serial_in(up, UART_RX);
1220 if (up->capabilities & UART_CAP_UUE)
1221 serial_outp(up, UART_IER, UART_IER_UUE);
1222 else
1223 serial_outp(up, UART_IER, 0);
1224
1225 out:
1226 spin_unlock_irqrestore(&up->port.lock, flags);
1227 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1228}
1229
1230static void autoconfig_irq(struct uart_8250_port *up)
1231{
1232 unsigned char save_mcr, save_ier;
1233 unsigned char save_ICP = 0;
1234 unsigned int ICP = 0;
1235 unsigned long irqs;
1236 int irq;
1237
1238 if (up->port.flags & UPF_FOURPORT) {
1239 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1240 save_ICP = inb_p(ICP);
1241 outb_p(0x80, ICP);
1242 (void) inb_p(ICP);
1243 }
1244
1245 /* forget possible initially masked and pending IRQ */
1246 probe_irq_off(probe_irq_on());
1247 save_mcr = serial_inp(up, UART_MCR);
1248 save_ier = serial_inp(up, UART_IER);
1249 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1250
1251 irqs = probe_irq_on();
1252 serial_outp(up, UART_MCR, 0);
1253 udelay(10);
1254 if (up->port.flags & UPF_FOURPORT) {
1255 serial_outp(up, UART_MCR,
1256 UART_MCR_DTR | UART_MCR_RTS);
1257 } else {
1258 serial_outp(up, UART_MCR,
1259 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1260 }
1261 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1262 (void)serial_inp(up, UART_LSR);
1263 (void)serial_inp(up, UART_RX);
1264 (void)serial_inp(up, UART_IIR);
1265 (void)serial_inp(up, UART_MSR);
1266 serial_outp(up, UART_TX, 0xFF);
1267 udelay(20);
1268 irq = probe_irq_off(irqs);
1269
1270 serial_outp(up, UART_MCR, save_mcr);
1271 serial_outp(up, UART_IER, save_ier);
1272
1273 if (up->port.flags & UPF_FOURPORT)
1274 outb_p(save_ICP, ICP);
1275
1276 up->port.irq = (irq > 0) ? irq : 0;
1277}
1278
1279static inline void __stop_tx(struct uart_8250_port *p)
1280{
1281 if (p->ier & UART_IER_THRI) {
1282 p->ier &= ~UART_IER_THRI;
1283 serial_out(p, UART_IER, p->ier);
1284 }
1285}
1286
1287static void serial8250_stop_tx(struct uart_port *port)
1288{
1289 struct uart_8250_port *up =
1290 container_of(port, struct uart_8250_port, port);
1291
1292 __stop_tx(up);
1293
1294 /*
1295 * We really want to stop the transmitter from sending.
1296 */
1297 if (up->port.type == PORT_16C950) {
1298 up->acr |= UART_ACR_TXDIS;
1299 serial_icr_write(up, UART_ACR, up->acr);
1300 }
1301}
1302
1303static void serial8250_start_tx(struct uart_port *port)
1304{
1305 struct uart_8250_port *up =
1306 container_of(port, struct uart_8250_port, port);
1307
1308 if (!(up->ier & UART_IER_THRI)) {
1309 up->ier |= UART_IER_THRI;
1310 serial_out(up, UART_IER, up->ier);
1311
1312 if (up->bugs & UART_BUG_TXEN) {
1313 unsigned char lsr;
1314 lsr = serial_in(up, UART_LSR);
1315 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1316 if ((up->port.type == PORT_RM9000) ?
1317 (lsr & UART_LSR_THRE) :
1318 (lsr & UART_LSR_TEMT))
1319 serial8250_tx_chars(up);
1320 }
1321 }
1322
1323 /*
1324 * Re-enable the transmitter if we disabled it.
1325 */
1326 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1327 up->acr &= ~UART_ACR_TXDIS;
1328 serial_icr_write(up, UART_ACR, up->acr);
1329 }
1330}
1331
1332static void serial8250_stop_rx(struct uart_port *port)
1333{
1334 struct uart_8250_port *up =
1335 container_of(port, struct uart_8250_port, port);
1336
1337 up->ier &= ~UART_IER_RLSI;
1338 up->port.read_status_mask &= ~UART_LSR_DR;
1339 serial_out(up, UART_IER, up->ier);
1340}
1341
1342static void serial8250_enable_ms(struct uart_port *port)
1343{
1344 struct uart_8250_port *up =
1345 container_of(port, struct uart_8250_port, port);
1346
1347 /* no MSR capabilities */
1348 if (up->bugs & UART_BUG_NOMSR)
1349 return;
1350
1351 up->ier |= UART_IER_MSI;
1352 serial_out(up, UART_IER, up->ier);
1353}
1354
1355/*
1356 * Clear the Tegra rx fifo after a break
1357 *
1358 * FIXME: This needs to become a port specific callback once we have a
1359 * framework for this
1360 */
1361static void clear_rx_fifo(struct uart_8250_port *up)
1362{
1363 unsigned int status, tmout = 10000;
1364 do {
1365 status = serial_in(up, UART_LSR);
1366 if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
1367 status = serial_in(up, UART_RX);
1368 else
1369 break;
1370 if (--tmout == 0)
1371 break;
1372 udelay(1);
1373 } while (1);
1374}
1375
1376/*
1377 * serial8250_rx_chars: processes according to the passed in LSR
1378 * value, and returns the remaining LSR bits not handled
1379 * by this Rx routine.
1380 */
1381unsigned char
1382serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1383{
1384 struct tty_struct *tty = up->port.state->port.tty;
1385 unsigned char ch;
1386 int max_count = 256;
1387 char flag;
1388
1389 do {
1390 if (likely(lsr & UART_LSR_DR))
1391 ch = serial_inp(up, UART_RX);
1392 else
1393 /*
1394 * Intel 82571 has a Serial Over Lan device that will
1395 * set UART_LSR_BI without setting UART_LSR_DR when
1396 * it receives a break. To avoid reading from the
1397 * receive buffer without UART_LSR_DR bit set, we
1398 * just force the read character to be 0
1399 */
1400 ch = 0;
1401
1402 flag = TTY_NORMAL;
1403 up->port.icount.rx++;
1404
1405 lsr |= up->lsr_saved_flags;
1406 up->lsr_saved_flags = 0;
1407
1408 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1409 /*
1410 * For statistics only
1411 */
1412 if (lsr & UART_LSR_BI) {
1413 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1414 up->port.icount.brk++;
1415 /*
1416 * If tegra port then clear the rx fifo to
1417 * accept another break/character.
1418 */
1419 if (up->port.type == PORT_TEGRA)
1420 clear_rx_fifo(up);
1421
1422 /*
1423 * We do the SysRQ and SAK checking
1424 * here because otherwise the break
1425 * may get masked by ignore_status_mask
1426 * or read_status_mask.
1427 */
1428 if (uart_handle_break(&up->port))
1429 goto ignore_char;
1430 } else if (lsr & UART_LSR_PE)
1431 up->port.icount.parity++;
1432 else if (lsr & UART_LSR_FE)
1433 up->port.icount.frame++;
1434 if (lsr & UART_LSR_OE)
1435 up->port.icount.overrun++;
1436
1437 /*
1438 * Mask off conditions which should be ignored.
1439 */
1440 lsr &= up->port.read_status_mask;
1441
1442 if (lsr & UART_LSR_BI) {
1443 DEBUG_INTR("handling break....");
1444 flag = TTY_BREAK;
1445 } else if (lsr & UART_LSR_PE)
1446 flag = TTY_PARITY;
1447 else if (lsr & UART_LSR_FE)
1448 flag = TTY_FRAME;
1449 }
1450 if (uart_handle_sysrq_char(&up->port, ch))
1451 goto ignore_char;
1452
1453 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1454
1455ignore_char:
1456 lsr = serial_inp(up, UART_LSR);
1457 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1458 spin_unlock(&up->port.lock);
1459 tty_flip_buffer_push(tty);
1460 spin_lock(&up->port.lock);
1461 return lsr;
1462}
1463EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1464
1465void serial8250_tx_chars(struct uart_8250_port *up)
1466{
1467 struct circ_buf *xmit = &up->port.state->xmit;
1468 int count;
1469
1470 if (up->port.x_char) {
1471 serial_outp(up, UART_TX, up->port.x_char);
1472 up->port.icount.tx++;
1473 up->port.x_char = 0;
1474 return;
1475 }
1476 if (uart_tx_stopped(&up->port)) {
1477 serial8250_stop_tx(&up->port);
1478 return;
1479 }
1480 if (uart_circ_empty(xmit)) {
1481 __stop_tx(up);
1482 return;
1483 }
1484
1485 count = up->tx_loadsz;
1486 do {
1487 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1488 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1489 up->port.icount.tx++;
1490 if (uart_circ_empty(xmit))
1491 break;
1492 } while (--count > 0);
1493
1494 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1495 uart_write_wakeup(&up->port);
1496
1497 DEBUG_INTR("THRE...");
1498
1499 if (uart_circ_empty(xmit))
1500 __stop_tx(up);
1501}
1502EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1503
1504unsigned int serial8250_modem_status(struct uart_8250_port *up)
1505{
1506 unsigned int status = serial_in(up, UART_MSR);
1507
1508 status |= up->msr_saved_flags;
1509 up->msr_saved_flags = 0;
1510 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1511 up->port.state != NULL) {
1512 if (status & UART_MSR_TERI)
1513 up->port.icount.rng++;
1514 if (status & UART_MSR_DDSR)
1515 up->port.icount.dsr++;
1516 if (status & UART_MSR_DDCD)
1517 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1518 if (status & UART_MSR_DCTS)
1519 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1520
1521 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
1522 }
1523
1524 return status;
1525}
1526EXPORT_SYMBOL_GPL(serial8250_modem_status);
1527
1528/*
1529 * This handles the interrupt from one port.
1530 */
1531int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1532{
1533 unsigned char status;
1534 unsigned long flags;
1535 struct uart_8250_port *up =
1536 container_of(port, struct uart_8250_port, port);
1537
1538 if (iir & UART_IIR_NO_INT)
1539 return 0;
1540
1541 spin_lock_irqsave(&up->port.lock, flags);
1542
1543 status = serial_inp(up, UART_LSR);
1544
1545 DEBUG_INTR("status = %x...", status);
1546
1547 if (status & (UART_LSR_DR | UART_LSR_BI))
1548 status = serial8250_rx_chars(up, status);
1549 serial8250_modem_status(up);
1550 if (status & UART_LSR_THRE)
1551 serial8250_tx_chars(up);
1552
1553 spin_unlock_irqrestore(&up->port.lock, flags);
1554 return 1;
1555}
1556EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1557
1558static int serial8250_default_handle_irq(struct uart_port *port)
1559{
1560 struct uart_8250_port *up =
1561 container_of(port, struct uart_8250_port, port);
1562 unsigned int iir = serial_in(up, UART_IIR);
1563
1564 return serial8250_handle_irq(port, iir);
1565}
1566
1567/*
1568 * This is the serial driver's interrupt routine.
1569 *
1570 * Arjan thinks the old way was overly complex, so it got simplified.
1571 * Alan disagrees, saying that need the complexity to handle the weird
1572 * nature of ISA shared interrupts. (This is a special exception.)
1573 *
1574 * In order to handle ISA shared interrupts properly, we need to check
1575 * that all ports have been serviced, and therefore the ISA interrupt
1576 * line has been de-asserted.
1577 *
1578 * This means we need to loop through all ports. checking that they
1579 * don't have an interrupt pending.
1580 */
1581static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1582{
1583 struct irq_info *i = dev_id;
1584 struct list_head *l, *end = NULL;
1585 int pass_counter = 0, handled = 0;
1586
1587 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1588
1589 spin_lock(&i->lock);
1590
1591 l = i->head;
1592 do {
1593 struct uart_8250_port *up;
1594 struct uart_port *port;
1595 bool skip;
1596
1597 up = list_entry(l, struct uart_8250_port, list);
1598 port = &up->port;
1599 skip = pass_counter && up->port.flags & UPF_IIR_ONCE;
1600
1601 if (!skip && port->handle_irq(port)) {
1602 handled = 1;
1603 end = NULL;
1604 } else if (end == NULL)
1605 end = l;
1606
1607 l = l->next;
1608
1609 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1610 /* If we hit this, we're dead. */
1611 printk_ratelimited(KERN_ERR
1612 "serial8250: too much work for irq%d\n", irq);
1613 break;
1614 }
1615 } while (l != end);
1616
1617 spin_unlock(&i->lock);
1618
1619 DEBUG_INTR("end.\n");
1620
1621 return IRQ_RETVAL(handled);
1622}
1623
1624/*
1625 * To support ISA shared interrupts, we need to have one interrupt
1626 * handler that ensures that the IRQ line has been deasserted
1627 * before returning. Failing to do this will result in the IRQ
1628 * line being stuck active, and, since ISA irqs are edge triggered,
1629 * no more IRQs will be seen.
1630 */
1631static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1632{
1633 spin_lock_irq(&i->lock);
1634
1635 if (!list_empty(i->head)) {
1636 if (i->head == &up->list)
1637 i->head = i->head->next;
1638 list_del(&up->list);
1639 } else {
1640 BUG_ON(i->head != &up->list);
1641 i->head = NULL;
1642 }
1643 spin_unlock_irq(&i->lock);
1644 /* List empty so throw away the hash node */
1645 if (i->head == NULL) {
1646 hlist_del(&i->node);
1647 kfree(i);
1648 }
1649}
1650
1651static int serial_link_irq_chain(struct uart_8250_port *up)
1652{
1653 struct hlist_head *h;
1654 struct hlist_node *n;
1655 struct irq_info *i;
1656 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1657
1658 mutex_lock(&hash_mutex);
1659
1660 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1661
1662 hlist_for_each(n, h) {
1663 i = hlist_entry(n, struct irq_info, node);
1664 if (i->irq == up->port.irq)
1665 break;
1666 }
1667
1668 if (n == NULL) {
1669 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1670 if (i == NULL) {
1671 mutex_unlock(&hash_mutex);
1672 return -ENOMEM;
1673 }
1674 spin_lock_init(&i->lock);
1675 i->irq = up->port.irq;
1676 hlist_add_head(&i->node, h);
1677 }
1678 mutex_unlock(&hash_mutex);
1679
1680 spin_lock_irq(&i->lock);
1681
1682 if (i->head) {
1683 list_add(&up->list, i->head);
1684 spin_unlock_irq(&i->lock);
1685
1686 ret = 0;
1687 } else {
1688 INIT_LIST_HEAD(&up->list);
1689 i->head = &up->list;
1690 spin_unlock_irq(&i->lock);
1691 irq_flags |= up->port.irqflags;
1692 ret = request_irq(up->port.irq, serial8250_interrupt,
1693 irq_flags, "serial", i);
1694 if (ret < 0)
1695 serial_do_unlink(i, up);
1696 }
1697
1698 return ret;
1699}
1700
1701static void serial_unlink_irq_chain(struct uart_8250_port *up)
1702{
1703 struct irq_info *i;
1704 struct hlist_node *n;
1705 struct hlist_head *h;
1706
1707 mutex_lock(&hash_mutex);
1708
1709 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1710
1711 hlist_for_each(n, h) {
1712 i = hlist_entry(n, struct irq_info, node);
1713 if (i->irq == up->port.irq)
1714 break;
1715 }
1716
1717 BUG_ON(n == NULL);
1718 BUG_ON(i->head == NULL);
1719
1720 if (list_empty(i->head))
1721 free_irq(up->port.irq, i);
1722
1723 serial_do_unlink(i, up);
1724 mutex_unlock(&hash_mutex);
1725}
1726
1727/*
1728 * This function is used to handle ports that do not have an
1729 * interrupt. This doesn't work very well for 16450's, but gives
1730 * barely passable results for a 16550A. (Although at the expense
1731 * of much CPU overhead).
1732 */
1733static void serial8250_timeout(unsigned long data)
1734{
1735 struct uart_8250_port *up = (struct uart_8250_port *)data;
1736
1737 up->port.handle_irq(&up->port);
1738 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1739}
1740
1741static void serial8250_backup_timeout(unsigned long data)
1742{
1743 struct uart_8250_port *up = (struct uart_8250_port *)data;
1744 unsigned int iir, ier = 0, lsr;
1745 unsigned long flags;
1746
1747 spin_lock_irqsave(&up->port.lock, flags);
1748
1749 /*
1750 * Must disable interrupts or else we risk racing with the interrupt
1751 * based handler.
1752 */
1753 if (is_real_interrupt(up->port.irq)) {
1754 ier = serial_in(up, UART_IER);
1755 serial_out(up, UART_IER, 0);
1756 }
1757
1758 iir = serial_in(up, UART_IIR);
1759
1760 /*
1761 * This should be a safe test for anyone who doesn't trust the
1762 * IIR bits on their UART, but it's specifically designed for
1763 * the "Diva" UART used on the management processor on many HP
1764 * ia64 and parisc boxes.
1765 */
1766 lsr = serial_in(up, UART_LSR);
1767 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1768 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1769 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1770 (lsr & UART_LSR_THRE)) {
1771 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1772 iir |= UART_IIR_THRI;
1773 }
1774
1775 if (!(iir & UART_IIR_NO_INT))
1776 serial8250_tx_chars(up);
1777
1778 if (is_real_interrupt(up->port.irq))
1779 serial_out(up, UART_IER, ier);
1780
1781 spin_unlock_irqrestore(&up->port.lock, flags);
1782
1783 /* Standard timer interval plus 0.2s to keep the port running */
1784 mod_timer(&up->timer,
1785 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1786}
1787
1788static unsigned int serial8250_tx_empty(struct uart_port *port)
1789{
1790 struct uart_8250_port *up =
1791 container_of(port, struct uart_8250_port, port);
1792 unsigned long flags;
1793 unsigned int lsr;
1794
1795 spin_lock_irqsave(&up->port.lock, flags);
1796 lsr = serial_in(up, UART_LSR);
1797 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1798 spin_unlock_irqrestore(&up->port.lock, flags);
1799
1800 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1801}
1802
1803static unsigned int serial8250_get_mctrl(struct uart_port *port)
1804{
1805 struct uart_8250_port *up =
1806 container_of(port, struct uart_8250_port, port);
1807 unsigned int status;
1808 unsigned int ret;
1809
1810 status = serial8250_modem_status(up);
1811
1812 ret = 0;
1813 if (status & UART_MSR_DCD)
1814 ret |= TIOCM_CAR;
1815 if (status & UART_MSR_RI)
1816 ret |= TIOCM_RNG;
1817 if (status & UART_MSR_DSR)
1818 ret |= TIOCM_DSR;
1819 if (status & UART_MSR_CTS)
1820 ret |= TIOCM_CTS;
1821 return ret;
1822}
1823
1824static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1825{
1826 struct uart_8250_port *up =
1827 container_of(port, struct uart_8250_port, port);
1828 unsigned char mcr = 0;
1829
1830 if (mctrl & TIOCM_RTS)
1831 mcr |= UART_MCR_RTS;
1832 if (mctrl & TIOCM_DTR)
1833 mcr |= UART_MCR_DTR;
1834 if (mctrl & TIOCM_OUT1)
1835 mcr |= UART_MCR_OUT1;
1836 if (mctrl & TIOCM_OUT2)
1837 mcr |= UART_MCR_OUT2;
1838 if (mctrl & TIOCM_LOOP)
1839 mcr |= UART_MCR_LOOP;
1840
1841 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1842
1843 serial_out(up, UART_MCR, mcr);
1844}
1845
1846static void serial8250_break_ctl(struct uart_port *port, int break_state)
1847{
1848 struct uart_8250_port *up =
1849 container_of(port, struct uart_8250_port, port);
1850 unsigned long flags;
1851
1852 spin_lock_irqsave(&up->port.lock, flags);
1853 if (break_state == -1)
1854 up->lcr |= UART_LCR_SBC;
1855 else
1856 up->lcr &= ~UART_LCR_SBC;
1857 serial_out(up, UART_LCR, up->lcr);
1858 spin_unlock_irqrestore(&up->port.lock, flags);
1859}
1860
1861/*
1862 * Wait for transmitter & holding register to empty
1863 */
1864static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1865{
1866 unsigned int status, tmout = 10000;
1867
1868 /* Wait up to 10ms for the character(s) to be sent. */
1869 for (;;) {
1870 status = serial_in(up, UART_LSR);
1871
1872 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1873
1874 if ((status & bits) == bits)
1875 break;
1876 if (--tmout == 0)
1877 break;
1878 udelay(1);
1879 }
1880
1881 /* Wait up to 1s for flow control if necessary */
1882 if (up->port.flags & UPF_CONS_FLOW) {
1883 unsigned int tmout;
1884 for (tmout = 1000000; tmout; tmout--) {
1885 unsigned int msr = serial_in(up, UART_MSR);
1886 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1887 if (msr & UART_MSR_CTS)
1888 break;
1889 udelay(1);
1890 touch_nmi_watchdog();
1891 }
1892 }
1893}
1894
1895#ifdef CONFIG_CONSOLE_POLL
1896/*
1897 * Console polling routines for writing and reading from the uart while
1898 * in an interrupt or debug context.
1899 */
1900
1901static int serial8250_get_poll_char(struct uart_port *port)
1902{
1903 struct uart_8250_port *up =
1904 container_of(port, struct uart_8250_port, port);
1905 unsigned char lsr = serial_inp(up, UART_LSR);
1906
1907 if (!(lsr & UART_LSR_DR))
1908 return NO_POLL_CHAR;
1909
1910 return serial_inp(up, UART_RX);
1911}
1912
1913
1914static void serial8250_put_poll_char(struct uart_port *port,
1915 unsigned char c)
1916{
1917 unsigned int ier;
1918 struct uart_8250_port *up =
1919 container_of(port, struct uart_8250_port, port);
1920
1921 /*
1922 * First save the IER then disable the interrupts
1923 */
1924 ier = serial_in(up, UART_IER);
1925 if (up->capabilities & UART_CAP_UUE)
1926 serial_out(up, UART_IER, UART_IER_UUE);
1927 else
1928 serial_out(up, UART_IER, 0);
1929
1930 wait_for_xmitr(up, BOTH_EMPTY);
1931 /*
1932 * Send the character out.
1933 * If a LF, also do CR...
1934 */
1935 serial_out(up, UART_TX, c);
1936 if (c == 10) {
1937 wait_for_xmitr(up, BOTH_EMPTY);
1938 serial_out(up, UART_TX, 13);
1939 }
1940
1941 /*
1942 * Finally, wait for transmitter to become empty
1943 * and restore the IER
1944 */
1945 wait_for_xmitr(up, BOTH_EMPTY);
1946 serial_out(up, UART_IER, ier);
1947}
1948
1949#endif /* CONFIG_CONSOLE_POLL */
1950
1951static int serial8250_startup(struct uart_port *port)
1952{
1953 struct uart_8250_port *up =
1954 container_of(port, struct uart_8250_port, port);
1955 unsigned long flags;
1956 unsigned char lsr, iir;
1957 int retval;
1958
1959 up->port.fifosize = uart_config[up->port.type].fifo_size;
1960 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1961 up->capabilities = uart_config[up->port.type].flags;
1962 up->mcr = 0;
1963
1964 if (up->port.iotype != up->cur_iotype)
1965 set_io_from_upio(port);
1966
1967 if (up->port.type == PORT_16C950) {
1968 /* Wake up and initialize UART */
1969 up->acr = 0;
1970 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1971 serial_outp(up, UART_EFR, UART_EFR_ECB);
1972 serial_outp(up, UART_IER, 0);
1973 serial_outp(up, UART_LCR, 0);
1974 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1975 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
1976 serial_outp(up, UART_EFR, UART_EFR_ECB);
1977 serial_outp(up, UART_LCR, 0);
1978 }
1979
1980#ifdef CONFIG_SERIAL_8250_RSA
1981 /*
1982 * If this is an RSA port, see if we can kick it up to the
1983 * higher speed clock.
1984 */
1985 enable_rsa(up);
1986#endif
1987
1988 /*
1989 * Clear the FIFO buffers and disable them.
1990 * (they will be reenabled in set_termios())
1991 */
1992 serial8250_clear_fifos(up);
1993
1994 /*
1995 * Clear the interrupt registers.
1996 */
1997 (void) serial_inp(up, UART_LSR);
1998 (void) serial_inp(up, UART_RX);
1999 (void) serial_inp(up, UART_IIR);
2000 (void) serial_inp(up, UART_MSR);
2001
2002 /*
2003 * At this point, there's no way the LSR could still be 0xff;
2004 * if it is, then bail out, because there's likely no UART
2005 * here.
2006 */
2007 if (!(up->port.flags & UPF_BUGGY_UART) &&
2008 (serial_inp(up, UART_LSR) == 0xff)) {
2009 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2010 serial_index(&up->port));
2011 return -ENODEV;
2012 }
2013
2014 /*
2015 * For a XR16C850, we need to set the trigger levels
2016 */
2017 if (up->port.type == PORT_16850) {
2018 unsigned char fctr;
2019
2020 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2021
2022 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2023 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2024 serial_outp(up, UART_TRG, UART_TRG_96);
2025 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2026 serial_outp(up, UART_TRG, UART_TRG_96);
2027
2028 serial_outp(up, UART_LCR, 0);
2029 }
2030
2031 if (is_real_interrupt(up->port.irq)) {
2032 unsigned char iir1;
2033 /*
2034 * Test for UARTs that do not reassert THRE when the
2035 * transmitter is idle and the interrupt has already
2036 * been cleared. Real 16550s should always reassert
2037 * this interrupt whenever the transmitter is idle and
2038 * the interrupt is enabled. Delays are necessary to
2039 * allow register changes to become visible.
2040 */
2041 spin_lock_irqsave(&up->port.lock, flags);
2042 if (up->port.irqflags & IRQF_SHARED)
2043 disable_irq_nosync(up->port.irq);
2044
2045 wait_for_xmitr(up, UART_LSR_THRE);
2046 serial_out_sync(up, UART_IER, UART_IER_THRI);
2047 udelay(1); /* allow THRE to set */
2048 iir1 = serial_in(up, UART_IIR);
2049 serial_out(up, UART_IER, 0);
2050 serial_out_sync(up, UART_IER, UART_IER_THRI);
2051 udelay(1); /* allow a working UART time to re-assert THRE */
2052 iir = serial_in(up, UART_IIR);
2053 serial_out(up, UART_IER, 0);
2054
2055 if (up->port.irqflags & IRQF_SHARED)
2056 enable_irq(up->port.irq);
2057 spin_unlock_irqrestore(&up->port.lock, flags);
2058
2059 /*
2060 * If the interrupt is not reasserted, setup a timer to
2061 * kick the UART on a regular basis.
2062 */
2063 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
2064 up->bugs |= UART_BUG_THRE;
2065 pr_debug("ttyS%d - using backup timer\n",
2066 serial_index(port));
2067 }
2068 }
2069
2070 /*
2071 * The above check will only give an accurate result the first time
2072 * the port is opened so this value needs to be preserved.
2073 */
2074 if (up->bugs & UART_BUG_THRE) {
2075 up->timer.function = serial8250_backup_timeout;
2076 up->timer.data = (unsigned long)up;
2077 mod_timer(&up->timer, jiffies +
2078 uart_poll_timeout(port) + HZ / 5);
2079 }
2080
2081 /*
2082 * If the "interrupt" for this port doesn't correspond with any
2083 * hardware interrupt, we use a timer-based system. The original
2084 * driver used to do this with IRQ0.
2085 */
2086 if (!is_real_interrupt(up->port.irq)) {
2087 up->timer.data = (unsigned long)up;
2088 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2089 } else {
2090 retval = serial_link_irq_chain(up);
2091 if (retval)
2092 return retval;
2093 }
2094
2095 /*
2096 * Now, initialize the UART
2097 */
2098 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
2099
2100 spin_lock_irqsave(&up->port.lock, flags);
2101 if (up->port.flags & UPF_FOURPORT) {
2102 if (!is_real_interrupt(up->port.irq))
2103 up->port.mctrl |= TIOCM_OUT1;
2104 } else
2105 /*
2106 * Most PC uarts need OUT2 raised to enable interrupts.
2107 */
2108 if (is_real_interrupt(up->port.irq))
2109 up->port.mctrl |= TIOCM_OUT2;
2110
2111 serial8250_set_mctrl(&up->port, up->port.mctrl);
2112
2113 /* Serial over Lan (SoL) hack:
2114 Intel 8257x Gigabit ethernet chips have a
2115 16550 emulation, to be used for Serial Over Lan.
2116 Those chips take a longer time than a normal
2117 serial device to signalize that a transmission
2118 data was queued. Due to that, the above test generally
2119 fails. One solution would be to delay the reading of
2120 iir. However, this is not reliable, since the timeout
2121 is variable. So, let's just don't test if we receive
2122 TX irq. This way, we'll never enable UART_BUG_TXEN.
2123 */
2124 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2125 goto dont_test_tx_en;
2126
2127 /*
2128 * Do a quick test to see if we receive an
2129 * interrupt when we enable the TX irq.
2130 */
2131 serial_outp(up, UART_IER, UART_IER_THRI);
2132 lsr = serial_in(up, UART_LSR);
2133 iir = serial_in(up, UART_IIR);
2134 serial_outp(up, UART_IER, 0);
2135
2136 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2137 if (!(up->bugs & UART_BUG_TXEN)) {
2138 up->bugs |= UART_BUG_TXEN;
2139 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2140 serial_index(port));
2141 }
2142 } else {
2143 up->bugs &= ~UART_BUG_TXEN;
2144 }
2145
2146dont_test_tx_en:
2147 spin_unlock_irqrestore(&up->port.lock, flags);
2148
2149 /*
2150 * Clear the interrupt registers again for luck, and clear the
2151 * saved flags to avoid getting false values from polling
2152 * routines or the previous session.
2153 */
2154 serial_inp(up, UART_LSR);
2155 serial_inp(up, UART_RX);
2156 serial_inp(up, UART_IIR);
2157 serial_inp(up, UART_MSR);
2158 up->lsr_saved_flags = 0;
2159 up->msr_saved_flags = 0;
2160
2161 /*
2162 * Finally, enable interrupts. Note: Modem status interrupts
2163 * are set via set_termios(), which will be occurring imminently
2164 * anyway, so we don't enable them here.
2165 */
2166 up->ier = UART_IER_RLSI | UART_IER_RDI;
2167 serial_outp(up, UART_IER, up->ier);
2168
2169 if (up->port.flags & UPF_FOURPORT) {
2170 unsigned int icp;
2171 /*
2172 * Enable interrupts on the AST Fourport board
2173 */
2174 icp = (up->port.iobase & 0xfe0) | 0x01f;
2175 outb_p(0x80, icp);
2176 (void) inb_p(icp);
2177 }
2178
2179 return 0;
2180}
2181
2182static void serial8250_shutdown(struct uart_port *port)
2183{
2184 struct uart_8250_port *up =
2185 container_of(port, struct uart_8250_port, port);
2186 unsigned long flags;
2187
2188 /*
2189 * Disable interrupts from this port
2190 */
2191 up->ier = 0;
2192 serial_outp(up, UART_IER, 0);
2193
2194 spin_lock_irqsave(&up->port.lock, flags);
2195 if (up->port.flags & UPF_FOURPORT) {
2196 /* reset interrupts on the AST Fourport board */
2197 inb((up->port.iobase & 0xfe0) | 0x1f);
2198 up->port.mctrl |= TIOCM_OUT1;
2199 } else
2200 up->port.mctrl &= ~TIOCM_OUT2;
2201
2202 serial8250_set_mctrl(&up->port, up->port.mctrl);
2203 spin_unlock_irqrestore(&up->port.lock, flags);
2204
2205 /*
2206 * Disable break condition and FIFOs
2207 */
2208 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2209 serial8250_clear_fifos(up);
2210
2211#ifdef CONFIG_SERIAL_8250_RSA
2212 /*
2213 * Reset the RSA board back to 115kbps compat mode.
2214 */
2215 disable_rsa(up);
2216#endif
2217
2218 /*
2219 * Read data port to reset things, and then unlink from
2220 * the IRQ chain.
2221 */
2222 (void) serial_in(up, UART_RX);
2223
2224 del_timer_sync(&up->timer);
2225 up->timer.function = serial8250_timeout;
2226 if (is_real_interrupt(up->port.irq))
2227 serial_unlink_irq_chain(up);
2228}
2229
2230static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2231{
2232 unsigned int quot;
2233
2234 /*
2235 * Handle magic divisors for baud rates above baud_base on
2236 * SMSC SuperIO chips.
2237 */
2238 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2239 baud == (port->uartclk/4))
2240 quot = 0x8001;
2241 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2242 baud == (port->uartclk/8))
2243 quot = 0x8002;
2244 else
2245 quot = uart_get_divisor(port, baud);
2246
2247 return quot;
2248}
2249
2250void
2251serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2252 struct ktermios *old)
2253{
2254 struct uart_8250_port *up =
2255 container_of(port, struct uart_8250_port, port);
2256 unsigned char cval, fcr = 0;
2257 unsigned long flags;
2258 unsigned int baud, quot;
2259
2260 switch (termios->c_cflag & CSIZE) {
2261 case CS5:
2262 cval = UART_LCR_WLEN5;
2263 break;
2264 case CS6:
2265 cval = UART_LCR_WLEN6;
2266 break;
2267 case CS7:
2268 cval = UART_LCR_WLEN7;
2269 break;
2270 default:
2271 case CS8:
2272 cval = UART_LCR_WLEN8;
2273 break;
2274 }
2275
2276 if (termios->c_cflag & CSTOPB)
2277 cval |= UART_LCR_STOP;
2278 if (termios->c_cflag & PARENB)
2279 cval |= UART_LCR_PARITY;
2280 if (!(termios->c_cflag & PARODD))
2281 cval |= UART_LCR_EPAR;
2282#ifdef CMSPAR
2283 if (termios->c_cflag & CMSPAR)
2284 cval |= UART_LCR_SPAR;
2285#endif
2286
2287 /*
2288 * Ask the core to calculate the divisor for us.
2289 */
2290 baud = uart_get_baud_rate(port, termios, old,
2291 port->uartclk / 16 / 0xffff,
2292 port->uartclk / 16);
2293 quot = serial8250_get_divisor(port, baud);
2294
2295 /*
2296 * Oxford Semi 952 rev B workaround
2297 */
2298 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2299 quot++;
2300
2301 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2302 if (baud < 2400)
2303 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2304 else
2305 fcr = uart_config[up->port.type].fcr;
2306 }
2307
2308 /*
2309 * MCR-based auto flow control. When AFE is enabled, RTS will be
2310 * deasserted when the receive FIFO contains more characters than
2311 * the trigger, or the MCR RTS bit is cleared. In the case where
2312 * the remote UART is not using CTS auto flow control, we must
2313 * have sufficient FIFO entries for the latency of the remote
2314 * UART to respond. IOW, at least 32 bytes of FIFO.
2315 */
2316 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2317 up->mcr &= ~UART_MCR_AFE;
2318 if (termios->c_cflag & CRTSCTS)
2319 up->mcr |= UART_MCR_AFE;
2320 }
2321
2322 /*
2323 * Ok, we're now changing the port state. Do it with
2324 * interrupts disabled.
2325 */
2326 spin_lock_irqsave(&up->port.lock, flags);
2327
2328 /*
2329 * Update the per-port timeout.
2330 */
2331 uart_update_timeout(port, termios->c_cflag, baud);
2332
2333 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2334 if (termios->c_iflag & INPCK)
2335 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2336 if (termios->c_iflag & (BRKINT | PARMRK))
2337 up->port.read_status_mask |= UART_LSR_BI;
2338
2339 /*
2340 * Characteres to ignore
2341 */
2342 up->port.ignore_status_mask = 0;
2343 if (termios->c_iflag & IGNPAR)
2344 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2345 if (termios->c_iflag & IGNBRK) {
2346 up->port.ignore_status_mask |= UART_LSR_BI;
2347 /*
2348 * If we're ignoring parity and break indicators,
2349 * ignore overruns too (for real raw support).
2350 */
2351 if (termios->c_iflag & IGNPAR)
2352 up->port.ignore_status_mask |= UART_LSR_OE;
2353 }
2354
2355 /*
2356 * ignore all characters if CREAD is not set
2357 */
2358 if ((termios->c_cflag & CREAD) == 0)
2359 up->port.ignore_status_mask |= UART_LSR_DR;
2360
2361 /*
2362 * CTS flow control flag and modem status interrupts
2363 */
2364 up->ier &= ~UART_IER_MSI;
2365 if (!(up->bugs & UART_BUG_NOMSR) &&
2366 UART_ENABLE_MS(&up->port, termios->c_cflag))
2367 up->ier |= UART_IER_MSI;
2368 if (up->capabilities & UART_CAP_UUE)
2369 up->ier |= UART_IER_UUE;
2370 if (up->capabilities & UART_CAP_RTOIE)
2371 up->ier |= UART_IER_RTOIE;
2372
2373 serial_out(up, UART_IER, up->ier);
2374
2375 if (up->capabilities & UART_CAP_EFR) {
2376 unsigned char efr = 0;
2377 /*
2378 * TI16C752/Startech hardware flow control. FIXME:
2379 * - TI16C752 requires control thresholds to be set.
2380 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2381 */
2382 if (termios->c_cflag & CRTSCTS)
2383 efr |= UART_EFR_CTS;
2384
2385 serial_outp(up, UART_LCR, UART_LCR_CONF_MODE_B);
2386 if (up->port.flags & UPF_EXAR_EFR)
2387 serial_outp(up, UART_XR_EFR, efr);
2388 else
2389 serial_outp(up, UART_EFR, efr);
2390 }
2391
2392#ifdef CONFIG_ARCH_OMAP
2393 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2394 if (cpu_is_omap1510() && is_omap_port(up)) {
2395 if (baud == 115200) {
2396 quot = 1;
2397 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2398 } else
2399 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2400 }
2401#endif
2402
2403 if (up->capabilities & UART_NATSEMI) {
2404 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2405 serial_outp(up, UART_LCR, 0xe0);
2406 } else {
2407 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2408 }
2409
2410 serial_dl_write(up, quot);
2411
2412 /*
2413 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2414 * is written without DLAB set, this mode will be disabled.
2415 */
2416 if (up->port.type == PORT_16750)
2417 serial_outp(up, UART_FCR, fcr);
2418
2419 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2420 up->lcr = cval; /* Save LCR */
2421 if (up->port.type != PORT_16750) {
2422 if (fcr & UART_FCR_ENABLE_FIFO) {
2423 /* emulated UARTs (Lucent Venus 167x) need two steps */
2424 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2425 }
2426 serial_outp(up, UART_FCR, fcr); /* set fcr */
2427 }
2428 serial8250_set_mctrl(&up->port, up->port.mctrl);
2429 spin_unlock_irqrestore(&up->port.lock, flags);
2430 /* Don't rewrite B0 */
2431 if (tty_termios_baud_rate(termios))
2432 tty_termios_encode_baud_rate(termios, baud, baud);
2433}
2434EXPORT_SYMBOL(serial8250_do_set_termios);
2435
2436static void
2437serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2438 struct ktermios *old)
2439{
2440 if (port->set_termios)
2441 port->set_termios(port, termios, old);
2442 else
2443 serial8250_do_set_termios(port, termios, old);
2444}
2445
2446static void
2447serial8250_set_ldisc(struct uart_port *port, int new)
2448{
2449 if (new == N_PPS) {
2450 port->flags |= UPF_HARDPPS_CD;
2451 serial8250_enable_ms(port);
2452 } else
2453 port->flags &= ~UPF_HARDPPS_CD;
2454}
2455
2456
2457void serial8250_do_pm(struct uart_port *port, unsigned int state,
2458 unsigned int oldstate)
2459{
2460 struct uart_8250_port *p =
2461 container_of(port, struct uart_8250_port, port);
2462
2463 serial8250_set_sleep(p, state != 0);
2464}
2465EXPORT_SYMBOL(serial8250_do_pm);
2466
2467static void
2468serial8250_pm(struct uart_port *port, unsigned int state,
2469 unsigned int oldstate)
2470{
2471 if (port->pm)
2472 port->pm(port, state, oldstate);
2473 else
2474 serial8250_do_pm(port, state, oldstate);
2475}
2476
2477static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2478{
2479 if (pt->port.iotype == UPIO_AU)
2480 return 0x1000;
2481#ifdef CONFIG_ARCH_OMAP
2482 if (is_omap_port(pt))
2483 return 0x16 << pt->port.regshift;
2484#endif
2485 return 8 << pt->port.regshift;
2486}
2487
2488/*
2489 * Resource handling.
2490 */
2491static int serial8250_request_std_resource(struct uart_8250_port *up)
2492{
2493 unsigned int size = serial8250_port_size(up);
2494 int ret = 0;
2495
2496 switch (up->port.iotype) {
2497 case UPIO_AU:
2498 case UPIO_TSI:
2499 case UPIO_MEM32:
2500 case UPIO_MEM:
2501 if (!up->port.mapbase)
2502 break;
2503
2504 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2505 ret = -EBUSY;
2506 break;
2507 }
2508
2509 if (up->port.flags & UPF_IOREMAP) {
2510 up->port.membase = ioremap_nocache(up->port.mapbase,
2511 size);
2512 if (!up->port.membase) {
2513 release_mem_region(up->port.mapbase, size);
2514 ret = -ENOMEM;
2515 }
2516 }
2517 break;
2518
2519 case UPIO_HUB6:
2520 case UPIO_PORT:
2521 if (!request_region(up->port.iobase, size, "serial"))
2522 ret = -EBUSY;
2523 break;
2524 }
2525 return ret;
2526}
2527
2528static void serial8250_release_std_resource(struct uart_8250_port *up)
2529{
2530 unsigned int size = serial8250_port_size(up);
2531
2532 switch (up->port.iotype) {
2533 case UPIO_AU:
2534 case UPIO_TSI:
2535 case UPIO_MEM32:
2536 case UPIO_MEM:
2537 if (!up->port.mapbase)
2538 break;
2539
2540 if (up->port.flags & UPF_IOREMAP) {
2541 iounmap(up->port.membase);
2542 up->port.membase = NULL;
2543 }
2544
2545 release_mem_region(up->port.mapbase, size);
2546 break;
2547
2548 case UPIO_HUB6:
2549 case UPIO_PORT:
2550 release_region(up->port.iobase, size);
2551 break;
2552 }
2553}
2554
2555static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2556{
2557 unsigned long start = UART_RSA_BASE << up->port.regshift;
2558 unsigned int size = 8 << up->port.regshift;
2559 int ret = -EINVAL;
2560
2561 switch (up->port.iotype) {
2562 case UPIO_HUB6:
2563 case UPIO_PORT:
2564 start += up->port.iobase;
2565 if (request_region(start, size, "serial-rsa"))
2566 ret = 0;
2567 else
2568 ret = -EBUSY;
2569 break;
2570 }
2571
2572 return ret;
2573}
2574
2575static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2576{
2577 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2578 unsigned int size = 8 << up->port.regshift;
2579
2580 switch (up->port.iotype) {
2581 case UPIO_HUB6:
2582 case UPIO_PORT:
2583 release_region(up->port.iobase + offset, size);
2584 break;
2585 }
2586}
2587
2588static void serial8250_release_port(struct uart_port *port)
2589{
2590 struct uart_8250_port *up =
2591 container_of(port, struct uart_8250_port, port);
2592
2593 serial8250_release_std_resource(up);
2594 if (up->port.type == PORT_RSA)
2595 serial8250_release_rsa_resource(up);
2596}
2597
2598static int serial8250_request_port(struct uart_port *port)
2599{
2600 struct uart_8250_port *up =
2601 container_of(port, struct uart_8250_port, port);
2602 int ret = 0;
2603
2604 ret = serial8250_request_std_resource(up);
2605 if (ret == 0 && up->port.type == PORT_RSA) {
2606 ret = serial8250_request_rsa_resource(up);
2607 if (ret < 0)
2608 serial8250_release_std_resource(up);
2609 }
2610
2611 return ret;
2612}
2613
2614static void serial8250_config_port(struct uart_port *port, int flags)
2615{
2616 struct uart_8250_port *up =
2617 container_of(port, struct uart_8250_port, port);
2618 int probeflags = PROBE_ANY;
2619 int ret;
2620
2621 /*
2622 * Find the region that we can probe for. This in turn
2623 * tells us whether we can probe for the type of port.
2624 */
2625 ret = serial8250_request_std_resource(up);
2626 if (ret < 0)
2627 return;
2628
2629 ret = serial8250_request_rsa_resource(up);
2630 if (ret < 0)
2631 probeflags &= ~PROBE_RSA;
2632
2633 if (up->port.iotype != up->cur_iotype)
2634 set_io_from_upio(port);
2635
2636 if (flags & UART_CONFIG_TYPE)
2637 autoconfig(up, probeflags);
2638
2639 /* if access method is AU, it is a 16550 with a quirk */
2640 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
2641 up->bugs |= UART_BUG_NOMSR;
2642
2643 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2644 autoconfig_irq(up);
2645
2646 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2647 serial8250_release_rsa_resource(up);
2648 if (up->port.type == PORT_UNKNOWN)
2649 serial8250_release_std_resource(up);
2650}
2651
2652static int
2653serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2654{
2655 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2656 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2657 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2658 ser->type == PORT_STARTECH)
2659 return -EINVAL;
2660 return 0;
2661}
2662
2663static const char *
2664serial8250_type(struct uart_port *port)
2665{
2666 int type = port->type;
2667
2668 if (type >= ARRAY_SIZE(uart_config))
2669 type = 0;
2670 return uart_config[type].name;
2671}
2672
2673static struct uart_ops serial8250_pops = {
2674 .tx_empty = serial8250_tx_empty,
2675 .set_mctrl = serial8250_set_mctrl,
2676 .get_mctrl = serial8250_get_mctrl,
2677 .stop_tx = serial8250_stop_tx,
2678 .start_tx = serial8250_start_tx,
2679 .stop_rx = serial8250_stop_rx,
2680 .enable_ms = serial8250_enable_ms,
2681 .break_ctl = serial8250_break_ctl,
2682 .startup = serial8250_startup,
2683 .shutdown = serial8250_shutdown,
2684 .set_termios = serial8250_set_termios,
2685 .set_ldisc = serial8250_set_ldisc,
2686 .pm = serial8250_pm,
2687 .type = serial8250_type,
2688 .release_port = serial8250_release_port,
2689 .request_port = serial8250_request_port,
2690 .config_port = serial8250_config_port,
2691 .verify_port = serial8250_verify_port,
2692#ifdef CONFIG_CONSOLE_POLL
2693 .poll_get_char = serial8250_get_poll_char,
2694 .poll_put_char = serial8250_put_poll_char,
2695#endif
2696};
2697
2698static struct uart_8250_port serial8250_ports[UART_NR];
2699
2700static void (*serial8250_isa_config)(int port, struct uart_port *up,
2701 unsigned short *capabilities);
2702
2703void serial8250_set_isa_configurator(
2704 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2705{
2706 serial8250_isa_config = v;
2707}
2708EXPORT_SYMBOL(serial8250_set_isa_configurator);
2709
2710static void __init serial8250_isa_init_ports(void)
2711{
2712 struct uart_8250_port *up;
2713 static int first = 1;
2714 int i, irqflag = 0;
2715
2716 if (!first)
2717 return;
2718 first = 0;
2719
2720 for (i = 0; i < nr_uarts; i++) {
2721 struct uart_8250_port *up = &serial8250_ports[i];
2722
2723 up->port.line = i;
2724 spin_lock_init(&up->port.lock);
2725
2726 init_timer(&up->timer);
2727 up->timer.function = serial8250_timeout;
2728
2729 /*
2730 * ALPHA_KLUDGE_MCR needs to be killed.
2731 */
2732 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2733 up->mcr_force = ALPHA_KLUDGE_MCR;
2734
2735 up->port.ops = &serial8250_pops;
2736 }
2737
2738 if (share_irqs)
2739 irqflag = IRQF_SHARED;
2740
2741 for (i = 0, up = serial8250_ports;
2742 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2743 i++, up++) {
2744 up->port.iobase = old_serial_port[i].port;
2745 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2746 up->port.irqflags = old_serial_port[i].irqflags;
2747 up->port.uartclk = old_serial_port[i].baud_base * 16;
2748 up->port.flags = old_serial_port[i].flags;
2749 up->port.hub6 = old_serial_port[i].hub6;
2750 up->port.membase = old_serial_port[i].iomem_base;
2751 up->port.iotype = old_serial_port[i].io_type;
2752 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2753 set_io_from_upio(&up->port);
2754 up->port.irqflags |= irqflag;
2755 if (serial8250_isa_config != NULL)
2756 serial8250_isa_config(i, &up->port, &up->capabilities);
2757
2758 }
2759}
2760
2761static void
2762serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2763{
2764 up->port.type = type;
2765 up->port.fifosize = uart_config[type].fifo_size;
2766 up->capabilities = uart_config[type].flags;
2767 up->tx_loadsz = uart_config[type].tx_loadsz;
2768}
2769
2770static void __init
2771serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2772{
2773 int i;
2774
2775 for (i = 0; i < nr_uarts; i++) {
2776 struct uart_8250_port *up = &serial8250_ports[i];
2777 up->cur_iotype = 0xFF;
2778 }
2779
2780 serial8250_isa_init_ports();
2781
2782 for (i = 0; i < nr_uarts; i++) {
2783 struct uart_8250_port *up = &serial8250_ports[i];
2784
2785 up->port.dev = dev;
2786
2787 if (up->port.flags & UPF_FIXED_TYPE)
2788 serial8250_init_fixed_type_port(up, up->port.type);
2789
2790 uart_add_one_port(drv, &up->port);
2791 }
2792}
2793
2794#ifdef CONFIG_SERIAL_8250_CONSOLE
2795
2796static void serial8250_console_putchar(struct uart_port *port, int ch)
2797{
2798 struct uart_8250_port *up =
2799 container_of(port, struct uart_8250_port, port);
2800
2801 wait_for_xmitr(up, UART_LSR_THRE);
2802 serial_out(up, UART_TX, ch);
2803}
2804
2805/*
2806 * Print a string to the serial port trying not to disturb
2807 * any possible real use of the port...
2808 *
2809 * The console_lock must be held when we get here.
2810 */
2811static void
2812serial8250_console_write(struct console *co, const char *s, unsigned int count)
2813{
2814 struct uart_8250_port *up = &serial8250_ports[co->index];
2815 unsigned long flags;
2816 unsigned int ier;
2817 int locked = 1;
2818
2819 touch_nmi_watchdog();
2820
2821 local_irq_save(flags);
2822 if (up->port.sysrq) {
2823 /* serial8250_handle_irq() already took the lock */
2824 locked = 0;
2825 } else if (oops_in_progress) {
2826 locked = spin_trylock(&up->port.lock);
2827 } else
2828 spin_lock(&up->port.lock);
2829
2830 /*
2831 * First save the IER then disable the interrupts
2832 */
2833 ier = serial_in(up, UART_IER);
2834
2835 if (up->capabilities & UART_CAP_UUE)
2836 serial_out(up, UART_IER, UART_IER_UUE);
2837 else
2838 serial_out(up, UART_IER, 0);
2839
2840 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2841
2842 /*
2843 * Finally, wait for transmitter to become empty
2844 * and restore the IER
2845 */
2846 wait_for_xmitr(up, BOTH_EMPTY);
2847 serial_out(up, UART_IER, ier);
2848
2849 /*
2850 * The receive handling will happen properly because the
2851 * receive ready bit will still be set; it is not cleared
2852 * on read. However, modem control will not, we must
2853 * call it if we have saved something in the saved flags
2854 * while processing with interrupts off.
2855 */
2856 if (up->msr_saved_flags)
2857 serial8250_modem_status(up);
2858
2859 if (locked)
2860 spin_unlock(&up->port.lock);
2861 local_irq_restore(flags);
2862}
2863
2864static int __init serial8250_console_setup(struct console *co, char *options)
2865{
2866 struct uart_port *port;
2867 int baud = 9600;
2868 int bits = 8;
2869 int parity = 'n';
2870 int flow = 'n';
2871
2872 /*
2873 * Check whether an invalid uart number has been specified, and
2874 * if so, search for the first available port that does have
2875 * console support.
2876 */
2877 if (co->index >= nr_uarts)
2878 co->index = 0;
2879 port = &serial8250_ports[co->index].port;
2880 if (!port->iobase && !port->membase)
2881 return -ENODEV;
2882
2883 if (options)
2884 uart_parse_options(options, &baud, &parity, &bits, &flow);
2885
2886 return uart_set_options(port, co, baud, parity, bits, flow);
2887}
2888
2889static int serial8250_console_early_setup(void)
2890{
2891 return serial8250_find_port_for_earlycon();
2892}
2893
2894static struct console serial8250_console = {
2895 .name = "ttyS",
2896 .write = serial8250_console_write,
2897 .device = uart_console_device,
2898 .setup = serial8250_console_setup,
2899 .early_setup = serial8250_console_early_setup,
2900 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2901 .index = -1,
2902 .data = &serial8250_reg,
2903};
2904
2905static int __init serial8250_console_init(void)
2906{
2907 if (nr_uarts > UART_NR)
2908 nr_uarts = UART_NR;
2909
2910 serial8250_isa_init_ports();
2911 register_console(&serial8250_console);
2912 return 0;
2913}
2914console_initcall(serial8250_console_init);
2915
2916int serial8250_find_port(struct uart_port *p)
2917{
2918 int line;
2919 struct uart_port *port;
2920
2921 for (line = 0; line < nr_uarts; line++) {
2922 port = &serial8250_ports[line].port;
2923 if (uart_match_port(p, port))
2924 return line;
2925 }
2926 return -ENODEV;
2927}
2928
2929#define SERIAL8250_CONSOLE &serial8250_console
2930#else
2931#define SERIAL8250_CONSOLE NULL
2932#endif
2933
2934static struct uart_driver serial8250_reg = {
2935 .owner = THIS_MODULE,
2936 .driver_name = "serial",
2937 .dev_name = "ttyS",
2938 .major = TTY_MAJOR,
2939 .minor = 64,
2940 .cons = SERIAL8250_CONSOLE,
2941};
2942
2943/*
2944 * early_serial_setup - early registration for 8250 ports
2945 *
2946 * Setup an 8250 port structure prior to console initialisation. Use
2947 * after console initialisation will cause undefined behaviour.
2948 */
2949int __init early_serial_setup(struct uart_port *port)
2950{
2951 struct uart_port *p;
2952
2953 if (port->line >= ARRAY_SIZE(serial8250_ports))
2954 return -ENODEV;
2955
2956 serial8250_isa_init_ports();
2957 p = &serial8250_ports[port->line].port;
2958 p->iobase = port->iobase;
2959 p->membase = port->membase;
2960 p->irq = port->irq;
2961 p->irqflags = port->irqflags;
2962 p->uartclk = port->uartclk;
2963 p->fifosize = port->fifosize;
2964 p->regshift = port->regshift;
2965 p->iotype = port->iotype;
2966 p->flags = port->flags;
2967 p->mapbase = port->mapbase;
2968 p->private_data = port->private_data;
2969 p->type = port->type;
2970 p->line = port->line;
2971
2972 set_io_from_upio(p);
2973 if (port->serial_in)
2974 p->serial_in = port->serial_in;
2975 if (port->serial_out)
2976 p->serial_out = port->serial_out;
2977 if (port->handle_irq)
2978 p->handle_irq = port->handle_irq;
2979 else
2980 p->handle_irq = serial8250_default_handle_irq;
2981
2982 return 0;
2983}
2984
2985/**
2986 * serial8250_suspend_port - suspend one serial port
2987 * @line: serial line number
2988 *
2989 * Suspend one serial port.
2990 */
2991void serial8250_suspend_port(int line)
2992{
2993 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2994}
2995
2996/**
2997 * serial8250_resume_port - resume one serial port
2998 * @line: serial line number
2999 *
3000 * Resume one serial port.
3001 */
3002void serial8250_resume_port(int line)
3003{
3004 struct uart_8250_port *up = &serial8250_ports[line];
3005
3006 if (up->capabilities & UART_NATSEMI) {
3007 /* Ensure it's still in high speed mode */
3008 serial_outp(up, UART_LCR, 0xE0);
3009
3010 ns16550a_goto_highspeed(up);
3011
3012 serial_outp(up, UART_LCR, 0);
3013 up->port.uartclk = 921600*16;
3014 }
3015 uart_resume_port(&serial8250_reg, &up->port);
3016}
3017
3018/*
3019 * Register a set of serial devices attached to a platform device. The
3020 * list is terminated with a zero flags entry, which means we expect
3021 * all entries to have at least UPF_BOOT_AUTOCONF set.
3022 */
3023static int __devinit serial8250_probe(struct platform_device *dev)
3024{
3025 struct plat_serial8250_port *p = dev->dev.platform_data;
3026 struct uart_port port;
3027 int ret, i, irqflag = 0;
3028
3029 memset(&port, 0, sizeof(struct uart_port));
3030
3031 if (share_irqs)
3032 irqflag = IRQF_SHARED;
3033
3034 for (i = 0; p && p->flags != 0; p++, i++) {
3035 port.iobase = p->iobase;
3036 port.membase = p->membase;
3037 port.irq = p->irq;
3038 port.irqflags = p->irqflags;
3039 port.uartclk = p->uartclk;
3040 port.regshift = p->regshift;
3041 port.iotype = p->iotype;
3042 port.flags = p->flags;
3043 port.mapbase = p->mapbase;
3044 port.hub6 = p->hub6;
3045 port.private_data = p->private_data;
3046 port.type = p->type;
3047 port.serial_in = p->serial_in;
3048 port.serial_out = p->serial_out;
3049 port.handle_irq = p->handle_irq;
3050 port.set_termios = p->set_termios;
3051 port.pm = p->pm;
3052 port.dev = &dev->dev;
3053 port.irqflags |= irqflag;
3054 ret = serial8250_register_port(&port);
3055 if (ret < 0) {
3056 dev_err(&dev->dev, "unable to register port at index %d "
3057 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3058 p->iobase, (unsigned long long)p->mapbase,
3059 p->irq, ret);
3060 }
3061 }
3062 return 0;
3063}
3064
3065/*
3066 * Remove serial ports registered against a platform device.
3067 */
3068static int __devexit serial8250_remove(struct platform_device *dev)
3069{
3070 int i;
3071
3072 for (i = 0; i < nr_uarts; i++) {
3073 struct uart_8250_port *up = &serial8250_ports[i];
3074
3075 if (up->port.dev == &dev->dev)
3076 serial8250_unregister_port(i);
3077 }
3078 return 0;
3079}
3080
3081static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3082{
3083 int i;
3084
3085 for (i = 0; i < UART_NR; i++) {
3086 struct uart_8250_port *up = &serial8250_ports[i];
3087
3088 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3089 uart_suspend_port(&serial8250_reg, &up->port);
3090 }
3091
3092 return 0;
3093}
3094
3095static int serial8250_resume(struct platform_device *dev)
3096{
3097 int i;
3098
3099 for (i = 0; i < UART_NR; i++) {
3100 struct uart_8250_port *up = &serial8250_ports[i];
3101
3102 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3103 serial8250_resume_port(i);
3104 }
3105
3106 return 0;
3107}
3108
3109static struct platform_driver serial8250_isa_driver = {
3110 .probe = serial8250_probe,
3111 .remove = __devexit_p(serial8250_remove),
3112 .suspend = serial8250_suspend,
3113 .resume = serial8250_resume,
3114 .driver = {
3115 .name = "serial8250",
3116 .owner = THIS_MODULE,
3117 },
3118};
3119
3120/*
3121 * This "device" covers _all_ ISA 8250-compatible serial devices listed
3122 * in the table in include/asm/serial.h
3123 */
3124static struct platform_device *serial8250_isa_devs;
3125
3126/*
3127 * serial8250_register_port and serial8250_unregister_port allows for
3128 * 16x50 serial ports to be configured at run-time, to support PCMCIA
3129 * modems and PCI multiport cards.
3130 */
3131static DEFINE_MUTEX(serial_mutex);
3132
3133static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3134{
3135 int i;
3136
3137 /*
3138 * First, find a port entry which matches.
3139 */
3140 for (i = 0; i < nr_uarts; i++)
3141 if (uart_match_port(&serial8250_ports[i].port, port))
3142 return &serial8250_ports[i];
3143
3144 /*
3145 * We didn't find a matching entry, so look for the first
3146 * free entry. We look for one which hasn't been previously
3147 * used (indicated by zero iobase).
3148 */
3149 for (i = 0; i < nr_uarts; i++)
3150 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3151 serial8250_ports[i].port.iobase == 0)
3152 return &serial8250_ports[i];
3153
3154 /*
3155 * That also failed. Last resort is to find any entry which
3156 * doesn't have a real port associated with it.
3157 */
3158 for (i = 0; i < nr_uarts; i++)
3159 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3160 return &serial8250_ports[i];
3161
3162 return NULL;
3163}
3164
3165/**
3166 * serial8250_register_port - register a serial port
3167 * @port: serial port template
3168 *
3169 * Configure the serial port specified by the request. If the
3170 * port exists and is in use, it is hung up and unregistered
3171 * first.
3172 *
3173 * The port is then probed and if necessary the IRQ is autodetected
3174 * If this fails an error is returned.
3175 *
3176 * On success the port is ready to use and the line number is returned.
3177 */
3178int serial8250_register_port(struct uart_port *port)
3179{
3180 struct uart_8250_port *uart;
3181 int ret = -ENOSPC;
3182
3183 if (port->uartclk == 0)
3184 return -EINVAL;
3185
3186 mutex_lock(&serial_mutex);
3187
3188 uart = serial8250_find_match_or_unused(port);
3189 if (uart) {
3190 uart_remove_one_port(&serial8250_reg, &uart->port);
3191
3192 uart->port.iobase = port->iobase;
3193 uart->port.membase = port->membase;
3194 uart->port.irq = port->irq;
3195 uart->port.irqflags = port->irqflags;
3196 uart->port.uartclk = port->uartclk;
3197 uart->port.fifosize = port->fifosize;
3198 uart->port.regshift = port->regshift;
3199 uart->port.iotype = port->iotype;
3200 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
3201 uart->port.mapbase = port->mapbase;
3202 uart->port.private_data = port->private_data;
3203 if (port->dev)
3204 uart->port.dev = port->dev;
3205
3206 if (port->flags & UPF_FIXED_TYPE)
3207 serial8250_init_fixed_type_port(uart, port->type);
3208
3209 set_io_from_upio(&uart->port);
3210 /* Possibly override default I/O functions. */
3211 if (port->serial_in)
3212 uart->port.serial_in = port->serial_in;
3213 if (port->serial_out)
3214 uart->port.serial_out = port->serial_out;
3215 if (port->handle_irq)
3216 uart->port.handle_irq = port->handle_irq;
3217 /* Possibly override set_termios call */
3218 if (port->set_termios)
3219 uart->port.set_termios = port->set_termios;
3220 if (port->pm)
3221 uart->port.pm = port->pm;
3222
3223 if (serial8250_isa_config != NULL)
3224 serial8250_isa_config(0, &uart->port,
3225 &uart->capabilities);
3226
3227 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3228 if (ret == 0)
3229 ret = uart->port.line;
3230 }
3231 mutex_unlock(&serial_mutex);
3232
3233 return ret;
3234}
3235EXPORT_SYMBOL(serial8250_register_port);
3236
3237/**
3238 * serial8250_unregister_port - remove a 16x50 serial port at runtime
3239 * @line: serial line number
3240 *
3241 * Remove one serial port. This may not be called from interrupt
3242 * context. We hand the port back to the our control.
3243 */
3244void serial8250_unregister_port(int line)
3245{
3246 struct uart_8250_port *uart = &serial8250_ports[line];
3247
3248 mutex_lock(&serial_mutex);
3249 uart_remove_one_port(&serial8250_reg, &uart->port);
3250 if (serial8250_isa_devs) {
3251 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3252 uart->port.type = PORT_UNKNOWN;
3253 uart->port.dev = &serial8250_isa_devs->dev;
3254 uart->capabilities = uart_config[uart->port.type].flags;
3255 uart_add_one_port(&serial8250_reg, &uart->port);
3256 } else {
3257 uart->port.dev = NULL;
3258 }
3259 mutex_unlock(&serial_mutex);
3260}
3261EXPORT_SYMBOL(serial8250_unregister_port);
3262
3263static int __init serial8250_init(void)
3264{
3265 int ret;
3266
3267 if (nr_uarts > UART_NR)
3268 nr_uarts = UART_NR;
3269
3270 printk(KERN_INFO "Serial: 8250/16550 driver, "
3271 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3272 share_irqs ? "en" : "dis");
3273
3274#ifdef CONFIG_SPARC
3275 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3276#else
3277 serial8250_reg.nr = UART_NR;
3278 ret = uart_register_driver(&serial8250_reg);
3279#endif
3280 if (ret)
3281 goto out;
3282
3283 serial8250_isa_devs = platform_device_alloc("serial8250",
3284 PLAT8250_DEV_LEGACY);
3285 if (!serial8250_isa_devs) {
3286 ret = -ENOMEM;
3287 goto unreg_uart_drv;
3288 }
3289
3290 ret = platform_device_add(serial8250_isa_devs);
3291 if (ret)
3292 goto put_dev;
3293
3294 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3295
3296 ret = platform_driver_register(&serial8250_isa_driver);
3297 if (ret == 0)
3298 goto out;
3299
3300 platform_device_del(serial8250_isa_devs);
3301put_dev:
3302 platform_device_put(serial8250_isa_devs);
3303unreg_uart_drv:
3304#ifdef CONFIG_SPARC
3305 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3306#else
3307 uart_unregister_driver(&serial8250_reg);
3308#endif
3309out:
3310 return ret;
3311}
3312
3313static void __exit serial8250_exit(void)
3314{
3315 struct platform_device *isa_dev = serial8250_isa_devs;
3316
3317 /*
3318 * This tells serial8250_unregister_port() not to re-register
3319 * the ports (thereby making serial8250_isa_driver permanently
3320 * in use.)
3321 */
3322 serial8250_isa_devs = NULL;
3323
3324 platform_driver_unregister(&serial8250_isa_driver);
3325 platform_device_unregister(isa_dev);
3326
3327#ifdef CONFIG_SPARC
3328 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3329#else
3330 uart_unregister_driver(&serial8250_reg);
3331#endif
3332}
3333
3334module_init(serial8250_init);
3335module_exit(serial8250_exit);
3336
3337EXPORT_SYMBOL(serial8250_suspend_port);
3338EXPORT_SYMBOL(serial8250_resume_port);
3339
3340MODULE_LICENSE("GPL");
3341MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3342
3343module_param(share_irqs, uint, 0644);
3344MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3345 " (unsafe)");
3346
3347module_param(nr_uarts, uint, 0644);
3348MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3349
3350module_param(skip_txen_test, uint, 0644);
3351MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3352
3353#ifdef CONFIG_SERIAL_8250_RSA
3354module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3355MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3356#endif
3357MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-22 12:26:44 -0500