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Diffstat (limited to 'drivers/spi/xilinx_spi.c')
-rw-r--r--drivers/spi/xilinx_spi.c355
1 files changed, 171 insertions, 184 deletions
diff --git a/drivers/spi/xilinx_spi.c b/drivers/spi/xilinx_spi.c
index 5a143b9f6361..9f386379c169 100644
--- a/drivers/spi/xilinx_spi.c
+++ b/drivers/spi/xilinx_spi.c
@@ -14,22 +14,20 @@
14#include <linux/module.h> 14#include <linux/module.h>
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/interrupt.h> 16#include <linux/interrupt.h>
17#include <linux/platform_device.h>
18
19#include <linux/of_platform.h>
20#include <linux/of_device.h>
21#include <linux/of_spi.h>
22 17
23#include <linux/spi/spi.h> 18#include <linux/spi/spi.h>
24#include <linux/spi/spi_bitbang.h> 19#include <linux/spi/spi_bitbang.h>
25#include <linux/io.h> 20#include <linux/io.h>
26 21
22#include "xilinx_spi.h"
23#include <linux/spi/xilinx_spi.h>
24
27#define XILINX_SPI_NAME "xilinx_spi" 25#define XILINX_SPI_NAME "xilinx_spi"
28 26
29/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) 27/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
30 * Product Specification", DS464 28 * Product Specification", DS464
31 */ 29 */
32#define XSPI_CR_OFFSET 0x62 /* 16-bit Control Register */ 30#define XSPI_CR_OFFSET 0x60 /* Control Register */
33 31
34#define XSPI_CR_ENABLE 0x02 32#define XSPI_CR_ENABLE 0x02
35#define XSPI_CR_MASTER_MODE 0x04 33#define XSPI_CR_MASTER_MODE 0x04
@@ -40,8 +38,9 @@
40#define XSPI_CR_RXFIFO_RESET 0x40 38#define XSPI_CR_RXFIFO_RESET 0x40
41#define XSPI_CR_MANUAL_SSELECT 0x80 39#define XSPI_CR_MANUAL_SSELECT 0x80
42#define XSPI_CR_TRANS_INHIBIT 0x100 40#define XSPI_CR_TRANS_INHIBIT 0x100
41#define XSPI_CR_LSB_FIRST 0x200
43 42
44#define XSPI_SR_OFFSET 0x67 /* 8-bit Status Register */ 43#define XSPI_SR_OFFSET 0x64 /* Status Register */
45 44
46#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ 45#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
47#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ 46#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
@@ -49,8 +48,8 @@
49#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ 48#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
50#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ 49#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
51 50
52#define XSPI_TXD_OFFSET 0x6b /* 8-bit Data Transmit Register */ 51#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
53#define XSPI_RXD_OFFSET 0x6f /* 8-bit Data Receive Register */ 52#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
54 53
55#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ 54#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
56 55
@@ -70,6 +69,7 @@
70#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ 69#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
71#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ 70#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
72#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ 71#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
72#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
73 73
74#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ 74#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
75#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ 75#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
@@ -78,35 +78,85 @@ struct xilinx_spi {
78 /* bitbang has to be first */ 78 /* bitbang has to be first */
79 struct spi_bitbang bitbang; 79 struct spi_bitbang bitbang;
80 struct completion done; 80 struct completion done;
81 81 struct resource mem; /* phys mem */
82 void __iomem *regs; /* virt. address of the control registers */ 82 void __iomem *regs; /* virt. address of the control registers */
83 83
84 u32 irq; 84 u32 irq;
85 85
86 u32 speed_hz; /* SCK has a fixed frequency of speed_hz Hz */
87
88 u8 *rx_ptr; /* pointer in the Tx buffer */ 86 u8 *rx_ptr; /* pointer in the Tx buffer */
89 const u8 *tx_ptr; /* pointer in the Rx buffer */ 87 const u8 *tx_ptr; /* pointer in the Rx buffer */
90 int remaining_bytes; /* the number of bytes left to transfer */ 88 int remaining_bytes; /* the number of bytes left to transfer */
89 u8 bits_per_word;
90 unsigned int (*read_fn) (void __iomem *);
91 void (*write_fn) (u32, void __iomem *);
92 void (*tx_fn) (struct xilinx_spi *);
93 void (*rx_fn) (struct xilinx_spi *);
91}; 94};
92 95
93static void xspi_init_hw(void __iomem *regs_base) 96static void xspi_tx8(struct xilinx_spi *xspi)
97{
98 xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
99 xspi->tx_ptr++;
100}
101
102static void xspi_tx16(struct xilinx_spi *xspi)
103{
104 xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
105 xspi->tx_ptr += 2;
106}
107
108static void xspi_tx32(struct xilinx_spi *xspi)
109{
110 xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
111 xspi->tx_ptr += 4;
112}
113
114static void xspi_rx8(struct xilinx_spi *xspi)
115{
116 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
117 if (xspi->rx_ptr) {
118 *xspi->rx_ptr = data & 0xff;
119 xspi->rx_ptr++;
120 }
121}
122
123static void xspi_rx16(struct xilinx_spi *xspi)
94{ 124{
125 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
126 if (xspi->rx_ptr) {
127 *(u16 *)(xspi->rx_ptr) = data & 0xffff;
128 xspi->rx_ptr += 2;
129 }
130}
131
132static void xspi_rx32(struct xilinx_spi *xspi)
133{
134 u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
135 if (xspi->rx_ptr) {
136 *(u32 *)(xspi->rx_ptr) = data;
137 xspi->rx_ptr += 4;
138 }
139}
140
141static void xspi_init_hw(struct xilinx_spi *xspi)
142{
143 void __iomem *regs_base = xspi->regs;
144
95 /* Reset the SPI device */ 145 /* Reset the SPI device */
96 out_be32(regs_base + XIPIF_V123B_RESETR_OFFSET, 146 xspi->write_fn(XIPIF_V123B_RESET_MASK,
97 XIPIF_V123B_RESET_MASK); 147 regs_base + XIPIF_V123B_RESETR_OFFSET);
98 /* Disable all the interrupts just in case */ 148 /* Disable all the interrupts just in case */
99 out_be32(regs_base + XIPIF_V123B_IIER_OFFSET, 0); 149 xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
100 /* Enable the global IPIF interrupt */ 150 /* Enable the global IPIF interrupt */
101 out_be32(regs_base + XIPIF_V123B_DGIER_OFFSET, 151 xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
102 XIPIF_V123B_GINTR_ENABLE); 152 regs_base + XIPIF_V123B_DGIER_OFFSET);
103 /* Deselect the slave on the SPI bus */ 153 /* Deselect the slave on the SPI bus */
104 out_be32(regs_base + XSPI_SSR_OFFSET, 0xffff); 154 xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
105 /* Disable the transmitter, enable Manual Slave Select Assertion, 155 /* Disable the transmitter, enable Manual Slave Select Assertion,
106 * put SPI controller into master mode, and enable it */ 156 * put SPI controller into master mode, and enable it */
107 out_be16(regs_base + XSPI_CR_OFFSET, 157 xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
108 XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT 158 XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
109 | XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE); 159 XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
110} 160}
111 161
112static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) 162static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
@@ -115,16 +165,16 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
115 165
116 if (is_on == BITBANG_CS_INACTIVE) { 166 if (is_on == BITBANG_CS_INACTIVE) {
117 /* Deselect the slave on the SPI bus */ 167 /* Deselect the slave on the SPI bus */
118 out_be32(xspi->regs + XSPI_SSR_OFFSET, 0xffff); 168 xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
119 } else if (is_on == BITBANG_CS_ACTIVE) { 169 } else if (is_on == BITBANG_CS_ACTIVE) {
120 /* Set the SPI clock phase and polarity */ 170 /* Set the SPI clock phase and polarity */
121 u16 cr = in_be16(xspi->regs + XSPI_CR_OFFSET) 171 u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
122 & ~XSPI_CR_MODE_MASK; 172 & ~XSPI_CR_MODE_MASK;
123 if (spi->mode & SPI_CPHA) 173 if (spi->mode & SPI_CPHA)
124 cr |= XSPI_CR_CPHA; 174 cr |= XSPI_CR_CPHA;
125 if (spi->mode & SPI_CPOL) 175 if (spi->mode & SPI_CPOL)
126 cr |= XSPI_CR_CPOL; 176 cr |= XSPI_CR_CPOL;
127 out_be16(xspi->regs + XSPI_CR_OFFSET, cr); 177 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
128 178
129 /* We do not check spi->max_speed_hz here as the SPI clock 179 /* We do not check spi->max_speed_hz here as the SPI clock
130 * frequency is not software programmable (the IP block design 180 * frequency is not software programmable (the IP block design
@@ -132,25 +182,27 @@ static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
132 */ 182 */
133 183
134 /* Activate the chip select */ 184 /* Activate the chip select */
135 out_be32(xspi->regs + XSPI_SSR_OFFSET, 185 xspi->write_fn(~(0x0001 << spi->chip_select),
136 ~(0x0001 << spi->chip_select)); 186 xspi->regs + XSPI_SSR_OFFSET);
137 } 187 }
138} 188}
139 189
140/* spi_bitbang requires custom setup_transfer() to be defined if there is a 190/* spi_bitbang requires custom setup_transfer() to be defined if there is a
141 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block 191 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
142 * supports just 8 bits per word, and SPI clock can't be changed in software. 192 * supports 8 or 16 bits per word which cannot be changed in software.
143 * Check for 8 bits per word. Chip select delay calculations could be 193 * SPI clock can't be changed in software either.
194 * Check for correct bits per word. Chip select delay calculations could be
144 * added here as soon as bitbang_work() can be made aware of the delay value. 195 * added here as soon as bitbang_work() can be made aware of the delay value.
145 */ 196 */
146static int xilinx_spi_setup_transfer(struct spi_device *spi, 197static int xilinx_spi_setup_transfer(struct spi_device *spi,
147 struct spi_transfer *t) 198 struct spi_transfer *t)
148{ 199{
200 struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
149 u8 bits_per_word; 201 u8 bits_per_word;
150 202
151 bits_per_word = (t && t->bits_per_word) 203 bits_per_word = (t && t->bits_per_word)
152 ? t->bits_per_word : spi->bits_per_word; 204 ? t->bits_per_word : spi->bits_per_word;
153 if (bits_per_word != 8) { 205 if (bits_per_word != xspi->bits_per_word) {
154 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n", 206 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
155 __func__, bits_per_word); 207 __func__, bits_per_word);
156 return -EINVAL; 208 return -EINVAL;
@@ -161,17 +213,16 @@ static int xilinx_spi_setup_transfer(struct spi_device *spi,
161 213
162static int xilinx_spi_setup(struct spi_device *spi) 214static int xilinx_spi_setup(struct spi_device *spi)
163{ 215{
164 struct spi_bitbang *bitbang; 216 /* always return 0, we can not check the number of bits.
165 struct xilinx_spi *xspi; 217 * There are cases when SPI setup is called before any driver is
166 int retval; 218 * there, in that case the SPI core defaults to 8 bits, which we
167 219 * do not support in some cases. But if we return an error, the
168 xspi = spi_master_get_devdata(spi->master); 220 * SPI device would not be registered and no driver can get hold of it
169 bitbang = &xspi->bitbang; 221 * When the driver is there, it will call SPI setup again with the
170 222 * correct number of bits per transfer.
171 retval = xilinx_spi_setup_transfer(spi, NULL); 223 * If a driver setups with the wrong bit number, it will fail when
172 if (retval < 0) 224 * it tries to do a transfer
173 return retval; 225 */
174
175 return 0; 226 return 0;
176} 227}
177 228
@@ -180,15 +231,14 @@ static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
180 u8 sr; 231 u8 sr;
181 232
182 /* Fill the Tx FIFO with as many bytes as possible */ 233 /* Fill the Tx FIFO with as many bytes as possible */
183 sr = in_8(xspi->regs + XSPI_SR_OFFSET); 234 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
184 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) { 235 while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
185 if (xspi->tx_ptr) { 236 if (xspi->tx_ptr)
186 out_8(xspi->regs + XSPI_TXD_OFFSET, *xspi->tx_ptr++); 237 xspi->tx_fn(xspi);
187 } else { 238 else
188 out_8(xspi->regs + XSPI_TXD_OFFSET, 0); 239 xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
189 } 240 xspi->remaining_bytes -= xspi->bits_per_word / 8;
190 xspi->remaining_bytes--; 241 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
191 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
192 } 242 }
193} 243}
194 244
@@ -210,18 +260,19 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
210 /* Enable the transmit empty interrupt, which we use to determine 260 /* Enable the transmit empty interrupt, which we use to determine
211 * progress on the transmission. 261 * progress on the transmission.
212 */ 262 */
213 ipif_ier = in_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET); 263 ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
214 out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, 264 xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
215 ipif_ier | XSPI_INTR_TX_EMPTY); 265 xspi->regs + XIPIF_V123B_IIER_OFFSET);
216 266
217 /* Start the transfer by not inhibiting the transmitter any longer */ 267 /* Start the transfer by not inhibiting the transmitter any longer */
218 cr = in_be16(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_TRANS_INHIBIT; 268 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
219 out_be16(xspi->regs + XSPI_CR_OFFSET, cr); 269 ~XSPI_CR_TRANS_INHIBIT;
270 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
220 271
221 wait_for_completion(&xspi->done); 272 wait_for_completion(&xspi->done);
222 273
223 /* Disable the transmit empty interrupt */ 274 /* Disable the transmit empty interrupt */
224 out_be32(xspi->regs + XIPIF_V123B_IIER_OFFSET, ipif_ier); 275 xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
225 276
226 return t->len - xspi->remaining_bytes; 277 return t->len - xspi->remaining_bytes;
227} 278}
@@ -238,8 +289,8 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
238 u32 ipif_isr; 289 u32 ipif_isr;
239 290
240 /* Get the IPIF interrupts, and clear them immediately */ 291 /* Get the IPIF interrupts, and clear them immediately */
241 ipif_isr = in_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET); 292 ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
242 out_be32(xspi->regs + XIPIF_V123B_IISR_OFFSET, ipif_isr); 293 xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
243 294
244 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ 295 if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
245 u16 cr; 296 u16 cr;
@@ -250,20 +301,15 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
250 * transmitter while the Isr refills the transmit register/FIFO, 301 * transmitter while the Isr refills the transmit register/FIFO,
251 * or make sure it is stopped if we're done. 302 * or make sure it is stopped if we're done.
252 */ 303 */
253 cr = in_be16(xspi->regs + XSPI_CR_OFFSET); 304 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
254 out_be16(xspi->regs + XSPI_CR_OFFSET, 305 xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
255 cr | XSPI_CR_TRANS_INHIBIT); 306 xspi->regs + XSPI_CR_OFFSET);
256 307
257 /* Read out all the data from the Rx FIFO */ 308 /* Read out all the data from the Rx FIFO */
258 sr = in_8(xspi->regs + XSPI_SR_OFFSET); 309 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
259 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) { 310 while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
260 u8 data; 311 xspi->rx_fn(xspi);
261 312 sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
262 data = in_8(xspi->regs + XSPI_RXD_OFFSET);
263 if (xspi->rx_ptr) {
264 *xspi->rx_ptr++ = data;
265 }
266 sr = in_8(xspi->regs + XSPI_SR_OFFSET);
267 } 313 }
268 314
269 /* See if there is more data to send */ 315 /* See if there is more data to send */
@@ -272,7 +318,7 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
272 /* Start the transfer by not inhibiting the 318 /* Start the transfer by not inhibiting the
273 * transmitter any longer 319 * transmitter any longer
274 */ 320 */
275 out_be16(xspi->regs + XSPI_CR_OFFSET, cr); 321 xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
276 } else { 322 } else {
277 /* No more data to send. 323 /* No more data to send.
278 * Indicate the transfer is completed. 324 * Indicate the transfer is completed.
@@ -284,40 +330,22 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
284 return IRQ_HANDLED; 330 return IRQ_HANDLED;
285} 331}
286 332
287static int __init xilinx_spi_of_probe(struct of_device *ofdev, 333struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
288 const struct of_device_id *match) 334 u32 irq, s16 bus_num)
289{ 335{
290 struct spi_master *master; 336 struct spi_master *master;
291 struct xilinx_spi *xspi; 337 struct xilinx_spi *xspi;
292 struct resource r_irq_struct; 338 struct xspi_platform_data *pdata = dev->platform_data;
293 struct resource r_mem_struct; 339 int ret;
294
295 struct resource *r_irq = &r_irq_struct;
296 struct resource *r_mem = &r_mem_struct;
297 int rc = 0;
298 const u32 *prop;
299 int len;
300
301 /* Get resources(memory, IRQ) associated with the device */
302 master = spi_alloc_master(&ofdev->dev, sizeof(struct xilinx_spi));
303 340
304 if (master == NULL) { 341 if (!pdata) {
305 return -ENOMEM; 342 dev_err(dev, "No platform data attached\n");
343 return NULL;
306 } 344 }
307 345
308 dev_set_drvdata(&ofdev->dev, master); 346 master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
309 347 if (!master)
310 rc = of_address_to_resource(ofdev->node, 0, r_mem); 348 return NULL;
311 if (rc) {
312 dev_warn(&ofdev->dev, "invalid address\n");
313 goto put_master;
314 }
315
316 rc = of_irq_to_resource(ofdev->node, 0, r_irq);
317 if (rc == NO_IRQ) {
318 dev_warn(&ofdev->dev, "no IRQ found\n");
319 goto put_master;
320 }
321 349
322 /* the spi->mode bits understood by this driver: */ 350 /* the spi->mode bits understood by this driver: */
323 master->mode_bits = SPI_CPOL | SPI_CPHA; 351 master->mode_bits = SPI_CPOL | SPI_CPHA;
@@ -330,128 +358,87 @@ static int __init xilinx_spi_of_probe(struct of_device *ofdev,
330 xspi->bitbang.master->setup = xilinx_spi_setup; 358 xspi->bitbang.master->setup = xilinx_spi_setup;
331 init_completion(&xspi->done); 359 init_completion(&xspi->done);
332 360
333 xspi->irq = r_irq->start; 361 if (!request_mem_region(mem->start, resource_size(mem),
334 362 XILINX_SPI_NAME))
335 if (!request_mem_region(r_mem->start,
336 r_mem->end - r_mem->start + 1, XILINX_SPI_NAME)) {
337 rc = -ENXIO;
338 dev_warn(&ofdev->dev, "memory request failure\n");
339 goto put_master; 363 goto put_master;
340 }
341 364
342 xspi->regs = ioremap(r_mem->start, r_mem->end - r_mem->start + 1); 365 xspi->regs = ioremap(mem->start, resource_size(mem));
343 if (xspi->regs == NULL) { 366 if (xspi->regs == NULL) {
344 rc = -ENOMEM; 367 dev_warn(dev, "ioremap failure\n");
345 dev_warn(&ofdev->dev, "ioremap failure\n"); 368 goto map_failed;
346 goto release_mem;
347 } 369 }
348 xspi->irq = r_irq->start;
349
350 /* dynamic bus assignment */
351 master->bus_num = -1;
352 370
353 /* number of slave select bits is required */ 371 master->bus_num = bus_num;
354 prop = of_get_property(ofdev->node, "xlnx,num-ss-bits", &len); 372 master->num_chipselect = pdata->num_chipselect;
355 if (!prop || len < sizeof(*prop)) { 373
356 dev_warn(&ofdev->dev, "no 'xlnx,num-ss-bits' property\n"); 374 xspi->mem = *mem;
357 goto unmap_io; 375 xspi->irq = irq;
376 if (pdata->little_endian) {
377 xspi->read_fn = ioread32;
378 xspi->write_fn = iowrite32;
379 } else {
380 xspi->read_fn = ioread32be;
381 xspi->write_fn = iowrite32be;
358 } 382 }
359 master->num_chipselect = *prop; 383 xspi->bits_per_word = pdata->bits_per_word;
384 if (xspi->bits_per_word == 8) {
385 xspi->tx_fn = xspi_tx8;
386 xspi->rx_fn = xspi_rx8;
387 } else if (xspi->bits_per_word == 16) {
388 xspi->tx_fn = xspi_tx16;
389 xspi->rx_fn = xspi_rx16;
390 } else if (xspi->bits_per_word == 32) {
391 xspi->tx_fn = xspi_tx32;
392 xspi->rx_fn = xspi_rx32;
393 } else
394 goto unmap_io;
395
360 396
361 /* SPI controller initializations */ 397 /* SPI controller initializations */
362 xspi_init_hw(xspi->regs); 398 xspi_init_hw(xspi);
363 399
364 /* Register for SPI Interrupt */ 400 /* Register for SPI Interrupt */
365 rc = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi); 401 ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
366 if (rc != 0) { 402 if (ret)
367 dev_warn(&ofdev->dev, "irq request failure: %d\n", xspi->irq);
368 goto unmap_io; 403 goto unmap_io;
369 }
370 404
371 rc = spi_bitbang_start(&xspi->bitbang); 405 ret = spi_bitbang_start(&xspi->bitbang);
372 if (rc != 0) { 406 if (ret) {
373 dev_err(&ofdev->dev, "spi_bitbang_start FAILED\n"); 407 dev_err(dev, "spi_bitbang_start FAILED\n");
374 goto free_irq; 408 goto free_irq;
375 } 409 }
376 410
377 dev_info(&ofdev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n", 411 dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
378 (unsigned int)r_mem->start, (u32)xspi->regs, xspi->irq); 412 (unsigned long long)mem->start, xspi->regs, xspi->irq);
379 413 return master;
380 /* Add any subnodes on the SPI bus */
381 of_register_spi_devices(master, ofdev->node);
382
383 return rc;
384 414
385free_irq: 415free_irq:
386 free_irq(xspi->irq, xspi); 416 free_irq(xspi->irq, xspi);
387unmap_io: 417unmap_io:
388 iounmap(xspi->regs); 418 iounmap(xspi->regs);
389release_mem: 419map_failed:
390 release_mem_region(r_mem->start, resource_size(r_mem)); 420 release_mem_region(mem->start, resource_size(mem));
391put_master: 421put_master:
392 spi_master_put(master); 422 spi_master_put(master);
393 return rc; 423 return NULL;
394} 424}
425EXPORT_SYMBOL(xilinx_spi_init);
395 426
396static int __devexit xilinx_spi_remove(struct of_device *ofdev) 427void xilinx_spi_deinit(struct spi_master *master)
397{ 428{
398 struct xilinx_spi *xspi; 429 struct xilinx_spi *xspi;
399 struct spi_master *master;
400 struct resource r_mem;
401 430
402 master = platform_get_drvdata(ofdev);
403 xspi = spi_master_get_devdata(master); 431 xspi = spi_master_get_devdata(master);
404 432
405 spi_bitbang_stop(&xspi->bitbang); 433 spi_bitbang_stop(&xspi->bitbang);
406 free_irq(xspi->irq, xspi); 434 free_irq(xspi->irq, xspi);
407 iounmap(xspi->regs); 435 iounmap(xspi->regs);
408 if (!of_address_to_resource(ofdev->node, 0, &r_mem))
409 release_mem_region(r_mem.start, resource_size(&r_mem));
410 dev_set_drvdata(&ofdev->dev, 0);
411 spi_master_put(xspi->bitbang.master);
412
413 return 0;
414}
415
416/* work with hotplug and coldplug */
417MODULE_ALIAS("platform:" XILINX_SPI_NAME);
418
419static int __exit xilinx_spi_of_remove(struct of_device *op)
420{
421 return xilinx_spi_remove(op);
422}
423 436
424static struct of_device_id xilinx_spi_of_match[] = { 437 release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
425 { .compatible = "xlnx,xps-spi-2.00.a", }, 438 spi_master_put(xspi->bitbang.master);
426 { .compatible = "xlnx,xps-spi-2.00.b", },
427 {}
428};
429
430MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
431
432static struct of_platform_driver xilinx_spi_of_driver = {
433 .owner = THIS_MODULE,
434 .name = "xilinx-xps-spi",
435 .match_table = xilinx_spi_of_match,
436 .probe = xilinx_spi_of_probe,
437 .remove = __exit_p(xilinx_spi_of_remove),
438 .driver = {
439 .name = "xilinx-xps-spi",
440 .owner = THIS_MODULE,
441 },
442};
443
444static int __init xilinx_spi_init(void)
445{
446 return of_register_platform_driver(&xilinx_spi_of_driver);
447} 439}
448module_init(xilinx_spi_init); 440EXPORT_SYMBOL(xilinx_spi_deinit);
449 441
450static void __exit xilinx_spi_exit(void)
451{
452 of_unregister_platform_driver(&xilinx_spi_of_driver);
453}
454module_exit(xilinx_spi_exit);
455MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); 442MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
456MODULE_DESCRIPTION("Xilinx SPI driver"); 443MODULE_DESCRIPTION("Xilinx SPI driver");
457MODULE_LICENSE("GPL"); 444MODULE_LICENSE("GPL");