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-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2.h1164
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h3323
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_init.h560
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_ioc.h1665
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_raid.h346
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_sas.h295
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_tool.h437
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_type.h56
8 files changed, 7846 insertions, 0 deletions
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2.h b/drivers/scsi/mpt3sas/mpi/mpi2.h
new file mode 100644
index 000000000000..03317ffea62c
--- /dev/null
+++ b/drivers/scsi/mpt3sas/mpi/mpi2.h
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1/*
2 * Copyright (c) 2000-2012 LSI Corporation.
3 *
4 *
5 * Name: mpi2.h
6 * Title: MPI Message independent structures and definitions
7 * including System Interface Register Set and
8 * scatter/gather formats.
9 * Creation Date: June 21, 2006
10 *
11 * mpi2.h Version: 02.00.26
12 *
13 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
14 * prefix are for use only on MPI v2.5 products, and must not be used
15 * with MPI v2.0 products. Unless otherwise noted, names beginning with
16 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
17 *
18 * Version History
19 * ---------------
20 *
21 * Date Version Description
22 * -------- -------- ------------------------------------------------------
23 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
24 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT.
25 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT.
26 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT.
27 * Moved ReplyPostHostIndex register to offset 0x6C of the
28 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for
29 * MPI2_REPLY_POST_HOST_INDEX_OFFSET.
30 * Added union of request descriptors.
31 * Added union of reply descriptors.
32 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT.
33 * Added define for MPI2_VERSION_02_00.
34 * Fixed the size of the FunctionDependent5 field in the
35 * MPI2_DEFAULT_REPLY structure.
36 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT.
37 * Removed the MPI-defined Fault Codes and extended the
38 * product specific codes up to 0xEFFF.
39 * Added a sixth key value for the WriteSequence register
40 * and changed the flush value to 0x0.
41 * Added message function codes for Diagnostic Buffer Post
42 * and Diagnsotic Release.
43 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED
44 * Moved MPI2_VERSION_UNION from mpi2_ioc.h.
45 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT.
46 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT.
47 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT.
48 * Added #defines for marking a reply descriptor as unused.
49 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT.
50 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT.
51 * Moved LUN field defines from mpi2_init.h.
52 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT.
53 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT.
54 * In all request and reply descriptors, replaced VF_ID
55 * field with MSIxIndex field.
56 * Removed DevHandle field from
57 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those
58 * bytes reserved.
59 * Added RAID Accelerator functionality.
60 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT.
61 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT.
62 * Added MSI-x index mask and shift for Reply Post Host
63 * Index register.
64 * Added function code for Host Based Discovery Action.
65 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT.
66 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL.
67 * Added defines for product-specific range of message
68 * function codes, 0xF0 to 0xFF.
69 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT.
70 * Added alternative defines for the SGE Direction bit.
71 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT.
72 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT.
73 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define.
74 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT.
75 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE.
76 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT.
77 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT.
78 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT.
79 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT.
80 * Incorporating additions for MPI v2.5.
81 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT.
82 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT.
83 * Added Hard Reset delay timings.
84 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT.
85 * --------------------------------------------------------------------------
86 */
87
88#ifndef MPI2_H
89#define MPI2_H
90
91/*****************************************************************************
92*
93* MPI Version Definitions
94*
95*****************************************************************************/
96
97#define MPI2_VERSION_MAJOR_MASK (0xFF00)
98#define MPI2_VERSION_MAJOR_SHIFT (8)
99#define MPI2_VERSION_MINOR_MASK (0x00FF)
100#define MPI2_VERSION_MINOR_SHIFT (0)
101
102/*major version for all MPI v2.x */
103#define MPI2_VERSION_MAJOR (0x02)
104
105/*minor version for MPI v2.0 compatible products */
106#define MPI2_VERSION_MINOR (0x00)
107#define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
108 MPI2_VERSION_MINOR)
109#define MPI2_VERSION_02_00 (0x0200)
110
111/*minor version for MPI v2.5 compatible products */
112#define MPI25_VERSION_MINOR (0x05)
113#define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \
114 MPI25_VERSION_MINOR)
115#define MPI2_VERSION_02_05 (0x0205)
116
117/*Unit and Dev versioning for this MPI header set */
118#define MPI2_HEADER_VERSION_UNIT (0x1A)
119#define MPI2_HEADER_VERSION_DEV (0x00)
120#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
121#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
122#define MPI2_HEADER_VERSION_DEV_MASK (0x00FF)
123#define MPI2_HEADER_VERSION_DEV_SHIFT (0)
124#define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \
125 MPI2_HEADER_VERSION_DEV)
126
127/*****************************************************************************
128*
129* IOC State Definitions
130*
131*****************************************************************************/
132
133#define MPI2_IOC_STATE_RESET (0x00000000)
134#define MPI2_IOC_STATE_READY (0x10000000)
135#define MPI2_IOC_STATE_OPERATIONAL (0x20000000)
136#define MPI2_IOC_STATE_FAULT (0x40000000)
137
138#define MPI2_IOC_STATE_MASK (0xF0000000)
139#define MPI2_IOC_STATE_SHIFT (28)
140
141/*Fault state range for prodcut specific codes */
142#define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000)
143#define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF)
144
145/*****************************************************************************
146*
147* System Interface Register Definitions
148*
149*****************************************************************************/
150
151typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
152 U32 Doorbell; /*0x00 */
153 U32 WriteSequence; /*0x04 */
154 U32 HostDiagnostic; /*0x08 */
155 U32 Reserved1; /*0x0C */
156 U32 DiagRWData; /*0x10 */
157 U32 DiagRWAddressLow; /*0x14 */
158 U32 DiagRWAddressHigh; /*0x18 */
159 U32 Reserved2[5]; /*0x1C */
160 U32 HostInterruptStatus; /*0x30 */
161 U32 HostInterruptMask; /*0x34 */
162 U32 DCRData; /*0x38 */
163 U32 DCRAddress; /*0x3C */
164 U32 Reserved3[2]; /*0x40 */
165 U32 ReplyFreeHostIndex; /*0x48 */
166 U32 Reserved4[8]; /*0x4C */
167 U32 ReplyPostHostIndex; /*0x6C */
168 U32 Reserved5; /*0x70 */
169 U32 HCBSize; /*0x74 */
170 U32 HCBAddressLow; /*0x78 */
171 U32 HCBAddressHigh; /*0x7C */
172 U32 Reserved6[16]; /*0x80 */
173 U32 RequestDescriptorPostLow; /*0xC0 */
174 U32 RequestDescriptorPostHigh; /*0xC4 */
175 U32 Reserved7[14]; /*0xC8 */
176} MPI2_SYSTEM_INTERFACE_REGS,
177 *PTR_MPI2_SYSTEM_INTERFACE_REGS,
178 Mpi2SystemInterfaceRegs_t,
179 *pMpi2SystemInterfaceRegs_t;
180
181/*
182 *Defines for working with the Doorbell register.
183 */
184#define MPI2_DOORBELL_OFFSET (0x00000000)
185
186/*IOC --> System values */
187#define MPI2_DOORBELL_USED (0x08000000)
188#define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000)
189#define MPI2_DOORBELL_WHO_INIT_SHIFT (24)
190#define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF)
191#define MPI2_DOORBELL_DATA_MASK (0x0000FFFF)
192
193/*System --> IOC values */
194#define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000)
195#define MPI2_DOORBELL_FUNCTION_SHIFT (24)
196#define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000)
197#define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16)
198
199/*
200 *Defines for the WriteSequence register
201 */
202#define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004)
203#define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F)
204#define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0)
205#define MPI2_WRSEQ_1ST_KEY_VALUE (0xF)
206#define MPI2_WRSEQ_2ND_KEY_VALUE (0x4)
207#define MPI2_WRSEQ_3RD_KEY_VALUE (0xB)
208#define MPI2_WRSEQ_4TH_KEY_VALUE (0x2)
209#define MPI2_WRSEQ_5TH_KEY_VALUE (0x7)
210#define MPI2_WRSEQ_6TH_KEY_VALUE (0xD)
211
212/*
213 *Defines for the HostDiagnostic register
214 */
215#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
216
217#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
218#define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000)
219#define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800)
220
221#define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400)
222#define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200)
223#define MPI2_DIAG_HCB_MODE (0x00000100)
224#define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080)
225#define MPI2_DIAG_FLASH_BAD_SIG (0x00000040)
226#define MPI2_DIAG_RESET_HISTORY (0x00000020)
227#define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010)
228#define MPI2_DIAG_RESET_ADAPTER (0x00000004)
229#define MPI2_DIAG_HOLD_IOC_RESET (0x00000002)
230
231/*
232 *Offsets for DiagRWData and address
233 */
234#define MPI2_DIAG_RW_DATA_OFFSET (0x00000010)
235#define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014)
236#define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018)
237
238/*
239 *Defines for the HostInterruptStatus register
240 */
241#define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030)
242#define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000)
243#define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS
244#define MPI2_HIS_RESET_IRQ_STATUS (0x40000000)
245#define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008)
246#define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001)
247#define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS
248
249/*
250 *Defines for the HostInterruptMask register
251 */
252#define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034)
253#define MPI2_HIM_RESET_IRQ_MASK (0x40000000)
254#define MPI2_HIM_REPLY_INT_MASK (0x00000008)
255#define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK
256#define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001)
257#define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK
258
259/*
260 *Offsets for DCRData and address
261 */
262#define MPI2_DCR_DATA_OFFSET (0x00000038)
263#define MPI2_DCR_ADDRESS_OFFSET (0x0000003C)
264
265/*
266 *Offset for the Reply Free Queue
267 */
268#define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048)
269
270/*
271 *Defines for the Reply Descriptor Post Queue
272 */
273#define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C)
274#define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF)
275#define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000)
276#define MPI2_RPHI_MSIX_INDEX_SHIFT (24)
277
278/*
279 *Defines for the HCBSize and address
280 */
281#define MPI2_HCB_SIZE_OFFSET (0x00000074)
282#define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000)
283#define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001)
284
285#define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078)
286#define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C)
287
288/*
289 *Offsets for the Request Queue
290 */
291#define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0)
292#define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4)
293
294/*Hard Reset delay timings */
295#define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000)
296#define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000)
297#define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000)
298
299/*****************************************************************************
300*
301* Message Descriptors
302*
303*****************************************************************************/
304
305/*Request Descriptors */
306
307/*Default Request Descriptor */
308typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR {
309 U8 RequestFlags; /*0x00 */
310 U8 MSIxIndex; /*0x01 */
311 U16 SMID; /*0x02 */
312 U16 LMID; /*0x04 */
313 U16 DescriptorTypeDependent; /*0x06 */
314} MPI2_DEFAULT_REQUEST_DESCRIPTOR,
315 *PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR,
316 Mpi2DefaultRequestDescriptor_t,
317 *pMpi2DefaultRequestDescriptor_t;
318
319/*defines for the RequestFlags field */
320#define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E)
321#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00)
322#define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02)
323#define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06)
324#define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08)
325#define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A)
326#define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C)
327
328#define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01)
329
330/*High Priority Request Descriptor */
331typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR {
332 U8 RequestFlags; /*0x00 */
333 U8 MSIxIndex; /*0x01 */
334 U16 SMID; /*0x02 */
335 U16 LMID; /*0x04 */
336 U16 Reserved1; /*0x06 */
337} MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
338 *PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR,
339 Mpi2HighPriorityRequestDescriptor_t,
340 *pMpi2HighPriorityRequestDescriptor_t;
341
342/*SCSI IO Request Descriptor */
343typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR {
344 U8 RequestFlags; /*0x00 */
345 U8 MSIxIndex; /*0x01 */
346 U16 SMID; /*0x02 */
347 U16 LMID; /*0x04 */
348 U16 DevHandle; /*0x06 */
349} MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
350 *PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR,
351 Mpi2SCSIIORequestDescriptor_t,
352 *pMpi2SCSIIORequestDescriptor_t;
353
354/*SCSI Target Request Descriptor */
355typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR {
356 U8 RequestFlags; /*0x00 */
357 U8 MSIxIndex; /*0x01 */
358 U16 SMID; /*0x02 */
359 U16 LMID; /*0x04 */
360 U16 IoIndex; /*0x06 */
361} MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
362 *PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR,
363 Mpi2SCSITargetRequestDescriptor_t,
364 *pMpi2SCSITargetRequestDescriptor_t;
365
366/*RAID Accelerator Request Descriptor */
367typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR {
368 U8 RequestFlags; /*0x00 */
369 U8 MSIxIndex; /*0x01 */
370 U16 SMID; /*0x02 */
371 U16 LMID; /*0x04 */
372 U16 Reserved; /*0x06 */
373} MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
374 *PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR,
375 Mpi2RAIDAcceleratorRequestDescriptor_t,
376 *pMpi2RAIDAcceleratorRequestDescriptor_t;
377
378/*Fast Path SCSI IO Request Descriptor */
379typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR
380 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
381 *PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR,
382 Mpi25FastPathSCSIIORequestDescriptor_t,
383 *pMpi25FastPathSCSIIORequestDescriptor_t;
384
385/*union of Request Descriptors */
386typedef union _MPI2_REQUEST_DESCRIPTOR_UNION {
387 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default;
388 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority;
389 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO;
390 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget;
391 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator;
392 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO;
393 U64 Words;
394} MPI2_REQUEST_DESCRIPTOR_UNION,
395 *PTR_MPI2_REQUEST_DESCRIPTOR_UNION,
396 Mpi2RequestDescriptorUnion_t,
397 *pMpi2RequestDescriptorUnion_t;
398
399/*Reply Descriptors */
400
401/*Default Reply Descriptor */
402typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR {
403 U8 ReplyFlags; /*0x00 */
404 U8 MSIxIndex; /*0x01 */
405 U16 DescriptorTypeDependent1; /*0x02 */
406 U32 DescriptorTypeDependent2; /*0x04 */
407} MPI2_DEFAULT_REPLY_DESCRIPTOR,
408 *PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR,
409 Mpi2DefaultReplyDescriptor_t,
410 *pMpi2DefaultReplyDescriptor_t;
411
412/*defines for the ReplyFlags field */
413#define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F)
414#define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00)
415#define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01)
416#define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02)
417#define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03)
418#define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05)
419#define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06)
420#define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F)
421
422/*values for marking a reply descriptor as unused */
423#define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF)
424#define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF)
425
426/*Address Reply Descriptor */
427typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR {
428 U8 ReplyFlags; /*0x00 */
429 U8 MSIxIndex; /*0x01 */
430 U16 SMID; /*0x02 */
431 U32 ReplyFrameAddress; /*0x04 */
432} MPI2_ADDRESS_REPLY_DESCRIPTOR,
433 *PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR,
434 Mpi2AddressReplyDescriptor_t,
435 *pMpi2AddressReplyDescriptor_t;
436
437#define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00)
438
439/*SCSI IO Success Reply Descriptor */
440typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR {
441 U8 ReplyFlags; /*0x00 */
442 U8 MSIxIndex; /*0x01 */
443 U16 SMID; /*0x02 */
444 U16 TaskTag; /*0x04 */
445 U16 Reserved1; /*0x06 */
446} MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
447 *PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
448 Mpi2SCSIIOSuccessReplyDescriptor_t,
449 *pMpi2SCSIIOSuccessReplyDescriptor_t;
450
451/*TargetAssist Success Reply Descriptor */
452typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR {
453 U8 ReplyFlags; /*0x00 */
454 U8 MSIxIndex; /*0x01 */
455 U16 SMID; /*0x02 */
456 U8 SequenceNumber; /*0x04 */
457 U8 Reserved1; /*0x05 */
458 U16 IoIndex; /*0x06 */
459} MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
460 *PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR,
461 Mpi2TargetAssistSuccessReplyDescriptor_t,
462 *pMpi2TargetAssistSuccessReplyDescriptor_t;
463
464/*Target Command Buffer Reply Descriptor */
465typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR {
466 U8 ReplyFlags; /*0x00 */
467 U8 MSIxIndex; /*0x01 */
468 U8 VP_ID; /*0x02 */
469 U8 Flags; /*0x03 */
470 U16 InitiatorDevHandle; /*0x04 */
471 U16 IoIndex; /*0x06 */
472} MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
473 *PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR,
474 Mpi2TargetCommandBufferReplyDescriptor_t,
475 *pMpi2TargetCommandBufferReplyDescriptor_t;
476
477/*defines for Flags field */
478#define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F)
479
480/*RAID Accelerator Success Reply Descriptor */
481typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR {
482 U8 ReplyFlags; /*0x00 */
483 U8 MSIxIndex; /*0x01 */
484 U16 SMID; /*0x02 */
485 U32 Reserved; /*0x04 */
486} MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
487 *PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR,
488 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t,
489 *pMpi2RAIDAcceleratorSuccessReplyDescriptor_t;
490
491/*Fast Path SCSI IO Success Reply Descriptor */
492typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR
493 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
494 *PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR,
495 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t,
496 *pMpi25FastPathSCSIIOSuccessReplyDescriptor_t;
497
498/*union of Reply Descriptors */
499typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
500 MPI2_DEFAULT_REPLY_DESCRIPTOR Default;
501 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply;
502 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess;
503 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess;
504 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer;
505 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess;
506 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess;
507 U64 Words;
508} MPI2_REPLY_DESCRIPTORS_UNION,
509 *PTR_MPI2_REPLY_DESCRIPTORS_UNION,
510 Mpi2ReplyDescriptorsUnion_t,
511 *pMpi2ReplyDescriptorsUnion_t;
512
513/*****************************************************************************
514*
515* Message Functions
516*
517*****************************************************************************/
518
519#define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00)
520#define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01)
521#define MPI2_FUNCTION_IOC_INIT (0x02)
522#define MPI2_FUNCTION_IOC_FACTS (0x03)
523#define MPI2_FUNCTION_CONFIG (0x04)
524#define MPI2_FUNCTION_PORT_FACTS (0x05)
525#define MPI2_FUNCTION_PORT_ENABLE (0x06)
526#define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07)
527#define MPI2_FUNCTION_EVENT_ACK (0x08)
528#define MPI2_FUNCTION_FW_DOWNLOAD (0x09)
529#define MPI2_FUNCTION_TARGET_ASSIST (0x0B)
530#define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C)
531#define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D)
532#define MPI2_FUNCTION_FW_UPLOAD (0x12)
533#define MPI2_FUNCTION_RAID_ACTION (0x15)
534#define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16)
535#define MPI2_FUNCTION_TOOLBOX (0x17)
536#define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18)
537#define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A)
538#define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B)
539#define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C)
540#define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D)
541#define MPI2_FUNCTION_DIAG_RELEASE (0x1E)
542#define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24)
543#define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25)
544#define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C)
545#define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F)
546#define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30)
547#define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31)
548#define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0)
549#define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF)
550
551/*Doorbell functions */
552#define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40)
553#define MPI2_FUNCTION_HANDSHAKE (0x42)
554
555/*****************************************************************************
556*
557* IOC Status Values
558*
559*****************************************************************************/
560
561/*mask for IOCStatus status value */
562#define MPI2_IOCSTATUS_MASK (0x7FFF)
563
564/****************************************************************************
565* Common IOCStatus values for all replies
566****************************************************************************/
567
568#define MPI2_IOCSTATUS_SUCCESS (0x0000)
569#define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001)
570#define MPI2_IOCSTATUS_BUSY (0x0002)
571#define MPI2_IOCSTATUS_INVALID_SGL (0x0003)
572#define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004)
573#define MPI2_IOCSTATUS_INVALID_VPID (0x0005)
574#define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006)
575#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
576#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
577#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
578
579/****************************************************************************
580* Config IOCStatus values
581****************************************************************************/
582
583#define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020)
584#define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021)
585#define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022)
586#define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023)
587#define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024)
588#define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025)
589
590/****************************************************************************
591* SCSI IO Reply
592****************************************************************************/
593
594#define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040)
595#define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042)
596#define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043)
597#define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044)
598#define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045)
599#define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046)
600#define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047)
601#define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048)
602#define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049)
603#define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A)
604#define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B)
605#define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C)
606
607/****************************************************************************
608* For use by SCSI Initiator and SCSI Target end-to-end data protection
609****************************************************************************/
610
611#define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D)
612#define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E)
613#define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F)
614
615/****************************************************************************
616* SCSI Target values
617****************************************************************************/
618
619#define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062)
620#define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063)
621#define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064)
622#define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065)
623#define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A)
624#define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D)
625#define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E)
626#define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F)
627#define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070)
628#define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071)
629
630/****************************************************************************
631* Serial Attached SCSI values
632****************************************************************************/
633
634#define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090)
635#define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091)
636
637/****************************************************************************
638* Diagnostic Buffer Post / Diagnostic Release values
639****************************************************************************/
640
641#define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0)
642
643/****************************************************************************
644* RAID Accelerator values
645****************************************************************************/
646
647#define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0)
648
649/****************************************************************************
650* IOCStatus flag to indicate that log info is available
651****************************************************************************/
652
653#define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000)
654
655/****************************************************************************
656* IOCLogInfo Types
657****************************************************************************/
658
659#define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000)
660#define MPI2_IOCLOGINFO_TYPE_SHIFT (28)
661#define MPI2_IOCLOGINFO_TYPE_NONE (0x0)
662#define MPI2_IOCLOGINFO_TYPE_SCSI (0x1)
663#define MPI2_IOCLOGINFO_TYPE_FC (0x2)
664#define MPI2_IOCLOGINFO_TYPE_SAS (0x3)
665#define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4)
666#define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF)
667
668/*****************************************************************************
669*
670* Standard Message Structures
671*
672*****************************************************************************/
673
674/****************************************************************************
675*Request Message Header for all request messages
676****************************************************************************/
677
678typedef struct _MPI2_REQUEST_HEADER {
679 U16 FunctionDependent1; /*0x00 */
680 U8 ChainOffset; /*0x02 */
681 U8 Function; /*0x03 */
682 U16 FunctionDependent2; /*0x04 */
683 U8 FunctionDependent3; /*0x06 */
684 U8 MsgFlags; /*0x07 */
685 U8 VP_ID; /*0x08 */
686 U8 VF_ID; /*0x09 */
687 U16 Reserved1; /*0x0A */
688} MPI2_REQUEST_HEADER, *PTR_MPI2_REQUEST_HEADER,
689 MPI2RequestHeader_t, *pMPI2RequestHeader_t;
690
691/****************************************************************************
692* Default Reply
693****************************************************************************/
694
695typedef struct _MPI2_DEFAULT_REPLY {
696 U16 FunctionDependent1; /*0x00 */
697 U8 MsgLength; /*0x02 */
698 U8 Function; /*0x03 */
699 U16 FunctionDependent2; /*0x04 */
700 U8 FunctionDependent3; /*0x06 */
701 U8 MsgFlags; /*0x07 */
702 U8 VP_ID; /*0x08 */
703 U8 VF_ID; /*0x09 */
704 U16 Reserved1; /*0x0A */
705 U16 FunctionDependent5; /*0x0C */
706 U16 IOCStatus; /*0x0E */
707 U32 IOCLogInfo; /*0x10 */
708} MPI2_DEFAULT_REPLY, *PTR_MPI2_DEFAULT_REPLY,
709 MPI2DefaultReply_t, *pMPI2DefaultReply_t;
710
711/*common version structure/union used in messages and configuration pages */
712
713typedef struct _MPI2_VERSION_STRUCT {
714 U8 Dev; /*0x00 */
715 U8 Unit; /*0x01 */
716 U8 Minor; /*0x02 */
717 U8 Major; /*0x03 */
718} MPI2_VERSION_STRUCT;
719
720typedef union _MPI2_VERSION_UNION {
721 MPI2_VERSION_STRUCT Struct;
722 U32 Word;
723} MPI2_VERSION_UNION;
724
725/*LUN field defines, common to many structures */
726#define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF)
727#define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000)
728#define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF)
729#define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000)
730#define MPI2_LUN_LEVEL_1_WORD (0xFF00)
731#define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00)
732
733/*****************************************************************************
734*
735* Fusion-MPT MPI Scatter Gather Elements
736*
737*****************************************************************************/
738
739/****************************************************************************
740* MPI Simple Element structures
741****************************************************************************/
742
743typedef struct _MPI2_SGE_SIMPLE32 {
744 U32 FlagsLength;
745 U32 Address;
746} MPI2_SGE_SIMPLE32, *PTR_MPI2_SGE_SIMPLE32,
747 Mpi2SGESimple32_t, *pMpi2SGESimple32_t;
748
749typedef struct _MPI2_SGE_SIMPLE64 {
750 U32 FlagsLength;
751 U64 Address;
752} MPI2_SGE_SIMPLE64, *PTR_MPI2_SGE_SIMPLE64,
753 Mpi2SGESimple64_t, *pMpi2SGESimple64_t;
754
755typedef struct _MPI2_SGE_SIMPLE_UNION {
756 U32 FlagsLength;
757 union {
758 U32 Address32;
759 U64 Address64;
760 } u;
761} MPI2_SGE_SIMPLE_UNION,
762 *PTR_MPI2_SGE_SIMPLE_UNION,
763 Mpi2SGESimpleUnion_t,
764 *pMpi2SGESimpleUnion_t;
765
766/****************************************************************************
767* MPI Chain Element structures - for MPI v2.0 products only
768****************************************************************************/
769
770typedef struct _MPI2_SGE_CHAIN32 {
771 U16 Length;
772 U8 NextChainOffset;
773 U8 Flags;
774 U32 Address;
775} MPI2_SGE_CHAIN32, *PTR_MPI2_SGE_CHAIN32,
776 Mpi2SGEChain32_t, *pMpi2SGEChain32_t;
777
778typedef struct _MPI2_SGE_CHAIN64 {
779 U16 Length;
780 U8 NextChainOffset;
781 U8 Flags;
782 U64 Address;
783} MPI2_SGE_CHAIN64, *PTR_MPI2_SGE_CHAIN64,
784 Mpi2SGEChain64_t, *pMpi2SGEChain64_t;
785
786typedef struct _MPI2_SGE_CHAIN_UNION {
787 U16 Length;
788 U8 NextChainOffset;
789 U8 Flags;
790 union {
791 U32 Address32;
792 U64 Address64;
793 } u;
794} MPI2_SGE_CHAIN_UNION,
795 *PTR_MPI2_SGE_CHAIN_UNION,
796 Mpi2SGEChainUnion_t,
797 *pMpi2SGEChainUnion_t;
798
799/****************************************************************************
800* MPI Transaction Context Element structures - for MPI v2.0 products only
801****************************************************************************/
802
803typedef struct _MPI2_SGE_TRANSACTION32 {
804 U8 Reserved;
805 U8 ContextSize;
806 U8 DetailsLength;
807 U8 Flags;
808 U32 TransactionContext[1];
809 U32 TransactionDetails[1];
810} MPI2_SGE_TRANSACTION32,
811 *PTR_MPI2_SGE_TRANSACTION32,
812 Mpi2SGETransaction32_t,
813 *pMpi2SGETransaction32_t;
814
815typedef struct _MPI2_SGE_TRANSACTION64 {
816 U8 Reserved;
817 U8 ContextSize;
818 U8 DetailsLength;
819 U8 Flags;
820 U32 TransactionContext[2];
821 U32 TransactionDetails[1];
822} MPI2_SGE_TRANSACTION64,
823 *PTR_MPI2_SGE_TRANSACTION64,
824 Mpi2SGETransaction64_t,
825 *pMpi2SGETransaction64_t;
826
827typedef struct _MPI2_SGE_TRANSACTION96 {
828 U8 Reserved;
829 U8 ContextSize;
830 U8 DetailsLength;
831 U8 Flags;
832 U32 TransactionContext[3];
833 U32 TransactionDetails[1];
834} MPI2_SGE_TRANSACTION96, *PTR_MPI2_SGE_TRANSACTION96,
835 Mpi2SGETransaction96_t, *pMpi2SGETransaction96_t;
836
837typedef struct _MPI2_SGE_TRANSACTION128 {
838 U8 Reserved;
839 U8 ContextSize;
840 U8 DetailsLength;
841 U8 Flags;
842 U32 TransactionContext[4];
843 U32 TransactionDetails[1];
844} MPI2_SGE_TRANSACTION128, *PTR_MPI2_SGE_TRANSACTION128,
845 Mpi2SGETransaction_t128, *pMpi2SGETransaction_t128;
846
847typedef struct _MPI2_SGE_TRANSACTION_UNION {
848 U8 Reserved;
849 U8 ContextSize;
850 U8 DetailsLength;
851 U8 Flags;
852 union {
853 U32 TransactionContext32[1];
854 U32 TransactionContext64[2];
855 U32 TransactionContext96[3];
856 U32 TransactionContext128[4];
857 } u;
858 U32 TransactionDetails[1];
859} MPI2_SGE_TRANSACTION_UNION,
860 *PTR_MPI2_SGE_TRANSACTION_UNION,
861 Mpi2SGETransactionUnion_t,
862 *pMpi2SGETransactionUnion_t;
863
864/****************************************************************************
865* MPI SGE union for IO SGL's - for MPI v2.0 products only
866****************************************************************************/
867
868typedef struct _MPI2_MPI_SGE_IO_UNION {
869 union {
870 MPI2_SGE_SIMPLE_UNION Simple;
871 MPI2_SGE_CHAIN_UNION Chain;
872 } u;
873} MPI2_MPI_SGE_IO_UNION, *PTR_MPI2_MPI_SGE_IO_UNION,
874 Mpi2MpiSGEIOUnion_t, *pMpi2MpiSGEIOUnion_t;
875
876/****************************************************************************
877* MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only
878****************************************************************************/
879
880typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION {
881 union {
882 MPI2_SGE_SIMPLE_UNION Simple;
883 MPI2_SGE_TRANSACTION_UNION Transaction;
884 } u;
885} MPI2_SGE_TRANS_SIMPLE_UNION,
886 *PTR_MPI2_SGE_TRANS_SIMPLE_UNION,
887 Mpi2SGETransSimpleUnion_t,
888 *pMpi2SGETransSimpleUnion_t;
889
890/****************************************************************************
891* All MPI SGE types union
892****************************************************************************/
893
894typedef struct _MPI2_MPI_SGE_UNION {
895 union {
896 MPI2_SGE_SIMPLE_UNION Simple;
897 MPI2_SGE_CHAIN_UNION Chain;
898 MPI2_SGE_TRANSACTION_UNION Transaction;
899 } u;
900} MPI2_MPI_SGE_UNION, *PTR_MPI2_MPI_SGE_UNION,
901 Mpi2MpiSgeUnion_t, *pMpi2MpiSgeUnion_t;
902
903/****************************************************************************
904* MPI SGE field definition and masks
905****************************************************************************/
906
907/*Flags field bit definitions */
908
909#define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80)
910#define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40)
911#define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30)
912#define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08)
913#define MPI2_SGE_FLAGS_DIRECTION (0x04)
914#define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02)
915#define MPI2_SGE_FLAGS_END_OF_LIST (0x01)
916
917#define MPI2_SGE_FLAGS_SHIFT (24)
918
919#define MPI2_SGE_LENGTH_MASK (0x00FFFFFF)
920#define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF)
921
922/*Element Type */
923
924#define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00)
925#define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10)
926#define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30)
927#define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30)
928
929/*Address location */
930
931#define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00)
932
933/*Direction */
934
935#define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00)
936#define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04)
937
938#define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST)
939#define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC)
940
941/*Address Size */
942
943#define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00)
944#define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02)
945
946/*Context Size */
947
948#define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00)
949#define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02)
950#define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04)
951#define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06)
952
953#define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000)
954#define MPI2_SGE_CHAIN_OFFSET_SHIFT (16)
955
956/****************************************************************************
957* MPI SGE operation Macros
958****************************************************************************/
959
960/*SIMPLE FlagsLength manipulations... */
961#define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT)
962#define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> \
963 MPI2_SGE_FLAGS_SHIFT)
964#define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK)
965#define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK)
966
967#define MPI2_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_SGE_SET_FLAGS(f) | \
968 MPI2_SGE_LENGTH(l))
969
970#define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength)
971#define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength)
972#define MPI2_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
973 MPI2_SGE_SET_FLAGS_LENGTH(f, l))
974
975/*CAUTION - The following are READ-MODIFY-WRITE! */
976#define MPI2_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
977 MPI2_SGE_SET_FLAGS(f))
978#define MPI2_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
979 MPI2_SGE_LENGTH(l))
980
981#define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> \
982 MPI2_SGE_CHAIN_OFFSET_SHIFT)
983
984/*****************************************************************************
985*
986* Fusion-MPT IEEE Scatter Gather Elements
987*
988*****************************************************************************/
989
990/****************************************************************************
991* IEEE Simple Element structures
992****************************************************************************/
993
994/*MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */
995typedef struct _MPI2_IEEE_SGE_SIMPLE32 {
996 U32 Address;
997 U32 FlagsLength;
998} MPI2_IEEE_SGE_SIMPLE32, *PTR_MPI2_IEEE_SGE_SIMPLE32,
999 Mpi2IeeeSgeSimple32_t, *pMpi2IeeeSgeSimple32_t;
1000
1001typedef struct _MPI2_IEEE_SGE_SIMPLE64 {
1002 U64 Address;
1003 U32 Length;
1004 U16 Reserved1;
1005 U8 Reserved2;
1006 U8 Flags;
1007} MPI2_IEEE_SGE_SIMPLE64, *PTR_MPI2_IEEE_SGE_SIMPLE64,
1008 Mpi2IeeeSgeSimple64_t, *pMpi2IeeeSgeSimple64_t;
1009
1010typedef union _MPI2_IEEE_SGE_SIMPLE_UNION {
1011 MPI2_IEEE_SGE_SIMPLE32 Simple32;
1012 MPI2_IEEE_SGE_SIMPLE64 Simple64;
1013} MPI2_IEEE_SGE_SIMPLE_UNION,
1014 *PTR_MPI2_IEEE_SGE_SIMPLE_UNION,
1015 Mpi2IeeeSgeSimpleUnion_t,
1016 *pMpi2IeeeSgeSimpleUnion_t;
1017
1018/****************************************************************************
1019* IEEE Chain Element structures
1020****************************************************************************/
1021
1022/*MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */
1023typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32;
1024
1025/*MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */
1026typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64;
1027
1028typedef union _MPI2_IEEE_SGE_CHAIN_UNION {
1029 MPI2_IEEE_SGE_CHAIN32 Chain32;
1030 MPI2_IEEE_SGE_CHAIN64 Chain64;
1031} MPI2_IEEE_SGE_CHAIN_UNION,
1032 *PTR_MPI2_IEEE_SGE_CHAIN_UNION,
1033 Mpi2IeeeSgeChainUnion_t,
1034 *pMpi2IeeeSgeChainUnion_t;
1035
1036/*MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 products only */
1037typedef struct _MPI25_IEEE_SGE_CHAIN64 {
1038 U64 Address;
1039 U32 Length;
1040 U16 Reserved1;
1041 U8 NextChainOffset;
1042 U8 Flags;
1043} MPI25_IEEE_SGE_CHAIN64,
1044 *PTR_MPI25_IEEE_SGE_CHAIN64,
1045 Mpi25IeeeSgeChain64_t,
1046 *pMpi25IeeeSgeChain64_t;
1047
1048/****************************************************************************
1049* All IEEE SGE types union
1050****************************************************************************/
1051
1052/*MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */
1053typedef struct _MPI2_IEEE_SGE_UNION {
1054 union {
1055 MPI2_IEEE_SGE_SIMPLE_UNION Simple;
1056 MPI2_IEEE_SGE_CHAIN_UNION Chain;
1057 } u;
1058} MPI2_IEEE_SGE_UNION, *PTR_MPI2_IEEE_SGE_UNION,
1059 Mpi2IeeeSgeUnion_t, *pMpi2IeeeSgeUnion_t;
1060
1061/****************************************************************************
1062* IEEE SGE union for IO SGL's
1063****************************************************************************/
1064
1065typedef union _MPI25_SGE_IO_UNION {
1066 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple;
1067 MPI25_IEEE_SGE_CHAIN64 IeeeChain;
1068} MPI25_SGE_IO_UNION, *PTR_MPI25_SGE_IO_UNION,
1069 Mpi25SGEIOUnion_t, *pMpi25SGEIOUnion_t;
1070
1071/****************************************************************************
1072* IEEE SGE field definitions and masks
1073****************************************************************************/
1074
1075/*Flags field bit definitions */
1076
1077#define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80)
1078#define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40)
1079
1080#define MPI2_IEEE32_SGE_FLAGS_SHIFT (24)
1081
1082#define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF)
1083
1084/*Element Type */
1085
1086#define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00)
1087#define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80)
1088
1089/*Data Location Address Space */
1090
1091#define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03)
1092#define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00)
1093#define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01)
1094#define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02)
1095#define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03)
1096#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03)
1097#define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR \
1098 (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR)
1099
1100/****************************************************************************
1101* IEEE SGE operation Macros
1102****************************************************************************/
1103
1104/*SIMPLE FlagsLength manipulations... */
1105#define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT)
1106#define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) \
1107 >> MPI2_IEEE32_SGE_FLAGS_SHIFT)
1108#define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK)
1109
1110#define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) |\
1111 MPI2_IEEE32_SGE_LENGTH(l))
1112
1113#define MPI2_IEEE32_pSGE_GET_FLAGS(psg) \
1114 MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength)
1115#define MPI2_IEEE32_pSGE_GET_LENGTH(psg) \
1116 MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength)
1117#define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg, f, l) ((psg)->FlagsLength = \
1118 MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l))
1119
1120/*CAUTION - The following are READ-MODIFY-WRITE! */
1121#define MPI2_IEEE32_pSGE_SET_FLAGS(psg, f) ((psg)->FlagsLength |= \
1122 MPI2_IEEE32_SGE_SET_FLAGS(f))
1123#define MPI2_IEEE32_pSGE_SET_LENGTH(psg, l) ((psg)->FlagsLength |= \
1124 MPI2_IEEE32_SGE_LENGTH(l))
1125
1126/*****************************************************************************
1127*
1128* Fusion-MPT MPI/IEEE Scatter Gather Unions
1129*
1130*****************************************************************************/
1131
1132typedef union _MPI2_SIMPLE_SGE_UNION {
1133 MPI2_SGE_SIMPLE_UNION MpiSimple;
1134 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1135} MPI2_SIMPLE_SGE_UNION, *PTR_MPI2_SIMPLE_SGE_UNION,
1136 Mpi2SimpleSgeUntion_t, *pMpi2SimpleSgeUntion_t;
1137
1138typedef union _MPI2_SGE_IO_UNION {
1139 MPI2_SGE_SIMPLE_UNION MpiSimple;
1140 MPI2_SGE_CHAIN_UNION MpiChain;
1141 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
1142 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain;
1143} MPI2_SGE_IO_UNION, *PTR_MPI2_SGE_IO_UNION,
1144 Mpi2SGEIOUnion_t, *pMpi2SGEIOUnion_t;
1145
1146/****************************************************************************
1147*
1148* Values for SGLFlags field, used in many request messages with an SGL
1149*
1150****************************************************************************/
1151
1152/*values for MPI SGL Data Location Address Space subfield */
1153#define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C)
1154#define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00)
1155#define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04)
1156#define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08)
1157#define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C)
1158/*values for SGL Type subfield */
1159#define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03)
1160#define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00)
1161#define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01)
1162#define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02)
1163
1164#endif
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h b/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h
new file mode 100644
index 000000000000..d8b2c3eedb57
--- /dev/null
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h
@@ -0,0 +1,3323 @@
1/*
2 * Copyright (c) 2000-2011 LSI Corporation.
3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
9 * mpi2_cnfg.h Version: 02.00.22
10 *
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used
13 * with MPI v2.0 products. Unless otherwise noted, names beginning with
14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
15 *
16 * Version History
17 * ---------------
18 *
19 * Date Version Description
20 * -------- -------- ------------------------------------------------------
21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
22 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
23 * Added Manufacturing Page 11.
24 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
25 * define.
26 * 06-26-07 02.00.02 Adding generic structure for product-specific
27 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
28 * Rework of BIOS Page 2 configuration page.
29 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
30 * forms.
31 * Added configuration pages IOC Page 8 and Driver
32 * Persistent Mapping Page 0.
33 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
34 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
35 * RAID Physical Disk Pages 0 and 1, RAID Configuration
36 * Page 0).
37 * Added new value for AccessStatus field of SAS Device
38 * Page 0 (_SATA_NEEDS_INITIALIZATION).
39 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
40 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
41 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
42 * NVDATA.
43 * Modified IOC Page 7 to use masks and added field for
44 * SASBroadcastPrimitiveMasks.
45 * Added MPI2_CONFIG_PAGE_BIOS_4.
46 * Added MPI2_CONFIG_PAGE_LOG_0.
47 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
48 * Added SAS Device IDs.
49 * Updated Integrated RAID configuration pages including
50 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
51 * Page 0.
52 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
53 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
54 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
55 * Added missing MaxNumRoutedSasAddresses field to
56 * MPI2_CONFIG_PAGE_EXPANDER_0.
57 * Added SAS Port Page 0.
58 * Modified structure layout for
59 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
60 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
61 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
62 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
63 * to 0x000000FF.
64 * Added two new values for the Physical Disk Coercion Size
65 * bits in the Flags field of Manufacturing Page 4.
66 * Added product-specific Manufacturing pages 16 to 31.
67 * Modified Flags bits for controlling write cache on SATA
68 * drives in IO Unit Page 1.
69 * Added new bit to AdditionalControlFlags of SAS IO Unit
70 * Page 1 to control Invalid Topology Correction.
71 * Added additional defines for RAID Volume Page 0
72 * VolumeStatusFlags field.
73 * Modified meaning of RAID Volume Page 0 VolumeSettings
74 * define for auto-configure of hot-swap drives.
75 * Added SupportedPhysDisks field to RAID Volume Page 1 and
76 * added related defines.
77 * Added PhysDiskAttributes field (and related defines) to
78 * RAID Physical Disk Page 0.
79 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
80 * Added three new DiscoveryStatus bits for SAS IO Unit
81 * Page 0 and SAS Expander Page 0.
82 * Removed multiplexing information from SAS IO Unit pages.
83 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
84 * Removed Zone Address Resolved bit from PhyInfo and from
85 * Expander Page 0 Flags field.
86 * Added two new AccessStatus values to SAS Device Page 0
87 * for indicating routing problems. Added 3 reserved words
88 * to this page.
89 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
90 * Inserted missing reserved field into structure for IOC
91 * Page 6.
92 * Added more pending task bits to RAID Volume Page 0
93 * VolumeStatusFlags defines.
94 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
95 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
96 * and SAS Expander Page 0 to flag a downstream initiator
97 * when in simplified routing mode.
98 * Removed SATA Init Failure defines for DiscoveryStatus
99 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
100 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
101 * Added PortGroups, DmaGroup, and ControlGroup fields to
102 * SAS Device Page 0.
103 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
104 * Unit Page 6.
105 * Added expander reduced functionality data to SAS
106 * Expander Page 0.
107 * Added SAS PHY Page 2 and SAS PHY Page 3.
108 * 07-30-09 02.00.12 Added IO Unit Page 7.
109 * Added new device ids.
110 * Added SAS IO Unit Page 5.
111 * Added partial and slumber power management capable flags
112 * to SAS Device Page 0 Flags field.
113 * Added PhyInfo defines for power condition.
114 * Added Ethernet configuration pages.
115 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
116 * Added SAS PHY Page 4 structure and defines.
117 * 02-10-10 02.00.14 Modified the comments for the configuration page
118 * structures that contain an array of data. The host
119 * should use the "count" field in the page data (e.g. the
120 * NumPhys field) to determine the number of valid elements
121 * in the array.
122 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
123 * Added PowerManagementCapabilities to IO Unit Page 7.
124 * Added PortWidthModGroup field to
125 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
126 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
129 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
130 * define.
131 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
132 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
133 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
134 * defines.
135 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
136 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
137 * the Pinout field.
138 * Added BoardTemperature and BoardTemperatureUnits fields
139 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
140 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
141 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
142 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
143 * Added IO Unit Page 8, IO Unit Page 9,
144 * and IO Unit Page 10.
145 * Added SASNotifyPrimitiveMasks field to
146 * MPI2_CONFIG_PAGE_IOC_7.
147 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
148 * 05-25-11 02.00.20 Cleaned up a few comments.
149 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
150 * for PCIe link as obsolete.
151 * Added SpinupFlags field containing a Disable Spin-up bit
152 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO
153 * Unit Page 4.
154 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
155 * Added UEFIVersion field to BIOS Page 1 and defined new
156 * BiosOptions bits.
157 * Incorporating additions for MPI v2.5.
158 * --------------------------------------------------------------------------
159 */
160
161#ifndef MPI2_CNFG_H
162#define MPI2_CNFG_H
163
164/*****************************************************************************
165* Configuration Page Header and defines
166*****************************************************************************/
167
168/*Config Page Header */
169typedef struct _MPI2_CONFIG_PAGE_HEADER {
170 U8 PageVersion; /*0x00 */
171 U8 PageLength; /*0x01 */
172 U8 PageNumber; /*0x02 */
173 U8 PageType; /*0x03 */
174} MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER,
175 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t;
176
177typedef union _MPI2_CONFIG_PAGE_HEADER_UNION {
178 MPI2_CONFIG_PAGE_HEADER Struct;
179 U8 Bytes[4];
180 U16 Word16[2];
181 U32 Word32;
182} MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
183 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion;
184
185/*Extended Config Page Header */
186typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER {
187 U8 PageVersion; /*0x00 */
188 U8 Reserved1; /*0x01 */
189 U8 PageNumber; /*0x02 */
190 U8 PageType; /*0x03 */
191 U16 ExtPageLength; /*0x04 */
192 U8 ExtPageType; /*0x06 */
193 U8 Reserved2; /*0x07 */
194} MPI2_CONFIG_EXTENDED_PAGE_HEADER,
195 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
196 Mpi2ConfigExtendedPageHeader_t,
197 *pMpi2ConfigExtendedPageHeader_t;
198
199typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION {
200 MPI2_CONFIG_PAGE_HEADER Struct;
201 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
202 U8 Bytes[8];
203 U16 Word16[4];
204 U32 Word32[2];
205} MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
206 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
207 Mpi2ConfigPageExtendedHeaderUnion,
208 *pMpi2ConfigPageExtendedHeaderUnion;
209
210
211/*PageType field values */
212#define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
213#define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
214#define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
215#define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
216
217#define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
218#define MPI2_CONFIG_PAGETYPE_IOC (0x01)
219#define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
220#define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
221#define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
222#define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
223#define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
224#define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
225
226#define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
227
228
229/*ExtPageType field values */
230#define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
231#define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
232#define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
233#define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
234#define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
235#define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
236#define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
237#define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
238#define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
239#define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
240#define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
241
242
243/*****************************************************************************
244* PageAddress defines
245*****************************************************************************/
246
247/*RAID Volume PageAddress format */
248#define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
249#define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
250#define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
251
252#define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
253
254
255/*RAID Physical Disk PageAddress format */
256#define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
257#define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
258#define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
259#define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
260
261#define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
262#define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
263
264
265/*SAS Expander PageAddress format */
266#define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
267#define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
268#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
269#define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
270
271#define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
272#define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
273#define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
274
275
276/*SAS Device PageAddress format */
277#define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
278#define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
279#define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
280
281#define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
282
283
284/*SAS PHY PageAddress format */
285#define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
286#define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
287#define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
288
289#define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
290#define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
291
292
293/*SAS Port PageAddress format */
294#define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
295#define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
296#define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
297
298#define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
299
300
301/*SAS Enclosure PageAddress format */
302#define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
303#define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
304#define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
305
306#define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
307
308
309/*RAID Configuration PageAddress format */
310#define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
311#define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
312#define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
313#define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
314
315#define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
316
317
318/*Driver Persistent Mapping PageAddress format */
319#define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
320#define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
321
322#define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
323#define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
324#define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
325
326
327/*Ethernet PageAddress format */
328#define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
329#define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
330
331#define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
332
333
334
335/****************************************************************************
336* Configuration messages
337****************************************************************************/
338
339/*Configuration Request Message */
340typedef struct _MPI2_CONFIG_REQUEST {
341 U8 Action; /*0x00 */
342 U8 SGLFlags; /*0x01 */
343 U8 ChainOffset; /*0x02 */
344 U8 Function; /*0x03 */
345 U16 ExtPageLength; /*0x04 */
346 U8 ExtPageType; /*0x06 */
347 U8 MsgFlags; /*0x07 */
348 U8 VP_ID; /*0x08 */
349 U8 VF_ID; /*0x09 */
350 U16 Reserved1; /*0x0A */
351 U8 Reserved2; /*0x0C */
352 U8 ProxyVF_ID; /*0x0D */
353 U16 Reserved4; /*0x0E */
354 U32 Reserved3; /*0x10 */
355 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
356 U32 PageAddress; /*0x18 */
357 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */
358} MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST,
359 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t;
360
361/*values for the Action field */
362#define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
363#define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
364#define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
365#define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
366#define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
367#define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
368#define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
369#define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
370
371/*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
372
373
374/*Config Reply Message */
375typedef struct _MPI2_CONFIG_REPLY {
376 U8 Action; /*0x00 */
377 U8 SGLFlags; /*0x01 */
378 U8 MsgLength; /*0x02 */
379 U8 Function; /*0x03 */
380 U16 ExtPageLength; /*0x04 */
381 U8 ExtPageType; /*0x06 */
382 U8 MsgFlags; /*0x07 */
383 U8 VP_ID; /*0x08 */
384 U8 VF_ID; /*0x09 */
385 U16 Reserved1; /*0x0A */
386 U16 Reserved2; /*0x0C */
387 U16 IOCStatus; /*0x0E */
388 U32 IOCLogInfo; /*0x10 */
389 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */
390} MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY,
391 Mpi2ConfigReply_t, *pMpi2ConfigReply_t;
392
393
394
395/*****************************************************************************
396*
397* C o n f i g u r a t i o n P a g e s
398*
399*****************************************************************************/
400
401/****************************************************************************
402* Manufacturing Config pages
403****************************************************************************/
404
405#define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
406
407/*MPI v2.0 SAS products */
408#define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
409#define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
410#define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
411#define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
412#define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
413#define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
414#define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
415
416#define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
417
418#define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
419#define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
420#define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
421#define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
422#define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
423#define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
424#define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
425#define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
426#define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
427
428/*MPI v2.5 SAS products */
429#define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096)
430#define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097)
431#define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090)
432#define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091)
433#define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094)
434#define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095)
435
436
437
438
439/*Manufacturing Page 0 */
440
441typedef struct _MPI2_CONFIG_PAGE_MAN_0 {
442 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
443 U8 ChipName[16]; /*0x04 */
444 U8 ChipRevision[8]; /*0x14 */
445 U8 BoardName[16]; /*0x1C */
446 U8 BoardAssembly[16]; /*0x2C */
447 U8 BoardTracerNumber[16]; /*0x3C */
448} MPI2_CONFIG_PAGE_MAN_0,
449 *PTR_MPI2_CONFIG_PAGE_MAN_0,
450 Mpi2ManufacturingPage0_t,
451 *pMpi2ManufacturingPage0_t;
452
453#define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
454
455
456/*Manufacturing Page 1 */
457
458typedef struct _MPI2_CONFIG_PAGE_MAN_1 {
459 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
460 U8 VPD[256]; /*0x04 */
461} MPI2_CONFIG_PAGE_MAN_1,
462 *PTR_MPI2_CONFIG_PAGE_MAN_1,
463 Mpi2ManufacturingPage1_t,
464 *pMpi2ManufacturingPage1_t;
465
466#define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
467
468
469typedef struct _MPI2_CHIP_REVISION_ID {
470 U16 DeviceID; /*0x00 */
471 U8 PCIRevisionID; /*0x02 */
472 U8 Reserved; /*0x03 */
473} MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID,
474 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t;
475
476
477/*Manufacturing Page 2 */
478
479/*
480 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
481 *one and check Header.PageLength at runtime.
482 */
483#ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
484#define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
485#endif
486
487typedef struct _MPI2_CONFIG_PAGE_MAN_2 {
488 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
489 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
490 U32
491 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/*0x08 */
492} MPI2_CONFIG_PAGE_MAN_2,
493 *PTR_MPI2_CONFIG_PAGE_MAN_2,
494 Mpi2ManufacturingPage2_t,
495 *pMpi2ManufacturingPage2_t;
496
497#define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
498
499
500/*Manufacturing Page 3 */
501
502/*
503 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
504 *one and check Header.PageLength at runtime.
505 */
506#ifndef MPI2_MAN_PAGE_3_INFO_WORDS
507#define MPI2_MAN_PAGE_3_INFO_WORDS (1)
508#endif
509
510typedef struct _MPI2_CONFIG_PAGE_MAN_3 {
511 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
512 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */
513 U32
514 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/*0x08 */
515} MPI2_CONFIG_PAGE_MAN_3,
516 *PTR_MPI2_CONFIG_PAGE_MAN_3,
517 Mpi2ManufacturingPage3_t,
518 *pMpi2ManufacturingPage3_t;
519
520#define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
521
522
523/*Manufacturing Page 4 */
524
525typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS {
526 U8 PowerSaveFlags; /*0x00 */
527 U8 InternalOperationsSleepTime; /*0x01 */
528 U8 InternalOperationsRunTime; /*0x02 */
529 U8 HostIdleTime; /*0x03 */
530} MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
531 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
532 Mpi2ManPage4PwrSaveSettings_t,
533 *pMpi2ManPage4PwrSaveSettings_t;
534
535/*defines for the PowerSaveFlags field */
536#define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
537#define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
538#define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
539#define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
540
541typedef struct _MPI2_CONFIG_PAGE_MAN_4 {
542 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
543 U32 Reserved1; /*0x04 */
544 U32 Flags; /*0x08 */
545 U8 InquirySize; /*0x0C */
546 U8 Reserved2; /*0x0D */
547 U16 Reserved3; /*0x0E */
548 U8 InquiryData[56]; /*0x10 */
549 U32 RAID0VolumeSettings; /*0x48 */
550 U32 RAID1EVolumeSettings; /*0x4C */
551 U32 RAID1VolumeSettings; /*0x50 */
552 U32 RAID10VolumeSettings; /*0x54 */
553 U32 Reserved4; /*0x58 */
554 U32 Reserved5; /*0x5C */
555 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */
556 U8 MaxOCEDisks; /*0x64 */
557 U8 ResyncRate; /*0x65 */
558 U16 DataScrubDuration; /*0x66 */
559 U8 MaxHotSpares; /*0x68 */
560 U8 MaxPhysDisksPerVol; /*0x69 */
561 U8 MaxPhysDisks; /*0x6A */
562 U8 MaxVolumes; /*0x6B */
563} MPI2_CONFIG_PAGE_MAN_4,
564 *PTR_MPI2_CONFIG_PAGE_MAN_4,
565 Mpi2ManufacturingPage4_t,
566 *pMpi2ManufacturingPage4_t;
567
568#define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
569
570/*Manufacturing Page 4 Flags field */
571#define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
572#define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
573
574#define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
575#define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
576#define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
577
578#define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
579#define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
580#define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
581#define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
582#define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
583
584#define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
585#define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
586#define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
587#define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
588
589#define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
590#define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
591#define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
592#define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
593#define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
594#define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
595#define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
596#define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
597
598
599/*Manufacturing Page 5 */
600
601/*
602 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
603 *one and check the value returned for NumPhys at runtime.
604 */
605#ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
606#define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
607#endif
608
609typedef struct _MPI2_MANUFACTURING5_ENTRY {
610 U64 WWID; /*0x00 */
611 U64 DeviceName; /*0x08 */
612} MPI2_MANUFACTURING5_ENTRY,
613 *PTR_MPI2_MANUFACTURING5_ENTRY,
614 Mpi2Manufacturing5Entry_t,
615 *pMpi2Manufacturing5Entry_t;
616
617typedef struct _MPI2_CONFIG_PAGE_MAN_5 {
618 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
619 U8 NumPhys; /*0x04 */
620 U8 Reserved1; /*0x05 */
621 U16 Reserved2; /*0x06 */
622 U32 Reserved3; /*0x08 */
623 U32 Reserved4; /*0x0C */
624 MPI2_MANUFACTURING5_ENTRY
625 Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/*0x08 */
626} MPI2_CONFIG_PAGE_MAN_5,
627 *PTR_MPI2_CONFIG_PAGE_MAN_5,
628 Mpi2ManufacturingPage5_t,
629 *pMpi2ManufacturingPage5_t;
630
631#define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
632
633
634/*Manufacturing Page 6 */
635
636typedef struct _MPI2_CONFIG_PAGE_MAN_6 {
637 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
638 U32 ProductSpecificInfo;/*0x04 */
639} MPI2_CONFIG_PAGE_MAN_6,
640 *PTR_MPI2_CONFIG_PAGE_MAN_6,
641 Mpi2ManufacturingPage6_t,
642 *pMpi2ManufacturingPage6_t;
643
644#define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
645
646
647/*Manufacturing Page 7 */
648
649typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO {
650 U32 Pinout; /*0x00 */
651 U8 Connector[16]; /*0x04 */
652 U8 Location; /*0x14 */
653 U8 ReceptacleID; /*0x15 */
654 U16 Slot; /*0x16 */
655 U32 Reserved2; /*0x18 */
656} MPI2_MANPAGE7_CONNECTOR_INFO,
657 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
658 Mpi2ManPage7ConnectorInfo_t,
659 *pMpi2ManPage7ConnectorInfo_t;
660
661/*defines for the Pinout field */
662#define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
663#define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
664
665#define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
666#define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
667#define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
668#define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
669#define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
670#define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
671#define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
672#define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
673#define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
674#define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
675#define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
676#define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
677#define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
678#define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
679#define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
680
681/*defines for the Location field */
682#define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
683#define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
684#define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
685#define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
686#define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
687#define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
688#define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
689
690/*
691 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
692 *one and check the value returned for NumPhys at runtime.
693 */
694#ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
695#define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
696#endif
697
698typedef struct _MPI2_CONFIG_PAGE_MAN_7 {
699 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
700 U32 Reserved1; /*0x04 */
701 U32 Reserved2; /*0x08 */
702 U32 Flags; /*0x0C */
703 U8 EnclosureName[16]; /*0x10 */
704 U8 NumPhys; /*0x20 */
705 U8 Reserved3; /*0x21 */
706 U16 Reserved4; /*0x22 */
707 MPI2_MANPAGE7_CONNECTOR_INFO
708 ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /*0x24 */
709} MPI2_CONFIG_PAGE_MAN_7,
710 *PTR_MPI2_CONFIG_PAGE_MAN_7,
711 Mpi2ManufacturingPage7_t,
712 *pMpi2ManufacturingPage7_t;
713
714#define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
715
716/*defines for the Flags field */
717#define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
718
719
720/*
721 *Generic structure to use for product-specific manufacturing pages
722 *(currently Manufacturing Page 8 through Manufacturing Page 31).
723 */
724
725typedef struct _MPI2_CONFIG_PAGE_MAN_PS {
726 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
727 U32 ProductSpecificInfo;/*0x04 */
728} MPI2_CONFIG_PAGE_MAN_PS,
729 *PTR_MPI2_CONFIG_PAGE_MAN_PS,
730 Mpi2ManufacturingPagePS_t,
731 *pMpi2ManufacturingPagePS_t;
732
733#define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
734#define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
735#define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
736#define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
737#define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
738#define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
739#define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
740#define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
741#define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
742#define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
743#define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
744#define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
745#define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
746#define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
747#define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
748#define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
749#define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
750#define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
751#define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
752#define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
753#define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
754#define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
755#define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
756#define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
757
758
759/****************************************************************************
760* IO Unit Config Pages
761****************************************************************************/
762
763/*IO Unit Page 0 */
764
765typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 {
766 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
767 U64 UniqueValue; /*0x04 */
768 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */
769 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */
770} MPI2_CONFIG_PAGE_IO_UNIT_0,
771 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
772 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t;
773
774#define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
775
776
777/*IO Unit Page 1 */
778
779typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
780 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
781 U32 Flags; /*0x04 */
782} MPI2_CONFIG_PAGE_IO_UNIT_1,
783 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
784 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t;
785
786#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
787
788/*IO Unit Page 1 Flags defines */
789#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
790#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
791#define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
792#define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
793#define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
794#define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
795#define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
796#define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
797#define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
798#define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
799#define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
800#define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
801
802
803/*IO Unit Page 3 */
804
805/*
806 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
807 *one and check the value returned for GPIOCount at runtime.
808 */
809#ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
810#define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
811#endif
812
813typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 {
814 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
815 U8 GPIOCount; /*0x04 */
816 U8 Reserved1; /*0x05 */
817 U16 Reserved2; /*0x06 */
818 U16
819 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */
820} MPI2_CONFIG_PAGE_IO_UNIT_3,
821 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
822 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t;
823
824#define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
825
826/*defines for IO Unit Page 3 GPIOVal field */
827#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
828#define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
829#define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
830#define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
831
832
833/*IO Unit Page 5 */
834
835/*
836 *Upper layer code (drivers, utilities, etc.) should leave this define set to
837 *one and check the value returned for NumDmaEngines at runtime.
838 */
839#ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
840#define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
841#endif
842
843typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
844 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
845 U64
846 RaidAcceleratorBufferBaseAddress; /*0x04 */
847 U64
848 RaidAcceleratorBufferSize; /*0x0C */
849 U64
850 RaidAcceleratorControlBaseAddress; /*0x14 */
851 U8 RAControlSize; /*0x1C */
852 U8 NumDmaEngines; /*0x1D */
853 U8 RAMinControlSize; /*0x1E */
854 U8 RAMaxControlSize; /*0x1F */
855 U32 Reserved1; /*0x20 */
856 U32 Reserved2; /*0x24 */
857 U32 Reserved3; /*0x28 */
858 U32
859 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /*0x2C */
860} MPI2_CONFIG_PAGE_IO_UNIT_5,
861 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
862 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t;
863
864#define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
865
866/*defines for IO Unit Page 5 DmaEngineCapabilities field */
867#define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
868#define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
869
870#define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
871#define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
872#define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
873#define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
874
875
876/*IO Unit Page 6 */
877
878typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
879 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
880 U16 Flags; /*0x04 */
881 U8 RAHostControlSize; /*0x06 */
882 U8 Reserved0; /*0x07 */
883 U64
884 RaidAcceleratorHostControlBaseAddress; /*0x08 */
885 U32 Reserved1; /*0x10 */
886 U32 Reserved2; /*0x14 */
887 U32 Reserved3; /*0x18 */
888} MPI2_CONFIG_PAGE_IO_UNIT_6,
889 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
890 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t;
891
892#define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
893
894/*defines for IO Unit Page 6 Flags field */
895#define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
896
897
898/*IO Unit Page 7 */
899
900typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
901 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
902 U8 CurrentPowerMode; /*0x04 */
903 U8 PreviousPowerMode; /*0x05 */
904 U8 PCIeWidth; /*0x06 */
905 U8 PCIeSpeed; /*0x07 */
906 U32 ProcessorState; /*0x08 */
907 U32
908 PowerManagementCapabilities; /*0x0C */
909 U16 IOCTemperature; /*0x10 */
910 U8
911 IOCTemperatureUnits; /*0x12 */
912 U8 IOCSpeed; /*0x13 */
913 U16 BoardTemperature; /*0x14 */
914 U8
915 BoardTemperatureUnits; /*0x16 */
916 U8 Reserved3; /*0x17 */
917} MPI2_CONFIG_PAGE_IO_UNIT_7,
918 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
919 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t;
920
921#define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
922
923/*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */
924#define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0)
925#define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00)
926#define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40)
927#define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80)
928#define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0)
929
930#define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07)
931#define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00)
932#define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01)
933#define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04)
934#define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05)
935#define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06)
936
937
938/*defines for IO Unit Page 7 PCIeWidth field */
939#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
940#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
941#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
942#define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
943
944/*defines for IO Unit Page 7 PCIeSpeed field */
945#define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
946#define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
947#define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
948
949/*defines for IO Unit Page 7 ProcessorState field */
950#define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
951#define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
952
953#define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
954#define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
955#define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
956
957/*defines for IO Unit Page 7 PowerManagementCapabilities field */
958#define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000)
959#define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000)
960#define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000)
961#define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000)
962#define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000)
963#define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000)
964#define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000)
965#define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000)
966#define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000)
967#define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400)
968#define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200)
969#define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100)
970#define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040)
971#define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020)
972#define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010)
973#define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008)
974#define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004)
975#define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002)
976#define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001)
977
978/*obsolete names for the PowerManagementCapabilities bits (above) */
979#define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
980#define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
981#define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
982#define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */
983#define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */
984
985
986/*defines for IO Unit Page 7 IOCTemperatureUnits field */
987#define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
988#define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
989#define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
990
991/*defines for IO Unit Page 7 IOCSpeed field */
992#define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
993#define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
994#define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
995#define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
996
997/*defines for IO Unit Page 7 BoardTemperatureUnits field */
998#define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
999#define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
1000#define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
1001
1002
1003/*IO Unit Page 8 */
1004
1005#define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
1006
1007typedef struct _MPI2_IOUNIT8_SENSOR {
1008 U16 Flags; /*0x00 */
1009 U16 Reserved1; /*0x02 */
1010 U16
1011 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */
1012 U32 Reserved2; /*0x0C */
1013 U32 Reserved3; /*0x10 */
1014 U32 Reserved4; /*0x14 */
1015} MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR,
1016 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t;
1017
1018/*defines for IO Unit Page 8 Sensor Flags field */
1019#define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
1020#define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
1021#define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
1022#define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
1023
1024/*
1025 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1026 *one and check the value returned for NumSensors at runtime.
1027 */
1028#ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
1029#define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
1030#endif
1031
1032typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
1033 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1034 U32 Reserved1; /*0x04 */
1035 U32 Reserved2; /*0x08 */
1036 U8 NumSensors; /*0x0C */
1037 U8 PollingInterval; /*0x0D */
1038 U16 Reserved3; /*0x0E */
1039 MPI2_IOUNIT8_SENSOR
1040 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/*0x10 */
1041} MPI2_CONFIG_PAGE_IO_UNIT_8,
1042 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
1043 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t;
1044
1045#define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
1046
1047
1048/*IO Unit Page 9 */
1049
1050typedef struct _MPI2_IOUNIT9_SENSOR {
1051 U16 CurrentTemperature; /*0x00 */
1052 U16 Reserved1; /*0x02 */
1053 U8 Flags; /*0x04 */
1054 U8 Reserved2; /*0x05 */
1055 U16 Reserved3; /*0x06 */
1056 U32 Reserved4; /*0x08 */
1057 U32 Reserved5; /*0x0C */
1058} MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR,
1059 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t;
1060
1061/*defines for IO Unit Page 9 Sensor Flags field */
1062#define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
1063
1064/*
1065 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1066 *one and check the value returned for NumSensors at runtime.
1067 */
1068#ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1069#define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
1070#endif
1071
1072typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1073 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1074 U32 Reserved1; /*0x04 */
1075 U32 Reserved2; /*0x08 */
1076 U8 NumSensors; /*0x0C */
1077 U8 Reserved4; /*0x0D */
1078 U16 Reserved3; /*0x0E */
1079 MPI2_IOUNIT9_SENSOR
1080 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/*0x10 */
1081} MPI2_CONFIG_PAGE_IO_UNIT_9,
1082 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1083 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t;
1084
1085#define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1086
1087
1088/*IO Unit Page 10 */
1089
1090typedef struct _MPI2_IOUNIT10_FUNCTION {
1091 U8 CreditPercent; /*0x00 */
1092 U8 Reserved1; /*0x01 */
1093 U16 Reserved2; /*0x02 */
1094} MPI2_IOUNIT10_FUNCTION,
1095 *PTR_MPI2_IOUNIT10_FUNCTION,
1096 Mpi2IOUnit10Function_t,
1097 *pMpi2IOUnit10Function_t;
1098
1099/*
1100 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1101 *one and check the value returned for NumFunctions at runtime.
1102 */
1103#ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1104#define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1105#endif
1106
1107typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1108 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1109 U8 NumFunctions; /*0x04 */
1110 U8 Reserved1; /*0x05 */
1111 U16 Reserved2; /*0x06 */
1112 U32 Reserved3; /*0x08 */
1113 U32 Reserved4; /*0x0C */
1114 MPI2_IOUNIT10_FUNCTION
1115 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/*0x10 */
1116} MPI2_CONFIG_PAGE_IO_UNIT_10,
1117 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1118 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t;
1119
1120#define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1121
1122
1123
1124/****************************************************************************
1125* IOC Config Pages
1126****************************************************************************/
1127
1128/*IOC Page 0 */
1129
1130typedef struct _MPI2_CONFIG_PAGE_IOC_0 {
1131 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1132 U32 Reserved1; /*0x04 */
1133 U32 Reserved2; /*0x08 */
1134 U16 VendorID; /*0x0C */
1135 U16 DeviceID; /*0x0E */
1136 U8 RevisionID; /*0x10 */
1137 U8 Reserved3; /*0x11 */
1138 U16 Reserved4; /*0x12 */
1139 U32 ClassCode; /*0x14 */
1140 U16 SubsystemVendorID; /*0x18 */
1141 U16 SubsystemID; /*0x1A */
1142} MPI2_CONFIG_PAGE_IOC_0,
1143 *PTR_MPI2_CONFIG_PAGE_IOC_0,
1144 Mpi2IOCPage0_t, *pMpi2IOCPage0_t;
1145
1146#define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1147
1148
1149/*IOC Page 1 */
1150
1151typedef struct _MPI2_CONFIG_PAGE_IOC_1 {
1152 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1153 U32 Flags; /*0x04 */
1154 U32 CoalescingTimeout; /*0x08 */
1155 U8 CoalescingDepth; /*0x0C */
1156 U8 PCISlotNum; /*0x0D */
1157 U8 PCIBusNum; /*0x0E */
1158 U8 PCIDomainSegment; /*0x0F */
1159 U32 Reserved1; /*0x10 */
1160 U32 Reserved2; /*0x14 */
1161} MPI2_CONFIG_PAGE_IOC_1,
1162 *PTR_MPI2_CONFIG_PAGE_IOC_1,
1163 Mpi2IOCPage1_t, *pMpi2IOCPage1_t;
1164
1165#define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1166
1167/*defines for IOC Page 1 Flags field */
1168#define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1169
1170#define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1171#define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1172#define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1173
1174/*IOC Page 6 */
1175
1176typedef struct _MPI2_CONFIG_PAGE_IOC_6 {
1177 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1178 U32
1179 CapabilitiesFlags; /*0x04 */
1180 U8 MaxDrivesRAID0; /*0x08 */
1181 U8 MaxDrivesRAID1; /*0x09 */
1182 U8
1183 MaxDrivesRAID1E; /*0x0A */
1184 U8
1185 MaxDrivesRAID10; /*0x0B */
1186 U8 MinDrivesRAID0; /*0x0C */
1187 U8 MinDrivesRAID1; /*0x0D */
1188 U8
1189 MinDrivesRAID1E; /*0x0E */
1190 U8
1191 MinDrivesRAID10; /*0x0F */
1192 U32 Reserved1; /*0x10 */
1193 U8
1194 MaxGlobalHotSpares; /*0x14 */
1195 U8 MaxPhysDisks; /*0x15 */
1196 U8 MaxVolumes; /*0x16 */
1197 U8 MaxConfigs; /*0x17 */
1198 U8 MaxOCEDisks; /*0x18 */
1199 U8 Reserved2; /*0x19 */
1200 U16 Reserved3; /*0x1A */
1201 U32
1202 SupportedStripeSizeMapRAID0; /*0x1C */
1203 U32
1204 SupportedStripeSizeMapRAID1E; /*0x20 */
1205 U32
1206 SupportedStripeSizeMapRAID10; /*0x24 */
1207 U32 Reserved4; /*0x28 */
1208 U32 Reserved5; /*0x2C */
1209 U16
1210 DefaultMetadataSize; /*0x30 */
1211 U16 Reserved6; /*0x32 */
1212 U16
1213 MaxBadBlockTableEntries; /*0x34 */
1214 U16 Reserved7; /*0x36 */
1215 U32
1216 IRNvsramVersion; /*0x38 */
1217} MPI2_CONFIG_PAGE_IOC_6,
1218 *PTR_MPI2_CONFIG_PAGE_IOC_6,
1219 Mpi2IOCPage6_t, *pMpi2IOCPage6_t;
1220
1221#define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1222
1223/*defines for IOC Page 6 CapabilitiesFlags */
1224#define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1225#define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1226#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1227#define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1228#define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1229#define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1230
1231
1232/*IOC Page 7 */
1233
1234#define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1235
1236typedef struct _MPI2_CONFIG_PAGE_IOC_7 {
1237 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1238 U32 Reserved1; /*0x04 */
1239 U32
1240 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */
1241 U16 SASBroadcastPrimitiveMasks; /*0x18 */
1242 U16 SASNotifyPrimitiveMasks; /*0x1A */
1243 U32 Reserved3; /*0x1C */
1244} MPI2_CONFIG_PAGE_IOC_7,
1245 *PTR_MPI2_CONFIG_PAGE_IOC_7,
1246 Mpi2IOCPage7_t, *pMpi2IOCPage7_t;
1247
1248#define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1249
1250
1251/*IOC Page 8 */
1252
1253typedef struct _MPI2_CONFIG_PAGE_IOC_8 {
1254 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1255 U8 NumDevsPerEnclosure; /*0x04 */
1256 U8 Reserved1; /*0x05 */
1257 U16 Reserved2; /*0x06 */
1258 U16 MaxPersistentEntries; /*0x08 */
1259 U16 MaxNumPhysicalMappedIDs; /*0x0A */
1260 U16 Flags; /*0x0C */
1261 U16 Reserved3; /*0x0E */
1262 U16 IRVolumeMappingFlags; /*0x10 */
1263 U16 Reserved4; /*0x12 */
1264 U32 Reserved5; /*0x14 */
1265} MPI2_CONFIG_PAGE_IOC_8,
1266 *PTR_MPI2_CONFIG_PAGE_IOC_8,
1267 Mpi2IOCPage8_t, *pMpi2IOCPage8_t;
1268
1269#define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1270
1271/*defines for IOC Page 8 Flags field */
1272#define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1273#define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1274
1275#define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1276#define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1277#define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1278
1279#define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1280#define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1281
1282/*defines for IOC Page 8 IRVolumeMappingFlags */
1283#define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1284#define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1285#define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1286
1287
1288/****************************************************************************
1289* BIOS Config Pages
1290****************************************************************************/
1291
1292/*BIOS Page 1 */
1293
1294typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1295 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1296 U32 BiosOptions; /*0x04 */
1297 U32 IOCSettings; /*0x08 */
1298 U32 Reserved1; /*0x0C */
1299 U32 DeviceSettings; /*0x10 */
1300 U16 NumberOfDevices; /*0x14 */
1301 U16 UEFIVersion; /*0x16 */
1302 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */
1303 U16 IOTimeoutSequential; /*0x1A */
1304 U16 IOTimeoutOther; /*0x1C */
1305 U16 IOTimeoutBlockDevicesRM; /*0x1E */
1306} MPI2_CONFIG_PAGE_BIOS_1,
1307 *PTR_MPI2_CONFIG_PAGE_BIOS_1,
1308 Mpi2BiosPage1_t, *pMpi2BiosPage1_t;
1309
1310#define MPI2_BIOSPAGE1_PAGEVERSION (0x05)
1311
1312/*values for BIOS Page 1 BiosOptions field */
1313#define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1314#define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1315#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1316#define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1317
1318#define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1319
1320/*values for BIOS Page 1 IOCSettings field */
1321#define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1322#define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1323#define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1324
1325#define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1326#define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1327#define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1328#define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1329
1330#define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1331#define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1332#define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1333#define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1334#define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1335
1336#define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1337
1338/*values for BIOS Page 1 DeviceSettings field */
1339#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1340#define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1341#define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1342#define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1343#define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1344
1345/*defines for BIOS Page 1 UEFIVersion field */
1346#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1347#define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1348#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1349#define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1350
1351
1352
1353/*BIOS Page 2 */
1354
1355typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER {
1356 U32 Reserved1; /*0x00 */
1357 U32 Reserved2; /*0x04 */
1358 U32 Reserved3; /*0x08 */
1359 U32 Reserved4; /*0x0C */
1360 U32 Reserved5; /*0x10 */
1361 U32 Reserved6; /*0x14 */
1362} MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1363 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1364 Mpi2BootDeviceAdapterOrder_t,
1365 *pMpi2BootDeviceAdapterOrder_t;
1366
1367typedef struct _MPI2_BOOT_DEVICE_SAS_WWID {
1368 U64 SASAddress; /*0x00 */
1369 U8 LUN[8]; /*0x08 */
1370 U32 Reserved1; /*0x10 */
1371 U32 Reserved2; /*0x14 */
1372} MPI2_BOOT_DEVICE_SAS_WWID,
1373 *PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1374 Mpi2BootDeviceSasWwid_t,
1375 *pMpi2BootDeviceSasWwid_t;
1376
1377typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT {
1378 U64 EnclosureLogicalID; /*0x00 */
1379 U32 Reserved1; /*0x08 */
1380 U32 Reserved2; /*0x0C */
1381 U16 SlotNumber; /*0x10 */
1382 U16 Reserved3; /*0x12 */
1383 U32 Reserved4; /*0x14 */
1384} MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1385 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1386 Mpi2BootDeviceEnclosureSlot_t,
1387 *pMpi2BootDeviceEnclosureSlot_t;
1388
1389typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME {
1390 U64 DeviceName; /*0x00 */
1391 U8 LUN[8]; /*0x08 */
1392 U32 Reserved1; /*0x10 */
1393 U32 Reserved2; /*0x14 */
1394} MPI2_BOOT_DEVICE_DEVICE_NAME,
1395 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1396 Mpi2BootDeviceDeviceName_t,
1397 *pMpi2BootDeviceDeviceName_t;
1398
1399typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE {
1400 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1401 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1402 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1403 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1404} MPI2_BIOSPAGE2_BOOT_DEVICE,
1405 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1406 Mpi2BiosPage2BootDevice_t,
1407 *pMpi2BiosPage2BootDevice_t;
1408
1409typedef struct _MPI2_CONFIG_PAGE_BIOS_2 {
1410 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1411 U32 Reserved1; /*0x04 */
1412 U32 Reserved2; /*0x08 */
1413 U32 Reserved3; /*0x0C */
1414 U32 Reserved4; /*0x10 */
1415 U32 Reserved5; /*0x14 */
1416 U32 Reserved6; /*0x18 */
1417 U8 ReqBootDeviceForm; /*0x1C */
1418 U8 Reserved7; /*0x1D */
1419 U16 Reserved8; /*0x1E */
1420 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */
1421 U8 ReqAltBootDeviceForm; /*0x38 */
1422 U8 Reserved9; /*0x39 */
1423 U16 Reserved10; /*0x3A */
1424 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */
1425 U8 CurrentBootDeviceForm; /*0x58 */
1426 U8 Reserved11; /*0x59 */
1427 U16 Reserved12; /*0x5A */
1428 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */
1429} MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2,
1430 Mpi2BiosPage2_t, *pMpi2BiosPage2_t;
1431
1432#define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1433
1434/*values for BIOS Page 2 BootDeviceForm fields */
1435#define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1436#define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1437#define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1438#define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1439#define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1440
1441
1442/*BIOS Page 3 */
1443
1444typedef struct _MPI2_ADAPTER_INFO {
1445 U8 PciBusNumber; /*0x00 */
1446 U8 PciDeviceAndFunctionNumber; /*0x01 */
1447 U16 AdapterFlags; /*0x02 */
1448} MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO,
1449 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t;
1450
1451#define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1452#define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1453
1454typedef struct _MPI2_CONFIG_PAGE_BIOS_3 {
1455 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1456 U32 GlobalFlags; /*0x04 */
1457 U32 BiosVersion; /*0x08 */
1458 MPI2_ADAPTER_INFO AdapterOrder[4]; /*0x0C */
1459 U32 Reserved1; /*0x1C */
1460} MPI2_CONFIG_PAGE_BIOS_3,
1461 *PTR_MPI2_CONFIG_PAGE_BIOS_3,
1462 Mpi2BiosPage3_t, *pMpi2BiosPage3_t;
1463
1464#define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1465
1466/*values for BIOS Page 3 GlobalFlags */
1467#define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1468#define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1469#define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1470
1471#define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1472#define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1473#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1474#define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1475
1476
1477/*BIOS Page 4 */
1478
1479/*
1480 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1481 *one and check the value returned for NumPhys at runtime.
1482 */
1483#ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1484#define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1485#endif
1486
1487typedef struct _MPI2_BIOS4_ENTRY {
1488 U64 ReassignmentWWID; /*0x00 */
1489 U64 ReassignmentDeviceName; /*0x08 */
1490} MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY,
1491 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t;
1492
1493typedef struct _MPI2_CONFIG_PAGE_BIOS_4 {
1494 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1495 U8 NumPhys; /*0x04 */
1496 U8 Reserved1; /*0x05 */
1497 U16 Reserved2; /*0x06 */
1498 MPI2_BIOS4_ENTRY
1499 Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /*0x08 */
1500} MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4,
1501 Mpi2BiosPage4_t, *pMpi2BiosPage4_t;
1502
1503#define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1504
1505
1506/****************************************************************************
1507* RAID Volume Config Pages
1508****************************************************************************/
1509
1510/*RAID Volume Page 0 */
1511
1512typedef struct _MPI2_RAIDVOL0_PHYS_DISK {
1513 U8 RAIDSetNum; /*0x00 */
1514 U8 PhysDiskMap; /*0x01 */
1515 U8 PhysDiskNum; /*0x02 */
1516 U8 Reserved; /*0x03 */
1517} MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK,
1518 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t;
1519
1520/*defines for the PhysDiskMap field */
1521#define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1522#define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1523
1524typedef struct _MPI2_RAIDVOL0_SETTINGS {
1525 U16 Settings; /*0x00 */
1526 U8 HotSparePool; /*0x01 */
1527 U8 Reserved; /*0x02 */
1528} MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS,
1529 Mpi2RaidVol0Settings_t,
1530 *pMpi2RaidVol0Settings_t;
1531
1532/*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1533#define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1534#define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1535#define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1536#define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1537#define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1538#define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1539#define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1540#define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1541
1542/*RAID Volume Page 0 VolumeSettings defines */
1543#define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1544#define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1545
1546#define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1547#define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1548#define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1549#define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1550
1551/*
1552 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1553 *one and check the value returned for NumPhysDisks at runtime.
1554 */
1555#ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1556#define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1557#endif
1558
1559typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 {
1560 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1561 U16 DevHandle; /*0x04 */
1562 U8 VolumeState; /*0x06 */
1563 U8 VolumeType; /*0x07 */
1564 U32 VolumeStatusFlags; /*0x08 */
1565 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */
1566 U64 MaxLBA; /*0x10 */
1567 U32 StripeSize; /*0x18 */
1568 U16 BlockSize; /*0x1C */
1569 U16 Reserved1; /*0x1E */
1570 U8 SupportedPhysDisks;/*0x20 */
1571 U8 ResyncRate; /*0x21 */
1572 U16 DataScrubDuration; /*0x22 */
1573 U8 NumPhysDisks; /*0x24 */
1574 U8 Reserved2; /*0x25 */
1575 U8 Reserved3; /*0x26 */
1576 U8 InactiveStatus; /*0x27 */
1577 MPI2_RAIDVOL0_PHYS_DISK
1578 PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /*0x28 */
1579} MPI2_CONFIG_PAGE_RAID_VOL_0,
1580 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1581 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t;
1582
1583#define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1584
1585/*values for RAID VolumeState */
1586#define MPI2_RAID_VOL_STATE_MISSING (0x00)
1587#define MPI2_RAID_VOL_STATE_FAILED (0x01)
1588#define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1589#define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1590#define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1591#define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1592
1593/*values for RAID VolumeType */
1594#define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1595#define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1596#define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1597#define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1598#define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1599
1600/*values for RAID Volume Page 0 VolumeStatusFlags field */
1601#define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1602#define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1603#define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1604#define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1605#define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1606#define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1607#define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1608#define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1609#define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1610#define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1611#define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1612#define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1613#define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1614#define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1615#define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1616#define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1617#define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1618#define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1619#define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1620
1621/*values for RAID Volume Page 0 SupportedPhysDisks field */
1622#define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1623#define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1624#define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1625#define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1626
1627/*values for RAID Volume Page 0 InactiveStatus field */
1628#define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1629#define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1630#define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1631#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1632#define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1633#define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1634#define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1635
1636
1637/*RAID Volume Page 1 */
1638
1639typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 {
1640 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1641 U16 DevHandle; /*0x04 */
1642 U16 Reserved0; /*0x06 */
1643 U8 GUID[24]; /*0x08 */
1644 U8 Name[16]; /*0x20 */
1645 U64 WWID; /*0x30 */
1646 U32 Reserved1; /*0x38 */
1647 U32 Reserved2; /*0x3C */
1648} MPI2_CONFIG_PAGE_RAID_VOL_1,
1649 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1650 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t;
1651
1652#define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1653
1654
1655/****************************************************************************
1656* RAID Physical Disk Config Pages
1657****************************************************************************/
1658
1659/*RAID Physical Disk Page 0 */
1660
1661typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS {
1662 U16 Reserved1; /*0x00 */
1663 U8 HotSparePool; /*0x02 */
1664 U8 Reserved2; /*0x03 */
1665} MPI2_RAIDPHYSDISK0_SETTINGS,
1666 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1667 Mpi2RaidPhysDisk0Settings_t,
1668 *pMpi2RaidPhysDisk0Settings_t;
1669
1670/*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1671
1672typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA {
1673 U8 VendorID[8]; /*0x00 */
1674 U8 ProductID[16]; /*0x08 */
1675 U8 ProductRevLevel[4]; /*0x18 */
1676 U8 SerialNum[32]; /*0x1C */
1677} MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1678 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1679 Mpi2RaidPhysDisk0InquiryData_t,
1680 *pMpi2RaidPhysDisk0InquiryData_t;
1681
1682typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 {
1683 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1684 U16 DevHandle; /*0x04 */
1685 U8 Reserved1; /*0x06 */
1686 U8 PhysDiskNum; /*0x07 */
1687 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */
1688 U32 Reserved2; /*0x0C */
1689 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */
1690 U32 Reserved3; /*0x4C */
1691 U8 PhysDiskState; /*0x50 */
1692 U8 OfflineReason; /*0x51 */
1693 U8 IncompatibleReason; /*0x52 */
1694 U8 PhysDiskAttributes; /*0x53 */
1695 U32 PhysDiskStatusFlags;/*0x54 */
1696 U64 DeviceMaxLBA; /*0x58 */
1697 U64 HostMaxLBA; /*0x60 */
1698 U64 CoercedMaxLBA; /*0x68 */
1699 U16 BlockSize; /*0x70 */
1700 U16 Reserved5; /*0x72 */
1701 U32 Reserved6; /*0x74 */
1702} MPI2_CONFIG_PAGE_RD_PDISK_0,
1703 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1704 Mpi2RaidPhysDiskPage0_t,
1705 *pMpi2RaidPhysDiskPage0_t;
1706
1707#define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1708
1709/*PhysDiskState defines */
1710#define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1711#define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1712#define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1713#define MPI2_RAID_PD_STATE_ONLINE (0x03)
1714#define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1715#define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1716#define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1717#define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1718
1719/*OfflineReason defines */
1720#define MPI2_PHYSDISK0_ONLINE (0x00)
1721#define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1722#define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1723#define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1724#define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1725#define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1726#define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1727
1728/*IncompatibleReason defines */
1729#define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1730#define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1731#define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1732#define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1733#define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1734#define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1735#define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1736#define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1737
1738/*PhysDiskAttributes defines */
1739#define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1740#define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1741#define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1742
1743#define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1744#define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1745#define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1746
1747/*PhysDiskStatusFlags defines */
1748#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1749#define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1750#define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1751#define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1752#define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1753#define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1754#define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1755#define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1756
1757
1758/*RAID Physical Disk Page 1 */
1759
1760/*
1761 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1762 *one and check the value returned for NumPhysDiskPaths at runtime.
1763 */
1764#ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1765#define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1766#endif
1767
1768typedef struct _MPI2_RAIDPHYSDISK1_PATH {
1769 U16 DevHandle; /*0x00 */
1770 U16 Reserved1; /*0x02 */
1771 U64 WWID; /*0x04 */
1772 U64 OwnerWWID; /*0x0C */
1773 U8 OwnerIdentifier; /*0x14 */
1774 U8 Reserved2; /*0x15 */
1775 U16 Flags; /*0x16 */
1776} MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH,
1777 Mpi2RaidPhysDisk1Path_t,
1778 *pMpi2RaidPhysDisk1Path_t;
1779
1780/*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1781#define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1782#define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1783#define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1784
1785typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 {
1786 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */
1787 U8 NumPhysDiskPaths; /*0x04 */
1788 U8 PhysDiskNum; /*0x05 */
1789 U16 Reserved1; /*0x06 */
1790 U32 Reserved2; /*0x08 */
1791 MPI2_RAIDPHYSDISK1_PATH
1792 PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/*0x0C */
1793} MPI2_CONFIG_PAGE_RD_PDISK_1,
1794 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1795 Mpi2RaidPhysDiskPage1_t,
1796 *pMpi2RaidPhysDiskPage1_t;
1797
1798#define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1799
1800
1801/****************************************************************************
1802* values for fields used by several types of SAS Config Pages
1803****************************************************************************/
1804
1805/*values for NegotiatedLinkRates fields */
1806#define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1807#define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1808#define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1809/*link rates used for Negotiated Physical and Logical Link Rate */
1810#define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1811#define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1812#define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1813#define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1814#define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1815#define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1816#define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1817#define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1818#define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1819#define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1820#define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B)
1821
1822
1823/*values for AttachedPhyInfo fields */
1824#define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1825#define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1826#define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1827
1828#define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1829#define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1830#define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1831#define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1832#define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1833#define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1834#define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1835#define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1836#define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1837#define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1838
1839
1840/*values for PhyInfo fields */
1841#define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1842
1843#define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1844#define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1845#define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1846#define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1847#define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1848
1849#define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1850#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1851#define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1852#define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1853#define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1854#define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1855
1856#define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1857#define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1858#define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1859#define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1860#define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1861#define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1862#define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1863#define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1864#define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1865#define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1866
1867#define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1868#define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1869#define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1870#define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1871
1872#define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1873#define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1874
1875#define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1876#define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1877#define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1878#define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1879
1880
1881/*values for SAS ProgrammedLinkRate fields */
1882#define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1883#define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1884#define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1885#define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1886#define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1887#define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1888#define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1889#define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1890#define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1891#define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1892#define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B)
1893
1894
1895/*values for SAS HwLinkRate fields */
1896#define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1897#define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1898#define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1899#define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1900#define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1901#define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1902#define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1903#define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1904#define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B)
1905
1906
1907
1908/****************************************************************************
1909* SAS IO Unit Config Pages
1910****************************************************************************/
1911
1912/*SAS IO Unit Page 0 */
1913
1914typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA {
1915 U8 Port; /*0x00 */
1916 U8 PortFlags; /*0x01 */
1917 U8 PhyFlags; /*0x02 */
1918 U8 NegotiatedLinkRate; /*0x03 */
1919 U32 ControllerPhyDeviceInfo;/*0x04 */
1920 U16 AttachedDevHandle; /*0x08 */
1921 U16 ControllerDevHandle; /*0x0A */
1922 U32 DiscoveryStatus; /*0x0C */
1923 U32 Reserved; /*0x10 */
1924} MPI2_SAS_IO_UNIT0_PHY_DATA,
1925 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1926 Mpi2SasIOUnit0PhyData_t,
1927 *pMpi2SasIOUnit0PhyData_t;
1928
1929/*
1930 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1931 *one and check the value returned for NumPhys at runtime.
1932 */
1933#ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1934#define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1935#endif
1936
1937typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 {
1938 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
1939 U32 Reserved1;/*0x08 */
1940 U8 NumPhys; /*0x0C */
1941 U8 Reserved2;/*0x0D */
1942 U16 Reserved3;/*0x0E */
1943 MPI2_SAS_IO_UNIT0_PHY_DATA
1944 PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /*0x10 */
1945} MPI2_CONFIG_PAGE_SASIOUNIT_0,
1946 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1947 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t;
1948
1949#define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1950
1951/*values for SAS IO Unit Page 0 PortFlags */
1952#define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1953#define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1954
1955/*values for SAS IO Unit Page 0 PhyFlags */
1956#define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1957#define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1958
1959/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1960
1961/*see mpi2_sas.h for values for
1962 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1963
1964/*values for SAS IO Unit Page 0 DiscoveryStatus */
1965#define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1966#define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1967#define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1968#define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1969#define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1970#define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1971#define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1972#define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1973#define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1974#define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1975#define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1976#define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1977#define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1978#define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1979#define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1980#define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1981#define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1982#define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1983#define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1984#define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1985
1986
1987/*SAS IO Unit Page 1 */
1988
1989typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA {
1990 U8 Port; /*0x00 */
1991 U8 PortFlags; /*0x01 */
1992 U8 PhyFlags; /*0x02 */
1993 U8 MaxMinLinkRate; /*0x03 */
1994 U32 ControllerPhyDeviceInfo; /*0x04 */
1995 U16 MaxTargetPortConnectTime; /*0x08 */
1996 U16 Reserved1; /*0x0A */
1997} MPI2_SAS_IO_UNIT1_PHY_DATA,
1998 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1999 Mpi2SasIOUnit1PhyData_t,
2000 *pMpi2SasIOUnit1PhyData_t;
2001
2002/*
2003 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2004 *one and check the value returned for NumPhys at runtime.
2005 */
2006#ifndef MPI2_SAS_IOUNIT1_PHY_MAX
2007#define MPI2_SAS_IOUNIT1_PHY_MAX (1)
2008#endif
2009
2010typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 {
2011 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2012 U16
2013 ControlFlags; /*0x08 */
2014 U16
2015 SASNarrowMaxQueueDepth; /*0x0A */
2016 U16
2017 AdditionalControlFlags; /*0x0C */
2018 U16
2019 SASWideMaxQueueDepth; /*0x0E */
2020 U8
2021 NumPhys; /*0x10 */
2022 U8
2023 SATAMaxQDepth; /*0x11 */
2024 U8
2025 ReportDeviceMissingDelay; /*0x12 */
2026 U8
2027 IODeviceMissingDelay; /*0x13 */
2028 MPI2_SAS_IO_UNIT1_PHY_DATA
2029 PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /*0x14 */
2030} MPI2_CONFIG_PAGE_SASIOUNIT_1,
2031 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
2032 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t;
2033
2034#define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
2035
2036/*values for SAS IO Unit Page 1 ControlFlags */
2037#define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2038#define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2039#define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2040#define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2041
2042#define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2043#define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2044#define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
2045#define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
2046#define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
2047
2048#define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2049#define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2050#define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2051#define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2052#define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
2053#define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2054#define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2055#define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2056
2057/*values for SAS IO Unit Page 1 AdditionalControlFlags */
2058#define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
2059#define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
2060#define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
2061#define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
2062#define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
2063#define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
2064#define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
2065#define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
2066
2067/*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
2068#define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
2069#define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
2070
2071/*values for SAS IO Unit Page 1 PortFlags */
2072#define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2073
2074/*values for SAS IO Unit Page 1 PhyFlags */
2075#define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
2076#define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
2077
2078/*values for SAS IO Unit Page 1 MaxMinLinkRate */
2079#define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
2080#define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
2081#define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
2082#define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
2083#define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0)
2084#define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
2085#define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
2086#define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
2087#define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
2088#define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B)
2089
2090/*see mpi2_sas.h for values for
2091 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2092
2093
2094/*SAS IO Unit Page 4 */
2095
2096typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP {
2097 U8 MaxTargetSpinup; /*0x00 */
2098 U8 SpinupDelay; /*0x01 */
2099 U8 SpinupFlags; /*0x02 */
2100 U8 Reserved1; /*0x03 */
2101} MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2102 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2103 Mpi2SasIOUnit4SpinupGroup_t,
2104 *pMpi2SasIOUnit4SpinupGroup_t;
2105/*defines for SAS IO Unit Page 4 SpinupFlags */
2106#define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2107
2108
2109/*
2110 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2111 *one and check the value returned for NumPhys at runtime.
2112 */
2113#ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2114#define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2115#endif
2116
2117typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 {
2118 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */
2119 MPI2_SAS_IOUNIT4_SPINUP_GROUP
2120 SpinupGroupParameters[4]; /*0x08 */
2121 U32
2122 Reserved1; /*0x18 */
2123 U32
2124 Reserved2; /*0x1C */
2125 U32
2126 Reserved3; /*0x20 */
2127 U8
2128 BootDeviceWaitTime; /*0x24 */
2129 U8
2130 Reserved4; /*0x25 */
2131 U16
2132 Reserved5; /*0x26 */
2133 U8
2134 NumPhys; /*0x28 */
2135 U8
2136 PEInitialSpinupDelay; /*0x29 */
2137 U8
2138 PEReplyDelay; /*0x2A */
2139 U8
2140 Flags; /*0x2B */
2141 U8
2142 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */
2143} MPI2_CONFIG_PAGE_SASIOUNIT_4,
2144 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2145 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t;
2146
2147#define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2148
2149/*defines for Flags field */
2150#define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2151
2152/*defines for PHY field */
2153#define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2154
2155
2156/*SAS IO Unit Page 5 */
2157
2158typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2159 U8 ControlFlags; /*0x00 */
2160 U8 PortWidthModGroup; /*0x01 */
2161 U16 InactivityTimerExponent; /*0x02 */
2162 U8 SATAPartialTimeout; /*0x04 */
2163 U8 Reserved2; /*0x05 */
2164 U8 SATASlumberTimeout; /*0x06 */
2165 U8 Reserved3; /*0x07 */
2166 U8 SASPartialTimeout; /*0x08 */
2167 U8 Reserved4; /*0x09 */
2168 U8 SASSlumberTimeout; /*0x0A */
2169 U8 Reserved5; /*0x0B */
2170} MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2171 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2172 Mpi2SasIOUnit5PhyPmSettings_t,
2173 *pMpi2SasIOUnit5PhyPmSettings_t;
2174
2175/*defines for ControlFlags field */
2176#define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2177#define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2178#define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2179#define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2180
2181/*defines for PortWidthModeGroup field */
2182#define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2183
2184/*defines for InactivityTimerExponent field */
2185#define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2186#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2187#define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2188#define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2189#define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2190#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2191#define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2192#define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2193
2194#define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2195#define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2196#define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2197#define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2198#define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2199#define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2200#define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2201#define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2202
2203/*
2204 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2205 *one and check the value returned for NumPhys at runtime.
2206 */
2207#ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2208#define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2209#endif
2210
2211typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2212 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2213 U8 NumPhys; /*0x08 */
2214 U8 Reserved1;/*0x09 */
2215 U16 Reserved2;/*0x0A */
2216 U32 Reserved3;/*0x0C */
2217 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS
2218 SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX];/*0x10 */
2219} MPI2_CONFIG_PAGE_SASIOUNIT_5,
2220 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2221 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t;
2222
2223#define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2224
2225
2226/*SAS IO Unit Page 6 */
2227
2228typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2229 U8 CurrentStatus; /*0x00 */
2230 U8 CurrentModulation; /*0x01 */
2231 U8 CurrentUtilization; /*0x02 */
2232 U8 Reserved1; /*0x03 */
2233 U32 Reserved2; /*0x04 */
2234} MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2235 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2236 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2237 *pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2238
2239/*defines for CurrentStatus field */
2240#define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2241#define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2242#define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2243#define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2244#define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2245#define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2246#define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2247#define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2248
2249/*defines for CurrentModulation field */
2250#define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2251#define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2252#define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2253#define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2254
2255/*
2256 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2257 *one and check the value returned for NumGroups at runtime.
2258 */
2259#ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2260#define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2261#endif
2262
2263typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2264 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2265 U32 Reserved1; /*0x08 */
2266 U32 Reserved2; /*0x0C */
2267 U8 NumGroups; /*0x10 */
2268 U8 Reserved3; /*0x11 */
2269 U16 Reserved4; /*0x12 */
2270 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2271 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /*0x14 */
2272} MPI2_CONFIG_PAGE_SASIOUNIT_6,
2273 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2274 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t;
2275
2276#define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2277
2278
2279/*SAS IO Unit Page 7 */
2280
2281typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2282 U8 Flags; /*0x00 */
2283 U8 Reserved1; /*0x01 */
2284 U16 Reserved2; /*0x02 */
2285 U8 Threshold75Pct; /*0x04 */
2286 U8 Threshold50Pct; /*0x05 */
2287 U8 Threshold25Pct; /*0x06 */
2288 U8 Reserved3; /*0x07 */
2289} MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2290 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2291 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2292 *pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2293
2294/*defines for Flags field */
2295#define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2296
2297
2298/*
2299 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2300 *one and check the value returned for NumGroups at runtime.
2301 */
2302#ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2303#define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2304#endif
2305
2306typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2307 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
2308 U8 SamplingInterval; /*0x08 */
2309 U8 WindowLength; /*0x09 */
2310 U16 Reserved1; /*0x0A */
2311 U32 Reserved2; /*0x0C */
2312 U32 Reserved3; /*0x10 */
2313 U8 NumGroups; /*0x14 */
2314 U8 Reserved4; /*0x15 */
2315 U16 Reserved5; /*0x16 */
2316 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2317 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX];/*0x18 */
2318} MPI2_CONFIG_PAGE_SASIOUNIT_7,
2319 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2320 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t;
2321
2322#define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2323
2324
2325/*SAS IO Unit Page 8 */
2326
2327typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2328 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2329 Header; /*0x00 */
2330 U32
2331 Reserved1; /*0x08 */
2332 U32
2333 PowerManagementCapabilities; /*0x0C */
2334 U8
2335 TxRxSleepStatus; /*0x10 */
2336 U8
2337 Reserved2; /*0x11 */
2338 U16
2339 Reserved3; /*0x12 */
2340} MPI2_CONFIG_PAGE_SASIOUNIT_8,
2341 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2342 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t;
2343
2344#define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2345
2346/*defines for PowerManagementCapabilities field */
2347#define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2348#define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2349#define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2350#define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2351#define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2352#define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2353#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2354#define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2355#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2356#define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2357
2358/*defines for TxRxSleepStatus field */
2359#define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00)
2360#define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01)
2361#define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02)
2362#define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03)
2363
2364
2365
2366/*SAS IO Unit Page 16 */
2367
2368typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2369 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2370 Header; /*0x00 */
2371 U64
2372 TimeStamp; /*0x08 */
2373 U32
2374 Reserved1; /*0x10 */
2375 U32
2376 Reserved2; /*0x14 */
2377 U32
2378 FastPathPendedRequests; /*0x18 */
2379 U32
2380 FastPathUnPendedRequests; /*0x1C */
2381 U32
2382 FastPathHostRequestStarts; /*0x20 */
2383 U32
2384 FastPathFirmwareRequestStarts; /*0x24 */
2385 U32
2386 FastPathHostCompletions; /*0x28 */
2387 U32
2388 FastPathFirmwareCompletions; /*0x2C */
2389 U32
2390 NonFastPathRequestStarts; /*0x30 */
2391 U32
2392 NonFastPathHostCompletions; /*0x30 */
2393} MPI2_CONFIG_PAGE_SASIOUNIT16,
2394 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2395 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t;
2396
2397#define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2398
2399
2400/****************************************************************************
2401* SAS Expander Config Pages
2402****************************************************************************/
2403
2404/*SAS Expander Page 0 */
2405
2406typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 {
2407 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2408 Header; /*0x00 */
2409 U8
2410 PhysicalPort; /*0x08 */
2411 U8
2412 ReportGenLength; /*0x09 */
2413 U16
2414 EnclosureHandle; /*0x0A */
2415 U64
2416 SASAddress; /*0x0C */
2417 U32
2418 DiscoveryStatus; /*0x14 */
2419 U16
2420 DevHandle; /*0x18 */
2421 U16
2422 ParentDevHandle; /*0x1A */
2423 U16
2424 ExpanderChangeCount; /*0x1C */
2425 U16
2426 ExpanderRouteIndexes; /*0x1E */
2427 U8
2428 NumPhys; /*0x20 */
2429 U8
2430 SASLevel; /*0x21 */
2431 U16
2432 Flags; /*0x22 */
2433 U16
2434 STPBusInactivityTimeLimit; /*0x24 */
2435 U16
2436 STPMaxConnectTimeLimit; /*0x26 */
2437 U16
2438 STP_SMP_NexusLossTime; /*0x28 */
2439 U16
2440 MaxNumRoutedSasAddresses; /*0x2A */
2441 U64
2442 ActiveZoneManagerSASAddress;/*0x2C */
2443 U16
2444 ZoneLockInactivityLimit; /*0x34 */
2445 U16
2446 Reserved1; /*0x36 */
2447 U8
2448 TimeToReducedFunc; /*0x38 */
2449 U8
2450 InitialTimeToReducedFunc; /*0x39 */
2451 U8
2452 MaxReducedFuncTime; /*0x3A */
2453 U8
2454 Reserved2; /*0x3B */
2455} MPI2_CONFIG_PAGE_EXPANDER_0,
2456 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2457 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t;
2458
2459#define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2460
2461/*values for SAS Expander Page 0 DiscoveryStatus field */
2462#define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2463#define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2464#define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2465#define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2466#define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2467#define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2468#define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2469#define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2470#define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2471#define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2472#define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2473#define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2474#define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2475#define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2476#define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2477#define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2478#define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2479#define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2480#define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2481#define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2482
2483/*values for SAS Expander Page 0 Flags field */
2484#define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2485#define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2486#define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2487#define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2488#define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2489#define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2490#define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2491#define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2492#define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2493#define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2494#define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2495
2496
2497/*SAS Expander Page 1 */
2498
2499typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 {
2500 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2501 Header; /*0x00 */
2502 U8
2503 PhysicalPort; /*0x08 */
2504 U8
2505 Reserved1; /*0x09 */
2506 U16
2507 Reserved2; /*0x0A */
2508 U8
2509 NumPhys; /*0x0C */
2510 U8
2511 Phy; /*0x0D */
2512 U16
2513 NumTableEntriesProgrammed; /*0x0E */
2514 U8
2515 ProgrammedLinkRate; /*0x10 */
2516 U8
2517 HwLinkRate; /*0x11 */
2518 U16
2519 AttachedDevHandle; /*0x12 */
2520 U32
2521 PhyInfo; /*0x14 */
2522 U32
2523 AttachedDeviceInfo; /*0x18 */
2524 U16
2525 ExpanderDevHandle; /*0x1C */
2526 U8
2527 ChangeCount; /*0x1E */
2528 U8
2529 NegotiatedLinkRate; /*0x1F */
2530 U8
2531 PhyIdentifier; /*0x20 */
2532 U8
2533 AttachedPhyIdentifier; /*0x21 */
2534 U8
2535 Reserved3; /*0x22 */
2536 U8
2537 DiscoveryInfo; /*0x23 */
2538 U32
2539 AttachedPhyInfo; /*0x24 */
2540 U8
2541 ZoneGroup; /*0x28 */
2542 U8
2543 SelfConfigStatus; /*0x29 */
2544 U16
2545 Reserved4; /*0x2A */
2546} MPI2_CONFIG_PAGE_EXPANDER_1,
2547 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2548 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t;
2549
2550#define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2551
2552/*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2553
2554/*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2555
2556/*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2557
2558/*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines
2559 *used for the AttachedDeviceInfo field */
2560
2561/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2562
2563/*values for SAS Expander Page 1 DiscoveryInfo field */
2564#define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2565#define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2566#define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2567
2568/*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2569
2570
2571/****************************************************************************
2572* SAS Device Config Pages
2573****************************************************************************/
2574
2575/*SAS Device Page 0 */
2576
2577typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 {
2578 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2579 Header; /*0x00 */
2580 U16
2581 Slot; /*0x08 */
2582 U16
2583 EnclosureHandle; /*0x0A */
2584 U64
2585 SASAddress; /*0x0C */
2586 U16
2587 ParentDevHandle; /*0x14 */
2588 U8
2589 PhyNum; /*0x16 */
2590 U8
2591 AccessStatus; /*0x17 */
2592 U16
2593 DevHandle; /*0x18 */
2594 U8
2595 AttachedPhyIdentifier; /*0x1A */
2596 U8
2597 ZoneGroup; /*0x1B */
2598 U32
2599 DeviceInfo; /*0x1C */
2600 U16
2601 Flags; /*0x20 */
2602 U8
2603 PhysicalPort; /*0x22 */
2604 U8
2605 MaxPortConnections; /*0x23 */
2606 U64
2607 DeviceName; /*0x24 */
2608 U8
2609 PortGroups; /*0x2C */
2610 U8
2611 DmaGroup; /*0x2D */
2612 U8
2613 ControlGroup; /*0x2E */
2614 U8
2615 Reserved1; /*0x2F */
2616 U32
2617 Reserved2; /*0x30 */
2618 U32
2619 Reserved3; /*0x34 */
2620} MPI2_CONFIG_PAGE_SAS_DEV_0,
2621 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2622 Mpi2SasDevicePage0_t,
2623 *pMpi2SasDevicePage0_t;
2624
2625#define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2626
2627/*values for SAS Device Page 0 AccessStatus field */
2628#define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2629#define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2630#define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2631#define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2632#define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2633#define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2634#define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2635#define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2636/*specific values for SATA Init failures */
2637#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2638#define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2639#define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2640#define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2641#define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2642#define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2643#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2644#define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2645#define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2646#define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2647#define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2648
2649/*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2650
2651/*values for SAS Device Page 0 Flags field */
2652#define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2653#define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000)
2654#define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000)
2655#define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2656#define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2657#define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2658#define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2659#define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2660#define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2661#define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2662#define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2663#define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2664#define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2665#define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2666
2667
2668/*SAS Device Page 1 */
2669
2670typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 {
2671 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2672 Header; /*0x00 */
2673 U32
2674 Reserved1; /*0x08 */
2675 U64
2676 SASAddress; /*0x0C */
2677 U32
2678 Reserved2; /*0x14 */
2679 U16
2680 DevHandle; /*0x18 */
2681 U16
2682 Reserved3; /*0x1A */
2683 U8
2684 InitialRegDeviceFIS[20];/*0x1C */
2685} MPI2_CONFIG_PAGE_SAS_DEV_1,
2686 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2687 Mpi2SasDevicePage1_t,
2688 *pMpi2SasDevicePage1_t;
2689
2690#define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2691
2692
2693/****************************************************************************
2694* SAS PHY Config Pages
2695****************************************************************************/
2696
2697/*SAS PHY Page 0 */
2698
2699typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 {
2700 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2701 Header; /*0x00 */
2702 U16
2703 OwnerDevHandle; /*0x08 */
2704 U16
2705 Reserved1; /*0x0A */
2706 U16
2707 AttachedDevHandle; /*0x0C */
2708 U8
2709 AttachedPhyIdentifier; /*0x0E */
2710 U8
2711 Reserved2; /*0x0F */
2712 U32
2713 AttachedPhyInfo; /*0x10 */
2714 U8
2715 ProgrammedLinkRate; /*0x14 */
2716 U8
2717 HwLinkRate; /*0x15 */
2718 U8
2719 ChangeCount; /*0x16 */
2720 U8
2721 Flags; /*0x17 */
2722 U32
2723 PhyInfo; /*0x18 */
2724 U8
2725 NegotiatedLinkRate; /*0x1C */
2726 U8
2727 Reserved3; /*0x1D */
2728 U16
2729 Reserved4; /*0x1E */
2730} MPI2_CONFIG_PAGE_SAS_PHY_0,
2731 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2732 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t;
2733
2734#define MPI2_SASPHY0_PAGEVERSION (0x03)
2735
2736/*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2737
2738/*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2739
2740/*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2741
2742/*values for SAS PHY Page 0 Flags field */
2743#define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2744
2745/*use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2746
2747/*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2748
2749
2750/*SAS PHY Page 1 */
2751
2752typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 {
2753 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2754 Header; /*0x00 */
2755 U32
2756 Reserved1; /*0x08 */
2757 U32
2758 InvalidDwordCount; /*0x0C */
2759 U32
2760 RunningDisparityErrorCount; /*0x10 */
2761 U32
2762 LossDwordSynchCount; /*0x14 */
2763 U32
2764 PhyResetProblemCount; /*0x18 */
2765} MPI2_CONFIG_PAGE_SAS_PHY_1,
2766 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2767 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t;
2768
2769#define MPI2_SASPHY1_PAGEVERSION (0x01)
2770
2771
2772/*SAS PHY Page 2 */
2773
2774typedef struct _MPI2_SASPHY2_PHY_EVENT {
2775 U8 PhyEventCode; /*0x00 */
2776 U8 Reserved1; /*0x01 */
2777 U16 Reserved2; /*0x02 */
2778 U32 PhyEventInfo; /*0x04 */
2779} MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT,
2780 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t;
2781
2782/*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2783
2784
2785/*
2786 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2787 *one and check the value returned for NumPhyEvents at runtime.
2788 */
2789#ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2790#define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2791#endif
2792
2793typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2794 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2795 Header; /*0x00 */
2796 U32
2797 Reserved1; /*0x08 */
2798 U8
2799 NumPhyEvents; /*0x0C */
2800 U8
2801 Reserved2; /*0x0D */
2802 U16
2803 Reserved3; /*0x0E */
2804 MPI2_SASPHY2_PHY_EVENT
2805 PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /*0x10 */
2806} MPI2_CONFIG_PAGE_SAS_PHY_2,
2807 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2808 Mpi2SasPhyPage2_t,
2809 *pMpi2SasPhyPage2_t;
2810
2811#define MPI2_SASPHY2_PAGEVERSION (0x00)
2812
2813
2814/*SAS PHY Page 3 */
2815
2816typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2817 U8 PhyEventCode; /*0x00 */
2818 U8 Reserved1; /*0x01 */
2819 U16 Reserved2; /*0x02 */
2820 U8 CounterType; /*0x04 */
2821 U8 ThresholdWindow; /*0x05 */
2822 U8 TimeUnits; /*0x06 */
2823 U8 Reserved3; /*0x07 */
2824 U32 EventThreshold; /*0x08 */
2825 U16 ThresholdFlags; /*0x0C */
2826 U16 Reserved4; /*0x0E */
2827} MPI2_SASPHY3_PHY_EVENT_CONFIG,
2828 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2829 Mpi2SasPhy3PhyEventConfig_t,
2830 *pMpi2SasPhy3PhyEventConfig_t;
2831
2832/*values for PhyEventCode field */
2833#define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2834#define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2835#define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2836#define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2837#define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2838#define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2839#define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2840#define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2841#define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2842#define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2843#define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2844#define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2845#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2846#define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2847#define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2848#define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2849#define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2850#define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2851#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2852#define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2853#define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2854#define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2855#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2856#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2857#define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2858#define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2859#define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2860#define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2861#define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2862#define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2863#define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2864#define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2865#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2866#define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2867#define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2868#define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2869#define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2870
2871/*values for the CounterType field */
2872#define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2873#define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2874#define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2875
2876/*values for the TimeUnits field */
2877#define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2878#define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2879#define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2880#define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2881
2882/*values for the ThresholdFlags field */
2883#define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2884#define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2885
2886/*
2887 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2888 *one and check the value returned for NumPhyEvents at runtime.
2889 */
2890#ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2891#define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2892#endif
2893
2894typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2895 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2896 Header; /*0x00 */
2897 U32
2898 Reserved1; /*0x08 */
2899 U8
2900 NumPhyEvents; /*0x0C */
2901 U8
2902 Reserved2; /*0x0D */
2903 U16
2904 Reserved3; /*0x0E */
2905 MPI2_SASPHY3_PHY_EVENT_CONFIG
2906 PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /*0x10 */
2907} MPI2_CONFIG_PAGE_SAS_PHY_3,
2908 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2909 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t;
2910
2911#define MPI2_SASPHY3_PAGEVERSION (0x00)
2912
2913
2914/*SAS PHY Page 4 */
2915
2916typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2917 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2918 Header; /*0x00 */
2919 U16
2920 Reserved1; /*0x08 */
2921 U8
2922 Reserved2; /*0x0A */
2923 U8
2924 Flags; /*0x0B */
2925 U8
2926 InitialFrame[28]; /*0x0C */
2927} MPI2_CONFIG_PAGE_SAS_PHY_4,
2928 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2929 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t;
2930
2931#define MPI2_SASPHY4_PAGEVERSION (0x00)
2932
2933/*values for the Flags field */
2934#define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2935#define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2936
2937
2938
2939
2940/****************************************************************************
2941* SAS Port Config Pages
2942****************************************************************************/
2943
2944/*SAS Port Page 0 */
2945
2946typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 {
2947 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2948 Header; /*0x00 */
2949 U8
2950 PortNumber; /*0x08 */
2951 U8
2952 PhysicalPort; /*0x09 */
2953 U8
2954 PortWidth; /*0x0A */
2955 U8
2956 PhysicalPortWidth; /*0x0B */
2957 U8
2958 ZoneGroup; /*0x0C */
2959 U8
2960 Reserved1; /*0x0D */
2961 U16
2962 Reserved2; /*0x0E */
2963 U64
2964 SASAddress; /*0x10 */
2965 U32
2966 DeviceInfo; /*0x18 */
2967 U32
2968 Reserved3; /*0x1C */
2969 U32
2970 Reserved4; /*0x20 */
2971} MPI2_CONFIG_PAGE_SAS_PORT_0,
2972 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2973 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t;
2974
2975#define MPI2_SASPORT0_PAGEVERSION (0x00)
2976
2977/*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2978
2979
2980/****************************************************************************
2981* SAS Enclosure Config Pages
2982****************************************************************************/
2983
2984/*SAS Enclosure Page 0 */
2985
2986typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
2987 MPI2_CONFIG_EXTENDED_PAGE_HEADER
2988 Header; /*0x00 */
2989 U32
2990 Reserved1; /*0x08 */
2991 U64
2992 EnclosureLogicalID; /*0x0C */
2993 U16
2994 Flags; /*0x14 */
2995 U16
2996 EnclosureHandle; /*0x16 */
2997 U16
2998 NumSlots; /*0x18 */
2999 U16
3000 StartSlot; /*0x1A */
3001 U16
3002 Reserved2; /*0x1C */
3003 U16
3004 SEPDevHandle; /*0x1E */
3005 U32
3006 Reserved3; /*0x20 */
3007 U32
3008 Reserved4; /*0x24 */
3009} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3010 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3011 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t;
3012
3013#define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
3014
3015/*values for SAS Enclosure Page 0 Flags field */
3016#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
3017#define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
3018#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
3019#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
3020#define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
3021#define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
3022#define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
3023
3024
3025/****************************************************************************
3026* Log Config Page
3027****************************************************************************/
3028
3029/*Log Page 0 */
3030
3031/*
3032 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3033 *one and check the value returned for NumLogEntries at runtime.
3034 */
3035#ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
3036#define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
3037#endif
3038
3039#define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
3040
3041typedef struct _MPI2_LOG_0_ENTRY {
3042 U64 TimeStamp; /*0x00 */
3043 U32 Reserved1; /*0x08 */
3044 U16 LogSequence; /*0x0C */
3045 U16 LogEntryQualifier; /*0x0E */
3046 U8 VP_ID; /*0x10 */
3047 U8 VF_ID; /*0x11 */
3048 U16 Reserved2; /*0x12 */
3049 U8
3050 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */
3051} MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY,
3052 Mpi2Log0Entry_t, *pMpi2Log0Entry_t;
3053
3054/*values for Log Page 0 LogEntry LogEntryQualifier field */
3055#define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
3056#define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
3057#define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
3058#define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
3059#define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
3060
3061typedef struct _MPI2_CONFIG_PAGE_LOG_0 {
3062 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3063 U32 Reserved1; /*0x08 */
3064 U32 Reserved2; /*0x0C */
3065 U16 NumLogEntries;/*0x10 */
3066 U16 Reserved3; /*0x12 */
3067 MPI2_LOG_0_ENTRY
3068 LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /*0x14 */
3069} MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0,
3070 Mpi2LogPage0_t, *pMpi2LogPage0_t;
3071
3072#define MPI2_LOG_0_PAGEVERSION (0x02)
3073
3074
3075/****************************************************************************
3076* RAID Config Page
3077****************************************************************************/
3078
3079/*RAID Page 0 */
3080
3081/*
3082 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
3083 *one and check the value returned for NumElements at runtime.
3084 */
3085#ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
3086#define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
3087#endif
3088
3089typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT {
3090 U16 ElementFlags; /*0x00 */
3091 U16 VolDevHandle; /*0x02 */
3092 U8 HotSparePool; /*0x04 */
3093 U8 PhysDiskNum; /*0x05 */
3094 U16 PhysDiskDevHandle; /*0x06 */
3095} MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3096 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
3097 Mpi2RaidConfig0ConfigElement_t,
3098 *pMpi2RaidConfig0ConfigElement_t;
3099
3100/*values for the ElementFlags field */
3101#define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
3102#define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
3103#define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
3104#define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
3105#define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
3106
3107
3108typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 {
3109 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3110 U8 NumHotSpares; /*0x08 */
3111 U8 NumPhysDisks; /*0x09 */
3112 U8 NumVolumes; /*0x0A */
3113 U8 ConfigNum; /*0x0B */
3114 U32 Flags; /*0x0C */
3115 U8 ConfigGUID[24]; /*0x10 */
3116 U32 Reserved1; /*0x28 */
3117 U8 NumElements; /*0x2C */
3118 U8 Reserved2; /*0x2D */
3119 U16 Reserved3; /*0x2E */
3120 MPI2_RAIDCONFIG0_CONFIG_ELEMENT
3121 ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /*0x30 */
3122} MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3123 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
3124 Mpi2RaidConfigurationPage0_t,
3125 *pMpi2RaidConfigurationPage0_t;
3126
3127#define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
3128
3129/*values for RAID Configuration Page 0 Flags field */
3130#define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
3131
3132
3133/****************************************************************************
3134* Driver Persistent Mapping Config Pages
3135****************************************************************************/
3136
3137/*Driver Persistent Mapping Page 0 */
3138
3139typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY {
3140 U64 PhysicalIdentifier; /*0x00 */
3141 U16 MappingInformation; /*0x08 */
3142 U16 DeviceIndex; /*0x0A */
3143 U32 PhysicalBitsMapping; /*0x0C */
3144 U32 Reserved1; /*0x10 */
3145} MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3146 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
3147 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t;
3148
3149typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 {
3150 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3151 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */
3152} MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3153 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
3154 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t;
3155
3156#define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
3157
3158/*values for Driver Persistent Mapping Page 0 MappingInformation field */
3159#define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
3160#define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
3161#define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
3162
3163
3164/****************************************************************************
3165* Ethernet Config Pages
3166****************************************************************************/
3167
3168/*Ethernet Page 0 */
3169
3170/*IP address (union of IPv4 and IPv6) */
3171typedef union _MPI2_ETHERNET_IP_ADDR {
3172 U32 IPv4Addr;
3173 U32 IPv6Addr[4];
3174} MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR,
3175 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t;
3176
3177#define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
3178
3179typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
3180 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */
3181 U8 NumInterfaces; /*0x08 */
3182 U8 Reserved0; /*0x09 */
3183 U16 Reserved1; /*0x0A */
3184 U32 Status; /*0x0C */
3185 U8 MediaState; /*0x10 */
3186 U8 Reserved2; /*0x11 */
3187 U16 Reserved3; /*0x12 */
3188 U8 MacAddress[6]; /*0x14 */
3189 U8 Reserved4; /*0x1A */
3190 U8 Reserved5; /*0x1B */
3191 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */
3192 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */
3193 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */
3194 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */
3195 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */
3196 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */
3197 U8
3198 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3199} MPI2_CONFIG_PAGE_ETHERNET_0,
3200 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
3201 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t;
3202
3203#define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
3204
3205/*values for Ethernet Page 0 Status field */
3206#define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
3207#define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
3208#define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
3209#define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
3210#define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
3211#define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
3212#define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
3213#define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
3214#define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
3215#define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
3216#define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
3217#define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
3218
3219/*values for Ethernet Page 0 MediaState field */
3220#define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
3221#define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
3222#define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
3223
3224#define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
3225#define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
3226#define MPI2_ETHPG0_MS_10MBIT (0x01)
3227#define MPI2_ETHPG0_MS_100MBIT (0x02)
3228#define MPI2_ETHPG0_MS_1GBIT (0x03)
3229
3230
3231/*Ethernet Page 1 */
3232
3233typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
3234 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3235 Header; /*0x00 */
3236 U32
3237 Reserved0; /*0x08 */
3238 U32
3239 Flags; /*0x0C */
3240 U8
3241 MediaState; /*0x10 */
3242 U8
3243 Reserved1; /*0x11 */
3244 U16
3245 Reserved2; /*0x12 */
3246 U8
3247 MacAddress[6]; /*0x14 */
3248 U8
3249 Reserved3; /*0x1A */
3250 U8
3251 Reserved4; /*0x1B */
3252 MPI2_ETHERNET_IP_ADDR
3253 StaticIpAddress; /*0x1C */
3254 MPI2_ETHERNET_IP_ADDR
3255 StaticSubnetMask; /*0x2C */
3256 MPI2_ETHERNET_IP_ADDR
3257 StaticGatewayIpAddress; /*0x3C */
3258 MPI2_ETHERNET_IP_ADDR
3259 StaticDNS1IpAddress; /*0x4C */
3260 MPI2_ETHERNET_IP_ADDR
3261 StaticDNS2IpAddress; /*0x5C */
3262 U32
3263 Reserved5; /*0x6C */
3264 U32
3265 Reserved6; /*0x70 */
3266 U32
3267 Reserved7; /*0x74 */
3268 U32
3269 Reserved8; /*0x78 */
3270 U8
3271 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */
3272} MPI2_CONFIG_PAGE_ETHERNET_1,
3273 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
3274 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t;
3275
3276#define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
3277
3278/*values for Ethernet Page 1 Flags field */
3279#define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
3280#define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
3281#define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
3282#define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
3283#define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
3284#define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
3285#define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
3286#define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
3287#define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
3288
3289/*values for Ethernet Page 1 MediaState field */
3290#define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
3291#define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
3292#define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
3293
3294#define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
3295#define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
3296#define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
3297#define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
3298#define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
3299
3300
3301/****************************************************************************
3302* Extended Manufacturing Config Pages
3303****************************************************************************/
3304
3305/*
3306 *Generic structure to use for product-specific extended manufacturing pages
3307 *(currently Extended Manufacturing Page 40 through Extended Manufacturing
3308 *Page 60).
3309 */
3310
3311typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3312 MPI2_CONFIG_EXTENDED_PAGE_HEADER
3313 Header; /*0x00 */
3314 U32
3315 ProductSpecificInfo; /*0x08 */
3316} MPI2_CONFIG_PAGE_EXT_MAN_PS,
3317 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3318 Mpi2ExtManufacturingPagePS_t,
3319 *pMpi2ExtManufacturingPagePS_t;
3320
3321/*PageVersion should be provided by product-specific code */
3322
3323#endif
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_init.h b/drivers/scsi/mpt3sas/mpi/mpi2_init.h
new file mode 100644
index 000000000000..a079e5242474
--- /dev/null
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_init.h
@@ -0,0 +1,560 @@
1/*
2 * Copyright (c) 2000-2012 LSI Corporation.
3 *
4 *
5 * Name: mpi2_init.h
6 * Title: MPI SCSI initiator mode messages and structures
7 * Creation Date: June 23, 2006
8 *
9 * mpi2_init.h Version: 02.00.14
10 *
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used
13 * with MPI v2.0 products. Unless otherwise noted, names beginning with
14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
15 *
16 * Version History
17 * ---------------
18 *
19 * Date Version Description
20 * -------- -------- ------------------------------------------------------
21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
22 * 10-31-07 02.00.01 Fixed name for pMpi2SCSITaskManagementRequest_t.
23 * 12-18-07 02.00.02 Modified Task Management Target Reset Method defines.
24 * 02-29-08 02.00.03 Added Query Task Set and Query Unit Attention.
25 * 03-03-08 02.00.04 Fixed name of struct _MPI2_SCSI_TASK_MANAGE_REPLY.
26 * 05-21-08 02.00.05 Fixed typo in name of Mpi2SepRequest_t.
27 * 10-02-08 02.00.06 Removed Untagged and No Disconnect values from SCSI IO
28 * Control field Task Attribute flags.
29 * Moved LUN field defines to mpi2.h becasue they are
30 * common to many structures.
31 * 05-06-09 02.00.07 Changed task management type of Query Unit Attention to
32 * Query Asynchronous Event.
33 * Defined two new bits in the SlotStatus field of the SCSI
34 * Enclosure Processor Request and Reply.
35 * 10-28-09 02.00.08 Added defines for decoding the ResponseInfo bytes for
36 * both SCSI IO Error Reply and SCSI Task Management Reply.
37 * Added ResponseInfo field to MPI2_SCSI_TASK_MANAGE_REPLY.
38 * Added MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG define.
39 * 02-10-10 02.00.09 Removed unused structure that had "#if 0" around it.
40 * 05-12-10 02.00.10 Added optional vendor-unique region to SCSI IO Request.
41 * 11-10-10 02.00.11 Added MPI2_SCSIIO_NUM_SGLOFFSETS define.
42 * 11-18-11 02.00.12 Incorporating additions for MPI v2.5.
43 * 02-06-12 02.00.13 Added alternate defines for Task Priority / Command
44 * Priority to match SAM-4.
45 * Added EEDPErrorOffset to MPI2_SCSI_IO_REPLY.
46 * 07-10-12 02.00.14 Added MPI2_SCSIIO_CONTROL_SHIFT_DATADIRECTION.
47 * --------------------------------------------------------------------------
48 */
49
50#ifndef MPI2_INIT_H
51#define MPI2_INIT_H
52
53/*****************************************************************************
54*
55* SCSI Initiator Messages
56*
57*****************************************************************************/
58
59/****************************************************************************
60* SCSI IO messages and associated structures
61****************************************************************************/
62
63typedef struct _MPI2_SCSI_IO_CDB_EEDP32 {
64 U8 CDB[20]; /*0x00 */
65 U32 PrimaryReferenceTag; /*0x14 */
66 U16 PrimaryApplicationTag; /*0x18 */
67 U16 PrimaryApplicationTagMask; /*0x1A */
68 U32 TransferLength; /*0x1C */
69} MPI2_SCSI_IO_CDB_EEDP32, *PTR_MPI2_SCSI_IO_CDB_EEDP32,
70 Mpi2ScsiIoCdbEedp32_t, *pMpi2ScsiIoCdbEedp32_t;
71
72/*MPI v2.0 CDB field */
73typedef union _MPI2_SCSI_IO_CDB_UNION {
74 U8 CDB32[32];
75 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
76 MPI2_SGE_SIMPLE_UNION SGE;
77} MPI2_SCSI_IO_CDB_UNION, *PTR_MPI2_SCSI_IO_CDB_UNION,
78 Mpi2ScsiIoCdb_t, *pMpi2ScsiIoCdb_t;
79
80/*MPI v2.0 SCSI IO Request Message */
81typedef struct _MPI2_SCSI_IO_REQUEST {
82 U16 DevHandle; /*0x00 */
83 U8 ChainOffset; /*0x02 */
84 U8 Function; /*0x03 */
85 U16 Reserved1; /*0x04 */
86 U8 Reserved2; /*0x06 */
87 U8 MsgFlags; /*0x07 */
88 U8 VP_ID; /*0x08 */
89 U8 VF_ID; /*0x09 */
90 U16 Reserved3; /*0x0A */
91 U32 SenseBufferLowAddress; /*0x0C */
92 U16 SGLFlags; /*0x10 */
93 U8 SenseBufferLength; /*0x12 */
94 U8 Reserved4; /*0x13 */
95 U8 SGLOffset0; /*0x14 */
96 U8 SGLOffset1; /*0x15 */
97 U8 SGLOffset2; /*0x16 */
98 U8 SGLOffset3; /*0x17 */
99 U32 SkipCount; /*0x18 */
100 U32 DataLength; /*0x1C */
101 U32 BidirectionalDataLength; /*0x20 */
102 U16 IoFlags; /*0x24 */
103 U16 EEDPFlags; /*0x26 */
104 U32 EEDPBlockSize; /*0x28 */
105 U32 SecondaryReferenceTag; /*0x2C */
106 U16 SecondaryApplicationTag; /*0x30 */
107 U16 ApplicationTagTranslationMask; /*0x32 */
108 U8 LUN[8]; /*0x34 */
109 U32 Control; /*0x3C */
110 MPI2_SCSI_IO_CDB_UNION CDB; /*0x40 */
111
112#ifdef MPI2_SCSI_IO_VENDOR_UNIQUE_REGION /*typically this is left undefined */
113 MPI2_SCSI_IO_VENDOR_UNIQUE VendorRegion;
114#endif
115
116 MPI2_SGE_IO_UNION SGL; /*0x60 */
117
118} MPI2_SCSI_IO_REQUEST, *PTR_MPI2_SCSI_IO_REQUEST,
119 Mpi2SCSIIORequest_t, *pMpi2SCSIIORequest_t;
120
121/*SCSI IO MsgFlags bits */
122
123/*MsgFlags for SenseBufferAddressSpace */
124#define MPI2_SCSIIO_MSGFLAGS_MASK_SENSE_ADDR (0x0C)
125#define MPI2_SCSIIO_MSGFLAGS_SYSTEM_SENSE_ADDR (0x00)
126#define MPI2_SCSIIO_MSGFLAGS_IOCDDR_SENSE_ADDR (0x04)
127#define MPI2_SCSIIO_MSGFLAGS_IOCPLB_SENSE_ADDR (0x08)
128#define MPI2_SCSIIO_MSGFLAGS_IOCPLBNTA_SENSE_ADDR (0x0C)
129
130/*SCSI IO SGLFlags bits */
131
132/*base values for Data Location Address Space */
133#define MPI2_SCSIIO_SGLFLAGS_ADDR_MASK (0x0C)
134#define MPI2_SCSIIO_SGLFLAGS_SYSTEM_ADDR (0x00)
135#define MPI2_SCSIIO_SGLFLAGS_IOCDDR_ADDR (0x04)
136#define MPI2_SCSIIO_SGLFLAGS_IOCPLB_ADDR (0x08)
137#define MPI2_SCSIIO_SGLFLAGS_IOCPLBNTA_ADDR (0x0C)
138
139/*base values for Type */
140#define MPI2_SCSIIO_SGLFLAGS_TYPE_MASK (0x03)
141#define MPI2_SCSIIO_SGLFLAGS_TYPE_MPI (0x00)
142#define MPI2_SCSIIO_SGLFLAGS_TYPE_IEEE32 (0x01)
143#define MPI2_SCSIIO_SGLFLAGS_TYPE_IEEE64 (0x02)
144
145/*shift values for each sub-field */
146#define MPI2_SCSIIO_SGLFLAGS_SGL3_SHIFT (12)
147#define MPI2_SCSIIO_SGLFLAGS_SGL2_SHIFT (8)
148#define MPI2_SCSIIO_SGLFLAGS_SGL1_SHIFT (4)
149#define MPI2_SCSIIO_SGLFLAGS_SGL0_SHIFT (0)
150
151/*number of SGLOffset fields */
152#define MPI2_SCSIIO_NUM_SGLOFFSETS (4)
153
154/*SCSI IO IoFlags bits */
155
156/*Large CDB Address Space */
157#define MPI2_SCSIIO_CDB_ADDR_MASK (0x6000)
158#define MPI2_SCSIIO_CDB_ADDR_SYSTEM (0x0000)
159#define MPI2_SCSIIO_CDB_ADDR_IOCDDR (0x2000)
160#define MPI2_SCSIIO_CDB_ADDR_IOCPLB (0x4000)
161#define MPI2_SCSIIO_CDB_ADDR_IOCPLBNTA (0x6000)
162
163#define MPI2_SCSIIO_IOFLAGS_LARGE_CDB (0x1000)
164#define MPI2_SCSIIO_IOFLAGS_BIDIRECTIONAL (0x0800)
165#define MPI2_SCSIIO_IOFLAGS_MULTICAST (0x0400)
166#define MPI2_SCSIIO_IOFLAGS_CMD_DETERMINES_DATA_DIR (0x0200)
167#define MPI2_SCSIIO_IOFLAGS_CDBLENGTH_MASK (0x01FF)
168
169/*SCSI IO EEDPFlags bits */
170
171#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000)
172#define MPI2_SCSIIO_EEDPFLAGS_INC_SEC_REFTAG (0x4000)
173#define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_APPTAG (0x2000)
174#define MPI2_SCSIIO_EEDPFLAGS_INC_SEC_APPTAG (0x1000)
175
176#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400)
177#define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200)
178#define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100)
179
180#define MPI2_SCSIIO_EEDPFLAGS_PASSTHRU_REFTAG (0x0008)
181
182#define MPI2_SCSIIO_EEDPFLAGS_MASK_OP (0x0007)
183#define MPI2_SCSIIO_EEDPFLAGS_NOOP_OP (0x0000)
184#define MPI2_SCSIIO_EEDPFLAGS_CHECK_OP (0x0001)
185#define MPI2_SCSIIO_EEDPFLAGS_STRIP_OP (0x0002)
186#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003)
187#define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004)
188#define MPI2_SCSIIO_EEDPFLAGS_REPLACE_OP (0x0006)
189#define MPI2_SCSIIO_EEDPFLAGS_CHECK_REGEN_OP (0x0007)
190
191/*SCSI IO LUN fields: use MPI2_LUN_ from mpi2.h */
192
193/*SCSI IO Control bits */
194#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_MASK (0xFC000000)
195#define MPI2_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26)
196
197#define MPI2_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000)
198#define MPI2_SCSIIO_CONTROL_SHIFT_DATADIRECTION (24)
199#define MPI2_SCSIIO_CONTROL_NODATATRANSFER (0x00000000)
200#define MPI2_SCSIIO_CONTROL_WRITE (0x01000000)
201#define MPI2_SCSIIO_CONTROL_READ (0x02000000)
202#define MPI2_SCSIIO_CONTROL_BIDIRECTIONAL (0x03000000)
203
204#define MPI2_SCSIIO_CONTROL_TASKPRI_MASK (0x00007800)
205#define MPI2_SCSIIO_CONTROL_TASKPRI_SHIFT (11)
206/*alternate name for the previous field; called Command Priority in SAM-4 */
207#define MPI2_SCSIIO_CONTROL_CMDPRI_MASK (0x00007800)
208#define MPI2_SCSIIO_CONTROL_CMDPRI_SHIFT (11)
209
210#define MPI2_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700)
211#define MPI2_SCSIIO_CONTROL_SIMPLEQ (0x00000000)
212#define MPI2_SCSIIO_CONTROL_HEADOFQ (0x00000100)
213#define MPI2_SCSIIO_CONTROL_ORDEREDQ (0x00000200)
214#define MPI2_SCSIIO_CONTROL_ACAQ (0x00000400)
215
216#define MPI2_SCSIIO_CONTROL_TLR_MASK (0x000000C0)
217#define MPI2_SCSIIO_CONTROL_NO_TLR (0x00000000)
218#define MPI2_SCSIIO_CONTROL_TLR_ON (0x00000040)
219#define MPI2_SCSIIO_CONTROL_TLR_OFF (0x00000080)
220
221/*MPI v2.5 CDB field */
222typedef union _MPI25_SCSI_IO_CDB_UNION {
223 U8 CDB32[32];
224 MPI2_SCSI_IO_CDB_EEDP32 EEDP32;
225 MPI2_IEEE_SGE_SIMPLE64 SGE;
226} MPI25_SCSI_IO_CDB_UNION, *PTR_MPI25_SCSI_IO_CDB_UNION,
227 Mpi25ScsiIoCdb_t, *pMpi25ScsiIoCdb_t;
228
229/*MPI v2.5 SCSI IO Request Message */
230typedef struct _MPI25_SCSI_IO_REQUEST {
231 U16 DevHandle; /*0x00 */
232 U8 ChainOffset; /*0x02 */
233 U8 Function; /*0x03 */
234 U16 Reserved1; /*0x04 */
235 U8 Reserved2; /*0x06 */
236 U8 MsgFlags; /*0x07 */
237 U8 VP_ID; /*0x08 */
238 U8 VF_ID; /*0x09 */
239 U16 Reserved3; /*0x0A */
240 U32 SenseBufferLowAddress; /*0x0C */
241 U8 DMAFlags; /*0x10 */
242 U8 Reserved5; /*0x11 */
243 U8 SenseBufferLength; /*0x12 */
244 U8 Reserved4; /*0x13 */
245 U8 SGLOffset0; /*0x14 */
246 U8 SGLOffset1; /*0x15 */
247 U8 SGLOffset2; /*0x16 */
248 U8 SGLOffset3; /*0x17 */
249 U32 SkipCount; /*0x18 */
250 U32 DataLength; /*0x1C */
251 U32 BidirectionalDataLength; /*0x20 */
252 U16 IoFlags; /*0x24 */
253 U16 EEDPFlags; /*0x26 */
254 U16 EEDPBlockSize; /*0x28 */
255 U16 Reserved6; /*0x2A */
256 U32 SecondaryReferenceTag; /*0x2C */
257 U16 SecondaryApplicationTag; /*0x30 */
258 U16 ApplicationTagTranslationMask; /*0x32 */
259 U8 LUN[8]; /*0x34 */
260 U32 Control; /*0x3C */
261 MPI25_SCSI_IO_CDB_UNION CDB; /*0x40 */
262
263#ifdef MPI25_SCSI_IO_VENDOR_UNIQUE_REGION /*typically this is left undefined */
264 MPI25_SCSI_IO_VENDOR_UNIQUE VendorRegion;
265#endif
266
267 MPI25_SGE_IO_UNION SGL; /*0x60 */
268
269} MPI25_SCSI_IO_REQUEST, *PTR_MPI25_SCSI_IO_REQUEST,
270 Mpi25SCSIIORequest_t, *pMpi25SCSIIORequest_t;
271
272/*use MPI2_SCSIIO_MSGFLAGS_ defines for the MsgFlags field */
273
274/*Defines for the DMAFlags field
275 * Each setting affects 4 SGLS, from SGL0 to SGL3.
276 * D = Data
277 * C = Cache DIF
278 * I = Interleaved
279 * H = Host DIF
280 */
281#define MPI25_SCSIIO_DMAFLAGS_OP_MASK (0x0F)
282#define MPI25_SCSIIO_DMAFLAGS_OP_D_D_D_D (0x00)
283#define MPI25_SCSIIO_DMAFLAGS_OP_D_D_D_C (0x01)
284#define MPI25_SCSIIO_DMAFLAGS_OP_D_D_D_I (0x02)
285#define MPI25_SCSIIO_DMAFLAGS_OP_D_D_C_C (0x03)
286#define MPI25_SCSIIO_DMAFLAGS_OP_D_D_C_I (0x04)
287#define MPI25_SCSIIO_DMAFLAGS_OP_D_D_I_I (0x05)
288#define MPI25_SCSIIO_DMAFLAGS_OP_D_C_C_C (0x06)
289#define MPI25_SCSIIO_DMAFLAGS_OP_D_C_C_I (0x07)
290#define MPI25_SCSIIO_DMAFLAGS_OP_D_C_I_I (0x08)
291#define MPI25_SCSIIO_DMAFLAGS_OP_D_I_I_I (0x09)
292#define MPI25_SCSIIO_DMAFLAGS_OP_D_H_D_D (0x0A)
293#define MPI25_SCSIIO_DMAFLAGS_OP_D_H_D_C (0x0B)
294#define MPI25_SCSIIO_DMAFLAGS_OP_D_H_D_I (0x0C)
295#define MPI25_SCSIIO_DMAFLAGS_OP_D_H_C_C (0x0D)
296#define MPI25_SCSIIO_DMAFLAGS_OP_D_H_C_I (0x0E)
297#define MPI25_SCSIIO_DMAFLAGS_OP_D_H_I_I (0x0F)
298
299/*number of SGLOffset fields */
300#define MPI25_SCSIIO_NUM_SGLOFFSETS (4)
301
302/*defines for the IoFlags field */
303#define MPI25_SCSIIO_IOFLAGS_IO_PATH_MASK (0xC000)
304#define MPI25_SCSIIO_IOFLAGS_NORMAL_PATH (0x0000)
305#define MPI25_SCSIIO_IOFLAGS_FAST_PATH (0x4000)
306
307#define MPI25_SCSIIO_IOFLAGS_LARGE_CDB (0x1000)
308#define MPI25_SCSIIO_IOFLAGS_BIDIRECTIONAL (0x0800)
309#define MPI25_SCSIIO_IOFLAGS_CDBLENGTH_MASK (0x01FF)
310
311/*MPI v2.5 defines for the EEDPFlags bits */
312/*use MPI2_SCSIIO_EEDPFLAGS_ defines for the other EEDPFlags bits */
313#define MPI25_SCSIIO_EEDPFLAGS_ESCAPE_MODE_MASK (0x00C0)
314#define MPI25_SCSIIO_EEDPFLAGS_COMPATIBLE_MODE (0x0000)
315#define MPI25_SCSIIO_EEDPFLAGS_DO_NOT_DISABLE_MODE (0x0040)
316#define MPI25_SCSIIO_EEDPFLAGS_APPTAG_DISABLE_MODE (0x0080)
317#define MPI25_SCSIIO_EEDPFLAGS_APPTAG_REFTAG_DISABLE_MODE (0x00C0)
318
319#define MPI25_SCSIIO_EEDPFLAGS_HOST_GUARD_METHOD_MASK (0x0030)
320#define MPI25_SCSIIO_EEDPFLAGS_T10_CRC_HOST_GUARD (0x0000)
321#define MPI25_SCSIIO_EEDPFLAGS_IP_CHKSUM_HOST_GUARD (0x0010)
322
323/*use MPI2_LUN_ defines from mpi2.h for the LUN field */
324
325/*use MPI2_SCSIIO_CONTROL_ defines for the Control field */
326
327/*NOTE: The SCSI IO Reply is nearly the same for MPI 2.0 and MPI 2.5, so
328 * MPI2_SCSI_IO_REPLY is used for both.
329 */
330
331/*SCSI IO Error Reply Message */
332typedef struct _MPI2_SCSI_IO_REPLY {
333 U16 DevHandle; /*0x00 */
334 U8 MsgLength; /*0x02 */
335 U8 Function; /*0x03 */
336 U16 Reserved1; /*0x04 */
337 U8 Reserved2; /*0x06 */
338 U8 MsgFlags; /*0x07 */
339 U8 VP_ID; /*0x08 */
340 U8 VF_ID; /*0x09 */
341 U16 Reserved3; /*0x0A */
342 U8 SCSIStatus; /*0x0C */
343 U8 SCSIState; /*0x0D */
344 U16 IOCStatus; /*0x0E */
345 U32 IOCLogInfo; /*0x10 */
346 U32 TransferCount; /*0x14 */
347 U32 SenseCount; /*0x18 */
348 U32 ResponseInfo; /*0x1C */
349 U16 TaskTag; /*0x20 */
350 U16 Reserved4; /*0x22 */
351 U32 BidirectionalTransferCount; /*0x24 */
352 U32 EEDPErrorOffset; /*0x28 *//*MPI 2.5 only; Reserved in MPI 2.0*/
353 U32 Reserved6; /*0x2C */
354} MPI2_SCSI_IO_REPLY, *PTR_MPI2_SCSI_IO_REPLY,
355 Mpi2SCSIIOReply_t, *pMpi2SCSIIOReply_t;
356
357/*SCSI IO Reply SCSIStatus values (SAM-4 status codes) */
358
359#define MPI2_SCSI_STATUS_GOOD (0x00)
360#define MPI2_SCSI_STATUS_CHECK_CONDITION (0x02)
361#define MPI2_SCSI_STATUS_CONDITION_MET (0x04)
362#define MPI2_SCSI_STATUS_BUSY (0x08)
363#define MPI2_SCSI_STATUS_INTERMEDIATE (0x10)
364#define MPI2_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14)
365#define MPI2_SCSI_STATUS_RESERVATION_CONFLICT (0x18)
366#define MPI2_SCSI_STATUS_COMMAND_TERMINATED (0x22) /*obsolete */
367#define MPI2_SCSI_STATUS_TASK_SET_FULL (0x28)
368#define MPI2_SCSI_STATUS_ACA_ACTIVE (0x30)
369#define MPI2_SCSI_STATUS_TASK_ABORTED (0x40)
370
371/*SCSI IO Reply SCSIState flags */
372
373#define MPI2_SCSI_STATE_RESPONSE_INFO_VALID (0x10)
374#define MPI2_SCSI_STATE_TERMINATED (0x08)
375#define MPI2_SCSI_STATE_NO_SCSI_STATUS (0x04)
376#define MPI2_SCSI_STATE_AUTOSENSE_FAILED (0x02)
377#define MPI2_SCSI_STATE_AUTOSENSE_VALID (0x01)
378
379/*masks and shifts for the ResponseInfo field */
380
381#define MPI2_SCSI_RI_MASK_REASONCODE (0x000000FF)
382#define MPI2_SCSI_RI_SHIFT_REASONCODE (0)
383
384#define MPI2_SCSI_TASKTAG_UNKNOWN (0xFFFF)
385
386/****************************************************************************
387* SCSI Task Management messages
388****************************************************************************/
389
390/*SCSI Task Management Request Message */
391typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST {
392 U16 DevHandle; /*0x00 */
393 U8 ChainOffset; /*0x02 */
394 U8 Function; /*0x03 */
395 U8 Reserved1; /*0x04 */
396 U8 TaskType; /*0x05 */
397 U8 Reserved2; /*0x06 */
398 U8 MsgFlags; /*0x07 */
399 U8 VP_ID; /*0x08 */
400 U8 VF_ID; /*0x09 */
401 U16 Reserved3; /*0x0A */
402 U8 LUN[8]; /*0x0C */
403 U32 Reserved4[7]; /*0x14 */
404 U16 TaskMID; /*0x30 */
405 U16 Reserved5; /*0x32 */
406} MPI2_SCSI_TASK_MANAGE_REQUEST,
407 *PTR_MPI2_SCSI_TASK_MANAGE_REQUEST,
408 Mpi2SCSITaskManagementRequest_t,
409 *pMpi2SCSITaskManagementRequest_t;
410
411/*TaskType values */
412
413#define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01)
414#define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02)
415#define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03)
416#define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05)
417#define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06)
418#define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07)
419#define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08)
420#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09)
421#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A)
422
423/*obsolete TaskType name */
424#define MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION \
425 (MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT)
426
427/*MsgFlags bits */
428
429#define MPI2_SCSITASKMGMT_MSGFLAGS_MASK_TARGET_RESET (0x18)
430#define MPI2_SCSITASKMGMT_MSGFLAGS_LINK_RESET (0x00)
431#define MPI2_SCSITASKMGMT_MSGFLAGS_NEXUS_RESET_SRST (0x08)
432#define MPI2_SCSITASKMGMT_MSGFLAGS_SAS_HARD_LINK_RESET (0x10)
433
434#define MPI2_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01)
435
436/*SCSI Task Management Reply Message */
437typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY {
438 U16 DevHandle; /*0x00 */
439 U8 MsgLength; /*0x02 */
440 U8 Function; /*0x03 */
441 U8 ResponseCode; /*0x04 */
442 U8 TaskType; /*0x05 */
443 U8 Reserved1; /*0x06 */
444 U8 MsgFlags; /*0x07 */
445 U8 VP_ID; /*0x08 */
446 U8 VF_ID; /*0x09 */
447 U16 Reserved2; /*0x0A */
448 U16 Reserved3; /*0x0C */
449 U16 IOCStatus; /*0x0E */
450 U32 IOCLogInfo; /*0x10 */
451 U32 TerminationCount; /*0x14 */
452 U32 ResponseInfo; /*0x18 */
453} MPI2_SCSI_TASK_MANAGE_REPLY,
454 *PTR_MPI2_SCSI_TASK_MANAGE_REPLY,
455 Mpi2SCSITaskManagementReply_t, *pMpi2SCSIManagementReply_t;
456
457/*ResponseCode values */
458
459#define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00)
460#define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02)
461#define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04)
462#define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05)
463#define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08)
464#define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09)
465#define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A)
466#define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80)
467
468/*masks and shifts for the ResponseInfo field */
469
470#define MPI2_SCSITASKMGMT_RI_MASK_REASONCODE (0x000000FF)
471#define MPI2_SCSITASKMGMT_RI_SHIFT_REASONCODE (0)
472#define MPI2_SCSITASKMGMT_RI_MASK_ARI2 (0x0000FF00)
473#define MPI2_SCSITASKMGMT_RI_SHIFT_ARI2 (8)
474#define MPI2_SCSITASKMGMT_RI_MASK_ARI1 (0x00FF0000)
475#define MPI2_SCSITASKMGMT_RI_SHIFT_ARI1 (16)
476#define MPI2_SCSITASKMGMT_RI_MASK_ARI0 (0xFF000000)
477#define MPI2_SCSITASKMGMT_RI_SHIFT_ARI0 (24)
478
479/****************************************************************************
480* SCSI Enclosure Processor messages
481****************************************************************************/
482
483/*SCSI Enclosure Processor Request Message */
484typedef struct _MPI2_SEP_REQUEST {
485 U16 DevHandle; /*0x00 */
486 U8 ChainOffset; /*0x02 */
487 U8 Function; /*0x03 */
488 U8 Action; /*0x04 */
489 U8 Flags; /*0x05 */
490 U8 Reserved1; /*0x06 */
491 U8 MsgFlags; /*0x07 */
492 U8 VP_ID; /*0x08 */
493 U8 VF_ID; /*0x09 */
494 U16 Reserved2; /*0x0A */
495 U32 SlotStatus; /*0x0C */
496 U32 Reserved3; /*0x10 */
497 U32 Reserved4; /*0x14 */
498 U32 Reserved5; /*0x18 */
499 U16 Slot; /*0x1C */
500 U16 EnclosureHandle; /*0x1E */
501} MPI2_SEP_REQUEST, *PTR_MPI2_SEP_REQUEST,
502 Mpi2SepRequest_t, *pMpi2SepRequest_t;
503
504/*Action defines */
505#define MPI2_SEP_REQ_ACTION_WRITE_STATUS (0x00)
506#define MPI2_SEP_REQ_ACTION_READ_STATUS (0x01)
507
508/*Flags defines */
509#define MPI2_SEP_REQ_FLAGS_DEVHANDLE_ADDRESS (0x00)
510#define MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS (0x01)
511
512/*SlotStatus defines */
513#define MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000)
514#define MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
515#define MPI2_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
516#define MPI2_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100)
517#define MPI2_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080)
518#define MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
519#define MPI2_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
520#define MPI2_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
521#define MPI2_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004)
522#define MPI2_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002)
523#define MPI2_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001)
524
525/*SCSI Enclosure Processor Reply Message */
526typedef struct _MPI2_SEP_REPLY {
527 U16 DevHandle; /*0x00 */
528 U8 MsgLength; /*0x02 */
529 U8 Function; /*0x03 */
530 U8 Action; /*0x04 */
531 U8 Flags; /*0x05 */
532 U8 Reserved1; /*0x06 */
533 U8 MsgFlags; /*0x07 */
534 U8 VP_ID; /*0x08 */
535 U8 VF_ID; /*0x09 */
536 U16 Reserved2; /*0x0A */
537 U16 Reserved3; /*0x0C */
538 U16 IOCStatus; /*0x0E */
539 U32 IOCLogInfo; /*0x10 */
540 U32 SlotStatus; /*0x14 */
541 U32 Reserved4; /*0x18 */
542 U16 Slot; /*0x1C */
543 U16 EnclosureHandle; /*0x1E */
544} MPI2_SEP_REPLY, *PTR_MPI2_SEP_REPLY,
545 Mpi2SepReply_t, *pMpi2SepReply_t;
546
547/*SlotStatus defines */
548#define MPI2_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000)
549#define MPI2_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000)
550#define MPI2_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200)
551#define MPI2_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100)
552#define MPI2_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080)
553#define MPI2_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040)
554#define MPI2_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010)
555#define MPI2_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008)
556#define MPI2_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004)
557#define MPI2_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002)
558#define MPI2_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001)
559
560#endif
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h b/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h
new file mode 100644
index 000000000000..0de425d8fd70
--- /dev/null
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h
@@ -0,0 +1,1665 @@
1/*
2 * Copyright (c) 2000-2012 LSI Corporation.
3 *
4 *
5 * Name: mpi2_ioc.h
6 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
7 * Creation Date: October 11, 2006
8 *
9 * mpi2_ioc.h Version: 02.00.21
10 *
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used
13 * with MPI v2.0 products. Unless otherwise noted, names beginning with
14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
15 *
16 * Version History
17 * ---------------
18 *
19 * Date Version Description
20 * -------- -------- ------------------------------------------------------
21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
22 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to
23 * MaxTargets.
24 * Added TotalImageSize field to FWDownload Request.
25 * Added reserved words to FWUpload Request.
26 * 06-26-07 02.00.02 Added IR Configuration Change List Event.
27 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit
28 * request and replaced it with
29 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth.
30 * Replaced the MinReplyQueueDepth field of the IOCFacts
31 * reply with MaxReplyDescriptorPostQueueDepth.
32 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum
33 * depth for the Reply Descriptor Post Queue.
34 * Added SASAddress field to Initiator Device Table
35 * Overflow Event data.
36 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING
37 * for SAS Initiator Device Status Change Event data.
38 * Modified Reason Code defines for SAS Topology Change
39 * List Event data, including adding a bit for PHY Vacant
40 * status, and adding a mask for the Reason Code.
41 * Added define for
42 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING.
43 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID.
44 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of
45 * the IOCFacts Reply.
46 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
47 * Moved MPI2_VERSION_UNION to mpi2.h.
48 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks
49 * instead of enables, and added SASBroadcastPrimitiveMasks
50 * field.
51 * Added Log Entry Added Event and related structure.
52 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID.
53 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET.
54 * Added MaxVolumes and MaxPersistentEntries fields to
55 * IOCFacts reply.
56 * Added ProtocalFlags and IOCCapabilities fields to
57 * MPI2_FW_IMAGE_HEADER.
58 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT.
59 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to
60 * a U16 (from a U32).
61 * Removed extra 's' from EventMasks name.
62 * 06-27-08 02.00.08 Fixed an offset in a comment.
63 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST.
64 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and
65 * renamed MinReplyFrameSize to ReplyFrameSize.
66 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX.
67 * Added two new RAIDOperation values for Integrated RAID
68 * Operations Status Event data.
69 * Added four new IR Configuration Change List Event data
70 * ReasonCode values.
71 * Added two new ReasonCode defines for SAS Device Status
72 * Change Event data.
73 * Added three new DiscoveryStatus bits for the SAS
74 * Discovery event data.
75 * Added Multiplexing Status Change bit to the PhyStatus
76 * field of the SAS Topology Change List event data.
77 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY.
78 * BootFlags are now product-specific.
79 * Added defines for the indivdual signature bytes
80 * for MPI2_INIT_IMAGE_FOOTER.
81 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define.
82 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR
83 * define.
84 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE
85 * define.
86 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define.
87 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define.
88 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define.
89 * Added two new reason codes for SAS Device Status Change
90 * Event.
91 * Added new event: SAS PHY Counter.
92 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure.
93 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define.
94 * Added new product id family for 2208.
95 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST.
96 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY.
97 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY.
98 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY.
99 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define.
100 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define.
101 * Added Host Based Discovery Phy Event data.
102 * Added defines for ProductID Product field
103 * (MPI2_FW_HEADER_PID_).
104 * Modified values for SAS ProductID Family
105 * (MPI2_FW_HEADER_PID_FAMILY_).
106 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines.
107 * Added PowerManagementControl Request structures and
108 * defines.
109 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete.
110 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define.
111 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC.
112 * 02-23-11 02.00.17 Added SAS NOTIFY Primitive event, and added
113 * SASNotifyPrimitiveMasks field to
114 * MPI2_EVENT_NOTIFICATION_REQUEST.
115 * Added Temperature Threshold Event.
116 * Added Host Message Event.
117 * Added Send Host Message request and reply.
118 * 05-25-11 02.00.18 For Extended Image Header, added
119 * MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC and
120 * MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC defines.
121 * Deprecated MPI2_EXT_IMAGE_TYPE_MAX define.
122 * 08-24-11 02.00.19 Added PhysicalPort field to
123 * MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE structure.
124 * Marked MPI2_PM_CONTROL_FEATURE_PCIE_LINK as obsolete.
125 * 11-18-11 02.00.20 Incorporating additions for MPI v2.5.
126 * 03-29-12 02.00.21 Added a product specific range to event values.
127 * --------------------------------------------------------------------------
128 */
129
130#ifndef MPI2_IOC_H
131#define MPI2_IOC_H
132
133/*****************************************************************************
134*
135* IOC Messages
136*
137*****************************************************************************/
138
139/****************************************************************************
140* IOCInit message
141****************************************************************************/
142
143/*IOCInit Request message */
144typedef struct _MPI2_IOC_INIT_REQUEST {
145 U8 WhoInit; /*0x00 */
146 U8 Reserved1; /*0x01 */
147 U8 ChainOffset; /*0x02 */
148 U8 Function; /*0x03 */
149 U16 Reserved2; /*0x04 */
150 U8 Reserved3; /*0x06 */
151 U8 MsgFlags; /*0x07 */
152 U8 VP_ID; /*0x08 */
153 U8 VF_ID; /*0x09 */
154 U16 Reserved4; /*0x0A */
155 U16 MsgVersion; /*0x0C */
156 U16 HeaderVersion; /*0x0E */
157 U32 Reserved5; /*0x10 */
158 U16 Reserved6; /*0x14 */
159 U8 Reserved7; /*0x16 */
160 U8 HostMSIxVectors; /*0x17 */
161 U16 Reserved8; /*0x18 */
162 U16 SystemRequestFrameSize; /*0x1A */
163 U16 ReplyDescriptorPostQueueDepth; /*0x1C */
164 U16 ReplyFreeQueueDepth; /*0x1E */
165 U32 SenseBufferAddressHigh; /*0x20 */
166 U32 SystemReplyAddressHigh; /*0x24 */
167 U64 SystemRequestFrameBaseAddress; /*0x28 */
168 U64 ReplyDescriptorPostQueueAddress; /*0x30 */
169 U64 ReplyFreeQueueAddress; /*0x38 */
170 U64 TimeStamp; /*0x40 */
171} MPI2_IOC_INIT_REQUEST, *PTR_MPI2_IOC_INIT_REQUEST,
172 Mpi2IOCInitRequest_t, *pMpi2IOCInitRequest_t;
173
174/*WhoInit values */
175#define MPI2_WHOINIT_NOT_INITIALIZED (0x00)
176#define MPI2_WHOINIT_SYSTEM_BIOS (0x01)
177#define MPI2_WHOINIT_ROM_BIOS (0x02)
178#define MPI2_WHOINIT_PCI_PEER (0x03)
179#define MPI2_WHOINIT_HOST_DRIVER (0x04)
180#define MPI2_WHOINIT_MANUFACTURER (0x05)
181
182/*MsgVersion */
183#define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00)
184#define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8)
185#define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF)
186#define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0)
187
188/*HeaderVersion */
189#define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00)
190#define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8)
191#define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF)
192#define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0)
193
194/*minimum depth for the Reply Descriptor Post Queue */
195#define MPI2_RDPQ_DEPTH_MIN (16)
196
197/*IOCInit Reply message */
198typedef struct _MPI2_IOC_INIT_REPLY {
199 U8 WhoInit; /*0x00 */
200 U8 Reserved1; /*0x01 */
201 U8 MsgLength; /*0x02 */
202 U8 Function; /*0x03 */
203 U16 Reserved2; /*0x04 */
204 U8 Reserved3; /*0x06 */
205 U8 MsgFlags; /*0x07 */
206 U8 VP_ID; /*0x08 */
207 U8 VF_ID; /*0x09 */
208 U16 Reserved4; /*0x0A */
209 U16 Reserved5; /*0x0C */
210 U16 IOCStatus; /*0x0E */
211 U32 IOCLogInfo; /*0x10 */
212} MPI2_IOC_INIT_REPLY, *PTR_MPI2_IOC_INIT_REPLY,
213 Mpi2IOCInitReply_t, *pMpi2IOCInitReply_t;
214
215/****************************************************************************
216* IOCFacts message
217****************************************************************************/
218
219/*IOCFacts Request message */
220typedef struct _MPI2_IOC_FACTS_REQUEST {
221 U16 Reserved1; /*0x00 */
222 U8 ChainOffset; /*0x02 */
223 U8 Function; /*0x03 */
224 U16 Reserved2; /*0x04 */
225 U8 Reserved3; /*0x06 */
226 U8 MsgFlags; /*0x07 */
227 U8 VP_ID; /*0x08 */
228 U8 VF_ID; /*0x09 */
229 U16 Reserved4; /*0x0A */
230} MPI2_IOC_FACTS_REQUEST, *PTR_MPI2_IOC_FACTS_REQUEST,
231 Mpi2IOCFactsRequest_t, *pMpi2IOCFactsRequest_t;
232
233/*IOCFacts Reply message */
234typedef struct _MPI2_IOC_FACTS_REPLY {
235 U16 MsgVersion; /*0x00 */
236 U8 MsgLength; /*0x02 */
237 U8 Function; /*0x03 */
238 U16 HeaderVersion; /*0x04 */
239 U8 IOCNumber; /*0x06 */
240 U8 MsgFlags; /*0x07 */
241 U8 VP_ID; /*0x08 */
242 U8 VF_ID; /*0x09 */
243 U16 Reserved1; /*0x0A */
244 U16 IOCExceptions; /*0x0C */
245 U16 IOCStatus; /*0x0E */
246 U32 IOCLogInfo; /*0x10 */
247 U8 MaxChainDepth; /*0x14 */
248 U8 WhoInit; /*0x15 */
249 U8 NumberOfPorts; /*0x16 */
250 U8 MaxMSIxVectors; /*0x17 */
251 U16 RequestCredit; /*0x18 */
252 U16 ProductID; /*0x1A */
253 U32 IOCCapabilities; /*0x1C */
254 MPI2_VERSION_UNION FWVersion; /*0x20 */
255 U16 IOCRequestFrameSize; /*0x24 */
256 U16 IOCMaxChainSegmentSize; /*0x26 */
257 U16 MaxInitiators; /*0x28 */
258 U16 MaxTargets; /*0x2A */
259 U16 MaxSasExpanders; /*0x2C */
260 U16 MaxEnclosures; /*0x2E */
261 U16 ProtocolFlags; /*0x30 */
262 U16 HighPriorityCredit; /*0x32 */
263 U16 MaxReplyDescriptorPostQueueDepth; /*0x34 */
264 U8 ReplyFrameSize; /*0x36 */
265 U8 MaxVolumes; /*0x37 */
266 U16 MaxDevHandle; /*0x38 */
267 U16 MaxPersistentEntries; /*0x3A */
268 U16 MinDevHandle; /*0x3C */
269 U16 Reserved4; /*0x3E */
270} MPI2_IOC_FACTS_REPLY, *PTR_MPI2_IOC_FACTS_REPLY,
271 Mpi2IOCFactsReply_t, *pMpi2IOCFactsReply_t;
272
273/*MsgVersion */
274#define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00)
275#define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8)
276#define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF)
277#define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0)
278
279/*HeaderVersion */
280#define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00)
281#define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8)
282#define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF)
283#define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0)
284
285/*IOCExceptions */
286#define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100)
287
288#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0)
289#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000)
290#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020)
291#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040)
292#define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060)
293
294#define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010)
295#define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008)
296#define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004)
297#define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002)
298#define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001)
299
300/*defines for WhoInit field are after the IOCInit Request */
301
302/*ProductID field uses MPI2_FW_HEADER_PID_ */
303
304/*IOCCapabilities */
305#define MPI25_IOCFACTS_CAPABILITY_FAST_PATH_CAPABLE (0x00020000)
306#define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000)
307#define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000)
308#define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000)
309#define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000)
310#define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000)
311#define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800)
312#define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100)
313#define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080)
314#define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040)
315#define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020)
316#define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010)
317#define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008)
318#define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004)
319
320/*ProtocolFlags */
321#define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001)
322#define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002)
323
324/****************************************************************************
325* PortFacts message
326****************************************************************************/
327
328/*PortFacts Request message */
329typedef struct _MPI2_PORT_FACTS_REQUEST {
330 U16 Reserved1; /*0x00 */
331 U8 ChainOffset; /*0x02 */
332 U8 Function; /*0x03 */
333 U16 Reserved2; /*0x04 */
334 U8 PortNumber; /*0x06 */
335 U8 MsgFlags; /*0x07 */
336 U8 VP_ID; /*0x08 */
337 U8 VF_ID; /*0x09 */
338 U16 Reserved3; /*0x0A */
339} MPI2_PORT_FACTS_REQUEST, *PTR_MPI2_PORT_FACTS_REQUEST,
340 Mpi2PortFactsRequest_t, *pMpi2PortFactsRequest_t;
341
342/*PortFacts Reply message */
343typedef struct _MPI2_PORT_FACTS_REPLY {
344 U16 Reserved1; /*0x00 */
345 U8 MsgLength; /*0x02 */
346 U8 Function; /*0x03 */
347 U16 Reserved2; /*0x04 */
348 U8 PortNumber; /*0x06 */
349 U8 MsgFlags; /*0x07 */
350 U8 VP_ID; /*0x08 */
351 U8 VF_ID; /*0x09 */
352 U16 Reserved3; /*0x0A */
353 U16 Reserved4; /*0x0C */
354 U16 IOCStatus; /*0x0E */
355 U32 IOCLogInfo; /*0x10 */
356 U8 Reserved5; /*0x14 */
357 U8 PortType; /*0x15 */
358 U16 Reserved6; /*0x16 */
359 U16 MaxPostedCmdBuffers; /*0x18 */
360 U16 Reserved7; /*0x1A */
361} MPI2_PORT_FACTS_REPLY, *PTR_MPI2_PORT_FACTS_REPLY,
362 Mpi2PortFactsReply_t, *pMpi2PortFactsReply_t;
363
364/*PortType values */
365#define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00)
366#define MPI2_PORTFACTS_PORTTYPE_FC (0x10)
367#define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20)
368#define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30)
369#define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31)
370
371/****************************************************************************
372* PortEnable message
373****************************************************************************/
374
375/*PortEnable Request message */
376typedef struct _MPI2_PORT_ENABLE_REQUEST {
377 U16 Reserved1; /*0x00 */
378 U8 ChainOffset; /*0x02 */
379 U8 Function; /*0x03 */
380 U8 Reserved2; /*0x04 */
381 U8 PortFlags; /*0x05 */
382 U8 Reserved3; /*0x06 */
383 U8 MsgFlags; /*0x07 */
384 U8 VP_ID; /*0x08 */
385 U8 VF_ID; /*0x09 */
386 U16 Reserved4; /*0x0A */
387} MPI2_PORT_ENABLE_REQUEST, *PTR_MPI2_PORT_ENABLE_REQUEST,
388 Mpi2PortEnableRequest_t, *pMpi2PortEnableRequest_t;
389
390/*PortEnable Reply message */
391typedef struct _MPI2_PORT_ENABLE_REPLY {
392 U16 Reserved1; /*0x00 */
393 U8 MsgLength; /*0x02 */
394 U8 Function; /*0x03 */
395 U8 Reserved2; /*0x04 */
396 U8 PortFlags; /*0x05 */
397 U8 Reserved3; /*0x06 */
398 U8 MsgFlags; /*0x07 */
399 U8 VP_ID; /*0x08 */
400 U8 VF_ID; /*0x09 */
401 U16 Reserved4; /*0x0A */
402 U16 Reserved5; /*0x0C */
403 U16 IOCStatus; /*0x0E */
404 U32 IOCLogInfo; /*0x10 */
405} MPI2_PORT_ENABLE_REPLY, *PTR_MPI2_PORT_ENABLE_REPLY,
406 Mpi2PortEnableReply_t, *pMpi2PortEnableReply_t;
407
408/****************************************************************************
409* EventNotification message
410****************************************************************************/
411
412/*EventNotification Request message */
413#define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4)
414
415typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST {
416 U16 Reserved1; /*0x00 */
417 U8 ChainOffset; /*0x02 */
418 U8 Function; /*0x03 */
419 U16 Reserved2; /*0x04 */
420 U8 Reserved3; /*0x06 */
421 U8 MsgFlags; /*0x07 */
422 U8 VP_ID; /*0x08 */
423 U8 VF_ID; /*0x09 */
424 U16 Reserved4; /*0x0A */
425 U32 Reserved5; /*0x0C */
426 U32 Reserved6; /*0x10 */
427 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS]; /*0x14 */
428 U16 SASBroadcastPrimitiveMasks; /*0x24 */
429 U16 SASNotifyPrimitiveMasks; /*0x26 */
430 U32 Reserved8; /*0x28 */
431} MPI2_EVENT_NOTIFICATION_REQUEST,
432 *PTR_MPI2_EVENT_NOTIFICATION_REQUEST,
433 Mpi2EventNotificationRequest_t,
434 *pMpi2EventNotificationRequest_t;
435
436/*EventNotification Reply message */
437typedef struct _MPI2_EVENT_NOTIFICATION_REPLY {
438 U16 EventDataLength; /*0x00 */
439 U8 MsgLength; /*0x02 */
440 U8 Function; /*0x03 */
441 U16 Reserved1; /*0x04 */
442 U8 AckRequired; /*0x06 */
443 U8 MsgFlags; /*0x07 */
444 U8 VP_ID; /*0x08 */
445 U8 VF_ID; /*0x09 */
446 U16 Reserved2; /*0x0A */
447 U16 Reserved3; /*0x0C */
448 U16 IOCStatus; /*0x0E */
449 U32 IOCLogInfo; /*0x10 */
450 U16 Event; /*0x14 */
451 U16 Reserved4; /*0x16 */
452 U32 EventContext; /*0x18 */
453 U32 EventData[1]; /*0x1C */
454} MPI2_EVENT_NOTIFICATION_REPLY, *PTR_MPI2_EVENT_NOTIFICATION_REPLY,
455 Mpi2EventNotificationReply_t,
456 *pMpi2EventNotificationReply_t;
457
458/*AckRequired */
459#define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00)
460#define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01)
461
462/*Event */
463#define MPI2_EVENT_LOG_DATA (0x0001)
464#define MPI2_EVENT_STATE_CHANGE (0x0002)
465#define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005)
466#define MPI2_EVENT_EVENT_CHANGE (0x000A)
467#define MPI2_EVENT_TASK_SET_FULL (0x000E) /*obsolete */
468#define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F)
469#define MPI2_EVENT_IR_OPERATION_STATUS (0x0014)
470#define MPI2_EVENT_SAS_DISCOVERY (0x0016)
471#define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017)
472#define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018)
473#define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019)
474#define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C)
475#define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D)
476#define MPI2_EVENT_IR_VOLUME (0x001E)
477#define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F)
478#define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020)
479#define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021)
480#define MPI2_EVENT_SAS_PHY_COUNTER (0x0022)
481#define MPI2_EVENT_GPIO_INTERRUPT (0x0023)
482#define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024)
483#define MPI2_EVENT_SAS_QUIESCE (0x0025)
484#define MPI2_EVENT_SAS_NOTIFY_PRIMITIVE (0x0026)
485#define MPI2_EVENT_TEMP_THRESHOLD (0x0027)
486#define MPI2_EVENT_HOST_MESSAGE (0x0028)
487#define MPI2_EVENT_POWER_PERFORMANCE_CHANGE (0x0029)
488#define MPI2_EVENT_MIN_PRODUCT_SPECIFIC (0x006E)
489#define MPI2_EVENT_MAX_PRODUCT_SPECIFIC (0x007F)
490
491/*Log Entry Added Event data */
492
493/*the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */
494#define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C)
495
496typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED {
497 U64 TimeStamp; /*0x00 */
498 U32 Reserved1; /*0x08 */
499 U16 LogSequence; /*0x0C */
500 U16 LogEntryQualifier; /*0x0E */
501 U8 VP_ID; /*0x10 */
502 U8 VF_ID; /*0x11 */
503 U16 Reserved2; /*0x12 */
504 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH]; /*0x14 */
505} MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
506 *PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED,
507 Mpi2EventDataLogEntryAdded_t,
508 *pMpi2EventDataLogEntryAdded_t;
509
510/*GPIO Interrupt Event data */
511
512typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT {
513 U8 GPIONum; /*0x00 */
514 U8 Reserved1; /*0x01 */
515 U16 Reserved2; /*0x02 */
516} MPI2_EVENT_DATA_GPIO_INTERRUPT,
517 *PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT,
518 Mpi2EventDataGpioInterrupt_t,
519 *pMpi2EventDataGpioInterrupt_t;
520
521/*Temperature Threshold Event data */
522
523typedef struct _MPI2_EVENT_DATA_TEMPERATURE {
524 U16 Status; /*0x00 */
525 U8 SensorNum; /*0x02 */
526 U8 Reserved1; /*0x03 */
527 U16 CurrentTemperature; /*0x04 */
528 U16 Reserved2; /*0x06 */
529 U32 Reserved3; /*0x08 */
530 U32 Reserved4; /*0x0C */
531} MPI2_EVENT_DATA_TEMPERATURE,
532 *PTR_MPI2_EVENT_DATA_TEMPERATURE,
533 Mpi2EventDataTemperature_t, *pMpi2EventDataTemperature_t;
534
535/*Temperature Threshold Event data Status bits */
536#define MPI2_EVENT_TEMPERATURE3_EXCEEDED (0x0008)
537#define MPI2_EVENT_TEMPERATURE2_EXCEEDED (0x0004)
538#define MPI2_EVENT_TEMPERATURE1_EXCEEDED (0x0002)
539#define MPI2_EVENT_TEMPERATURE0_EXCEEDED (0x0001)
540
541/*Host Message Event data */
542
543typedef struct _MPI2_EVENT_DATA_HOST_MESSAGE {
544 U8 SourceVF_ID; /*0x00 */
545 U8 Reserved1; /*0x01 */
546 U16 Reserved2; /*0x02 */
547 U32 Reserved3; /*0x04 */
548 U32 HostData[1]; /*0x08 */
549} MPI2_EVENT_DATA_HOST_MESSAGE, *PTR_MPI2_EVENT_DATA_HOST_MESSAGE,
550 Mpi2EventDataHostMessage_t, *pMpi2EventDataHostMessage_t;
551
552/*Power Performance Change Event */
553
554typedef struct _MPI2_EVENT_DATA_POWER_PERF_CHANGE {
555 U8 CurrentPowerMode; /*0x00 */
556 U8 PreviousPowerMode; /*0x01 */
557 U16 Reserved1; /*0x02 */
558} MPI2_EVENT_DATA_POWER_PERF_CHANGE,
559 *PTR_MPI2_EVENT_DATA_POWER_PERF_CHANGE,
560 Mpi2EventDataPowerPerfChange_t,
561 *pMpi2EventDataPowerPerfChange_t;
562
563/*defines for CurrentPowerMode and PreviousPowerMode fields */
564#define MPI2_EVENT_PM_INIT_MASK (0xC0)
565#define MPI2_EVENT_PM_INIT_UNAVAILABLE (0x00)
566#define MPI2_EVENT_PM_INIT_HOST (0x40)
567#define MPI2_EVENT_PM_INIT_IO_UNIT (0x80)
568#define MPI2_EVENT_PM_INIT_PCIE_DPA (0xC0)
569
570#define MPI2_EVENT_PM_MODE_MASK (0x07)
571#define MPI2_EVENT_PM_MODE_UNAVAILABLE (0x00)
572#define MPI2_EVENT_PM_MODE_UNKNOWN (0x01)
573#define MPI2_EVENT_PM_MODE_FULL_POWER (0x04)
574#define MPI2_EVENT_PM_MODE_REDUCED_POWER (0x05)
575#define MPI2_EVENT_PM_MODE_STANDBY (0x06)
576
577/*Hard Reset Received Event data */
578
579typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED {
580 U8 Reserved1; /*0x00 */
581 U8 Port; /*0x01 */
582 U16 Reserved2; /*0x02 */
583} MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
584 *PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED,
585 Mpi2EventDataHardResetReceived_t,
586 *pMpi2EventDataHardResetReceived_t;
587
588/*Task Set Full Event data */
589/* this event is obsolete */
590
591typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL {
592 U16 DevHandle; /*0x00 */
593 U16 CurrentDepth; /*0x02 */
594} MPI2_EVENT_DATA_TASK_SET_FULL, *PTR_MPI2_EVENT_DATA_TASK_SET_FULL,
595 Mpi2EventDataTaskSetFull_t, *pMpi2EventDataTaskSetFull_t;
596
597/*SAS Device Status Change Event data */
598
599typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE {
600 U16 TaskTag; /*0x00 */
601 U8 ReasonCode; /*0x02 */
602 U8 PhysicalPort; /*0x03 */
603 U8 ASC; /*0x04 */
604 U8 ASCQ; /*0x05 */
605 U16 DevHandle; /*0x06 */
606 U32 Reserved2; /*0x08 */
607 U64 SASAddress; /*0x0C */
608 U8 LUN[8]; /*0x14 */
609} MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
610 *PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE,
611 Mpi2EventDataSasDeviceStatusChange_t,
612 *pMpi2EventDataSasDeviceStatusChange_t;
613
614/*SAS Device Status Change Event data ReasonCode values */
615#define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05)
616#define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07)
617#define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08)
618#define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09)
619#define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A)
620#define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B)
621#define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C)
622#define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D)
623#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E)
624#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F)
625#define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10)
626#define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11)
627#define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12)
628
629/*Integrated RAID Operation Status Event data */
630
631typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS {
632 U16 VolDevHandle; /*0x00 */
633 U16 Reserved1; /*0x02 */
634 U8 RAIDOperation; /*0x04 */
635 U8 PercentComplete; /*0x05 */
636 U16 Reserved2; /*0x06 */
637 U32 Resereved3; /*0x08 */
638} MPI2_EVENT_DATA_IR_OPERATION_STATUS,
639 *PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS,
640 Mpi2EventDataIrOperationStatus_t,
641 *pMpi2EventDataIrOperationStatus_t;
642
643/*Integrated RAID Operation Status Event data RAIDOperation values */
644#define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00)
645#define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01)
646#define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02)
647#define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03)
648#define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04)
649
650/*Integrated RAID Volume Event data */
651
652typedef struct _MPI2_EVENT_DATA_IR_VOLUME {
653 U16 VolDevHandle; /*0x00 */
654 U8 ReasonCode; /*0x02 */
655 U8 Reserved1; /*0x03 */
656 U32 NewValue; /*0x04 */
657 U32 PreviousValue; /*0x08 */
658} MPI2_EVENT_DATA_IR_VOLUME, *PTR_MPI2_EVENT_DATA_IR_VOLUME,
659 Mpi2EventDataIrVolume_t, *pMpi2EventDataIrVolume_t;
660
661/*Integrated RAID Volume Event data ReasonCode values */
662#define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01)
663#define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02)
664#define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03)
665
666/*Integrated RAID Physical Disk Event data */
667
668typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK {
669 U16 Reserved1; /*0x00 */
670 U8 ReasonCode; /*0x02 */
671 U8 PhysDiskNum; /*0x03 */
672 U16 PhysDiskDevHandle; /*0x04 */
673 U16 Reserved2; /*0x06 */
674 U16 Slot; /*0x08 */
675 U16 EnclosureHandle; /*0x0A */
676 U32 NewValue; /*0x0C */
677 U32 PreviousValue; /*0x10 */
678} MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
679 *PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK,
680 Mpi2EventDataIrPhysicalDisk_t,
681 *pMpi2EventDataIrPhysicalDisk_t;
682
683/*Integrated RAID Physical Disk Event data ReasonCode values */
684#define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01)
685#define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02)
686#define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03)
687
688/*Integrated RAID Configuration Change List Event data */
689
690/*
691 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
692 *one and check NumElements at runtime.
693 */
694#ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT
695#define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1)
696#endif
697
698typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT {
699 U16 ElementFlags; /*0x00 */
700 U16 VolDevHandle; /*0x02 */
701 U8 ReasonCode; /*0x04 */
702 U8 PhysDiskNum; /*0x05 */
703 U16 PhysDiskDevHandle; /*0x06 */
704} MPI2_EVENT_IR_CONFIG_ELEMENT, *PTR_MPI2_EVENT_IR_CONFIG_ELEMENT,
705 Mpi2EventIrConfigElement_t, *pMpi2EventIrConfigElement_t;
706
707/*IR Configuration Change List Event data ElementFlags values */
708#define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F)
709#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000)
710#define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001)
711#define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002)
712
713/*IR Configuration Change List Event data ReasonCode values */
714#define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01)
715#define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02)
716#define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03)
717#define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04)
718#define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05)
719#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06)
720#define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07)
721#define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08)
722#define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09)
723
724typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST {
725 U8 NumElements; /*0x00 */
726 U8 Reserved1; /*0x01 */
727 U8 Reserved2; /*0x02 */
728 U8 ConfigNum; /*0x03 */
729 U32 Flags; /*0x04 */
730 MPI2_EVENT_IR_CONFIG_ELEMENT
731 ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT];/*0x08 */
732} MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
733 *PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST,
734 Mpi2EventDataIrConfigChangeList_t,
735 *pMpi2EventDataIrConfigChangeList_t;
736
737/*IR Configuration Change List Event data Flags values */
738#define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001)
739
740/*SAS Discovery Event data */
741
742typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY {
743 U8 Flags; /*0x00 */
744 U8 ReasonCode; /*0x01 */
745 U8 PhysicalPort; /*0x02 */
746 U8 Reserved1; /*0x03 */
747 U32 DiscoveryStatus; /*0x04 */
748} MPI2_EVENT_DATA_SAS_DISCOVERY,
749 *PTR_MPI2_EVENT_DATA_SAS_DISCOVERY,
750 Mpi2EventDataSasDiscovery_t, *pMpi2EventDataSasDiscovery_t;
751
752/*SAS Discovery Event data Flags values */
753#define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02)
754#define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01)
755
756/*SAS Discovery Event data ReasonCode values */
757#define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01)
758#define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02)
759
760/*SAS Discovery Event data DiscoveryStatus values */
761#define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
762#define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000)
763#define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000)
764#define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
765#define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000)
766#define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
767#define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
768#define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000)
769#define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
770#define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800)
771#define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400)
772#define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200)
773#define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100)
774#define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080)
775#define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040)
776#define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020)
777#define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010)
778#define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004)
779#define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002)
780#define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001)
781
782/*SAS Broadcast Primitive Event data */
783
784typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE {
785 U8 PhyNum; /*0x00 */
786 U8 Port; /*0x01 */
787 U8 PortWidth; /*0x02 */
788 U8 Primitive; /*0x03 */
789} MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
790 *PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE,
791 Mpi2EventDataSasBroadcastPrimitive_t,
792 *pMpi2EventDataSasBroadcastPrimitive_t;
793
794/*defines for the Primitive field */
795#define MPI2_EVENT_PRIMITIVE_CHANGE (0x01)
796#define MPI2_EVENT_PRIMITIVE_SES (0x02)
797#define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03)
798#define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04)
799#define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05)
800#define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06)
801#define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07)
802#define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08)
803
804/*SAS Notify Primitive Event data */
805
806typedef struct _MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE {
807 U8 PhyNum; /*0x00 */
808 U8 Port; /*0x01 */
809 U8 Reserved1; /*0x02 */
810 U8 Primitive; /*0x03 */
811} MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
812 *PTR_MPI2_EVENT_DATA_SAS_NOTIFY_PRIMITIVE,
813 Mpi2EventDataSasNotifyPrimitive_t,
814 *pMpi2EventDataSasNotifyPrimitive_t;
815
816/*defines for the Primitive field */
817#define MPI2_EVENT_NOTIFY_ENABLE_SPINUP (0x01)
818#define MPI2_EVENT_NOTIFY_POWER_LOSS_EXPECTED (0x02)
819#define MPI2_EVENT_NOTIFY_RESERVED1 (0x03)
820#define MPI2_EVENT_NOTIFY_RESERVED2 (0x04)
821
822/*SAS Initiator Device Status Change Event data */
823
824typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE {
825 U8 ReasonCode; /*0x00 */
826 U8 PhysicalPort; /*0x01 */
827 U16 DevHandle; /*0x02 */
828 U64 SASAddress; /*0x04 */
829} MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
830 *PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE,
831 Mpi2EventDataSasInitDevStatusChange_t,
832 *pMpi2EventDataSasInitDevStatusChange_t;
833
834/*SAS Initiator Device Status Change event ReasonCode values */
835#define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01)
836#define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02)
837
838/*SAS Initiator Device Table Overflow Event data */
839
840typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW {
841 U16 MaxInit; /*0x00 */
842 U16 CurrentInit; /*0x02 */
843 U64 SASAddress; /*0x04 */
844} MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
845 *PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW,
846 Mpi2EventDataSasInitTableOverflow_t,
847 *pMpi2EventDataSasInitTableOverflow_t;
848
849/*SAS Topology Change List Event data */
850
851/*
852 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
853 *one and check NumEntries at runtime.
854 */
855#ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT
856#define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1)
857#endif
858
859typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY {
860 U16 AttachedDevHandle; /*0x00 */
861 U8 LinkRate; /*0x02 */
862 U8 PhyStatus; /*0x03 */
863} MPI2_EVENT_SAS_TOPO_PHY_ENTRY, *PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY,
864 Mpi2EventSasTopoPhyEntry_t, *pMpi2EventSasTopoPhyEntry_t;
865
866typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST {
867 U16 EnclosureHandle; /*0x00 */
868 U16 ExpanderDevHandle; /*0x02 */
869 U8 NumPhys; /*0x04 */
870 U8 Reserved1; /*0x05 */
871 U16 Reserved2; /*0x06 */
872 U8 NumEntries; /*0x08 */
873 U8 StartPhyNum; /*0x09 */
874 U8 ExpStatus; /*0x0A */
875 U8 PhysicalPort; /*0x0B */
876 MPI2_EVENT_SAS_TOPO_PHY_ENTRY
877 PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /*0x0C */
878} MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
879 *PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST,
880 Mpi2EventDataSasTopologyChangeList_t,
881 *pMpi2EventDataSasTopologyChangeList_t;
882
883/*values for the ExpStatus field */
884#define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00)
885#define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01)
886#define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02)
887#define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03)
888#define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04)
889
890/*defines for the LinkRate field */
891#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0)
892#define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4)
893#define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F)
894#define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0)
895
896#define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00)
897#define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01)
898#define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02)
899#define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03)
900#define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04)
901#define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05)
902#define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06)
903#define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08)
904#define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09)
905#define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A)
906#define MPI25_EVENT_SAS_TOPO_LR_RATE_12_0 (0x0B)
907
908/*values for the PhyStatus field */
909#define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80)
910#define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10)
911/*values for the PhyStatus ReasonCode sub-field */
912#define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F)
913#define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01)
914#define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02)
915#define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03)
916#define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04)
917#define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05)
918
919/*SAS Enclosure Device Status Change Event data */
920
921typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE {
922 U16 EnclosureHandle; /*0x00 */
923 U8 ReasonCode; /*0x02 */
924 U8 PhysicalPort; /*0x03 */
925 U64 EnclosureLogicalID; /*0x04 */
926 U16 NumSlots; /*0x0C */
927 U16 StartSlot; /*0x0E */
928 U32 PhyBits; /*0x10 */
929} MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
930 *PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE,
931 Mpi2EventDataSasEnclDevStatusChange_t,
932 *pMpi2EventDataSasEnclDevStatusChange_t;
933
934/*SAS Enclosure Device Status Change event ReasonCode values */
935#define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01)
936#define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02)
937
938/*SAS PHY Counter Event data */
939
940typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER {
941 U64 TimeStamp; /*0x00 */
942 U32 Reserved1; /*0x08 */
943 U8 PhyEventCode; /*0x0C */
944 U8 PhyNum; /*0x0D */
945 U16 Reserved2; /*0x0E */
946 U32 PhyEventInfo; /*0x10 */
947 U8 CounterType; /*0x14 */
948 U8 ThresholdWindow; /*0x15 */
949 U8 TimeUnits; /*0x16 */
950 U8 Reserved3; /*0x17 */
951 U32 EventThreshold; /*0x18 */
952 U16 ThresholdFlags; /*0x1C */
953 U16 Reserved4; /*0x1E */
954} MPI2_EVENT_DATA_SAS_PHY_COUNTER,
955 *PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER,
956 Mpi2EventDataSasPhyCounter_t,
957 *pMpi2EventDataSasPhyCounter_t;
958
959/*use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h
960 *for the PhyEventCode field */
961
962/*use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h
963 *for the CounterType field */
964
965/*use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h
966 *for the TimeUnits field */
967
968/*use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h
969 *for the ThresholdFlags field */
970
971/*SAS Quiesce Event data */
972
973typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE {
974 U8 ReasonCode; /*0x00 */
975 U8 Reserved1; /*0x01 */
976 U16 Reserved2; /*0x02 */
977 U32 Reserved3; /*0x04 */
978} MPI2_EVENT_DATA_SAS_QUIESCE,
979 *PTR_MPI2_EVENT_DATA_SAS_QUIESCE,
980 Mpi2EventDataSasQuiesce_t, *pMpi2EventDataSasQuiesce_t;
981
982/*SAS Quiesce Event data ReasonCode values */
983#define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01)
984#define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02)
985
986/*Host Based Discovery Phy Event data */
987
988typedef struct _MPI2_EVENT_HBD_PHY_SAS {
989 U8 Flags; /*0x00 */
990 U8 NegotiatedLinkRate; /*0x01 */
991 U8 PhyNum; /*0x02 */
992 U8 PhysicalPort; /*0x03 */
993 U32 Reserved1; /*0x04 */
994 U8 InitialFrame[28]; /*0x08 */
995} MPI2_EVENT_HBD_PHY_SAS, *PTR_MPI2_EVENT_HBD_PHY_SAS,
996 Mpi2EventHbdPhySas_t, *pMpi2EventHbdPhySas_t;
997
998/*values for the Flags field */
999#define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02)
1000#define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01)
1001
1002/*use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h
1003 *for the NegotiatedLinkRate field */
1004
1005typedef union _MPI2_EVENT_HBD_DESCRIPTOR {
1006 MPI2_EVENT_HBD_PHY_SAS Sas;
1007} MPI2_EVENT_HBD_DESCRIPTOR, *PTR_MPI2_EVENT_HBD_DESCRIPTOR,
1008 Mpi2EventHbdDescriptor_t, *pMpi2EventHbdDescriptor_t;
1009
1010typedef struct _MPI2_EVENT_DATA_HBD_PHY {
1011 U8 DescriptorType; /*0x00 */
1012 U8 Reserved1; /*0x01 */
1013 U16 Reserved2; /*0x02 */
1014 U32 Reserved3; /*0x04 */
1015 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /*0x08 */
1016} MPI2_EVENT_DATA_HBD_PHY, *PTR_MPI2_EVENT_DATA_HBD_PHY,
1017 Mpi2EventDataHbdPhy_t,
1018 *pMpi2EventDataMpi2EventDataHbdPhy_t;
1019
1020/*values for the DescriptorType field */
1021#define MPI2_EVENT_HBD_DT_SAS (0x01)
1022
1023/****************************************************************************
1024* EventAck message
1025****************************************************************************/
1026
1027/*EventAck Request message */
1028typedef struct _MPI2_EVENT_ACK_REQUEST {
1029 U16 Reserved1; /*0x00 */
1030 U8 ChainOffset; /*0x02 */
1031 U8 Function; /*0x03 */
1032 U16 Reserved2; /*0x04 */
1033 U8 Reserved3; /*0x06 */
1034 U8 MsgFlags; /*0x07 */
1035 U8 VP_ID; /*0x08 */
1036 U8 VF_ID; /*0x09 */
1037 U16 Reserved4; /*0x0A */
1038 U16 Event; /*0x0C */
1039 U16 Reserved5; /*0x0E */
1040 U32 EventContext; /*0x10 */
1041} MPI2_EVENT_ACK_REQUEST, *PTR_MPI2_EVENT_ACK_REQUEST,
1042 Mpi2EventAckRequest_t, *pMpi2EventAckRequest_t;
1043
1044/*EventAck Reply message */
1045typedef struct _MPI2_EVENT_ACK_REPLY {
1046 U16 Reserved1; /*0x00 */
1047 U8 MsgLength; /*0x02 */
1048 U8 Function; /*0x03 */
1049 U16 Reserved2; /*0x04 */
1050 U8 Reserved3; /*0x06 */
1051 U8 MsgFlags; /*0x07 */
1052 U8 VP_ID; /*0x08 */
1053 U8 VF_ID; /*0x09 */
1054 U16 Reserved4; /*0x0A */
1055 U16 Reserved5; /*0x0C */
1056 U16 IOCStatus; /*0x0E */
1057 U32 IOCLogInfo; /*0x10 */
1058} MPI2_EVENT_ACK_REPLY, *PTR_MPI2_EVENT_ACK_REPLY,
1059 Mpi2EventAckReply_t, *pMpi2EventAckReply_t;
1060
1061/****************************************************************************
1062* SendHostMessage message
1063****************************************************************************/
1064
1065/*SendHostMessage Request message */
1066typedef struct _MPI2_SEND_HOST_MESSAGE_REQUEST {
1067 U16 HostDataLength; /*0x00 */
1068 U8 ChainOffset; /*0x02 */
1069 U8 Function; /*0x03 */
1070 U16 Reserved1; /*0x04 */
1071 U8 Reserved2; /*0x06 */
1072 U8 MsgFlags; /*0x07 */
1073 U8 VP_ID; /*0x08 */
1074 U8 VF_ID; /*0x09 */
1075 U16 Reserved3; /*0x0A */
1076 U8 Reserved4; /*0x0C */
1077 U8 DestVF_ID; /*0x0D */
1078 U16 Reserved5; /*0x0E */
1079 U32 Reserved6; /*0x10 */
1080 U32 Reserved7; /*0x14 */
1081 U32 Reserved8; /*0x18 */
1082 U32 Reserved9; /*0x1C */
1083 U32 Reserved10; /*0x20 */
1084 U32 HostData[1]; /*0x24 */
1085} MPI2_SEND_HOST_MESSAGE_REQUEST,
1086 *PTR_MPI2_SEND_HOST_MESSAGE_REQUEST,
1087 Mpi2SendHostMessageRequest_t,
1088 *pMpi2SendHostMessageRequest_t;
1089
1090/*SendHostMessage Reply message */
1091typedef struct _MPI2_SEND_HOST_MESSAGE_REPLY {
1092 U16 HostDataLength; /*0x00 */
1093 U8 MsgLength; /*0x02 */
1094 U8 Function; /*0x03 */
1095 U16 Reserved1; /*0x04 */
1096 U8 Reserved2; /*0x06 */
1097 U8 MsgFlags; /*0x07 */
1098 U8 VP_ID; /*0x08 */
1099 U8 VF_ID; /*0x09 */
1100 U16 Reserved3; /*0x0A */
1101 U16 Reserved4; /*0x0C */
1102 U16 IOCStatus; /*0x0E */
1103 U32 IOCLogInfo; /*0x10 */
1104} MPI2_SEND_HOST_MESSAGE_REPLY, *PTR_MPI2_SEND_HOST_MESSAGE_REPLY,
1105 Mpi2SendHostMessageReply_t, *pMpi2SendHostMessageReply_t;
1106
1107/****************************************************************************
1108* FWDownload message
1109****************************************************************************/
1110
1111/*MPI v2.0 FWDownload Request message */
1112typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1113 U8 ImageType; /*0x00 */
1114 U8 Reserved1; /*0x01 */
1115 U8 ChainOffset; /*0x02 */
1116 U8 Function; /*0x03 */
1117 U16 Reserved2; /*0x04 */
1118 U8 Reserved3; /*0x06 */
1119 U8 MsgFlags; /*0x07 */
1120 U8 VP_ID; /*0x08 */
1121 U8 VF_ID; /*0x09 */
1122 U16 Reserved4; /*0x0A */
1123 U32 TotalImageSize; /*0x0C */
1124 U32 Reserved5; /*0x10 */
1125 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1126} MPI2_FW_DOWNLOAD_REQUEST, *PTR_MPI2_FW_DOWNLOAD_REQUEST,
1127 Mpi2FWDownloadRequest, *pMpi2FWDownloadRequest;
1128
1129#define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01)
1130
1131#define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01)
1132#define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02)
1133#define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06)
1134#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07)
1135#define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08)
1136#define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09)
1137#define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A)
1138#define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1139#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1140
1141/*MPI v2.0 FWDownload TransactionContext Element */
1142typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
1143 U8 Reserved1; /*0x00 */
1144 U8 ContextSize; /*0x01 */
1145 U8 DetailsLength; /*0x02 */
1146 U8 Flags; /*0x03 */
1147 U32 Reserved2; /*0x04 */
1148 U32 ImageOffset; /*0x08 */
1149 U32 ImageSize; /*0x0C */
1150} MPI2_FW_DOWNLOAD_TCSGE, *PTR_MPI2_FW_DOWNLOAD_TCSGE,
1151 Mpi2FWDownloadTCSGE_t, *pMpi2FWDownloadTCSGE_t;
1152
1153/*MPI v2.5 FWDownload Request message */
1154typedef struct _MPI25_FW_DOWNLOAD_REQUEST {
1155 U8 ImageType; /*0x00 */
1156 U8 Reserved1; /*0x01 */
1157 U8 ChainOffset; /*0x02 */
1158 U8 Function; /*0x03 */
1159 U16 Reserved2; /*0x04 */
1160 U8 Reserved3; /*0x06 */
1161 U8 MsgFlags; /*0x07 */
1162 U8 VP_ID; /*0x08 */
1163 U8 VF_ID; /*0x09 */
1164 U16 Reserved4; /*0x0A */
1165 U32 TotalImageSize; /*0x0C */
1166 U32 Reserved5; /*0x10 */
1167 U32 Reserved6; /*0x14 */
1168 U32 ImageOffset; /*0x18 */
1169 U32 ImageSize; /*0x1C */
1170 MPI25_SGE_IO_UNION SGL; /*0x20 */
1171} MPI25_FW_DOWNLOAD_REQUEST, *PTR_MPI25_FW_DOWNLOAD_REQUEST,
1172 Mpi25FWDownloadRequest, *pMpi25FWDownloadRequest;
1173
1174/*FWDownload Reply message */
1175typedef struct _MPI2_FW_DOWNLOAD_REPLY {
1176 U8 ImageType; /*0x00 */
1177 U8 Reserved1; /*0x01 */
1178 U8 MsgLength; /*0x02 */
1179 U8 Function; /*0x03 */
1180 U16 Reserved2; /*0x04 */
1181 U8 Reserved3; /*0x06 */
1182 U8 MsgFlags; /*0x07 */
1183 U8 VP_ID; /*0x08 */
1184 U8 VF_ID; /*0x09 */
1185 U16 Reserved4; /*0x0A */
1186 U16 Reserved5; /*0x0C */
1187 U16 IOCStatus; /*0x0E */
1188 U32 IOCLogInfo; /*0x10 */
1189} MPI2_FW_DOWNLOAD_REPLY, *PTR_MPI2_FW_DOWNLOAD_REPLY,
1190 Mpi2FWDownloadReply_t, *pMpi2FWDownloadReply_t;
1191
1192/****************************************************************************
1193* FWUpload message
1194****************************************************************************/
1195
1196/*MPI v2.0 FWUpload Request message */
1197typedef struct _MPI2_FW_UPLOAD_REQUEST {
1198 U8 ImageType; /*0x00 */
1199 U8 Reserved1; /*0x01 */
1200 U8 ChainOffset; /*0x02 */
1201 U8 Function; /*0x03 */
1202 U16 Reserved2; /*0x04 */
1203 U8 Reserved3; /*0x06 */
1204 U8 MsgFlags; /*0x07 */
1205 U8 VP_ID; /*0x08 */
1206 U8 VF_ID; /*0x09 */
1207 U16 Reserved4; /*0x0A */
1208 U32 Reserved5; /*0x0C */
1209 U32 Reserved6; /*0x10 */
1210 MPI2_MPI_SGE_UNION SGL; /*0x14 */
1211} MPI2_FW_UPLOAD_REQUEST, *PTR_MPI2_FW_UPLOAD_REQUEST,
1212 Mpi2FWUploadRequest_t, *pMpi2FWUploadRequest_t;
1213
1214#define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00)
1215#define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01)
1216#define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02)
1217#define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05)
1218#define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06)
1219#define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07)
1220#define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08)
1221#define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09)
1222#define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A)
1223#define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B)
1224
1225/*MPI v2.0 FWUpload TransactionContext Element */
1226typedef struct _MPI2_FW_UPLOAD_TCSGE {
1227 U8 Reserved1; /*0x00 */
1228 U8 ContextSize; /*0x01 */
1229 U8 DetailsLength; /*0x02 */
1230 U8 Flags; /*0x03 */
1231 U32 Reserved2; /*0x04 */
1232 U32 ImageOffset; /*0x08 */
1233 U32 ImageSize; /*0x0C */
1234} MPI2_FW_UPLOAD_TCSGE, *PTR_MPI2_FW_UPLOAD_TCSGE,
1235 Mpi2FWUploadTCSGE_t, *pMpi2FWUploadTCSGE_t;
1236
1237/*MPI v2.5 FWUpload Request message */
1238typedef struct _MPI25_FW_UPLOAD_REQUEST {
1239 U8 ImageType; /*0x00 */
1240 U8 Reserved1; /*0x01 */
1241 U8 ChainOffset; /*0x02 */
1242 U8 Function; /*0x03 */
1243 U16 Reserved2; /*0x04 */
1244 U8 Reserved3; /*0x06 */
1245 U8 MsgFlags; /*0x07 */
1246 U8 VP_ID; /*0x08 */
1247 U8 VF_ID; /*0x09 */
1248 U16 Reserved4; /*0x0A */
1249 U32 Reserved5; /*0x0C */
1250 U32 Reserved6; /*0x10 */
1251 U32 Reserved7; /*0x14 */
1252 U32 ImageOffset; /*0x18 */
1253 U32 ImageSize; /*0x1C */
1254 MPI25_SGE_IO_UNION SGL; /*0x20 */
1255} MPI25_FW_UPLOAD_REQUEST, *PTR_MPI25_FW_UPLOAD_REQUEST,
1256 Mpi25FWUploadRequest_t, *pMpi25FWUploadRequest_t;
1257
1258/*FWUpload Reply message */
1259typedef struct _MPI2_FW_UPLOAD_REPLY {
1260 U8 ImageType; /*0x00 */
1261 U8 Reserved1; /*0x01 */
1262 U8 MsgLength; /*0x02 */
1263 U8 Function; /*0x03 */
1264 U16 Reserved2; /*0x04 */
1265 U8 Reserved3; /*0x06 */
1266 U8 MsgFlags; /*0x07 */
1267 U8 VP_ID; /*0x08 */
1268 U8 VF_ID; /*0x09 */
1269 U16 Reserved4; /*0x0A */
1270 U16 Reserved5; /*0x0C */
1271 U16 IOCStatus; /*0x0E */
1272 U32 IOCLogInfo; /*0x10 */
1273 U32 ActualImageSize; /*0x14 */
1274} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1275 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1276
1277/*FW Image Header */
1278typedef struct _MPI2_FW_IMAGE_HEADER {
1279 U32 Signature; /*0x00 */
1280 U32 Signature0; /*0x04 */
1281 U32 Signature1; /*0x08 */
1282 U32 Signature2; /*0x0C */
1283 MPI2_VERSION_UNION MPIVersion; /*0x10 */
1284 MPI2_VERSION_UNION FWVersion; /*0x14 */
1285 MPI2_VERSION_UNION NVDATAVersion; /*0x18 */
1286 MPI2_VERSION_UNION PackageVersion; /*0x1C */
1287 U16 VendorID; /*0x20 */
1288 U16 ProductID; /*0x22 */
1289 U16 ProtocolFlags; /*0x24 */
1290 U16 Reserved26; /*0x26 */
1291 U32 IOCCapabilities; /*0x28 */
1292 U32 ImageSize; /*0x2C */
1293 U32 NextImageHeaderOffset; /*0x30 */
1294 U32 Checksum; /*0x34 */
1295 U32 Reserved38; /*0x38 */
1296 U32 Reserved3C; /*0x3C */
1297 U32 Reserved40; /*0x40 */
1298 U32 Reserved44; /*0x44 */
1299 U32 Reserved48; /*0x48 */
1300 U32 Reserved4C; /*0x4C */
1301 U32 Reserved50; /*0x50 */
1302 U32 Reserved54; /*0x54 */
1303 U32 Reserved58; /*0x58 */
1304 U32 Reserved5C; /*0x5C */
1305 U32 Reserved60; /*0x60 */
1306 U32 FirmwareVersionNameWhat; /*0x64 */
1307 U8 FirmwareVersionName[32]; /*0x68 */
1308 U32 VendorNameWhat; /*0x88 */
1309 U8 VendorName[32]; /*0x8C */
1310 U32 PackageNameWhat; /*0x88 */
1311 U8 PackageName[32]; /*0x8C */
1312 U32 ReservedD0; /*0xD0 */
1313 U32 ReservedD4; /*0xD4 */
1314 U32 ReservedD8; /*0xD8 */
1315 U32 ReservedDC; /*0xDC */
1316 U32 ReservedE0; /*0xE0 */
1317 U32 ReservedE4; /*0xE4 */
1318 U32 ReservedE8; /*0xE8 */
1319 U32 ReservedEC; /*0xEC */
1320 U32 ReservedF0; /*0xF0 */
1321 U32 ReservedF4; /*0xF4 */
1322 U32 ReservedF8; /*0xF8 */
1323 U32 ReservedFC; /*0xFC */
1324} MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1325 Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1326
1327/*Signature field */
1328#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1329#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1330#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1331
1332/*Signature0 field */
1333#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1334#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1335
1336/*Signature1 field */
1337#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1338#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1339
1340/*Signature2 field */
1341#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1342#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1343
1344/*defines for using the ProductID field */
1345#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1346#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1347
1348#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1349#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1350#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1351#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1352
1353#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1354/*SAS ProductID Family bits */
1355#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1356#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1357#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1358
1359/*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1360
1361/*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1362
1363#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1364#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1365#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1366
1367#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1368
1369#define MPI2_FW_HEADER_SIZE (0x100)
1370
1371/*Extended Image Header */
1372typedef struct _MPI2_EXT_IMAGE_HEADER {
1373 U8 ImageType; /*0x00 */
1374 U8 Reserved1; /*0x01 */
1375 U16 Reserved2; /*0x02 */
1376 U32 Checksum; /*0x04 */
1377 U32 ImageSize; /*0x08 */
1378 U32 NextImageHeaderOffset; /*0x0C */
1379 U32 PackageVersion; /*0x10 */
1380 U32 Reserved3; /*0x14 */
1381 U32 Reserved4; /*0x18 */
1382 U32 Reserved5; /*0x1C */
1383 U8 IdentifyString[32]; /*0x20 */
1384} MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1385 Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1386
1387/*useful offsets */
1388#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1389#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1390#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1391
1392#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1393
1394/*defines for the ImageType field */
1395#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1396#define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1397#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1398#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1399#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1400#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1401#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1402#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1403#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1404#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1405
1406#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1407
1408/*FLASH Layout Extended Image Data */
1409
1410/*
1411 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1412 *one and check RegionsPerLayout at runtime.
1413 */
1414#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1415#define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1416#endif
1417
1418/*
1419 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1420 *one and check NumberOfLayouts at runtime.
1421 */
1422#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1423#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1424#endif
1425
1426typedef struct _MPI2_FLASH_REGION {
1427 U8 RegionType; /*0x00 */
1428 U8 Reserved1; /*0x01 */
1429 U16 Reserved2; /*0x02 */
1430 U32 RegionOffset; /*0x04 */
1431 U32 RegionSize; /*0x08 */
1432 U32 Reserved3; /*0x0C */
1433} MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1434 Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1435
1436typedef struct _MPI2_FLASH_LAYOUT {
1437 U32 FlashSize; /*0x00 */
1438 U32 Reserved1; /*0x04 */
1439 U32 Reserved2; /*0x08 */
1440 U32 Reserved3; /*0x0C */
1441 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
1442} MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1443 Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1444
1445typedef struct _MPI2_FLASH_LAYOUT_DATA {
1446 U8 ImageRevision; /*0x00 */
1447 U8 Reserved1; /*0x01 */
1448 U8 SizeOfRegion; /*0x02 */
1449 U8 Reserved2; /*0x03 */
1450 U16 NumberOfLayouts; /*0x04 */
1451 U16 RegionsPerLayout; /*0x06 */
1452 U16 MinimumSectorAlignment; /*0x08 */
1453 U16 Reserved3; /*0x0A */
1454 U32 Reserved4; /*0x0C */
1455 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
1456} MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1457 Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1458
1459/*defines for the RegionType field */
1460#define MPI2_FLASH_REGION_UNUSED (0x00)
1461#define MPI2_FLASH_REGION_FIRMWARE (0x01)
1462#define MPI2_FLASH_REGION_BIOS (0x02)
1463#define MPI2_FLASH_REGION_NVDATA (0x03)
1464#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1465#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1466#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1467#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1468#define MPI2_FLASH_REGION_MEGARAID (0x09)
1469#define MPI2_FLASH_REGION_INIT (0x0A)
1470
1471/*ImageRevision */
1472#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1473
1474/*Supported Devices Extended Image Data */
1475
1476/*
1477 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1478 *one and check NumberOfDevices at runtime.
1479 */
1480#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1481#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1482#endif
1483
1484typedef struct _MPI2_SUPPORTED_DEVICE {
1485 U16 DeviceID; /*0x00 */
1486 U16 VendorID; /*0x02 */
1487 U16 DeviceIDMask; /*0x04 */
1488 U16 Reserved1; /*0x06 */
1489 U8 LowPCIRev; /*0x08 */
1490 U8 HighPCIRev; /*0x09 */
1491 U16 Reserved2; /*0x0A */
1492 U32 Reserved3; /*0x0C */
1493} MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1494 Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1495
1496typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1497 U8 ImageRevision; /*0x00 */
1498 U8 Reserved1; /*0x01 */
1499 U8 NumberOfDevices; /*0x02 */
1500 U8 Reserved2; /*0x03 */
1501 U32 Reserved3; /*0x04 */
1502 MPI2_SUPPORTED_DEVICE
1503 SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1504} MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1505 Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1506
1507/*ImageRevision */
1508#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1509
1510/*Init Extended Image Data */
1511
1512typedef struct _MPI2_INIT_IMAGE_FOOTER {
1513 U32 BootFlags; /*0x00 */
1514 U32 ImageSize; /*0x04 */
1515 U32 Signature0; /*0x08 */
1516 U32 Signature1; /*0x0C */
1517 U32 Signature2; /*0x10 */
1518 U32 ResetVector; /*0x14 */
1519} MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1520 Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1521
1522/*defines for the BootFlags field */
1523#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1524
1525/*defines for the ImageSize field */
1526#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1527
1528/*defines for the Signature0 field */
1529#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1530#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1531
1532/*defines for the Signature1 field */
1533#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1534#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1535
1536/*defines for the Signature2 field */
1537#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1538#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1539
1540/*Signature fields as individual bytes */
1541#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1542#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1543#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1544#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1545
1546#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1547#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1548#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1549#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1550
1551#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1552#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1553#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1554#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1555
1556/*defines for the ResetVector field */
1557#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1558
1559/****************************************************************************
1560* PowerManagementControl message
1561****************************************************************************/
1562
1563/*PowerManagementControl Request message */
1564typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST {
1565 U8 Feature; /*0x00 */
1566 U8 Reserved1; /*0x01 */
1567 U8 ChainOffset; /*0x02 */
1568 U8 Function; /*0x03 */
1569 U16 Reserved2; /*0x04 */
1570 U8 Reserved3; /*0x06 */
1571 U8 MsgFlags; /*0x07 */
1572 U8 VP_ID; /*0x08 */
1573 U8 VF_ID; /*0x09 */
1574 U16 Reserved4; /*0x0A */
1575 U8 Parameter1; /*0x0C */
1576 U8 Parameter2; /*0x0D */
1577 U8 Parameter3; /*0x0E */
1578 U8 Parameter4; /*0x0F */
1579 U32 Reserved5; /*0x10 */
1580 U32 Reserved6; /*0x14 */
1581} MPI2_PWR_MGMT_CONTROL_REQUEST, *PTR_MPI2_PWR_MGMT_CONTROL_REQUEST,
1582 Mpi2PwrMgmtControlRequest_t, *pMpi2PwrMgmtControlRequest_t;
1583
1584/*defines for the Feature field */
1585#define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01)
1586#define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02)
1587#define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) /*obsolete */
1588#define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04)
1589#define MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE (0x05)
1590#define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80)
1591#define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF)
1592
1593/*parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */
1594/*Parameter1 contains a PHY number */
1595/*Parameter2 indicates power condition action using these defines */
1596#define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01)
1597#define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02)
1598#define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03)
1599/*Parameter3 and Parameter4 are reserved */
1600
1601/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION
1602 * Feature */
1603/*Parameter1 contains SAS port width modulation group number */
1604/*Parameter2 indicates IOC action using these defines */
1605#define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01)
1606#define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02)
1607#define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03)
1608/*Parameter3 indicates desired modulation level using these defines */
1609#define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00)
1610#define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01)
1611#define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02)
1612#define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03)
1613/*Parameter4 is reserved */
1614
1615/*this next set (_PCIE_LINK) is obsolete */
1616/*parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */
1617/*Parameter1 indicates desired PCIe link speed using these defines */
1618#define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) /*obsolete */
1619#define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) /*obsolete */
1620#define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) /*obsolete */
1621/*Parameter2 indicates desired PCIe link width using these defines */
1622#define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) /*obsolete */
1623#define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) /*obsolete */
1624#define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) /*obsolete */
1625#define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) /*obsolete */
1626/*Parameter3 and Parameter4 are reserved */
1627
1628/*parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */
1629/*Parameter1 indicates desired IOC hardware clock speed using these defines */
1630#define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01)
1631#define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02)
1632#define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04)
1633#define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08)
1634/*Parameter2, Parameter3, and Parameter4 are reserved */
1635
1636/*parameter usage for the MPI2_PM_CONTROL_FEATURE_GLOBAL_PWR_MGMT_MODE Feature*/
1637/*Parameter1 indicates host action regarding global power management mode */
1638#define MPI2_PM_CONTROL_PARAM1_TAKE_CONTROL (0x01)
1639#define MPI2_PM_CONTROL_PARAM1_CHANGE_GLOBAL_MODE (0x02)
1640#define MPI2_PM_CONTROL_PARAM1_RELEASE_CONTROL (0x03)
1641/*Parameter2 indicates the requested global power management mode */
1642#define MPI2_PM_CONTROL_PARAM2_FULL_PWR_PERF (0x01)
1643#define MPI2_PM_CONTROL_PARAM2_REDUCED_PWR_PERF (0x08)
1644#define MPI2_PM_CONTROL_PARAM2_STANDBY (0x40)
1645/*Parameter3 and Parameter4 are reserved */
1646
1647/*PowerManagementControl Reply message */
1648typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY {
1649 U8 Feature; /*0x00 */
1650 U8 Reserved1; /*0x01 */
1651 U8 MsgLength; /*0x02 */
1652 U8 Function; /*0x03 */
1653 U16 Reserved2; /*0x04 */
1654 U8 Reserved3; /*0x06 */
1655 U8 MsgFlags; /*0x07 */
1656 U8 VP_ID; /*0x08 */
1657 U8 VF_ID; /*0x09 */
1658 U16 Reserved4; /*0x0A */
1659 U16 Reserved5; /*0x0C */
1660 U16 IOCStatus; /*0x0E */
1661 U32 IOCLogInfo; /*0x10 */
1662} MPI2_PWR_MGMT_CONTROL_REPLY, *PTR_MPI2_PWR_MGMT_CONTROL_REPLY,
1663 Mpi2PwrMgmtControlReply_t, *pMpi2PwrMgmtControlReply_t;
1664
1665#endif
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_raid.h b/drivers/scsi/mpt3sas/mpi/mpi2_raid.h
new file mode 100644
index 000000000000..d1d9866cf300
--- /dev/null
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_raid.h
@@ -0,0 +1,346 @@
1/*
2 * Copyright (c) 2000-2012 LSI Corporation.
3 *
4 *
5 * Name: mpi2_raid.h
6 * Title: MPI Integrated RAID messages and structures
7 * Creation Date: April 26, 2007
8 *
9 * mpi2_raid.h Version: 02.00.08
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 08-31-07 02.00.01 Modifications to RAID Action request and reply,
18 * including the Actions and ActionData.
19 * 02-29-08 02.00.02 Added MPI2_RAID_ACTION_ADATA_DISABL_FULL_REBUILD.
20 * 05-21-08 02.00.03 Added MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS so that
21 * the PhysDisk array in MPI2_RAID_VOLUME_CREATION_STRUCT
22 * can be sized by the build environment.
23 * 07-30-09 02.00.04 Added proper define for the Use Default Settings bit of
24 * VolumeCreationFlags and marked the old one as obsolete.
25 * 05-12-10 02.00.05 Added MPI2_RAID_VOL_FLAGS_OP_MDC define.
26 * 08-24-10 02.00.06 Added MPI2_RAID_ACTION_COMPATIBILITY_CHECK along with
27 * related structures and defines.
28 * Added product-specific range to RAID Action values.
29 * 11-18-11 02.00.07 Incorporating additions for MPI v2.5.
30 * 02-06-12 02.00.08 Added MPI2_RAID_ACTION_PHYSDISK_HIDDEN.
31 * --------------------------------------------------------------------------
32 */
33
34#ifndef MPI2_RAID_H
35#define MPI2_RAID_H
36
37/*****************************************************************************
38*
39* Integrated RAID Messages
40*
41*****************************************************************************/
42
43/****************************************************************************
44* RAID Action messages
45****************************************************************************/
46
47/*ActionDataWord defines for use with MPI2_RAID_ACTION_DELETE_VOLUME action */
48#define MPI2_RAID_ACTION_ADATA_KEEP_LBA0 (0x00000000)
49#define MPI2_RAID_ACTION_ADATA_ZERO_LBA0 (0x00000001)
50
51/*use MPI2_RAIDVOL0_SETTING_ defines from mpi2_cnfg.h for
52 *MPI2_RAID_ACTION_CHANGE_VOL_WRITE_CACHE action */
53
54/*ActionDataWord defines for use with
55 *MPI2_RAID_ACTION_DISABLE_ALL_VOLUMES action */
56#define MPI2_RAID_ACTION_ADATA_DISABL_FULL_REBUILD (0x00000001)
57
58/*ActionDataWord for MPI2_RAID_ACTION_SET_RAID_FUNCTION_RATE Action */
59typedef struct _MPI2_RAID_ACTION_RATE_DATA {
60 U8 RateToChange; /*0x00 */
61 U8 RateOrMode; /*0x01 */
62 U16 DataScrubDuration; /*0x02 */
63} MPI2_RAID_ACTION_RATE_DATA, *PTR_MPI2_RAID_ACTION_RATE_DATA,
64 Mpi2RaidActionRateData_t, *pMpi2RaidActionRateData_t;
65
66#define MPI2_RAID_ACTION_SET_RATE_RESYNC (0x00)
67#define MPI2_RAID_ACTION_SET_RATE_DATA_SCRUB (0x01)
68#define MPI2_RAID_ACTION_SET_RATE_POWERSAVE_MODE (0x02)
69
70/*ActionDataWord for MPI2_RAID_ACTION_START_RAID_FUNCTION Action */
71typedef struct _MPI2_RAID_ACTION_START_RAID_FUNCTION {
72 U8 RAIDFunction; /*0x00 */
73 U8 Flags; /*0x01 */
74 U16 Reserved1; /*0x02 */
75} MPI2_RAID_ACTION_START_RAID_FUNCTION,
76 *PTR_MPI2_RAID_ACTION_START_RAID_FUNCTION,
77 Mpi2RaidActionStartRaidFunction_t,
78 *pMpi2RaidActionStartRaidFunction_t;
79
80/*defines for the RAIDFunction field */
81#define MPI2_RAID_ACTION_START_BACKGROUND_INIT (0x00)
82#define MPI2_RAID_ACTION_START_ONLINE_CAP_EXPANSION (0x01)
83#define MPI2_RAID_ACTION_START_CONSISTENCY_CHECK (0x02)
84
85/*defines for the Flags field */
86#define MPI2_RAID_ACTION_START_NEW (0x00)
87#define MPI2_RAID_ACTION_START_RESUME (0x01)
88
89/*ActionDataWord for MPI2_RAID_ACTION_STOP_RAID_FUNCTION Action */
90typedef struct _MPI2_RAID_ACTION_STOP_RAID_FUNCTION {
91 U8 RAIDFunction; /*0x00 */
92 U8 Flags; /*0x01 */
93 U16 Reserved1; /*0x02 */
94} MPI2_RAID_ACTION_STOP_RAID_FUNCTION,
95 *PTR_MPI2_RAID_ACTION_STOP_RAID_FUNCTION,
96 Mpi2RaidActionStopRaidFunction_t,
97 *pMpi2RaidActionStopRaidFunction_t;
98
99/*defines for the RAIDFunction field */
100#define MPI2_RAID_ACTION_STOP_BACKGROUND_INIT (0x00)
101#define MPI2_RAID_ACTION_STOP_ONLINE_CAP_EXPANSION (0x01)
102#define MPI2_RAID_ACTION_STOP_CONSISTENCY_CHECK (0x02)
103
104/*defines for the Flags field */
105#define MPI2_RAID_ACTION_STOP_ABORT (0x00)
106#define MPI2_RAID_ACTION_STOP_PAUSE (0x01)
107
108/*ActionDataWord for MPI2_RAID_ACTION_CREATE_HOT_SPARE Action */
109typedef struct _MPI2_RAID_ACTION_HOT_SPARE {
110 U8 HotSparePool; /*0x00 */
111 U8 Reserved1; /*0x01 */
112 U16 DevHandle; /*0x02 */
113} MPI2_RAID_ACTION_HOT_SPARE, *PTR_MPI2_RAID_ACTION_HOT_SPARE,
114 Mpi2RaidActionHotSpare_t, *pMpi2RaidActionHotSpare_t;
115
116/*ActionDataWord for MPI2_RAID_ACTION_DEVICE_FW_UPDATE_MODE Action */
117typedef struct _MPI2_RAID_ACTION_FW_UPDATE_MODE {
118 U8 Flags; /*0x00 */
119 U8 DeviceFirmwareUpdateModeTimeout; /*0x01 */
120 U16 Reserved1; /*0x02 */
121} MPI2_RAID_ACTION_FW_UPDATE_MODE,
122 *PTR_MPI2_RAID_ACTION_FW_UPDATE_MODE,
123 Mpi2RaidActionFwUpdateMode_t,
124 *pMpi2RaidActionFwUpdateMode_t;
125
126/*ActionDataWord defines for use with
127 *MPI2_RAID_ACTION_DEVICE_FW_UPDATE_MODE action */
128#define MPI2_RAID_ACTION_ADATA_DISABLE_FW_UPDATE (0x00)
129#define MPI2_RAID_ACTION_ADATA_ENABLE_FW_UPDATE (0x01)
130
131typedef union _MPI2_RAID_ACTION_DATA {
132 U32 Word;
133 MPI2_RAID_ACTION_RATE_DATA Rates;
134 MPI2_RAID_ACTION_START_RAID_FUNCTION StartRaidFunction;
135 MPI2_RAID_ACTION_STOP_RAID_FUNCTION StopRaidFunction;
136 MPI2_RAID_ACTION_HOT_SPARE HotSpare;
137 MPI2_RAID_ACTION_FW_UPDATE_MODE FwUpdateMode;
138} MPI2_RAID_ACTION_DATA, *PTR_MPI2_RAID_ACTION_DATA,
139 Mpi2RaidActionData_t, *pMpi2RaidActionData_t;
140
141/*RAID Action Request Message */
142typedef struct _MPI2_RAID_ACTION_REQUEST {
143 U8 Action; /*0x00 */
144 U8 Reserved1; /*0x01 */
145 U8 ChainOffset; /*0x02 */
146 U8 Function; /*0x03 */
147 U16 VolDevHandle; /*0x04 */
148 U8 PhysDiskNum; /*0x06 */
149 U8 MsgFlags; /*0x07 */
150 U8 VP_ID; /*0x08 */
151 U8 VF_ID; /*0x09 */
152 U16 Reserved2; /*0x0A */
153 U32 Reserved3; /*0x0C */
154 MPI2_RAID_ACTION_DATA ActionDataWord; /*0x10 */
155 MPI2_SGE_SIMPLE_UNION ActionDataSGE; /*0x14 */
156} MPI2_RAID_ACTION_REQUEST, *PTR_MPI2_RAID_ACTION_REQUEST,
157 Mpi2RaidActionRequest_t, *pMpi2RaidActionRequest_t;
158
159/*RAID Action request Action values */
160
161#define MPI2_RAID_ACTION_INDICATOR_STRUCT (0x01)
162#define MPI2_RAID_ACTION_CREATE_VOLUME (0x02)
163#define MPI2_RAID_ACTION_DELETE_VOLUME (0x03)
164#define MPI2_RAID_ACTION_DISABLE_ALL_VOLUMES (0x04)
165#define MPI2_RAID_ACTION_ENABLE_ALL_VOLUMES (0x05)
166#define MPI2_RAID_ACTION_PHYSDISK_OFFLINE (0x0A)
167#define MPI2_RAID_ACTION_PHYSDISK_ONLINE (0x0B)
168#define MPI2_RAID_ACTION_FAIL_PHYSDISK (0x0F)
169#define MPI2_RAID_ACTION_ACTIVATE_VOLUME (0x11)
170#define MPI2_RAID_ACTION_DEVICE_FW_UPDATE_MODE (0x15)
171#define MPI2_RAID_ACTION_CHANGE_VOL_WRITE_CACHE (0x17)
172#define MPI2_RAID_ACTION_SET_VOLUME_NAME (0x18)
173#define MPI2_RAID_ACTION_SET_RAID_FUNCTION_RATE (0x19)
174#define MPI2_RAID_ACTION_ENABLE_FAILED_VOLUME (0x1C)
175#define MPI2_RAID_ACTION_CREATE_HOT_SPARE (0x1D)
176#define MPI2_RAID_ACTION_DELETE_HOT_SPARE (0x1E)
177#define MPI2_RAID_ACTION_SYSTEM_SHUTDOWN_INITIATED (0x20)
178#define MPI2_RAID_ACTION_START_RAID_FUNCTION (0x21)
179#define MPI2_RAID_ACTION_STOP_RAID_FUNCTION (0x22)
180#define MPI2_RAID_ACTION_COMPATIBILITY_CHECK (0x23)
181#define MPI2_RAID_ACTION_PHYSDISK_HIDDEN (0x24)
182#define MPI2_RAID_ACTION_MIN_PRODUCT_SPECIFIC (0x80)
183#define MPI2_RAID_ACTION_MAX_PRODUCT_SPECIFIC (0xFF)
184
185/*RAID Volume Creation Structure */
186
187/*
188 *The following define can be customized for the targeted product.
189 */
190#ifndef MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS
191#define MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS (1)
192#endif
193
194typedef struct _MPI2_RAID_VOLUME_PHYSDISK {
195 U8 RAIDSetNum; /*0x00 */
196 U8 PhysDiskMap; /*0x01 */
197 U16 PhysDiskDevHandle; /*0x02 */
198} MPI2_RAID_VOLUME_PHYSDISK, *PTR_MPI2_RAID_VOLUME_PHYSDISK,
199 Mpi2RaidVolumePhysDisk_t, *pMpi2RaidVolumePhysDisk_t;
200
201/*defines for the PhysDiskMap field */
202#define MPI2_RAIDACTION_PHYSDISK_PRIMARY (0x01)
203#define MPI2_RAIDACTION_PHYSDISK_SECONDARY (0x02)
204
205typedef struct _MPI2_RAID_VOLUME_CREATION_STRUCT {
206 U8 NumPhysDisks; /*0x00 */
207 U8 VolumeType; /*0x01 */
208 U16 Reserved1; /*0x02 */
209 U32 VolumeCreationFlags; /*0x04 */
210 U32 VolumeSettings; /*0x08 */
211 U8 Reserved2; /*0x0C */
212 U8 ResyncRate; /*0x0D */
213 U16 DataScrubDuration; /*0x0E */
214 U64 VolumeMaxLBA; /*0x10 */
215 U32 StripeSize; /*0x18 */
216 U8 Name[16]; /*0x1C */
217 MPI2_RAID_VOLUME_PHYSDISK
218 PhysDisk[MPI2_RAID_VOL_CREATION_NUM_PHYSDISKS]; /*0x2C */
219} MPI2_RAID_VOLUME_CREATION_STRUCT,
220 *PTR_MPI2_RAID_VOLUME_CREATION_STRUCT,
221 Mpi2RaidVolumeCreationStruct_t,
222 *pMpi2RaidVolumeCreationStruct_t;
223
224/*use MPI2_RAID_VOL_TYPE_ defines from mpi2_cnfg.h for VolumeType */
225
226/*defines for the VolumeCreationFlags field */
227#define MPI2_RAID_VOL_CREATION_DEFAULT_SETTINGS (0x80000000)
228#define MPI2_RAID_VOL_CREATION_BACKGROUND_INIT (0x00000004)
229#define MPI2_RAID_VOL_CREATION_LOW_LEVEL_INIT (0x00000002)
230#define MPI2_RAID_VOL_CREATION_MIGRATE_DATA (0x00000001)
231/*The following is an obsolete define.
232 *It must be shifted left 24 bits in order to set the proper bit.
233 */
234#define MPI2_RAID_VOL_CREATION_USE_DEFAULT_SETTINGS (0x80)
235
236/*RAID Online Capacity Expansion Structure */
237
238typedef struct _MPI2_RAID_ONLINE_CAPACITY_EXPANSION {
239 U32 Flags; /*0x00 */
240 U16 DevHandle0; /*0x04 */
241 U16 Reserved1; /*0x06 */
242 U16 DevHandle1; /*0x08 */
243 U16 Reserved2; /*0x0A */
244} MPI2_RAID_ONLINE_CAPACITY_EXPANSION,
245 *PTR_MPI2_RAID_ONLINE_CAPACITY_EXPANSION,
246 Mpi2RaidOnlineCapacityExpansion_t,
247 *pMpi2RaidOnlineCapacityExpansion_t;
248
249/*RAID Compatibility Input Structure */
250
251typedef struct _MPI2_RAID_COMPATIBILITY_INPUT_STRUCT {
252 U16 SourceDevHandle; /*0x00 */
253 U16 CandidateDevHandle; /*0x02 */
254 U32 Flags; /*0x04 */
255 U32 Reserved1; /*0x08 */
256 U32 Reserved2; /*0x0C */
257} MPI2_RAID_COMPATIBILITY_INPUT_STRUCT,
258 *PTR_MPI2_RAID_COMPATIBILITY_INPUT_STRUCT,
259 Mpi2RaidCompatibilityInputStruct_t,
260 *pMpi2RaidCompatibilityInputStruct_t;
261
262/*defines for RAID Compatibility Structure Flags field */
263#define MPI2_RAID_COMPAT_SOURCE_IS_VOLUME_FLAG (0x00000002)
264#define MPI2_RAID_COMPAT_REPORT_SOURCE_INFO_FLAG (0x00000001)
265
266/*RAID Volume Indicator Structure */
267
268typedef struct _MPI2_RAID_VOL_INDICATOR {
269 U64 TotalBlocks; /*0x00 */
270 U64 BlocksRemaining; /*0x08 */
271 U32 Flags; /*0x10 */
272} MPI2_RAID_VOL_INDICATOR, *PTR_MPI2_RAID_VOL_INDICATOR,
273 Mpi2RaidVolIndicator_t, *pMpi2RaidVolIndicator_t;
274
275/*defines for RAID Volume Indicator Flags field */
276#define MPI2_RAID_VOL_FLAGS_OP_MASK (0x0000000F)
277#define MPI2_RAID_VOL_FLAGS_OP_BACKGROUND_INIT (0x00000000)
278#define MPI2_RAID_VOL_FLAGS_OP_ONLINE_CAP_EXPANSION (0x00000001)
279#define MPI2_RAID_VOL_FLAGS_OP_CONSISTENCY_CHECK (0x00000002)
280#define MPI2_RAID_VOL_FLAGS_OP_RESYNC (0x00000003)
281#define MPI2_RAID_VOL_FLAGS_OP_MDC (0x00000004)
282
283/*RAID Compatibility Result Structure */
284
285typedef struct _MPI2_RAID_COMPATIBILITY_RESULT_STRUCT {
286 U8 State; /*0x00 */
287 U8 Reserved1; /*0x01 */
288 U16 Reserved2; /*0x02 */
289 U32 GenericAttributes; /*0x04 */
290 U32 OEMSpecificAttributes; /*0x08 */
291 U32 Reserved3; /*0x0C */
292 U32 Reserved4; /*0x10 */
293} MPI2_RAID_COMPATIBILITY_RESULT_STRUCT,
294 *PTR_MPI2_RAID_COMPATIBILITY_RESULT_STRUCT,
295 Mpi2RaidCompatibilityResultStruct_t,
296 *pMpi2RaidCompatibilityResultStruct_t;
297
298/*defines for RAID Compatibility Result Structure State field */
299#define MPI2_RAID_COMPAT_STATE_COMPATIBLE (0x00)
300#define MPI2_RAID_COMPAT_STATE_NOT_COMPATIBLE (0x01)
301
302/*defines for RAID Compatibility Result Structure GenericAttributes field */
303#define MPI2_RAID_COMPAT_GENATTRIB_4K_SECTOR (0x00000010)
304
305#define MPI2_RAID_COMPAT_GENATTRIB_MEDIA_MASK (0x0000000C)
306#define MPI2_RAID_COMPAT_GENATTRIB_SOLID_STATE_DRIVE (0x00000008)
307#define MPI2_RAID_COMPAT_GENATTRIB_HARD_DISK_DRIVE (0x00000004)
308
309#define MPI2_RAID_COMPAT_GENATTRIB_PROTOCOL_MASK (0x00000003)
310#define MPI2_RAID_COMPAT_GENATTRIB_SAS_PROTOCOL (0x00000002)
311#define MPI2_RAID_COMPAT_GENATTRIB_SATA_PROTOCOL (0x00000001)
312
313/*RAID Action Reply ActionData union */
314typedef union _MPI2_RAID_ACTION_REPLY_DATA {
315 U32 Word[5];
316 MPI2_RAID_VOL_INDICATOR RaidVolumeIndicator;
317 U16 VolDevHandle;
318 U8 VolumeState;
319 U8 PhysDiskNum;
320 MPI2_RAID_COMPATIBILITY_RESULT_STRUCT RaidCompatibilityResult;
321} MPI2_RAID_ACTION_REPLY_DATA, *PTR_MPI2_RAID_ACTION_REPLY_DATA,
322 Mpi2RaidActionReplyData_t, *pMpi2RaidActionReplyData_t;
323
324/*use MPI2_RAIDVOL0_SETTING_ defines from mpi2_cnfg.h for
325 *MPI2_RAID_ACTION_CHANGE_VOL_WRITE_CACHE action */
326
327/*RAID Action Reply Message */
328typedef struct _MPI2_RAID_ACTION_REPLY {
329 U8 Action; /*0x00 */
330 U8 Reserved1; /*0x01 */
331 U8 MsgLength; /*0x02 */
332 U8 Function; /*0x03 */
333 U16 VolDevHandle; /*0x04 */
334 U8 PhysDiskNum; /*0x06 */
335 U8 MsgFlags; /*0x07 */
336 U8 VP_ID; /*0x08 */
337 U8 VF_ID; /*0x09 */
338 U16 Reserved2; /*0x0A */
339 U16 Reserved3; /*0x0C */
340 U16 IOCStatus; /*0x0E */
341 U32 IOCLogInfo; /*0x10 */
342 MPI2_RAID_ACTION_REPLY_DATA ActionData; /*0x14 */
343} MPI2_RAID_ACTION_REPLY, *PTR_MPI2_RAID_ACTION_REPLY,
344 Mpi2RaidActionReply_t, *pMpi2RaidActionReply_t;
345
346#endif
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_sas.h b/drivers/scsi/mpt3sas/mpi/mpi2_sas.h
new file mode 100644
index 000000000000..b4e7084aba31
--- /dev/null
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_sas.h
@@ -0,0 +1,295 @@
1/*
2 * Copyright (c) 2000-2012 LSI Corporation.
3 *
4 *
5 * Name: mpi2_sas.h
6 * Title: MPI Serial Attached SCSI structures and definitions
7 * Creation Date: February 9, 2007
8 *
9 * mpi2_sas.h Version: 02.00.07
10 *
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used
13 * with MPI v2.0 products. Unless otherwise noted, names beginning with
14 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products.
15 *
16 * Version History
17 * ---------------
18 *
19 * Date Version Description
20 * -------- -------- ------------------------------------------------------
21 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
22 * 06-26-07 02.00.01 Added Clear All Persistent Operation to SAS IO Unit
23 * Control Request.
24 * 10-02-08 02.00.02 Added Set IOC Parameter Operation to SAS IO Unit Control
25 * Request.
26 * 10-28-09 02.00.03 Changed the type of SGL in MPI2_SATA_PASSTHROUGH_REQUEST
27 * to MPI2_SGE_IO_UNION since it supports chained SGLs.
28 * 05-12-10 02.00.04 Modified some comments.
29 * 08-11-10 02.00.05 Added NCQ operations to SAS IO Unit Control.
30 * 11-18-11 02.00.06 Incorporating additions for MPI v2.5.
31 * 07-10-12 02.00.07 Added MPI2_SATA_PT_SGE_UNION for use in the SATA
32 * Passthrough Request message.
33 * --------------------------------------------------------------------------
34 */
35
36#ifndef MPI2_SAS_H
37#define MPI2_SAS_H
38
39/*
40 *Values for SASStatus.
41 */
42#define MPI2_SASSTATUS_SUCCESS (0x00)
43#define MPI2_SASSTATUS_UNKNOWN_ERROR (0x01)
44#define MPI2_SASSTATUS_INVALID_FRAME (0x02)
45#define MPI2_SASSTATUS_UTC_BAD_DEST (0x03)
46#define MPI2_SASSTATUS_UTC_BREAK_RECEIVED (0x04)
47#define MPI2_SASSTATUS_UTC_CONNECT_RATE_NOT_SUPPORTED (0x05)
48#define MPI2_SASSTATUS_UTC_PORT_LAYER_REQUEST (0x06)
49#define MPI2_SASSTATUS_UTC_PROTOCOL_NOT_SUPPORTED (0x07)
50#define MPI2_SASSTATUS_UTC_STP_RESOURCES_BUSY (0x08)
51#define MPI2_SASSTATUS_UTC_WRONG_DESTINATION (0x09)
52#define MPI2_SASSTATUS_SHORT_INFORMATION_UNIT (0x0A)
53#define MPI2_SASSTATUS_LONG_INFORMATION_UNIT (0x0B)
54#define MPI2_SASSTATUS_XFER_RDY_INCORRECT_WRITE_DATA (0x0C)
55#define MPI2_SASSTATUS_XFER_RDY_REQUEST_OFFSET_ERROR (0x0D)
56#define MPI2_SASSTATUS_XFER_RDY_NOT_EXPECTED (0x0E)
57#define MPI2_SASSTATUS_DATA_INCORRECT_DATA_LENGTH (0x0F)
58#define MPI2_SASSTATUS_DATA_TOO_MUCH_READ_DATA (0x10)
59#define MPI2_SASSTATUS_DATA_OFFSET_ERROR (0x11)
60#define MPI2_SASSTATUS_SDSF_NAK_RECEIVED (0x12)
61#define MPI2_SASSTATUS_SDSF_CONNECTION_FAILED (0x13)
62#define MPI2_SASSTATUS_INITIATOR_RESPONSE_TIMEOUT (0x14)
63
64/*
65 *Values for the SAS DeviceInfo field used in SAS Device Status Change Event
66 *data and SAS Configuration pages.
67 */
68#define MPI2_SAS_DEVICE_INFO_SEP (0x00004000)
69#define MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE (0x00002000)
70#define MPI2_SAS_DEVICE_INFO_LSI_DEVICE (0x00001000)
71#define MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH (0x00000800)
72#define MPI2_SAS_DEVICE_INFO_SSP_TARGET (0x00000400)
73#define MPI2_SAS_DEVICE_INFO_STP_TARGET (0x00000200)
74#define MPI2_SAS_DEVICE_INFO_SMP_TARGET (0x00000100)
75#define MPI2_SAS_DEVICE_INFO_SATA_DEVICE (0x00000080)
76#define MPI2_SAS_DEVICE_INFO_SSP_INITIATOR (0x00000040)
77#define MPI2_SAS_DEVICE_INFO_STP_INITIATOR (0x00000020)
78#define MPI2_SAS_DEVICE_INFO_SMP_INITIATOR (0x00000010)
79#define MPI2_SAS_DEVICE_INFO_SATA_HOST (0x00000008)
80
81#define MPI2_SAS_DEVICE_INFO_MASK_DEVICE_TYPE (0x00000007)
82#define MPI2_SAS_DEVICE_INFO_NO_DEVICE (0x00000000)
83#define MPI2_SAS_DEVICE_INFO_END_DEVICE (0x00000001)
84#define MPI2_SAS_DEVICE_INFO_EDGE_EXPANDER (0x00000002)
85#define MPI2_SAS_DEVICE_INFO_FANOUT_EXPANDER (0x00000003)
86
87/*****************************************************************************
88*
89* SAS Messages
90*
91*****************************************************************************/
92
93/****************************************************************************
94* SMP Passthrough messages
95****************************************************************************/
96
97/*SMP Passthrough Request Message */
98typedef struct _MPI2_SMP_PASSTHROUGH_REQUEST {
99 U8 PassthroughFlags; /*0x00 */
100 U8 PhysicalPort; /*0x01 */
101 U8 ChainOffset; /*0x02 */
102 U8 Function; /*0x03 */
103 U16 RequestDataLength; /*0x04 */
104 U8 SGLFlags; /*0x06*//*MPI v2.0 only. Reserved on MPI v2.5*/
105 U8 MsgFlags; /*0x07 */
106 U8 VP_ID; /*0x08 */
107 U8 VF_ID; /*0x09 */
108 U16 Reserved1; /*0x0A */
109 U32 Reserved2; /*0x0C */
110 U64 SASAddress; /*0x10 */
111 U32 Reserved3; /*0x18 */
112 U32 Reserved4; /*0x1C */
113 MPI2_SIMPLE_SGE_UNION SGL;/*0x20 */
114} MPI2_SMP_PASSTHROUGH_REQUEST, *PTR_MPI2_SMP_PASSTHROUGH_REQUEST,
115 Mpi2SmpPassthroughRequest_t, *pMpi2SmpPassthroughRequest_t;
116
117/*values for PassthroughFlags field */
118#define MPI2_SMP_PT_REQ_PT_FLAGS_IMMEDIATE (0x80)
119
120/*MPI v2.0: use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
121
122/*SMP Passthrough Reply Message */
123typedef struct _MPI2_SMP_PASSTHROUGH_REPLY {
124 U8 PassthroughFlags; /*0x00 */
125 U8 PhysicalPort; /*0x01 */
126 U8 MsgLength; /*0x02 */
127 U8 Function; /*0x03 */
128 U16 ResponseDataLength; /*0x04 */
129 U8 SGLFlags; /*0x06 */
130 U8 MsgFlags; /*0x07 */
131 U8 VP_ID; /*0x08 */
132 U8 VF_ID; /*0x09 */
133 U16 Reserved1; /*0x0A */
134 U8 Reserved2; /*0x0C */
135 U8 SASStatus; /*0x0D */
136 U16 IOCStatus; /*0x0E */
137 U32 IOCLogInfo; /*0x10 */
138 U32 Reserved3; /*0x14 */
139 U8 ResponseData[4]; /*0x18 */
140} MPI2_SMP_PASSTHROUGH_REPLY, *PTR_MPI2_SMP_PASSTHROUGH_REPLY,
141 Mpi2SmpPassthroughReply_t, *pMpi2SmpPassthroughReply_t;
142
143/*values for PassthroughFlags field */
144#define MPI2_SMP_PT_REPLY_PT_FLAGS_IMMEDIATE (0x80)
145
146/*values for SASStatus field are at the top of this file */
147
148/****************************************************************************
149* SATA Passthrough messages
150****************************************************************************/
151
152typedef union _MPI2_SATA_PT_SGE_UNION {
153 MPI2_SGE_SIMPLE_UNION MpiSimple; /*MPI v2.0 only */
154 MPI2_SGE_CHAIN_UNION MpiChain; /*MPI v2.0 only */
155 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple;
156 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; /*MPI v2.0 only */
157 MPI25_IEEE_SGE_CHAIN64 IeeeChain64; /*MPI v2.5 only */
158} MPI2_SATA_PT_SGE_UNION, *PTR_MPI2_SATA_PT_SGE_UNION,
159 Mpi2SataPTSGEUnion_t, *pMpi2SataPTSGEUnion_t;
160
161/*SATA Passthrough Request Message */
162typedef struct _MPI2_SATA_PASSTHROUGH_REQUEST {
163 U16 DevHandle; /*0x00 */
164 U8 ChainOffset; /*0x02 */
165 U8 Function; /*0x03 */
166 U16 PassthroughFlags; /*0x04 */
167 U8 SGLFlags; /*0x06*//*MPI v2.0 only. Reserved on MPI v2.5*/
168 U8 MsgFlags; /*0x07 */
169 U8 VP_ID; /*0x08 */
170 U8 VF_ID; /*0x09 */
171 U16 Reserved1; /*0x0A */
172 U32 Reserved2; /*0x0C */
173 U32 Reserved3; /*0x10 */
174 U32 Reserved4; /*0x14 */
175 U32 DataLength; /*0x18 */
176 U8 CommandFIS[20]; /*0x1C */
177 MPI2_SATA_PT_SGE_UNION SGL;/*0x30*//*MPI v2.5: IEEE 64 elements only*/
178} MPI2_SATA_PASSTHROUGH_REQUEST, *PTR_MPI2_SATA_PASSTHROUGH_REQUEST,
179 Mpi2SataPassthroughRequest_t,
180 *pMpi2SataPassthroughRequest_t;
181
182/*values for PassthroughFlags field */
183#define MPI2_SATA_PT_REQ_PT_FLAGS_EXECUTE_DIAG (0x0100)
184#define MPI2_SATA_PT_REQ_PT_FLAGS_DMA (0x0020)
185#define MPI2_SATA_PT_REQ_PT_FLAGS_PIO (0x0010)
186#define MPI2_SATA_PT_REQ_PT_FLAGS_UNSPECIFIED_VU (0x0004)
187#define MPI2_SATA_PT_REQ_PT_FLAGS_WRITE (0x0002)
188#define MPI2_SATA_PT_REQ_PT_FLAGS_READ (0x0001)
189
190/*MPI v2.0: use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
191
192/*SATA Passthrough Reply Message */
193typedef struct _MPI2_SATA_PASSTHROUGH_REPLY {
194 U16 DevHandle; /*0x00 */
195 U8 MsgLength; /*0x02 */
196 U8 Function; /*0x03 */
197 U16 PassthroughFlags; /*0x04 */
198 U8 SGLFlags; /*0x06 */
199 U8 MsgFlags; /*0x07 */
200 U8 VP_ID; /*0x08 */
201 U8 VF_ID; /*0x09 */
202 U16 Reserved1; /*0x0A */
203 U8 Reserved2; /*0x0C */
204 U8 SASStatus; /*0x0D */
205 U16 IOCStatus; /*0x0E */
206 U32 IOCLogInfo; /*0x10 */
207 U8 StatusFIS[20]; /*0x14 */
208 U32 StatusControlRegisters; /*0x28 */
209 U32 TransferCount; /*0x2C */
210} MPI2_SATA_PASSTHROUGH_REPLY, *PTR_MPI2_SATA_PASSTHROUGH_REPLY,
211 Mpi2SataPassthroughReply_t, *pMpi2SataPassthroughReply_t;
212
213/*values for SASStatus field are at the top of this file */
214
215/****************************************************************************
216* SAS IO Unit Control messages
217****************************************************************************/
218
219/*SAS IO Unit Control Request Message */
220typedef struct _MPI2_SAS_IOUNIT_CONTROL_REQUEST {
221 U8 Operation; /*0x00 */
222 U8 Reserved1; /*0x01 */
223 U8 ChainOffset; /*0x02 */
224 U8 Function; /*0x03 */
225 U16 DevHandle; /*0x04 */
226 U8 IOCParameter; /*0x06 */
227 U8 MsgFlags; /*0x07 */
228 U8 VP_ID; /*0x08 */
229 U8 VF_ID; /*0x09 */
230 U16 Reserved3; /*0x0A */
231 U16 Reserved4; /*0x0C */
232 U8 PhyNum; /*0x0E */
233 U8 PrimFlags; /*0x0F */
234 U32 Primitive; /*0x10 */
235 U8 LookupMethod; /*0x14 */
236 U8 Reserved5; /*0x15 */
237 U16 SlotNumber; /*0x16 */
238 U64 LookupAddress; /*0x18 */
239 U32 IOCParameterValue; /*0x20 */
240 U32 Reserved7; /*0x24 */
241 U32 Reserved8; /*0x28 */
242} MPI2_SAS_IOUNIT_CONTROL_REQUEST,
243 *PTR_MPI2_SAS_IOUNIT_CONTROL_REQUEST,
244 Mpi2SasIoUnitControlRequest_t,
245 *pMpi2SasIoUnitControlRequest_t;
246
247/*values for the Operation field */
248#define MPI2_SAS_OP_CLEAR_ALL_PERSISTENT (0x02)
249#define MPI2_SAS_OP_PHY_LINK_RESET (0x06)
250#define MPI2_SAS_OP_PHY_HARD_RESET (0x07)
251#define MPI2_SAS_OP_PHY_CLEAR_ERROR_LOG (0x08)
252#define MPI2_SAS_OP_SEND_PRIMITIVE (0x0A)
253#define MPI2_SAS_OP_FORCE_FULL_DISCOVERY (0x0B)
254#define MPI2_SAS_OP_TRANSMIT_PORT_SELECT_SIGNAL (0x0C)
255#define MPI2_SAS_OP_REMOVE_DEVICE (0x0D)
256#define MPI2_SAS_OP_LOOKUP_MAPPING (0x0E)
257#define MPI2_SAS_OP_SET_IOC_PARAMETER (0x0F)
258#define MPI25_SAS_OP_ENABLE_FP_DEVICE (0x10)
259#define MPI25_SAS_OP_DISABLE_FP_DEVICE (0x11)
260#define MPI25_SAS_OP_ENABLE_FP_ALL (0x12)
261#define MPI25_SAS_OP_DISABLE_FP_ALL (0x13)
262#define MPI2_SAS_OP_DEV_ENABLE_NCQ (0x14)
263#define MPI2_SAS_OP_DEV_DISABLE_NCQ (0x15)
264#define MPI2_SAS_OP_PRODUCT_SPECIFIC_MIN (0x80)
265
266/*values for the PrimFlags field */
267#define MPI2_SAS_PRIMFLAGS_SINGLE (0x08)
268#define MPI2_SAS_PRIMFLAGS_TRIPLE (0x02)
269#define MPI2_SAS_PRIMFLAGS_REDUNDANT (0x01)
270
271/*values for the LookupMethod field */
272#define MPI2_SAS_LOOKUP_METHOD_SAS_ADDRESS (0x01)
273#define MPI2_SAS_LOOKUP_METHOD_SAS_ENCLOSURE_SLOT (0x02)
274#define MPI2_SAS_LOOKUP_METHOD_SAS_DEVICE_NAME (0x03)
275
276/*SAS IO Unit Control Reply Message */
277typedef struct _MPI2_SAS_IOUNIT_CONTROL_REPLY {
278 U8 Operation; /*0x00 */
279 U8 Reserved1; /*0x01 */
280 U8 MsgLength; /*0x02 */
281 U8 Function; /*0x03 */
282 U16 DevHandle; /*0x04 */
283 U8 IOCParameter; /*0x06 */
284 U8 MsgFlags; /*0x07 */
285 U8 VP_ID; /*0x08 */
286 U8 VF_ID; /*0x09 */
287 U16 Reserved3; /*0x0A */
288 U16 Reserved4; /*0x0C */
289 U16 IOCStatus; /*0x0E */
290 U32 IOCLogInfo; /*0x10 */
291} MPI2_SAS_IOUNIT_CONTROL_REPLY,
292 *PTR_MPI2_SAS_IOUNIT_CONTROL_REPLY,
293 Mpi2SasIoUnitControlReply_t, *pMpi2SasIoUnitControlReply_t;
294
295#endif
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_tool.h b/drivers/scsi/mpt3sas/mpi/mpi2_tool.h
new file mode 100644
index 000000000000..71453d11c1c1
--- /dev/null
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_tool.h
@@ -0,0 +1,437 @@
1/*
2 * Copyright (c) 2000-2012 LSI Corporation.
3 *
4 *
5 * Name: mpi2_tool.h
6 * Title: MPI diagnostic tool structures and definitions
7 * Creation Date: March 26, 2007
8 *
9 * mpi2_tool.h Version: 02.00.09
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 12-18-07 02.00.01 Added Diagnostic Buffer Post and Diagnostic Release
18 * structures and defines.
19 * 02-29-08 02.00.02 Modified various names to make them 32-character unique.
20 * 05-06-09 02.00.03 Added ISTWI Read Write Tool and Diagnostic CLI Tool.
21 * 07-30-09 02.00.04 Added ExtendedType field to DiagnosticBufferPost request
22 * and reply messages.
23 * Added MPI2_DIAG_BUF_TYPE_EXTENDED.
24 * Incremented MPI2_DIAG_BUF_TYPE_COUNT.
25 * 05-12-10 02.00.05 Added Diagnostic Data Upload tool.
26 * 08-11-10 02.00.06 Added defines that were missing for Diagnostic Buffer
27 * Post Request.
28 * 05-25-11 02.00.07 Added Flags field and related defines to
29 * MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST.
30 * 11-18-11 02.00.08 Incorporating additions for MPI v2.5.
31 * 07-10-12 02.00.09 Add MPI v2.5 Toolbox Diagnostic CLI Tool Request
32 * message.
33 * --------------------------------------------------------------------------
34 */
35
36#ifndef MPI2_TOOL_H
37#define MPI2_TOOL_H
38
39/*****************************************************************************
40*
41* Toolbox Messages
42*
43*****************************************************************************/
44
45/*defines for the Tools */
46#define MPI2_TOOLBOX_CLEAN_TOOL (0x00)
47#define MPI2_TOOLBOX_MEMORY_MOVE_TOOL (0x01)
48#define MPI2_TOOLBOX_DIAG_DATA_UPLOAD_TOOL (0x02)
49#define MPI2_TOOLBOX_ISTWI_READ_WRITE_TOOL (0x03)
50#define MPI2_TOOLBOX_BEACON_TOOL (0x05)
51#define MPI2_TOOLBOX_DIAGNOSTIC_CLI_TOOL (0x06)
52
53/****************************************************************************
54* Toolbox reply
55****************************************************************************/
56
57typedef struct _MPI2_TOOLBOX_REPLY {
58 U8 Tool; /*0x00 */
59 U8 Reserved1; /*0x01 */
60 U8 MsgLength; /*0x02 */
61 U8 Function; /*0x03 */
62 U16 Reserved2; /*0x04 */
63 U8 Reserved3; /*0x06 */
64 U8 MsgFlags; /*0x07 */
65 U8 VP_ID; /*0x08 */
66 U8 VF_ID; /*0x09 */
67 U16 Reserved4; /*0x0A */
68 U16 Reserved5; /*0x0C */
69 U16 IOCStatus; /*0x0E */
70 U32 IOCLogInfo; /*0x10 */
71} MPI2_TOOLBOX_REPLY, *PTR_MPI2_TOOLBOX_REPLY,
72 Mpi2ToolboxReply_t, *pMpi2ToolboxReply_t;
73
74/****************************************************************************
75* Toolbox Clean Tool request
76****************************************************************************/
77
78typedef struct _MPI2_TOOLBOX_CLEAN_REQUEST {
79 U8 Tool; /*0x00 */
80 U8 Reserved1; /*0x01 */
81 U8 ChainOffset; /*0x02 */
82 U8 Function; /*0x03 */
83 U16 Reserved2; /*0x04 */
84 U8 Reserved3; /*0x06 */
85 U8 MsgFlags; /*0x07 */
86 U8 VP_ID; /*0x08 */
87 U8 VF_ID; /*0x09 */
88 U16 Reserved4; /*0x0A */
89 U32 Flags; /*0x0C */
90} MPI2_TOOLBOX_CLEAN_REQUEST, *PTR_MPI2_TOOLBOX_CLEAN_REQUEST,
91 Mpi2ToolboxCleanRequest_t, *pMpi2ToolboxCleanRequest_t;
92
93/*values for the Flags field */
94#define MPI2_TOOLBOX_CLEAN_BOOT_SERVICES (0x80000000)
95#define MPI2_TOOLBOX_CLEAN_PERSIST_MANUFACT_PAGES (0x40000000)
96#define MPI2_TOOLBOX_CLEAN_OTHER_PERSIST_PAGES (0x20000000)
97#define MPI2_TOOLBOX_CLEAN_FW_CURRENT (0x10000000)
98#define MPI2_TOOLBOX_CLEAN_FW_BACKUP (0x08000000)
99#define MPI2_TOOLBOX_CLEAN_MEGARAID (0x02000000)
100#define MPI2_TOOLBOX_CLEAN_INITIALIZATION (0x01000000)
101#define MPI2_TOOLBOX_CLEAN_FLASH (0x00000004)
102#define MPI2_TOOLBOX_CLEAN_SEEPROM (0x00000002)
103#define MPI2_TOOLBOX_CLEAN_NVSRAM (0x00000001)
104
105/****************************************************************************
106* Toolbox Memory Move request
107****************************************************************************/
108
109typedef struct _MPI2_TOOLBOX_MEM_MOVE_REQUEST {
110 U8 Tool; /*0x00 */
111 U8 Reserved1; /*0x01 */
112 U8 ChainOffset; /*0x02 */
113 U8 Function; /*0x03 */
114 U16 Reserved2; /*0x04 */
115 U8 Reserved3; /*0x06 */
116 U8 MsgFlags; /*0x07 */
117 U8 VP_ID; /*0x08 */
118 U8 VF_ID; /*0x09 */
119 U16 Reserved4; /*0x0A */
120 MPI2_SGE_SIMPLE_UNION SGL; /*0x0C */
121} MPI2_TOOLBOX_MEM_MOVE_REQUEST, *PTR_MPI2_TOOLBOX_MEM_MOVE_REQUEST,
122 Mpi2ToolboxMemMoveRequest_t, *pMpi2ToolboxMemMoveRequest_t;
123
124/****************************************************************************
125* Toolbox Diagnostic Data Upload request
126****************************************************************************/
127
128typedef struct _MPI2_TOOLBOX_DIAG_DATA_UPLOAD_REQUEST {
129 U8 Tool; /*0x00 */
130 U8 Reserved1; /*0x01 */
131 U8 ChainOffset; /*0x02 */
132 U8 Function; /*0x03 */
133 U16 Reserved2; /*0x04 */
134 U8 Reserved3; /*0x06 */
135 U8 MsgFlags; /*0x07 */
136 U8 VP_ID; /*0x08 */
137 U8 VF_ID; /*0x09 */
138 U16 Reserved4; /*0x0A */
139 U8 SGLFlags; /*0x0C */
140 U8 Reserved5; /*0x0D */
141 U16 Reserved6; /*0x0E */
142 U32 Flags; /*0x10 */
143 U32 DataLength; /*0x14 */
144 MPI2_SGE_SIMPLE_UNION SGL; /*0x18 */
145} MPI2_TOOLBOX_DIAG_DATA_UPLOAD_REQUEST,
146 *PTR_MPI2_TOOLBOX_DIAG_DATA_UPLOAD_REQUEST,
147 Mpi2ToolboxDiagDataUploadRequest_t,
148 *pMpi2ToolboxDiagDataUploadRequest_t;
149
150/*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
151
152typedef struct _MPI2_DIAG_DATA_UPLOAD_HEADER {
153 U32 DiagDataLength; /*00h */
154 U8 FormatCode; /*04h */
155 U8 Reserved1; /*05h */
156 U16 Reserved2; /*06h */
157} MPI2_DIAG_DATA_UPLOAD_HEADER, *PTR_MPI2_DIAG_DATA_UPLOAD_HEADER,
158 Mpi2DiagDataUploadHeader_t, *pMpi2DiagDataUploadHeader_t;
159
160/****************************************************************************
161* Toolbox ISTWI Read Write Tool
162****************************************************************************/
163
164/*Toolbox ISTWI Read Write Tool request message */
165typedef struct _MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST {
166 U8 Tool; /*0x00 */
167 U8 Reserved1; /*0x01 */
168 U8 ChainOffset; /*0x02 */
169 U8 Function; /*0x03 */
170 U16 Reserved2; /*0x04 */
171 U8 Reserved3; /*0x06 */
172 U8 MsgFlags; /*0x07 */
173 U8 VP_ID; /*0x08 */
174 U8 VF_ID; /*0x09 */
175 U16 Reserved4; /*0x0A */
176 U32 Reserved5; /*0x0C */
177 U32 Reserved6; /*0x10 */
178 U8 DevIndex; /*0x14 */
179 U8 Action; /*0x15 */
180 U8 SGLFlags; /*0x16 */
181 U8 Flags; /*0x17 */
182 U16 TxDataLength; /*0x18 */
183 U16 RxDataLength; /*0x1A */
184 U32 Reserved8; /*0x1C */
185 U32 Reserved9; /*0x20 */
186 U32 Reserved10; /*0x24 */
187 U32 Reserved11; /*0x28 */
188 U32 Reserved12; /*0x2C */
189 MPI2_SGE_SIMPLE_UNION SGL; /*0x30 */
190} MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST,
191 *PTR_MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST,
192 Mpi2ToolboxIstwiReadWriteRequest_t,
193 *pMpi2ToolboxIstwiReadWriteRequest_t;
194
195/*values for the Action field */
196#define MPI2_TOOL_ISTWI_ACTION_READ_DATA (0x01)
197#define MPI2_TOOL_ISTWI_ACTION_WRITE_DATA (0x02)
198#define MPI2_TOOL_ISTWI_ACTION_SEQUENCE (0x03)
199#define MPI2_TOOL_ISTWI_ACTION_RESERVE_BUS (0x10)
200#define MPI2_TOOL_ISTWI_ACTION_RELEASE_BUS (0x11)
201#define MPI2_TOOL_ISTWI_ACTION_RESET (0x12)
202
203/*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
204
205/*values for the Flags field */
206#define MPI2_TOOL_ISTWI_FLAG_AUTO_RESERVE_RELEASE (0x80)
207#define MPI2_TOOL_ISTWI_FLAG_PAGE_ADDR_MASK (0x07)
208
209/*Toolbox ISTWI Read Write Tool reply message */
210typedef struct _MPI2_TOOLBOX_ISTWI_REPLY {
211 U8 Tool; /*0x00 */
212 U8 Reserved1; /*0x01 */
213 U8 MsgLength; /*0x02 */
214 U8 Function; /*0x03 */
215 U16 Reserved2; /*0x04 */
216 U8 Reserved3; /*0x06 */
217 U8 MsgFlags; /*0x07 */
218 U8 VP_ID; /*0x08 */
219 U8 VF_ID; /*0x09 */
220 U16 Reserved4; /*0x0A */
221 U16 Reserved5; /*0x0C */
222 U16 IOCStatus; /*0x0E */
223 U32 IOCLogInfo; /*0x10 */
224 U8 DevIndex; /*0x14 */
225 U8 Action; /*0x15 */
226 U8 IstwiStatus; /*0x16 */
227 U8 Reserved6; /*0x17 */
228 U16 TxDataCount; /*0x18 */
229 U16 RxDataCount; /*0x1A */
230} MPI2_TOOLBOX_ISTWI_REPLY, *PTR_MPI2_TOOLBOX_ISTWI_REPLY,
231 Mpi2ToolboxIstwiReply_t, *pMpi2ToolboxIstwiReply_t;
232
233/****************************************************************************
234* Toolbox Beacon Tool request
235****************************************************************************/
236
237typedef struct _MPI2_TOOLBOX_BEACON_REQUEST {
238 U8 Tool; /*0x00 */
239 U8 Reserved1; /*0x01 */
240 U8 ChainOffset; /*0x02 */
241 U8 Function; /*0x03 */
242 U16 Reserved2; /*0x04 */
243 U8 Reserved3; /*0x06 */
244 U8 MsgFlags; /*0x07 */
245 U8 VP_ID; /*0x08 */
246 U8 VF_ID; /*0x09 */
247 U16 Reserved4; /*0x0A */
248 U8 Reserved5; /*0x0C */
249 U8 PhysicalPort; /*0x0D */
250 U8 Reserved6; /*0x0E */
251 U8 Flags; /*0x0F */
252} MPI2_TOOLBOX_BEACON_REQUEST, *PTR_MPI2_TOOLBOX_BEACON_REQUEST,
253 Mpi2ToolboxBeaconRequest_t, *pMpi2ToolboxBeaconRequest_t;
254
255/*values for the Flags field */
256#define MPI2_TOOLBOX_FLAGS_BEACONMODE_OFF (0x00)
257#define MPI2_TOOLBOX_FLAGS_BEACONMODE_ON (0x01)
258
259/****************************************************************************
260* Toolbox Diagnostic CLI Tool
261****************************************************************************/
262
263#define MPI2_TOOLBOX_DIAG_CLI_CMD_LENGTH (0x5C)
264
265/*MPI v2.0 Toolbox Diagnostic CLI Tool request message */
266typedef struct _MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST {
267 U8 Tool; /*0x00 */
268 U8 Reserved1; /*0x01 */
269 U8 ChainOffset; /*0x02 */
270 U8 Function; /*0x03 */
271 U16 Reserved2; /*0x04 */
272 U8 Reserved3; /*0x06 */
273 U8 MsgFlags; /*0x07 */
274 U8 VP_ID; /*0x08 */
275 U8 VF_ID; /*0x09 */
276 U16 Reserved4; /*0x0A */
277 U8 SGLFlags; /*0x0C */
278 U8 Reserved5; /*0x0D */
279 U16 Reserved6; /*0x0E */
280 U32 DataLength; /*0x10 */
281 U8 DiagnosticCliCommand[MPI2_TOOLBOX_DIAG_CLI_CMD_LENGTH];/*0x14 */
282 MPI2_SGE_SIMPLE_UNION SGL; /*0x70 */
283} MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST,
284 *PTR_MPI2_TOOLBOX_DIAGNOSTIC_CLI_REQUEST,
285 Mpi2ToolboxDiagnosticCliRequest_t,
286 *pMpi2ToolboxDiagnosticCliRequest_t;
287
288/*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
289
290/*MPI v2.5 Toolbox Diagnostic CLI Tool request message */
291typedef struct _MPI25_TOOLBOX_DIAGNOSTIC_CLI_REQUEST {
292 U8 Tool; /*0x00 */
293 U8 Reserved1; /*0x01 */
294 U8 ChainOffset; /*0x02 */
295 U8 Function; /*0x03 */
296 U16 Reserved2; /*0x04 */
297 U8 Reserved3; /*0x06 */
298 U8 MsgFlags; /*0x07 */
299 U8 VP_ID; /*0x08 */
300 U8 VF_ID; /*0x09 */
301 U16 Reserved4; /*0x0A */
302 U32 Reserved5; /*0x0C */
303 U32 DataLength; /*0x10 */
304 U8 DiagnosticCliCommand[MPI2_TOOLBOX_DIAG_CLI_CMD_LENGTH];/*0x14 */
305 MPI25_SGE_IO_UNION SGL; /*0x70 */
306} MPI25_TOOLBOX_DIAGNOSTIC_CLI_REQUEST,
307 *PTR_MPI25_TOOLBOX_DIAGNOSTIC_CLI_REQUEST,
308 Mpi25ToolboxDiagnosticCliRequest_t,
309 *pMpi25ToolboxDiagnosticCliRequest_t;
310
311/*Toolbox Diagnostic CLI Tool reply message */
312typedef struct _MPI2_TOOLBOX_DIAGNOSTIC_CLI_REPLY {
313 U8 Tool; /*0x00 */
314 U8 Reserved1; /*0x01 */
315 U8 MsgLength; /*0x02 */
316 U8 Function; /*0x03 */
317 U16 Reserved2; /*0x04 */
318 U8 Reserved3; /*0x06 */
319 U8 MsgFlags; /*0x07 */
320 U8 VP_ID; /*0x08 */
321 U8 VF_ID; /*0x09 */
322 U16 Reserved4; /*0x0A */
323 U16 Reserved5; /*0x0C */
324 U16 IOCStatus; /*0x0E */
325 U32 IOCLogInfo; /*0x10 */
326 U32 ReturnedDataLength; /*0x14 */
327} MPI2_TOOLBOX_DIAGNOSTIC_CLI_REPLY,
328 *PTR_MPI2_TOOLBOX_DIAG_CLI_REPLY,
329 Mpi2ToolboxDiagnosticCliReply_t,
330 *pMpi2ToolboxDiagnosticCliReply_t;
331
332/*****************************************************************************
333*
334* Diagnostic Buffer Messages
335*
336*****************************************************************************/
337
338/****************************************************************************
339* Diagnostic Buffer Post request
340****************************************************************************/
341
342typedef struct _MPI2_DIAG_BUFFER_POST_REQUEST {
343 U8 ExtendedType; /*0x00 */
344 U8 BufferType; /*0x01 */
345 U8 ChainOffset; /*0x02 */
346 U8 Function; /*0x03 */
347 U16 Reserved2; /*0x04 */
348 U8 Reserved3; /*0x06 */
349 U8 MsgFlags; /*0x07 */
350 U8 VP_ID; /*0x08 */
351 U8 VF_ID; /*0x09 */
352 U16 Reserved4; /*0x0A */
353 U64 BufferAddress; /*0x0C */
354 U32 BufferLength; /*0x14 */
355 U32 Reserved5; /*0x18 */
356 U32 Reserved6; /*0x1C */
357 U32 Flags; /*0x20 */
358 U32 ProductSpecific[23]; /*0x24 */
359} MPI2_DIAG_BUFFER_POST_REQUEST, *PTR_MPI2_DIAG_BUFFER_POST_REQUEST,
360 Mpi2DiagBufferPostRequest_t, *pMpi2DiagBufferPostRequest_t;
361
362/*values for the ExtendedType field */
363#define MPI2_DIAG_EXTENDED_TYPE_UTILIZATION (0x02)
364
365/*values for the BufferType field */
366#define MPI2_DIAG_BUF_TYPE_TRACE (0x00)
367#define MPI2_DIAG_BUF_TYPE_SNAPSHOT (0x01)
368#define MPI2_DIAG_BUF_TYPE_EXTENDED (0x02)
369/*count of the number of buffer types */
370#define MPI2_DIAG_BUF_TYPE_COUNT (0x03)
371
372/*values for the Flags field */
373#define MPI2_DIAG_BUF_FLAG_RELEASE_ON_FULL (0x00000002)
374#define MPI2_DIAG_BUF_FLAG_IMMEDIATE_RELEASE (0x00000001)
375
376/****************************************************************************
377* Diagnostic Buffer Post reply
378****************************************************************************/
379
380typedef struct _MPI2_DIAG_BUFFER_POST_REPLY {
381 U8 ExtendedType; /*0x00 */
382 U8 BufferType; /*0x01 */
383 U8 MsgLength; /*0x02 */
384 U8 Function; /*0x03 */
385 U16 Reserved2; /*0x04 */
386 U8 Reserved3; /*0x06 */
387 U8 MsgFlags; /*0x07 */
388 U8 VP_ID; /*0x08 */
389 U8 VF_ID; /*0x09 */
390 U16 Reserved4; /*0x0A */
391 U16 Reserved5; /*0x0C */
392 U16 IOCStatus; /*0x0E */
393 U32 IOCLogInfo; /*0x10 */
394 U32 TransferLength; /*0x14 */
395} MPI2_DIAG_BUFFER_POST_REPLY, *PTR_MPI2_DIAG_BUFFER_POST_REPLY,
396 Mpi2DiagBufferPostReply_t, *pMpi2DiagBufferPostReply_t;
397
398/****************************************************************************
399* Diagnostic Release request
400****************************************************************************/
401
402typedef struct _MPI2_DIAG_RELEASE_REQUEST {
403 U8 Reserved1; /*0x00 */
404 U8 BufferType; /*0x01 */
405 U8 ChainOffset; /*0x02 */
406 U8 Function; /*0x03 */
407 U16 Reserved2; /*0x04 */
408 U8 Reserved3; /*0x06 */
409 U8 MsgFlags; /*0x07 */
410 U8 VP_ID; /*0x08 */
411 U8 VF_ID; /*0x09 */
412 U16 Reserved4; /*0x0A */
413} MPI2_DIAG_RELEASE_REQUEST, *PTR_MPI2_DIAG_RELEASE_REQUEST,
414 Mpi2DiagReleaseRequest_t, *pMpi2DiagReleaseRequest_t;
415
416/****************************************************************************
417* Diagnostic Buffer Post reply
418****************************************************************************/
419
420typedef struct _MPI2_DIAG_RELEASE_REPLY {
421 U8 Reserved1; /*0x00 */
422 U8 BufferType; /*0x01 */
423 U8 MsgLength; /*0x02 */
424 U8 Function; /*0x03 */
425 U16 Reserved2; /*0x04 */
426 U8 Reserved3; /*0x06 */
427 U8 MsgFlags; /*0x07 */
428 U8 VP_ID; /*0x08 */
429 U8 VF_ID; /*0x09 */
430 U16 Reserved4; /*0x0A */
431 U16 Reserved5; /*0x0C */
432 U16 IOCStatus; /*0x0E */
433 U32 IOCLogInfo; /*0x10 */
434} MPI2_DIAG_RELEASE_REPLY, *PTR_MPI2_DIAG_RELEASE_REPLY,
435 Mpi2DiagReleaseReply_t, *pMpi2DiagReleaseReply_t;
436
437#endif
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_type.h b/drivers/scsi/mpt3sas/mpi/mpi2_type.h
new file mode 100644
index 000000000000..516f959573f5
--- /dev/null
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_type.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (c) 2000-2007 LSI Corporation.
3 *
4 *
5 * Name: mpi2_type.h
6 * Title: MPI basic type definitions
7 * Creation Date: August 16, 2006
8 *
9 * mpi2_type.h Version: 02.00.00
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * --------------------------------------------------------------------------
18 */
19
20#ifndef MPI2_TYPE_H
21#define MPI2_TYPE_H
22
23/*******************************************************************************
24 * Define * if it hasn't already been defined. By default
25 * * is defined to be a near pointer. MPI2_POINTER can be defined as
26 * a far pointer by defining * as "far *" before this header file is
27 * included.
28 */
29
30/* the basic types may have already been included by mpi_type.h */
31#ifndef MPI_TYPE_H
32/*****************************************************************************
33*
34* Basic Types
35*
36*****************************************************************************/
37
38typedef u8 U8;
39typedef __le16 U16;
40typedef __le32 U32;
41typedef __le64 U64 __attribute__ ((aligned(4)));
42
43/*****************************************************************************
44*
45* Pointer Types
46*
47*****************************************************************************/
48
49typedef U8 *PU8;
50typedef U16 *PU16;
51typedef U32 *PU32;
52typedef U64 *PU64;
53
54#endif
55
56#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-11 21:57:29 -0400