1 files changed, 63 insertions, 1 deletions

diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index 1663e0b6b5a0..31c5787970db 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -10422,6 +10422,28 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
                                          MDIO_PMA_DEVAD,
                                          MDIO_PMA_REG_8481_LED1_MASK,
                                          0x0);
+                        if (phy->type ==
+                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
+                                /* Disable MI_INT interrupt before setting LED4
+                                 * source to constant off.
+                                 */
+                                if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
+                                           params->port*4) &
+                                    NIG_MASK_MI_INT) {
+                                        params->link_flags |=
+                                        LINK_FLAGS_INT_DISABLED;
+
+                                        bnx2x_bits_dis(
+                                                bp,
+                                                NIG_REG_MASK_INTERRUPT_PORT0 +
+                                                params->port*4,
+                                                NIG_MASK_MI_INT);
+                                }
+                                bnx2x_cl45_write(bp, phy,
+                                                 MDIO_PMA_DEVAD,
+                                                 MDIO_PMA_REG_8481_SIGNAL_MASK,
+                                                 0x0);
+                        }
                 }
                 break;
         case LED_MODE_ON:
@@ -10468,6 +10490,28 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
                                          MDIO_PMA_DEVAD,
                                          MDIO_PMA_REG_8481_LED1_MASK,
                                          0x20);
+                        if (phy->type ==
+                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
+                                /* Disable MI_INT interrupt before setting LED4
+                                 * source to constant on.
+                                 */
+                                if (REG_RD(bp, NIG_REG_MASK_INTERRUPT_PORT0 +
+                                           params->port*4) &
+                                    NIG_MASK_MI_INT) {
+                                        params->link_flags |=
+                                        LINK_FLAGS_INT_DISABLED;
+
+                                        bnx2x_bits_dis(
+                                                bp,
+                                                NIG_REG_MASK_INTERRUPT_PORT0 +
+                                                params->port*4,
+                                                NIG_MASK_MI_INT);
+                                }
+                                bnx2x_cl45_write(bp, phy,
+                                                 MDIO_PMA_DEVAD,
+                                                 MDIO_PMA_REG_8481_SIGNAL_MASK,
+                                                 0x20);
+                        }
                 }
                 break;
 
@@ -10532,6 +10576,22 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
                                          MDIO_PMA_DEVAD,
                                          MDIO_PMA_REG_8481_LINK_SIGNAL,
                                          val);
+                        if (phy->type ==
+                            PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
+                                /* Restore LED4 source to external link,
+                                 * and re-enable interrupts.
+                                 */
+                                bnx2x_cl45_write(bp, phy,
+                                                 MDIO_PMA_DEVAD,
+                                                 MDIO_PMA_REG_8481_SIGNAL_MASK,
+                                                 0x40);
+                                if (params->link_flags &
+                                    LINK_FLAGS_INT_DISABLED) {
+                                        bnx2x_link_int_enable(params);
+                                        params->link_flags &=
+                                                ~LINK_FLAGS_INT_DISABLED;
+                                }
+                        }
                 }
                 break;
         }
@@ -11791,6 +11851,8 @@ static int bnx2x_populate_int_phy(struct bnx2x *bp, u32 shmem_base, u8 port,
                         phy->media_type = ETH_PHY_KR;
                         phy->flags |= FLAGS_WC_DUAL_MODE;
                         phy->supported &= (SUPPORTED_20000baseKR2_Full |
+                                           SUPPORTED_10000baseT_Full |
+                                           SUPPORTED_1000baseT_Full |
                                            SUPPORTED_Autoneg |
                                            SUPPORTED_FIBRE |
                                            SUPPORTED_Pause |
@@ -13437,7 +13499,7 @@ void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
                 struct bnx2x_phy *phy = &params->phy[INT_PHY];
                 bnx2x_set_aer_mmd(params, phy);
                 if ((phy->supported & SUPPORTED_20000baseKR2_Full) &&
-                    (phy->speed_cap_mask & SPEED_20000))
+                    (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G))
                         bnx2x_check_kr2_wa(params, vars, phy);
                 bnx2x_check_over_curr(params, vars);
                 if (vars->rx_tx_asic_rst)