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path: root/drivers/net/chelsio/vsc7326.c
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Diffstat (limited to 'drivers/net/chelsio/vsc7326.c')
-rw-r--r--drivers/net/chelsio/vsc7326.c57
1 files changed, 28 insertions, 29 deletions
diff --git a/drivers/net/chelsio/vsc7326.c b/drivers/net/chelsio/vsc7326.c
index 8c4a31e20e21..bdd25c0b8458 100644
--- a/drivers/net/chelsio/vsc7326.c
+++ b/drivers/net/chelsio/vsc7326.c
@@ -234,14 +234,14 @@ static void run_table(adapter_t *adapter, struct init_table *ib, int len)
234 234
235static int bist_rd(adapter_t *adapter, int moduleid, int address) 235static int bist_rd(adapter_t *adapter, int moduleid, int address)
236{ 236{
237 int data=0; 237 int data = 0;
238 u32 result=0; 238 u32 result = 0;
239 239
240 if( (address != 0x0) && 240 if ((address != 0x0) &&
241 (address != 0x1) && 241 (address != 0x1) &&
242 (address != 0x2) && 242 (address != 0x2) &&
243 (address != 0xd) && 243 (address != 0xd) &&
244 (address != 0xe)) 244 (address != 0xe))
245 CH_ERR("No bist address: 0x%x\n", address); 245 CH_ERR("No bist address: 0x%x\n", address);
246 246
247 data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) | 247 data = ((0x00 << 24) | ((address & 0xff) << 16) | (0x00 << 8) |
@@ -251,9 +251,9 @@ static int bist_rd(adapter_t *adapter, int moduleid, int address)
251 udelay(10); 251 udelay(10);
252 252
253 vsc_read(adapter, REG_RAM_BIST_RESULT, &result); 253 vsc_read(adapter, REG_RAM_BIST_RESULT, &result);
254 if((result & (1<<9)) != 0x0) 254 if ((result & (1 << 9)) != 0x0)
255 CH_ERR("Still in bist read: 0x%x\n", result); 255 CH_ERR("Still in bist read: 0x%x\n", result);
256 else if((result & (1<<8)) != 0x0) 256 else if ((result & (1 << 8)) != 0x0)
257 CH_ERR("bist read error: 0x%x\n", result); 257 CH_ERR("bist read error: 0x%x\n", result);
258 258
259 return (result & 0xff); 259 return (result & 0xff);
@@ -261,17 +261,17 @@ static int bist_rd(adapter_t *adapter, int moduleid, int address)
261 261
262static int bist_wr(adapter_t *adapter, int moduleid, int address, int value) 262static int bist_wr(adapter_t *adapter, int moduleid, int address, int value)
263{ 263{
264 int data=0; 264 int data = 0;
265 u32 result=0; 265 u32 result = 0;
266 266
267 if( (address != 0x0) && 267 if ((address != 0x0) &&
268 (address != 0x1) && 268 (address != 0x1) &&
269 (address != 0x2) && 269 (address != 0x2) &&
270 (address != 0xd) && 270 (address != 0xd) &&
271 (address != 0xe)) 271 (address != 0xe))
272 CH_ERR("No bist address: 0x%x\n", address); 272 CH_ERR("No bist address: 0x%x\n", address);
273 273
274 if( value>255 ) 274 if (value > 255)
275 CH_ERR("Suspicious write out of range value: 0x%x\n", value); 275 CH_ERR("Suspicious write out of range value: 0x%x\n", value);
276 276
277 data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) | 277 data = ((0x01 << 24) | ((address & 0xff) << 16) | (value << 8) |
@@ -281,9 +281,9 @@ static int bist_wr(adapter_t *adapter, int moduleid, int address, int value)
281 udelay(5); 281 udelay(5);
282 282
283 vsc_read(adapter, REG_RAM_BIST_CMD, &result); 283 vsc_read(adapter, REG_RAM_BIST_CMD, &result);
284 if((result & (1<<27)) != 0x0) 284 if ((result & (1 << 27)) != 0x0)
285 CH_ERR("Still in bist write: 0x%x\n", result); 285 CH_ERR("Still in bist write: 0x%x\n", result);
286 else if((result & (1<<26)) != 0x0) 286 else if ((result & (1 << 26)) != 0x0)
287 CH_ERR("bist write error: 0x%x\n", result); 287 CH_ERR("bist write error: 0x%x\n", result);
288 288
289 return 0; 289 return 0;
@@ -321,15 +321,14 @@ static int enable_mem(adapter_t *adapter, int moduleid)
321 321
322static int run_bist_all(adapter_t *adapter) 322static int run_bist_all(adapter_t *adapter)
323{ 323{
324 int port=0; 324 int port = 0;
325 u32 val=0; 325 u32 val = 0;
326 326
327 vsc_write(adapter, REG_MEM_BIST, 0x5); 327 vsc_write(adapter, REG_MEM_BIST, 0x5);
328 vsc_read(adapter, REG_MEM_BIST, &val); 328 vsc_read(adapter, REG_MEM_BIST, &val);
329 329
330 for(port=0; port<12; port++){ 330 for (port = 0; port < 12; port++)
331 vsc_write(adapter, REG_DEV_SETUP(port), 0x0); 331 vsc_write(adapter, REG_DEV_SETUP(port), 0x0);
332 }
333 332
334 udelay(300); 333 udelay(300);
335 vsc_write(adapter, REG_SPI4_MISC, 0x00040409); 334 vsc_write(adapter, REG_SPI4_MISC, 0x00040409);
@@ -352,9 +351,9 @@ static int run_bist_all(adapter_t *adapter)
352 udelay(300); 351 udelay(300);
353 vsc_write(adapter, REG_SPI4_MISC, 0x60040400); 352 vsc_write(adapter, REG_SPI4_MISC, 0x60040400);
354 udelay(300); 353 udelay(300);
355 for(port=0; port<12; port++){ 354 for (port = 0; port < 12; port++)
356 vsc_write(adapter, REG_DEV_SETUP(port), 0x1); 355 vsc_write(adapter, REG_DEV_SETUP(port), 0x1);
357 } 356
358 udelay(300); 357 udelay(300);
359 vsc_write(adapter, REG_MEM_BIST, 0x0); 358 vsc_write(adapter, REG_MEM_BIST, 0x0);
360 mdelay(10); 359 mdelay(10);
@@ -612,7 +611,7 @@ static void port_stats_update(struct cmac *mac)
612 rmon_update(mac, REG_RX_SYMBOL_CARRIER(port), 611 rmon_update(mac, REG_RX_SYMBOL_CARRIER(port),
613 &mac->stats.RxSymbolErrors); 612 &mac->stats.RxSymbolErrors);
614 rmon_update(mac, REG_RX_SIZE_1519_TO_MAX(port), 613 rmon_update(mac, REG_RX_SIZE_1519_TO_MAX(port),
615 &mac->stats.RxJumboFramesOK); 614 &mac->stats.RxJumboFramesOK);
616 615
617 /* Tx stats (skip collision stats as we are full-duplex only) */ 616 /* Tx stats (skip collision stats as we are full-duplex only) */
618 rmon_update(mac, REG_TX_OK_BYTES(port), &mac->stats.TxOctetsOK); 617 rmon_update(mac, REG_TX_OK_BYTES(port), &mac->stats.TxOctetsOK);
@@ -624,7 +623,7 @@ static void port_stats_update(struct cmac *mac)
624 rmon_update(mac, REG_TX_PAUSE(port), &mac->stats.TxPauseFrames); 623 rmon_update(mac, REG_TX_PAUSE(port), &mac->stats.TxPauseFrames);
625 rmon_update(mac, REG_TX_UNDERRUN(port), &mac->stats.TxUnderrun); 624 rmon_update(mac, REG_TX_UNDERRUN(port), &mac->stats.TxUnderrun);
626 rmon_update(mac, REG_TX_SIZE_1519_TO_MAX(port), 625 rmon_update(mac, REG_TX_SIZE_1519_TO_MAX(port),
627 &mac->stats.TxJumboFramesOK); 626 &mac->stats.TxJumboFramesOK);
628} 627}
629 628
630/* 629/*