diff options
Diffstat (limited to 'drivers/mfd/max77693-irq.c')
-rw-r--r-- | drivers/mfd/max77693-irq.c | 309 |
1 files changed, 309 insertions, 0 deletions
diff --git a/drivers/mfd/max77693-irq.c b/drivers/mfd/max77693-irq.c new file mode 100644 index 000000000000..2b403569e0a6 --- /dev/null +++ b/drivers/mfd/max77693-irq.c | |||
@@ -0,0 +1,309 @@ | |||
1 | /* | ||
2 | * max77693-irq.c - Interrupt controller support for MAX77693 | ||
3 | * | ||
4 | * Copyright (C) 2012 Samsung Electronics Co.Ltd | ||
5 | * SangYoung Son <hello.son@samsung.com> | ||
6 | * | ||
7 | * This program is not provided / owned by Maxim Integrated Products. | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
22 | * | ||
23 | * This driver is based on max8997-irq.c | ||
24 | */ | ||
25 | |||
26 | #include <linux/err.h> | ||
27 | #include <linux/irq.h> | ||
28 | #include <linux/interrupt.h> | ||
29 | #include <linux/module.h> | ||
30 | #include <linux/irqdomain.h> | ||
31 | #include <linux/mfd/max77693.h> | ||
32 | #include <linux/mfd/max77693-private.h> | ||
33 | |||
34 | static const u8 max77693_mask_reg[] = { | ||
35 | [LED_INT] = MAX77693_LED_REG_FLASH_INT_MASK, | ||
36 | [TOPSYS_INT] = MAX77693_PMIC_REG_TOPSYS_INT_MASK, | ||
37 | [CHG_INT] = MAX77693_CHG_REG_CHG_INT_MASK, | ||
38 | [MUIC_INT1] = MAX77693_MUIC_REG_INTMASK1, | ||
39 | [MUIC_INT2] = MAX77693_MUIC_REG_INTMASK2, | ||
40 | [MUIC_INT3] = MAX77693_MUIC_REG_INTMASK3, | ||
41 | }; | ||
42 | |||
43 | static struct regmap *max77693_get_regmap(struct max77693_dev *max77693, | ||
44 | enum max77693_irq_source src) | ||
45 | { | ||
46 | switch (src) { | ||
47 | case LED_INT ... CHG_INT: | ||
48 | return max77693->regmap; | ||
49 | case MUIC_INT1 ... MUIC_INT3: | ||
50 | return max77693->regmap_muic; | ||
51 | default: | ||
52 | return ERR_PTR(-EINVAL); | ||
53 | } | ||
54 | } | ||
55 | |||
56 | struct max77693_irq_data { | ||
57 | int mask; | ||
58 | enum max77693_irq_source group; | ||
59 | }; | ||
60 | |||
61 | #define DECLARE_IRQ(idx, _group, _mask) \ | ||
62 | [(idx)] = { .group = (_group), .mask = (_mask) } | ||
63 | static const struct max77693_irq_data max77693_irqs[] = { | ||
64 | DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_OPEN, LED_INT, 1 << 0), | ||
65 | DECLARE_IRQ(MAX77693_LED_IRQ_FLED2_SHORT, LED_INT, 1 << 1), | ||
66 | DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_OPEN, LED_INT, 1 << 2), | ||
67 | DECLARE_IRQ(MAX77693_LED_IRQ_FLED1_SHORT, LED_INT, 1 << 3), | ||
68 | DECLARE_IRQ(MAX77693_LED_IRQ_MAX_FLASH, LED_INT, 1 << 4), | ||
69 | |||
70 | DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T120C_INT, TOPSYS_INT, 1 << 0), | ||
71 | DECLARE_IRQ(MAX77693_TOPSYS_IRQ_T140C_INT, TOPSYS_INT, 1 << 1), | ||
72 | DECLARE_IRQ(MAX77693_TOPSYS_IRQ_LOWSYS_INT, TOPSYS_INT, 1 << 3), | ||
73 | |||
74 | DECLARE_IRQ(MAX77693_CHG_IRQ_BYP_I, CHG_INT, 1 << 0), | ||
75 | DECLARE_IRQ(MAX77693_CHG_IRQ_THM_I, CHG_INT, 1 << 2), | ||
76 | DECLARE_IRQ(MAX77693_CHG_IRQ_BAT_I, CHG_INT, 1 << 3), | ||
77 | DECLARE_IRQ(MAX77693_CHG_IRQ_CHG_I, CHG_INT, 1 << 4), | ||
78 | DECLARE_IRQ(MAX77693_CHG_IRQ_CHGIN_I, CHG_INT, 1 << 6), | ||
79 | |||
80 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC, MUIC_INT1, 1 << 0), | ||
81 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_LOW, MUIC_INT1, 1 << 1), | ||
82 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC_ERR, MUIC_INT1, 1 << 2), | ||
83 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT1_ADC1K, MUIC_INT1, 1 << 3), | ||
84 | |||
85 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGTYP, MUIC_INT2, 1 << 0), | ||
86 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_CHGDETREUN, MUIC_INT2, 1 << 1), | ||
87 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DCDTMR, MUIC_INT2, 1 << 2), | ||
88 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_DXOVP, MUIC_INT2, 1 << 3), | ||
89 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VBVOLT, MUIC_INT2, 1 << 4), | ||
90 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT2_VIDRM, MUIC_INT2, 1 << 5), | ||
91 | |||
92 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_EOC, MUIC_INT3, 1 << 0), | ||
93 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CGMBC, MUIC_INT3, 1 << 1), | ||
94 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_OVP, MUIC_INT3, 1 << 2), | ||
95 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR, MUIC_INT3, 1 << 3), | ||
96 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_CHG_ENABLED, MUIC_INT3, 1 << 4), | ||
97 | DECLARE_IRQ(MAX77693_MUIC_IRQ_INT3_BAT_DET, MUIC_INT3, 1 << 5), | ||
98 | }; | ||
99 | |||
100 | static void max77693_irq_lock(struct irq_data *data) | ||
101 | { | ||
102 | struct max77693_dev *max77693 = irq_get_chip_data(data->irq); | ||
103 | |||
104 | mutex_lock(&max77693->irqlock); | ||
105 | } | ||
106 | |||
107 | static void max77693_irq_sync_unlock(struct irq_data *data) | ||
108 | { | ||
109 | struct max77693_dev *max77693 = irq_get_chip_data(data->irq); | ||
110 | int i; | ||
111 | |||
112 | for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) { | ||
113 | u8 mask_reg = max77693_mask_reg[i]; | ||
114 | struct regmap *map = max77693_get_regmap(max77693, i); | ||
115 | |||
116 | if (mask_reg == MAX77693_REG_INVALID || | ||
117 | IS_ERR_OR_NULL(map)) | ||
118 | continue; | ||
119 | max77693->irq_masks_cache[i] = max77693->irq_masks_cur[i]; | ||
120 | |||
121 | max77693_write_reg(map, max77693_mask_reg[i], | ||
122 | max77693->irq_masks_cur[i]); | ||
123 | } | ||
124 | |||
125 | mutex_unlock(&max77693->irqlock); | ||
126 | } | ||
127 | |||
128 | static const inline struct max77693_irq_data * | ||
129 | irq_to_max77693_irq(struct max77693_dev *max77693, int irq) | ||
130 | { | ||
131 | return &max77693_irqs[irq]; | ||
132 | } | ||
133 | |||
134 | static void max77693_irq_mask(struct irq_data *data) | ||
135 | { | ||
136 | struct max77693_dev *max77693 = irq_get_chip_data(data->irq); | ||
137 | const struct max77693_irq_data *irq_data = | ||
138 | irq_to_max77693_irq(max77693, data->irq); | ||
139 | |||
140 | if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3) | ||
141 | max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask; | ||
142 | else | ||
143 | max77693->irq_masks_cur[irq_data->group] |= irq_data->mask; | ||
144 | } | ||
145 | |||
146 | static void max77693_irq_unmask(struct irq_data *data) | ||
147 | { | ||
148 | struct max77693_dev *max77693 = irq_get_chip_data(data->irq); | ||
149 | const struct max77693_irq_data *irq_data = | ||
150 | irq_to_max77693_irq(max77693, data->irq); | ||
151 | |||
152 | if (irq_data->group >= MUIC_INT1 && irq_data->group <= MUIC_INT3) | ||
153 | max77693->irq_masks_cur[irq_data->group] |= irq_data->mask; | ||
154 | else | ||
155 | max77693->irq_masks_cur[irq_data->group] &= ~irq_data->mask; | ||
156 | } | ||
157 | |||
158 | static struct irq_chip max77693_irq_chip = { | ||
159 | .name = "max77693", | ||
160 | .irq_bus_lock = max77693_irq_lock, | ||
161 | .irq_bus_sync_unlock = max77693_irq_sync_unlock, | ||
162 | .irq_mask = max77693_irq_mask, | ||
163 | .irq_unmask = max77693_irq_unmask, | ||
164 | }; | ||
165 | |||
166 | #define MAX77693_IRQSRC_CHG (1 << 0) | ||
167 | #define MAX77693_IRQSRC_TOP (1 << 1) | ||
168 | #define MAX77693_IRQSRC_FLASH (1 << 2) | ||
169 | #define MAX77693_IRQSRC_MUIC (1 << 3) | ||
170 | static irqreturn_t max77693_irq_thread(int irq, void *data) | ||
171 | { | ||
172 | struct max77693_dev *max77693 = data; | ||
173 | u8 irq_reg[MAX77693_IRQ_GROUP_NR] = {}; | ||
174 | u8 irq_src; | ||
175 | int ret; | ||
176 | int i, cur_irq; | ||
177 | |||
178 | ret = max77693_read_reg(max77693->regmap, MAX77693_PMIC_REG_INTSRC, | ||
179 | &irq_src); | ||
180 | if (ret < 0) { | ||
181 | dev_err(max77693->dev, "Failed to read interrupt source: %d\n", | ||
182 | ret); | ||
183 | return IRQ_NONE; | ||
184 | } | ||
185 | |||
186 | if (irq_src & MAX77693_IRQSRC_CHG) | ||
187 | /* CHG_INT */ | ||
188 | ret = max77693_read_reg(max77693->regmap, MAX77693_CHG_REG_CHG_INT, | ||
189 | &irq_reg[CHG_INT]); | ||
190 | |||
191 | if (irq_src & MAX77693_IRQSRC_TOP) | ||
192 | /* TOPSYS_INT */ | ||
193 | ret = max77693_read_reg(max77693->regmap, | ||
194 | MAX77693_PMIC_REG_TOPSYS_INT, &irq_reg[TOPSYS_INT]); | ||
195 | |||
196 | if (irq_src & MAX77693_IRQSRC_FLASH) | ||
197 | /* LED_INT */ | ||
198 | ret = max77693_read_reg(max77693->regmap, | ||
199 | MAX77693_LED_REG_FLASH_INT, &irq_reg[LED_INT]); | ||
200 | |||
201 | if (irq_src & MAX77693_IRQSRC_MUIC) | ||
202 | /* MUIC INT1 ~ INT3 */ | ||
203 | max77693_bulk_read(max77693->regmap, MAX77693_MUIC_REG_INT1, | ||
204 | MAX77693_NUM_IRQ_MUIC_REGS, &irq_reg[MUIC_INT1]); | ||
205 | |||
206 | /* Apply masking */ | ||
207 | for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) { | ||
208 | if (i >= MUIC_INT1 && i <= MUIC_INT3) | ||
209 | irq_reg[i] &= max77693->irq_masks_cur[i]; | ||
210 | else | ||
211 | irq_reg[i] &= ~max77693->irq_masks_cur[i]; | ||
212 | } | ||
213 | |||
214 | /* Report */ | ||
215 | for (i = 0; i < MAX77693_IRQ_NR; i++) { | ||
216 | if (irq_reg[max77693_irqs[i].group] & max77693_irqs[i].mask) { | ||
217 | cur_irq = irq_find_mapping(max77693->irq_domain, i); | ||
218 | if (cur_irq) | ||
219 | handle_nested_irq(cur_irq); | ||
220 | } | ||
221 | } | ||
222 | |||
223 | return IRQ_HANDLED; | ||
224 | } | ||
225 | |||
226 | int max77693_irq_resume(struct max77693_dev *max77693) | ||
227 | { | ||
228 | if (max77693->irq) | ||
229 | max77693_irq_thread(0, max77693); | ||
230 | |||
231 | return 0; | ||
232 | } | ||
233 | |||
234 | static int max77693_irq_domain_map(struct irq_domain *d, unsigned int irq, | ||
235 | irq_hw_number_t hw) | ||
236 | { | ||
237 | struct max77693_dev *max77693 = d->host_data; | ||
238 | |||
239 | irq_set_chip_data(irq, max77693); | ||
240 | irq_set_chip_and_handler(irq, &max77693_irq_chip, handle_edge_irq); | ||
241 | irq_set_nested_thread(irq, 1); | ||
242 | #ifdef CONFIG_ARM | ||
243 | set_irq_flags(irq, IRQF_VALID); | ||
244 | #else | ||
245 | irq_set_noprobe(irq); | ||
246 | #endif | ||
247 | return 0; | ||
248 | } | ||
249 | |||
250 | static struct irq_domain_ops max77693_irq_domain_ops = { | ||
251 | .map = max77693_irq_domain_map, | ||
252 | }; | ||
253 | |||
254 | int max77693_irq_init(struct max77693_dev *max77693) | ||
255 | { | ||
256 | struct irq_domain *domain; | ||
257 | int i; | ||
258 | int ret; | ||
259 | |||
260 | mutex_init(&max77693->irqlock); | ||
261 | |||
262 | /* Mask individual interrupt sources */ | ||
263 | for (i = 0; i < MAX77693_IRQ_GROUP_NR; i++) { | ||
264 | struct regmap *map; | ||
265 | /* MUIC IRQ 0:MASK 1:NOT MASK */ | ||
266 | /* Other IRQ 1:MASK 0:NOT MASK */ | ||
267 | if (i >= MUIC_INT1 && i <= MUIC_INT3) { | ||
268 | max77693->irq_masks_cur[i] = 0x00; | ||
269 | max77693->irq_masks_cache[i] = 0x00; | ||
270 | } else { | ||
271 | max77693->irq_masks_cur[i] = 0xff; | ||
272 | max77693->irq_masks_cache[i] = 0xff; | ||
273 | } | ||
274 | map = max77693_get_regmap(max77693, i); | ||
275 | |||
276 | if (IS_ERR_OR_NULL(map)) | ||
277 | continue; | ||
278 | if (max77693_mask_reg[i] == MAX77693_REG_INVALID) | ||
279 | continue; | ||
280 | if (i >= MUIC_INT1 && i <= MUIC_INT3) | ||
281 | max77693_write_reg(map, max77693_mask_reg[i], 0x00); | ||
282 | else | ||
283 | max77693_write_reg(map, max77693_mask_reg[i], 0xff); | ||
284 | } | ||
285 | |||
286 | domain = irq_domain_add_linear(NULL, MAX77693_IRQ_NR, | ||
287 | &max77693_irq_domain_ops, max77693); | ||
288 | if (!domain) { | ||
289 | dev_err(max77693->dev, "could not create irq domain\n"); | ||
290 | return -ENODEV; | ||
291 | } | ||
292 | max77693->irq_domain = domain; | ||
293 | |||
294 | ret = request_threaded_irq(max77693->irq, NULL, max77693_irq_thread, | ||
295 | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, | ||
296 | "max77693-irq", max77693); | ||
297 | |||
298 | if (ret) | ||
299 | dev_err(max77693->dev, "Failed to request IRQ %d: %d\n", | ||
300 | max77693->irq, ret); | ||
301 | |||
302 | return 0; | ||
303 | } | ||
304 | |||
305 | void max77693_irq_exit(struct max77693_dev *max77693) | ||
306 | { | ||
307 | if (max77693->irq) | ||
308 | free_irq(max77693->irq, max77693); | ||
309 | } | ||