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path: root/drivers/media/video/sn9c102/sn9c102_mi0343.c
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Diffstat (limited to 'drivers/media/video/sn9c102/sn9c102_mi0343.c')
-rw-r--r--drivers/media/video/sn9c102/sn9c102_mi0343.c106
1 files changed, 53 insertions, 53 deletions
diff --git a/drivers/media/video/sn9c102/sn9c102_mi0343.c b/drivers/media/video/sn9c102/sn9c102_mi0343.c
index d9aa7a61095d..4169ea4a2e20 100644
--- a/drivers/media/video/sn9c102/sn9c102_mi0343.c
+++ b/drivers/media/video/sn9c102/sn9c102_mi0343.c
@@ -39,64 +39,64 @@ static int mi0343_init(struct sn9c102_device* cam)
39 err += sn9c102_write_reg(cam, 0xa0, 0x19); 39 err += sn9c102_write_reg(cam, 0xa0, 0x19);
40 40
41 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id, 41 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id,
42 0x0d, 0x00, 0x01, 0, 0); 42 0x0d, 0x00, 0x01, 0, 0);
43 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id, 43 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id,
44 0x0d, 0x00, 0x00, 0, 0); 44 0x0d, 0x00, 0x00, 0, 0);
45 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id, 45 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id,
46 0x03, 0x01, 0xe1, 0, 0); 46 0x03, 0x01, 0xe1, 0, 0);
47 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id, 47 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id,
48 0x04, 0x02, 0x81, 0, 0); 48 0x04, 0x02, 0x81, 0, 0);
49 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id, 49 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id,
50 0x05, 0x00, 0x17, 0, 0); 50 0x05, 0x00, 0x17, 0, 0);
51 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id, 51 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id,
52 0x06, 0x00, 0x11, 0, 0); 52 0x06, 0x00, 0x11, 0, 0);
53 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id, 53 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, mi0343.i2c_slave_id,
54 0x62, 0x04, 0x9a, 0, 0); 54 0x62, 0x04, 0x9a, 0, 0);
55 55
56 return err; 56 return err;
57} 57}
58 58
59 59
60static int mi0343_get_ctrl(struct sn9c102_device* cam, 60static int mi0343_get_ctrl(struct sn9c102_device* cam,
61 struct v4l2_control* ctrl) 61 struct v4l2_control* ctrl)
62{ 62{
63 switch (ctrl->id) { 63 switch (ctrl->id) {
64 case V4L2_CID_EXPOSURE: 64 case V4L2_CID_EXPOSURE:
65 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id, 65 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id,
66 0x09, 2+1, mi0343_i2c_data) < 0) 66 0x09, 2+1, mi0343_i2c_data) < 0)
67 return -EIO; 67 return -EIO;
68 ctrl->value = mi0343_i2c_data[2]; 68 ctrl->value = mi0343_i2c_data[2];
69 return 0; 69 return 0;
70 case V4L2_CID_GAIN: 70 case V4L2_CID_GAIN:
71 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id, 71 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id,
72 0x35, 2+1, mi0343_i2c_data) < 0) 72 0x35, 2+1, mi0343_i2c_data) < 0)
73 return -EIO; 73 return -EIO;
74 break; 74 break;
75 case V4L2_CID_HFLIP: 75 case V4L2_CID_HFLIP:
76 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id, 76 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id,
77 0x20, 2+1, mi0343_i2c_data) < 0) 77 0x20, 2+1, mi0343_i2c_data) < 0)
78 return -EIO; 78 return -EIO;
79 ctrl->value = mi0343_i2c_data[3] & 0x20 ? 1 : 0; 79 ctrl->value = mi0343_i2c_data[3] & 0x20 ? 1 : 0;
80 return 0; 80 return 0;
81 case V4L2_CID_VFLIP: 81 case V4L2_CID_VFLIP:
82 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id, 82 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id,
83 0x20, 2+1, mi0343_i2c_data) < 0) 83 0x20, 2+1, mi0343_i2c_data) < 0)
84 return -EIO; 84 return -EIO;
85 ctrl->value = mi0343_i2c_data[3] & 0x80 ? 1 : 0; 85 ctrl->value = mi0343_i2c_data[3] & 0x80 ? 1 : 0;
86 return 0; 86 return 0;
87 case V4L2_CID_RED_BALANCE: 87 case V4L2_CID_RED_BALANCE:
88 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id, 88 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id,
89 0x2d, 2+1, mi0343_i2c_data) < 0) 89 0x2d, 2+1, mi0343_i2c_data) < 0)
90 return -EIO; 90 return -EIO;
91 break; 91 break;
92 case V4L2_CID_BLUE_BALANCE: 92 case V4L2_CID_BLUE_BALANCE:
93 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id, 93 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id,
94 0x2c, 2+1, mi0343_i2c_data) < 0) 94 0x2c, 2+1, mi0343_i2c_data) < 0)
95 return -EIO; 95 return -EIO;
96 break; 96 break;
97 case SN9C102_V4L2_CID_GREEN_BALANCE: 97 case SN9C102_V4L2_CID_GREEN_BALANCE:
98 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id, 98 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id,
99 0x2e, 2+1, mi0343_i2c_data) < 0) 99 0x2e, 2+1, mi0343_i2c_data) < 0)
100 return -EIO; 100 return -EIO;
101 break; 101 break;
102 default: 102 default:
@@ -121,8 +121,8 @@ static int mi0343_get_ctrl(struct sn9c102_device* cam,
121} 121}
122 122
123 123
124static int mi0343_set_ctrl(struct sn9c102_device* cam, 124static int mi0343_set_ctrl(struct sn9c102_device* cam,
125 const struct v4l2_control* ctrl) 125 const struct v4l2_control* ctrl)
126{ 126{
127 u16 reg = 0; 127 u16 reg = 0;
128 int err = 0; 128 int err = 0;
@@ -144,51 +144,51 @@ static int mi0343_set_ctrl(struct sn9c102_device* cam,
144 switch (ctrl->id) { 144 switch (ctrl->id) {
145 case V4L2_CID_EXPOSURE: 145 case V4L2_CID_EXPOSURE:
146 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 146 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
147 mi0343.i2c_slave_id, 147 mi0343.i2c_slave_id,
148 0x09, ctrl->value, 0x00, 148 0x09, ctrl->value, 0x00,
149 0, 0); 149 0, 0);
150 break; 150 break;
151 case V4L2_CID_GAIN: 151 case V4L2_CID_GAIN:
152 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 152 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
153 mi0343.i2c_slave_id, 153 mi0343.i2c_slave_id,
154 0x35, reg >> 8, reg & 0xff, 154 0x35, reg >> 8, reg & 0xff,
155 0, 0); 155 0, 0);
156 break; 156 break;
157 case V4L2_CID_HFLIP: 157 case V4L2_CID_HFLIP:
158 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 158 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
159 mi0343.i2c_slave_id, 159 mi0343.i2c_slave_id,
160 0x20, ctrl->value ? 0x40:0x00, 160 0x20, ctrl->value ? 0x40:0x00,
161 ctrl->value ? 0x20:0x00, 161 ctrl->value ? 0x20:0x00,
162 0, 0); 162 0, 0);
163 break; 163 break;
164 case V4L2_CID_VFLIP: 164 case V4L2_CID_VFLIP:
165 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 165 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
166 mi0343.i2c_slave_id, 166 mi0343.i2c_slave_id,
167 0x20, ctrl->value ? 0x80:0x00, 167 0x20, ctrl->value ? 0x80:0x00,
168 ctrl->value ? 0x80:0x00, 168 ctrl->value ? 0x80:0x00,
169 0, 0); 169 0, 0);
170 break; 170 break;
171 case V4L2_CID_RED_BALANCE: 171 case V4L2_CID_RED_BALANCE:
172 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 172 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
173 mi0343.i2c_slave_id, 173 mi0343.i2c_slave_id,
174 0x2d, reg >> 8, reg & 0xff, 174 0x2d, reg >> 8, reg & 0xff,
175 0, 0); 175 0, 0);
176 break; 176 break;
177 case V4L2_CID_BLUE_BALANCE: 177 case V4L2_CID_BLUE_BALANCE:
178 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 178 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
179 mi0343.i2c_slave_id, 179 mi0343.i2c_slave_id,
180 0x2c, reg >> 8, reg & 0xff, 180 0x2c, reg >> 8, reg & 0xff,
181 0, 0); 181 0, 0);
182 break; 182 break;
183 case SN9C102_V4L2_CID_GREEN_BALANCE: 183 case SN9C102_V4L2_CID_GREEN_BALANCE:
184 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 184 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
185 mi0343.i2c_slave_id, 185 mi0343.i2c_slave_id,
186 0x2b, reg >> 8, reg & 0xff, 186 0x2b, reg >> 8, reg & 0xff,
187 0, 0); 187 0, 0);
188 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 188 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
189 mi0343.i2c_slave_id, 189 mi0343.i2c_slave_id,
190 0x2e, reg >> 8, reg & 0xff, 190 0x2e, reg >> 8, reg & 0xff,
191 0, 0); 191 0, 0);
192 break; 192 break;
193 default: 193 default:
194 return -EINVAL; 194 return -EINVAL;
@@ -198,8 +198,8 @@ static int mi0343_set_ctrl(struct sn9c102_device* cam,
198} 198}
199 199
200 200
201static int mi0343_set_crop(struct sn9c102_device* cam, 201static int mi0343_set_crop(struct sn9c102_device* cam,
202 const struct v4l2_rect* rect) 202 const struct v4l2_rect* rect)
203{ 203{
204 struct sn9c102_sensor* s = &mi0343; 204 struct sn9c102_sensor* s = &mi0343;
205 int err = 0; 205 int err = 0;
@@ -213,20 +213,20 @@ static int mi0343_set_crop(struct sn9c102_device* cam,
213} 213}
214 214
215 215
216static int mi0343_set_pix_format(struct sn9c102_device* cam, 216static int mi0343_set_pix_format(struct sn9c102_device* cam,
217 const struct v4l2_pix_format* pix) 217 const struct v4l2_pix_format* pix)
218{ 218{
219 int err = 0; 219 int err = 0;
220 220
221 if (pix->pixelformat == V4L2_PIX_FMT_SN9C10X) { 221 if (pix->pixelformat == V4L2_PIX_FMT_SN9C10X) {
222 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 222 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
223 mi0343.i2c_slave_id, 223 mi0343.i2c_slave_id,
224 0x0a, 0x00, 0x03, 0, 0); 224 0x0a, 0x00, 0x03, 0, 0);
225 err += sn9c102_write_reg(cam, 0x20, 0x19); 225 err += sn9c102_write_reg(cam, 0x20, 0x19);
226 } else { 226 } else {
227 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4, 227 err += sn9c102_i2c_try_raw_write(cam, &mi0343, 4,
228 mi0343.i2c_slave_id, 228 mi0343.i2c_slave_id,
229 0x0a, 0x00, 0x05, 0, 0); 229 0x0a, 0x00, 0x05, 0, 0);
230 err += sn9c102_write_reg(cam, 0xa0, 0x19); 230 err += sn9c102_write_reg(cam, 0xa0, 0x19);
231 } 231 }
232 232
@@ -351,7 +351,7 @@ int sn9c102_probe_mi0343(struct sn9c102_device* cam)
351 return -EIO; 351 return -EIO;
352 352
353 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id, 0x00, 353 if (sn9c102_i2c_try_raw_read(cam, &mi0343, mi0343.i2c_slave_id, 0x00,
354 2, mi0343_i2c_data) < 0) 354 2, mi0343_i2c_data) < 0)
355 return -EIO; 355 return -EIO;
356 356
357 if (mi0343_i2c_data[4] != 0x32 && mi0343_i2c_data[3] != 0xe3) 357 if (mi0343_i2c_data[4] != 0x32 && mi0343_i2c_data[3] != 0xe3)
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 09:48:17 -0500