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Diffstat (limited to 'drivers/media/video/cx231xx/cx231xx-417.c')
-rw-r--r--drivers/media/video/cx231xx/cx231xx-417.c2230
1 files changed, 2230 insertions, 0 deletions
diff --git a/drivers/media/video/cx231xx/cx231xx-417.c b/drivers/media/video/cx231xx/cx231xx-417.c
new file mode 100644
index 000000000000..d0e0d713a466
--- /dev/null
+++ b/drivers/media/video/cx231xx/cx231xx-417.c
@@ -0,0 +1,2230 @@
1/*
2 *
3 * Support for a cx23417 mpeg encoder via cx231xx host port.
4 *
5 * (c) 2004 Jelle Foks <jelle@foks.us>
6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
7 * (c) 2008 Steven Toth <stoth@linuxtv.org>
8 * - CX23885/7/8 support
9 *
10 * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/module.h>
28#include <linux/moduleparam.h>
29#include <linux/init.h>
30#include <linux/fs.h>
31#include <linux/delay.h>
32#include <linux/device.h>
33#include <linux/firmware.h>
34#include <linux/smp_lock.h>
35#include <media/v4l2-common.h>
36#include <media/v4l2-ioctl.h>
37#include <media/cx2341x.h>
38#include <linux/usb.h>
39
40#include "cx231xx.h"
41/*#include "cx23885-ioctl.h"*/
42
43#define CX231xx_FIRM_IMAGE_SIZE 376836
44#define CX231xx_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
45
46/* for polaris ITVC*/
47#define ITVC_WRITE_DIR 0x03FDFC00
48#define ITVC_READ_DIR 0x0001FC00
49
50#define MCI_MEMORY_DATA_BYTE0 0x00
51#define MCI_MEMORY_DATA_BYTE1 0x08
52#define MCI_MEMORY_DATA_BYTE2 0x10
53#define MCI_MEMORY_DATA_BYTE3 0x18
54
55#define MCI_MEMORY_ADDRESS_BYTE2 0x20
56#define MCI_MEMORY_ADDRESS_BYTE1 0x28
57#define MCI_MEMORY_ADDRESS_BYTE0 0x30
58
59#define MCI_REGISTER_DATA_BYTE0 0x40
60#define MCI_REGISTER_DATA_BYTE1 0x48
61#define MCI_REGISTER_DATA_BYTE2 0x50
62#define MCI_REGISTER_DATA_BYTE3 0x58
63
64#define MCI_REGISTER_ADDRESS_BYTE0 0x60
65#define MCI_REGISTER_ADDRESS_BYTE1 0x68
66
67#define MCI_REGISTER_MODE 0x70
68
69/*Read and write modes
70 for polaris ITVC*/
71#define MCI_MODE_REGISTER_READ 0x000
72#define MCI_MODE_REGISTER_WRITE 0x100
73#define MCI_MODE_MEMORY_READ 0x000
74#define MCI_MODE_MEMORY_WRITE 0x4000
75
76static unsigned int mpegbufs = 8;
77module_param(mpegbufs, int, 0644);
78MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
79static unsigned int mpeglines = 128;
80module_param(mpeglines, int, 0644);
81MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
82static unsigned int mpeglinesize = 512;
83module_param(mpeglinesize, int, 0644);
84MODULE_PARM_DESC(mpeglinesize,
85 "number of bytes in each line of an MPEG buffer, range 512-1024");
86
87static unsigned int v4l_debug = 1;
88module_param(v4l_debug, int, 0644);
89MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
90struct cx231xx_dmaqueue *dma_qq;
91#define dprintk(level, fmt, arg...)\
92 do { if (v4l_debug >= level) \
93 printk(KERN_INFO "%s: " fmt, \
94 (dev) ? dev->name : "cx231xx[?]", ## arg); \
95 } while (0)
96
97static struct cx231xx_tvnorm cx231xx_tvnorms[] = {
98 {
99 .name = "NTSC-M",
100 .id = V4L2_STD_NTSC_M,
101 }, {
102 .name = "NTSC-JP",
103 .id = V4L2_STD_NTSC_M_JP,
104 }, {
105 .name = "PAL-BG",
106 .id = V4L2_STD_PAL_BG,
107 }, {
108 .name = "PAL-DK",
109 .id = V4L2_STD_PAL_DK,
110 }, {
111 .name = "PAL-I",
112 .id = V4L2_STD_PAL_I,
113 }, {
114 .name = "PAL-M",
115 .id = V4L2_STD_PAL_M,
116 }, {
117 .name = "PAL-N",
118 .id = V4L2_STD_PAL_N,
119 }, {
120 .name = "PAL-Nc",
121 .id = V4L2_STD_PAL_Nc,
122 }, {
123 .name = "PAL-60",
124 .id = V4L2_STD_PAL_60,
125 }, {
126 .name = "SECAM-L",
127 .id = V4L2_STD_SECAM_L,
128 }, {
129 .name = "SECAM-DK",
130 .id = V4L2_STD_SECAM_DK,
131 }
132};
133
134/* ------------------------------------------------------------------ */
135enum cx231xx_capture_type {
136 CX231xx_MPEG_CAPTURE,
137 CX231xx_RAW_CAPTURE,
138 CX231xx_RAW_PASSTHRU_CAPTURE
139};
140enum cx231xx_capture_bits {
141 CX231xx_RAW_BITS_NONE = 0x00,
142 CX231xx_RAW_BITS_YUV_CAPTURE = 0x01,
143 CX231xx_RAW_BITS_PCM_CAPTURE = 0x02,
144 CX231xx_RAW_BITS_VBI_CAPTURE = 0x04,
145 CX231xx_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
146 CX231xx_RAW_BITS_TO_HOST_CAPTURE = 0x10
147};
148enum cx231xx_capture_end {
149 CX231xx_END_AT_GOP, /* stop at the end of gop, generate irq */
150 CX231xx_END_NOW, /* stop immediately, no irq */
151};
152enum cx231xx_framerate {
153 CX231xx_FRAMERATE_NTSC_30, /* NTSC: 30fps */
154 CX231xx_FRAMERATE_PAL_25 /* PAL: 25fps */
155};
156enum cx231xx_stream_port {
157 CX231xx_OUTPUT_PORT_MEMORY,
158 CX231xx_OUTPUT_PORT_STREAMING,
159 CX231xx_OUTPUT_PORT_SERIAL
160};
161enum cx231xx_data_xfer_status {
162 CX231xx_MORE_BUFFERS_FOLLOW,
163 CX231xx_LAST_BUFFER,
164};
165enum cx231xx_picture_mask {
166 CX231xx_PICTURE_MASK_NONE,
167 CX231xx_PICTURE_MASK_I_FRAMES,
168 CX231xx_PICTURE_MASK_I_P_FRAMES = 0x3,
169 CX231xx_PICTURE_MASK_ALL_FRAMES = 0x7,
170};
171enum cx231xx_vbi_mode_bits {
172 CX231xx_VBI_BITS_SLICED,
173 CX231xx_VBI_BITS_RAW,
174};
175enum cx231xx_vbi_insertion_bits {
176 CX231xx_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
177 CX231xx_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
178 CX231xx_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
179 CX231xx_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
180 CX231xx_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
181};
182enum cx231xx_dma_unit {
183 CX231xx_DMA_BYTES,
184 CX231xx_DMA_FRAMES,
185};
186enum cx231xx_dma_transfer_status_bits {
187 CX231xx_DMA_TRANSFER_BITS_DONE = 0x01,
188 CX231xx_DMA_TRANSFER_BITS_ERROR = 0x04,
189 CX231xx_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
190};
191enum cx231xx_pause {
192 CX231xx_PAUSE_ENCODING,
193 CX231xx_RESUME_ENCODING,
194};
195enum cx231xx_copyright {
196 CX231xx_COPYRIGHT_OFF,
197 CX231xx_COPYRIGHT_ON,
198};
199enum cx231xx_notification_type {
200 CX231xx_NOTIFICATION_REFRESH,
201};
202enum cx231xx_notification_status {
203 CX231xx_NOTIFICATION_OFF,
204 CX231xx_NOTIFICATION_ON,
205};
206enum cx231xx_notification_mailbox {
207 CX231xx_NOTIFICATION_NO_MAILBOX = -1,
208};
209enum cx231xx_field1_lines {
210 CX231xx_FIELD1_SAA7114 = 0x00EF, /* 239 */
211 CX231xx_FIELD1_SAA7115 = 0x00F0, /* 240 */
212 CX231xx_FIELD1_MICRONAS = 0x0105, /* 261 */
213};
214enum cx231xx_field2_lines {
215 CX231xx_FIELD2_SAA7114 = 0x00EF, /* 239 */
216 CX231xx_FIELD2_SAA7115 = 0x00F0, /* 240 */
217 CX231xx_FIELD2_MICRONAS = 0x0106, /* 262 */
218};
219enum cx231xx_custom_data_type {
220 CX231xx_CUSTOM_EXTENSION_USR_DATA,
221 CX231xx_CUSTOM_PRIVATE_PACKET,
222};
223enum cx231xx_mute {
224 CX231xx_UNMUTE,
225 CX231xx_MUTE,
226};
227enum cx231xx_mute_video_mask {
228 CX231xx_MUTE_VIDEO_V_MASK = 0x0000FF00,
229 CX231xx_MUTE_VIDEO_U_MASK = 0x00FF0000,
230 CX231xx_MUTE_VIDEO_Y_MASK = 0xFF000000,
231};
232enum cx231xx_mute_video_shift {
233 CX231xx_MUTE_VIDEO_V_SHIFT = 8,
234 CX231xx_MUTE_VIDEO_U_SHIFT = 16,
235 CX231xx_MUTE_VIDEO_Y_SHIFT = 24,
236};
237
238/* defines below are from ivtv-driver.h */
239#define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
240
241/* Firmware API commands */
242#define IVTV_API_STD_TIMEOUT 500
243
244/* Registers */
245/* IVTV_REG_OFFSET */
246#define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
247#define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
248#define IVTV_REG_SPU (0x9050)
249#define IVTV_REG_HW_BLOCKS (0x9054)
250#define IVTV_REG_VPU (0x9058)
251#define IVTV_REG_APU (0xA064)
252
253/**** Bit definitions for MC417_RWD and MC417_OEN registers ***
254 bits 31-16
255+-----------+
256| Reserved |
257+-----------+
258 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
259+-------+-------+-------+-------+-------+-------+-------+-------+
260| MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
261+-------+-------+-------+-------+-------+-------+-------+-------+
262 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
263+-------+-------+-------+-------+-------+-------+-------+-------+
264|MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
265+-------+-------+-------+-------+-------+-------+-------+-------+
266***/
267#define MC417_MIWR 0x8000
268#define MC417_MIRD 0x4000
269#define MC417_MICS 0x2000
270#define MC417_MIRDY 0x1000
271#define MC417_MIADDR 0x0F00
272#define MC417_MIDATA 0x00FF
273
274
275/*** Bit definitions for MC417_CTL register ****
276 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
277+--------+-------------+--------+--------------+------------+
278|Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
279+--------+-------------+--------+--------------+------------+
280***/
281#define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
282#define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
283#define MC417_UART_GPIO_EN 0x00000001
284
285/* Values for speed control */
286#define MC417_SPD_CTL_SLOW 0x1
287#define MC417_SPD_CTL_MEDIUM 0x0
288#define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
289
290/* Values for GPIO select */
291#define MC417_GPIO_SEL_GPIO3 0x3
292#define MC417_GPIO_SEL_GPIO2 0x2
293#define MC417_GPIO_SEL_GPIO1 0x1
294#define MC417_GPIO_SEL_GPIO0 0x0
295
296
297#define CX23417_GPIO_MASK 0xFC0003FF
298int setITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 value)
299{
300 int status = 0;
301 u32 _gpio_direction = 0;
302
303 _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
304 _gpio_direction = _gpio_direction|gpio_direction;
305 status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
306 (u8 *)&value, 4, 0, 0);
307 return status;
308}
309int getITVCReg(struct cx231xx *dev, u32 gpio_direction, u32 *pValue)
310{
311 int status = 0;
312 u32 _gpio_direction = 0;
313
314 _gpio_direction = _gpio_direction & CX23417_GPIO_MASK;
315 _gpio_direction = _gpio_direction|gpio_direction;
316
317 status = cx231xx_send_gpio_cmd(dev, _gpio_direction,
318 (u8 *)pValue, 4, 0, 1);
319 return status;
320}
321int waitForMciComplete(struct cx231xx *dev)
322{
323 u32 gpio;
324 u32 gpio_driection = 0;
325 u8 count = 0;
326 getITVCReg(dev, gpio_driection, &gpio);
327
328 while (!(gpio&0x020000)) {
329 msleep(10);
330
331 getITVCReg(dev, gpio_driection, &gpio);
332
333 if (count++ > 100) {
334 dprintk(3, "ERROR: Timeout - gpio=%x\n", gpio);
335 return -1;
336 }
337 }
338 return 0;
339}
340int mc417_register_write(struct cx231xx *dev, u16 address, u32 value)
341{
342 u32 temp;
343 int status = 0;
344
345 temp = 0x82|MCI_REGISTER_DATA_BYTE0|((value&0x000000FF)<<8);
346 temp = temp<<10;
347 status = setITVCReg(dev, ITVC_WRITE_DIR, temp);
348 if (status < 0)
349 return status;
350 temp = temp|((0x05)<<10);
351 setITVCReg(dev, ITVC_WRITE_DIR, temp);
352
353 /*write data byte 1;*/
354 temp = 0x82|MCI_REGISTER_DATA_BYTE1|(value&0x0000FF00);
355 temp = temp<<10;
356 setITVCReg(dev, ITVC_WRITE_DIR, temp);
357 temp = temp|((0x05)<<10);
358 setITVCReg(dev, ITVC_WRITE_DIR, temp);
359
360 /*write data byte 2;*/
361 temp = 0x82|MCI_REGISTER_DATA_BYTE2|((value&0x00FF0000)>>8);
362 temp = temp<<10;
363 setITVCReg(dev, ITVC_WRITE_DIR, temp);
364 temp = temp|((0x05)<<10);
365 setITVCReg(dev, ITVC_WRITE_DIR, temp);
366
367 /*write data byte 3;*/
368 temp = 0x82|MCI_REGISTER_DATA_BYTE3|((value&0xFF000000)>>16);
369 temp = temp<<10;
370 setITVCReg(dev, ITVC_WRITE_DIR, temp);
371 temp = temp|((0x05)<<10);
372 setITVCReg(dev, ITVC_WRITE_DIR, temp);
373
374 /*write address byte 0;*/
375 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x000000FF)<<8);
376 temp = temp<<10;
377 setITVCReg(dev, ITVC_WRITE_DIR, temp);
378 temp = temp|((0x05)<<10);
379 setITVCReg(dev, ITVC_WRITE_DIR, temp);
380
381 /*write address byte 1;*/
382 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0x0000FF00);
383 temp = temp<<10;
384 setITVCReg(dev, ITVC_WRITE_DIR, temp);
385 temp = temp|((0x05)<<10);
386 setITVCReg(dev, ITVC_WRITE_DIR, temp);
387
388 /*Write that the mode is write.*/
389 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_WRITE;
390 temp = temp<<10;
391 setITVCReg(dev, ITVC_WRITE_DIR, temp);
392 temp = temp|((0x05)<<10);
393 setITVCReg(dev, ITVC_WRITE_DIR, temp);
394
395 return waitForMciComplete(dev);
396
397}
398
399
400int mc417_register_read(struct cx231xx *dev, u16 address, u32 *value)
401{
402 /*write address byte 0;*/
403 u32 temp;
404 u32 return_value = 0;
405 int ret = 0;
406
407 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE0|((address&0x00FF)<<8);
408 temp = temp<<10;
409 setITVCReg(dev, ITVC_WRITE_DIR, temp);
410 temp = temp|((0x05)<<10);
411 setITVCReg(dev, ITVC_WRITE_DIR, temp);
412
413 /*write address byte 1;*/
414 temp = 0x82|MCI_REGISTER_ADDRESS_BYTE1|(address&0xFF00);
415 temp = temp<<10;
416 setITVCReg(dev, ITVC_WRITE_DIR, temp);
417 temp = temp|((0x05)<<10);
418 setITVCReg(dev, ITVC_WRITE_DIR, temp);
419
420 /*write that the mode is read;*/
421 temp = 0x82 | MCI_REGISTER_MODE | MCI_MODE_REGISTER_READ;
422 temp = temp<<10;
423 setITVCReg(dev, ITVC_WRITE_DIR, temp);
424 temp = temp|((0x05)<<10);
425 setITVCReg(dev, ITVC_WRITE_DIR, temp);
426
427 /*wait for the MIRDY line to be asserted ,
428 signalling that the read is done;*/
429 ret = waitForMciComplete(dev);
430
431
432 /*switch the DATA- GPIO to input mode;*/
433
434 /*Read data byte 0;*/
435 temp = (0x82|MCI_REGISTER_DATA_BYTE0)<<10;
436 setITVCReg(dev, ITVC_READ_DIR, temp);
437 temp = ((0x81|MCI_REGISTER_DATA_BYTE0)<<10);
438 setITVCReg(dev, ITVC_READ_DIR, temp);
439 getITVCReg(dev, ITVC_READ_DIR, &temp);
440 return_value |= ((temp&0x03FC0000)>>18);
441 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
442
443 /* Read data byte 1;*/
444 temp = (0x82|MCI_REGISTER_DATA_BYTE1)<<10;
445 setITVCReg(dev, ITVC_READ_DIR, temp);
446 temp = ((0x81|MCI_REGISTER_DATA_BYTE1)<<10);
447 setITVCReg(dev, ITVC_READ_DIR, temp);
448 getITVCReg(dev, ITVC_READ_DIR, &temp);
449
450 return_value |= ((temp&0x03FC0000)>>10);
451 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
452
453 /*Read data byte 2;*/
454 temp = (0x82|MCI_REGISTER_DATA_BYTE2)<<10;
455 setITVCReg(dev, ITVC_READ_DIR, temp);
456 temp = ((0x81|MCI_REGISTER_DATA_BYTE2)<<10);
457 setITVCReg(dev, ITVC_READ_DIR, temp);
458 getITVCReg(dev, ITVC_READ_DIR, &temp);
459 return_value |= ((temp&0x03FC0000)>>2);
460 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
461
462 /*Read data byte 3;*/
463 temp = (0x82|MCI_REGISTER_DATA_BYTE3)<<10;
464 setITVCReg(dev, ITVC_READ_DIR, temp);
465 temp = ((0x81|MCI_REGISTER_DATA_BYTE3)<<10);
466 setITVCReg(dev, ITVC_READ_DIR, temp);
467 getITVCReg(dev, ITVC_READ_DIR, &temp);
468 return_value |= ((temp&0x03FC0000)<<6);
469 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
470
471 *value = return_value;
472
473
474 return ret;
475}
476
477int mc417_memory_write(struct cx231xx *dev, u32 address, u32 value)
478{
479
480 /*write data byte 0;*/
481
482 u32 temp;
483 int ret = 0;
484
485 temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8);
486 temp = temp<<10;
487 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
488 if (ret < 0)
489 return ret;
490 temp = temp|((0x05)<<10);
491 setITVCReg(dev, ITVC_WRITE_DIR, temp);
492
493 /*write data byte 1;*/
494 temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
495 temp = temp<<10;
496 setITVCReg(dev, ITVC_WRITE_DIR, temp);
497 temp = temp|((0x05)<<10);
498 setITVCReg(dev, ITVC_WRITE_DIR, temp);
499
500 /*write data byte 2;*/
501 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
502 temp = temp<<10;
503 setITVCReg(dev, ITVC_WRITE_DIR, temp);
504 temp = temp|((0x05)<<10);
505 setITVCReg(dev, ITVC_WRITE_DIR, temp);
506
507 /*write data byte 3;*/
508 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
509 temp = temp<<10;
510 setITVCReg(dev, ITVC_WRITE_DIR, temp);
511 temp = temp|((0x05)<<10);
512 setITVCReg(dev, ITVC_WRITE_DIR, temp);
513
514 /* write address byte 2;*/
515 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
516 ((address & 0x003F0000)>>8);
517 temp = temp<<10;
518 setITVCReg(dev, ITVC_WRITE_DIR, temp);
519 temp = temp|((0x05)<<10);
520 setITVCReg(dev, ITVC_WRITE_DIR, temp);
521
522 /* write address byte 1;*/
523 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
524 temp = temp<<10;
525 setITVCReg(dev, ITVC_WRITE_DIR, temp);
526 temp = temp|((0x05)<<10);
527 setITVCReg(dev, ITVC_WRITE_DIR, temp);
528
529 /* write address byte 0;*/
530 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
531 temp = temp<<10;
532 setITVCReg(dev, ITVC_WRITE_DIR, temp);
533 temp = temp|((0x05)<<10);
534 setITVCReg(dev, ITVC_WRITE_DIR, temp);
535
536 /*wait for MIRDY line;*/
537 waitForMciComplete(dev);
538
539return 0;
540
541}
542
543int mc417_memory_read(struct cx231xx *dev, u32 address, u32 *value)
544{
545
546 u32 temp = 0;
547 u32 return_value = 0;
548 int ret = 0;
549
550 /*write address byte 2;*/
551 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_READ |
552 ((address & 0x003F0000)>>8);
553 temp = temp<<10;
554 ret = setITVCReg(dev, ITVC_WRITE_DIR, temp);
555 if (ret < 0)
556 return ret;
557 temp = temp|((0x05)<<10);
558 setITVCReg(dev, ITVC_WRITE_DIR, temp);
559
560 /*write address byte 1*/
561 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
562 temp = temp<<10;
563 setITVCReg(dev, ITVC_WRITE_DIR, temp);
564 temp = temp|((0x05)<<10);
565 setITVCReg(dev, ITVC_WRITE_DIR, temp);
566
567 /*write address byte 0*/
568 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0 | ((address & 0x00FF)<<8);
569 temp = temp<<10;
570 setITVCReg(dev, ITVC_WRITE_DIR, temp);
571 temp = temp|((0x05)<<10);
572 setITVCReg(dev, ITVC_WRITE_DIR, temp);
573
574 /*Wait for MIRDY line*/
575 ret = waitForMciComplete(dev);
576
577
578 /*Read data byte 3;*/
579 temp = (0x82|MCI_MEMORY_DATA_BYTE3)<<10;
580 setITVCReg(dev, ITVC_READ_DIR, temp);
581 temp = ((0x81|MCI_MEMORY_DATA_BYTE3)<<10);
582 setITVCReg(dev, ITVC_READ_DIR, temp);
583 getITVCReg(dev, ITVC_READ_DIR, &temp);
584 return_value |= ((temp&0x03FC0000)<<6);
585 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
586
587 /*Read data byte 2;*/
588 temp = (0x82|MCI_MEMORY_DATA_BYTE2)<<10;
589 setITVCReg(dev, ITVC_READ_DIR, temp);
590 temp = ((0x81|MCI_MEMORY_DATA_BYTE2)<<10);
591 setITVCReg(dev, ITVC_READ_DIR, temp);
592 getITVCReg(dev, ITVC_READ_DIR, &temp);
593 return_value |= ((temp&0x03FC0000)>>2);
594 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
595
596 /* Read data byte 1;*/
597 temp = (0x82|MCI_MEMORY_DATA_BYTE1)<<10;
598 setITVCReg(dev, ITVC_READ_DIR, temp);
599 temp = ((0x81|MCI_MEMORY_DATA_BYTE1)<<10);
600 setITVCReg(dev, ITVC_READ_DIR, temp);
601 getITVCReg(dev, ITVC_READ_DIR, &temp);
602 return_value |= ((temp&0x03FC0000)>>10);
603 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
604
605 /*Read data byte 0;*/
606 temp = (0x82|MCI_MEMORY_DATA_BYTE0)<<10;
607 setITVCReg(dev, ITVC_READ_DIR, temp);
608 temp = ((0x81|MCI_MEMORY_DATA_BYTE0)<<10);
609 setITVCReg(dev, ITVC_READ_DIR, temp);
610 getITVCReg(dev, ITVC_READ_DIR, &temp);
611 return_value |= ((temp&0x03FC0000)>>18);
612 setITVCReg(dev, ITVC_READ_DIR, (0x87<<10));
613
614 *value = return_value;
615 return ret;
616}
617
618void mc417_gpio_set(struct cx231xx *dev, u32 mask)
619{
620 u32 val;
621
622 /* Set the gpio value */
623 mc417_register_read(dev, 0x900C, &val);
624 val |= (mask & 0x000ffff);
625 mc417_register_write(dev, 0x900C, val);
626}
627
628void mc417_gpio_clear(struct cx231xx *dev, u32 mask)
629{
630 u32 val;
631
632 /* Clear the gpio value */
633 mc417_register_read(dev, 0x900C, &val);
634 val &= ~(mask & 0x0000ffff);
635 mc417_register_write(dev, 0x900C, val);
636}
637
638void mc417_gpio_enable(struct cx231xx *dev, u32 mask, int asoutput)
639{
640 u32 val;
641
642 /* Enable GPIO direction bits */
643 mc417_register_read(dev, 0x9020, &val);
644 if (asoutput)
645 val |= (mask & 0x0000ffff);
646 else
647 val &= ~(mask & 0x0000ffff);
648
649 mc417_register_write(dev, 0x9020, val);
650}
651/* ------------------------------------------------------------------ */
652
653/* MPEG encoder API */
654static char *cmd_to_str(int cmd)
655{
656 switch (cmd) {
657 case CX2341X_ENC_PING_FW:
658 return "PING_FW";
659 case CX2341X_ENC_START_CAPTURE:
660 return "START_CAPTURE";
661 case CX2341X_ENC_STOP_CAPTURE:
662 return "STOP_CAPTURE";
663 case CX2341X_ENC_SET_AUDIO_ID:
664 return "SET_AUDIO_ID";
665 case CX2341X_ENC_SET_VIDEO_ID:
666 return "SET_VIDEO_ID";
667 case CX2341X_ENC_SET_PCR_ID:
668 return "SET_PCR_PID";
669 case CX2341X_ENC_SET_FRAME_RATE:
670 return "SET_FRAME_RATE";
671 case CX2341X_ENC_SET_FRAME_SIZE:
672 return "SET_FRAME_SIZE";
673 case CX2341X_ENC_SET_BIT_RATE:
674 return "SET_BIT_RATE";
675 case CX2341X_ENC_SET_GOP_PROPERTIES:
676 return "SET_GOP_PROPERTIES";
677 case CX2341X_ENC_SET_ASPECT_RATIO:
678 return "SET_ASPECT_RATIO";
679 case CX2341X_ENC_SET_DNR_FILTER_MODE:
680 return "SET_DNR_FILTER_PROPS";
681 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
682 return "SET_DNR_FILTER_PROPS";
683 case CX2341X_ENC_SET_CORING_LEVELS:
684 return "SET_CORING_LEVELS";
685 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
686 return "SET_SPATIAL_FILTER_TYPE";
687 case CX2341X_ENC_SET_VBI_LINE:
688 return "SET_VBI_LINE";
689 case CX2341X_ENC_SET_STREAM_TYPE:
690 return "SET_STREAM_TYPE";
691 case CX2341X_ENC_SET_OUTPUT_PORT:
692 return "SET_OUTPUT_PORT";
693 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
694 return "SET_AUDIO_PROPERTIES";
695 case CX2341X_ENC_HALT_FW:
696 return "HALT_FW";
697 case CX2341X_ENC_GET_VERSION:
698 return "GET_VERSION";
699 case CX2341X_ENC_SET_GOP_CLOSURE:
700 return "SET_GOP_CLOSURE";
701 case CX2341X_ENC_GET_SEQ_END:
702 return "GET_SEQ_END";
703 case CX2341X_ENC_SET_PGM_INDEX_INFO:
704 return "SET_PGM_INDEX_INFO";
705 case CX2341X_ENC_SET_VBI_CONFIG:
706 return "SET_VBI_CONFIG";
707 case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
708 return "SET_DMA_BLOCK_SIZE";
709 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
710 return "GET_PREV_DMA_INFO_MB_10";
711 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
712 return "GET_PREV_DMA_INFO_MB_9";
713 case CX2341X_ENC_SCHED_DMA_TO_HOST:
714 return "SCHED_DMA_TO_HOST";
715 case CX2341X_ENC_INITIALIZE_INPUT:
716 return "INITIALIZE_INPUT";
717 case CX2341X_ENC_SET_FRAME_DROP_RATE:
718 return "SET_FRAME_DROP_RATE";
719 case CX2341X_ENC_PAUSE_ENCODER:
720 return "PAUSE_ENCODER";
721 case CX2341X_ENC_REFRESH_INPUT:
722 return "REFRESH_INPUT";
723 case CX2341X_ENC_SET_COPYRIGHT:
724 return "SET_COPYRIGHT";
725 case CX2341X_ENC_SET_EVENT_NOTIFICATION:
726 return "SET_EVENT_NOTIFICATION";
727 case CX2341X_ENC_SET_NUM_VSYNC_LINES:
728 return "SET_NUM_VSYNC_LINES";
729 case CX2341X_ENC_SET_PLACEHOLDER:
730 return "SET_PLACEHOLDER";
731 case CX2341X_ENC_MUTE_VIDEO:
732 return "MUTE_VIDEO";
733 case CX2341X_ENC_MUTE_AUDIO:
734 return "MUTE_AUDIO";
735 case CX2341X_ENC_MISC:
736 return "MISC";
737 default:
738 return "UNKNOWN";
739 }
740}
741
742static int cx231xx_mbox_func(void *priv,
743 u32 command,
744 int in,
745 int out,
746 u32 data[CX2341X_MBOX_MAX_DATA])
747{
748 struct cx231xx *dev = priv;
749 unsigned long timeout;
750 u32 value, flag, retval = 0;
751 int i;
752
753 dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
754 cmd_to_str(command));
755
756 /* this may not be 100% safe if we can't read any memory location
757 without side effects */
758 mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
759 if (value != 0x12345678) {
760 dprintk(3,
761 "Firmware and/or mailbox pointer not initialized "
762 "or corrupted, signature = 0x%x, cmd = %s\n", value,
763 cmd_to_str(command));
764 return -1;
765 }
766
767 /* This read looks at 32 bits, but flag is only 8 bits.
768 * Seems we also bail if CMD or TIMEOUT bytes are set???
769 */
770 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
771 if (flag) {
772 dprintk(3, "ERROR: Mailbox appears to be in use "
773 "(%x), cmd = %s\n", flag, cmd_to_str(command));
774 return -1;
775 }
776
777 flag |= 1; /* tell 'em we're working on it */
778 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
779
780 /* write command + args + fill remaining with zeros */
781 /* command code */
782 mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
783 mc417_memory_write(dev, dev->cx23417_mailbox + 3,
784 IVTV_API_STD_TIMEOUT); /* timeout */
785 for (i = 0; i < in; i++) {
786 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
787 dprintk(3, "API Input %d = %d\n", i, data[i]);
788 }
789 for (; i < CX2341X_MBOX_MAX_DATA; i++)
790 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
791
792 flag |= 3; /* tell 'em we're done writing */
793 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
794
795 /* wait for firmware to handle the API command */
796 timeout = jiffies + msecs_to_jiffies(10);
797 for (;;) {
798 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
799 if (0 != (flag & 4))
800 break;
801 if (time_after(jiffies, timeout)) {
802 dprintk(3, "ERROR: API Mailbox timeout\n");
803 return -1;
804 }
805 udelay(10);
806 }
807
808 /* read output values */
809 for (i = 0; i < out; i++) {
810 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
811 dprintk(3, "API Output %d = %d\n", i, data[i]);
812 }
813
814 mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
815 dprintk(3, "API result = %d\n", retval);
816
817 flag = 0;
818 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
819
820 return retval;
821}
822
823/* We don't need to call the API often, so using just one
824 * mailbox will probably suffice
825 */
826static int cx231xx_api_cmd(struct cx231xx *dev,
827 u32 command,
828 u32 inputcnt,
829 u32 outputcnt,
830 ...)
831{
832 u32 data[CX2341X_MBOX_MAX_DATA];
833 va_list vargs;
834 int i, err;
835
836 dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
837
838 va_start(vargs, outputcnt);
839 for (i = 0; i < inputcnt; i++)
840 data[i] = va_arg(vargs, int);
841
842 err = cx231xx_mbox_func(dev, command, inputcnt, outputcnt, data);
843 for (i = 0; i < outputcnt; i++) {
844 int *vptr = va_arg(vargs, int *);
845 *vptr = data[i];
846 }
847 va_end(vargs);
848
849 return err;
850}
851
852static int cx231xx_find_mailbox(struct cx231xx *dev)
853{
854 u32 signature[4] = {
855 0x12345678, 0x34567812, 0x56781234, 0x78123456
856 };
857 int signaturecnt = 0;
858 u32 value;
859 int i;
860 int ret = 0;
861
862 dprintk(2, "%s()\n", __func__);
863
864 for (i = 0; i < 0x100; i++) {/*CX231xx_FIRM_IMAGE_SIZE*/
865 ret = mc417_memory_read(dev, i, &value);
866 if (ret < 0)
867 return ret;
868 if (value == signature[signaturecnt])
869 signaturecnt++;
870 else
871 signaturecnt = 0;
872 if (4 == signaturecnt) {
873 dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
874 return i+1;
875 }
876 }
877 dprintk(3, "Mailbox signature values not found!\n");
878 return -1;
879}
880void mciWriteMemoryToGPIO(struct cx231xx *dev, u32 address, u32 value,
881 u32 *p_fw_image)
882{
883
884 u32 temp = 0;
885 int i = 0;
886
887 temp = 0x82|MCI_MEMORY_DATA_BYTE0|((value&0x000000FF)<<8);
888 temp = temp<<10;
889 *p_fw_image = temp;
890 p_fw_image++;
891 temp = temp|((0x05)<<10);
892 *p_fw_image = temp;
893 p_fw_image++;
894
895 /*write data byte 1;*/
896 temp = 0x82|MCI_MEMORY_DATA_BYTE1|(value&0x0000FF00);
897 temp = temp<<10;
898 *p_fw_image = temp;
899 p_fw_image++;
900 temp = temp|((0x05)<<10);
901 *p_fw_image = temp;
902 p_fw_image++;
903
904 /*write data byte 2;*/
905 temp = 0x82|MCI_MEMORY_DATA_BYTE2|((value&0x00FF0000)>>8);
906 temp = temp<<10;
907 *p_fw_image = temp;
908 p_fw_image++;
909 temp = temp|((0x05)<<10);
910 *p_fw_image = temp;
911 p_fw_image++;
912
913 /*write data byte 3;*/
914 temp = 0x82|MCI_MEMORY_DATA_BYTE3|((value&0xFF000000)>>16);
915 temp = temp<<10;
916 *p_fw_image = temp;
917 p_fw_image++;
918 temp = temp|((0x05)<<10);
919 *p_fw_image = temp;
920 p_fw_image++;
921
922 /* write address byte 2;*/
923 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE2 | MCI_MODE_MEMORY_WRITE |
924 ((address & 0x003F0000)>>8);
925 temp = temp<<10;
926 *p_fw_image = temp;
927 p_fw_image++;
928 temp = temp|((0x05)<<10);
929 *p_fw_image = temp;
930 p_fw_image++;
931
932 /* write address byte 1;*/
933 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE1 | (address & 0xFF00);
934 temp = temp<<10;
935 *p_fw_image = temp;
936 p_fw_image++;
937 temp = temp|((0x05)<<10);
938 *p_fw_image = temp;
939 p_fw_image++;
940
941 /* write address byte 0;*/
942 temp = 0x82|MCI_MEMORY_ADDRESS_BYTE0|((address & 0x00FF)<<8);
943 temp = temp<<10;
944 *p_fw_image = temp;
945 p_fw_image++;
946 temp = temp|((0x05)<<10);
947 *p_fw_image = temp;
948 p_fw_image++;
949
950 for (i = 0; i < 6; i++) {
951 *p_fw_image = 0xFFFFFFFF;
952 p_fw_image++;
953 }
954
955}
956
957
958static int cx231xx_load_firmware(struct cx231xx *dev)
959{
960 static const unsigned char magic[8] = {
961 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
962 };
963 const struct firmware *firmware;
964 int i, retval = 0;
965 u32 value = 0;
966 u32 gpio_output = 0;
967 /*u32 checksum = 0;*/
968 /*u32 *dataptr;*/
969 u32 transfer_size = 0;
970 u32 fw_data = 0;
971 u32 address = 0;
972 /*u32 current_fw[800];*/
973 u32 *p_current_fw, *p_fw;
974 u32 *p_fw_data;
975 int frame = 0;
976 u16 _buffer_size = 4096;
977 u8 *p_buffer;
978
979 p_current_fw = (u32 *)vmalloc(1884180*4);
980 p_fw = p_current_fw;
981 if (p_current_fw == 0) {
982 dprintk(2, "FAIL!!!\n");
983 return -1;
984 }
985
986 p_buffer = (u8 *)vmalloc(4096);
987 if (p_buffer == 0) {
988 dprintk(2, "FAIL!!!\n");
989 return -1;
990 }
991
992 dprintk(2, "%s()\n", __func__);
993
994 /* Save GPIO settings before reset of APU */
995 retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
996 retval |= mc417_memory_read(dev, 0x900C, &value);
997
998 retval = mc417_register_write(dev,
999 IVTV_REG_VPU, 0xFFFFFFED);
1000 retval |= mc417_register_write(dev,
1001 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
1002 retval |= mc417_register_write(dev,
1003 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
1004 retval |= mc417_register_write(dev,
1005 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
1006 retval |= mc417_register_write(dev,
1007 IVTV_REG_APU, 0);
1008
1009 if (retval != 0) {
1010 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1011 __func__);
1012 return -1;
1013 }
1014
1015 retval = request_firmware(&firmware, CX231xx_FIRM_IMAGE_NAME,
1016 &dev->udev->dev);
1017
1018 if (retval != 0) {
1019 printk(KERN_ERR
1020 "ERROR: Hotplug firmware request failed (%s).\n",
1021 CX231xx_FIRM_IMAGE_NAME);
1022 printk(KERN_ERR "Please fix your hotplug setup, the board will "
1023 "not work without firmware loaded!\n");
1024 return -1;
1025 }
1026
1027 if (firmware->size != CX231xx_FIRM_IMAGE_SIZE) {
1028 printk(KERN_ERR "ERROR: Firmware size mismatch "
1029 "(have %zd, expected %d)\n",
1030 firmware->size, CX231xx_FIRM_IMAGE_SIZE);
1031 release_firmware(firmware);
1032 return -1;
1033 }
1034
1035 if (0 != memcmp(firmware->data, magic, 8)) {
1036 printk(KERN_ERR
1037 "ERROR: Firmware magic mismatch, wrong file?\n");
1038 release_firmware(firmware);
1039 return -1;
1040 }
1041
1042 initGPIO(dev);
1043
1044 /* transfer to the chip */
1045 dprintk(2, "Loading firmware to GPIO...\n");
1046 p_fw_data = (u32 *)firmware->data;
1047 dprintk(2, "firmware->size=%d\n", firmware->size);
1048 for (transfer_size = 0; transfer_size < firmware->size;
1049 transfer_size += 4) {
1050 fw_data = *p_fw_data;
1051
1052 mciWriteMemoryToGPIO(dev, address, fw_data, p_current_fw);
1053 address = address + 1;
1054 p_current_fw += 20;
1055 p_fw_data += 1;
1056 }
1057
1058/*download the firmware by ep5-out*/
1059
1060 for (frame = 0; frame < (int)(CX231xx_FIRM_IMAGE_SIZE*20/_buffer_size);
1061 frame++) {
1062 for (i = 0; i < _buffer_size; i++) {
1063 *(p_buffer+i) =
1064 (u8)(*(p_fw+(frame*128*8+(i++/4))) & 0x000000FF);
1065 *(p_buffer+i) =
1066 (u8)((*(p_fw+(frame*128*8+(i++/4))) & 0x0000FF00)>>8);
1067 *(p_buffer+i) =
1068 (u8)((*(p_fw+(frame*128*8+(i++/4))) & 0x00FF0000)>>16);
1069 *(p_buffer+i) =
1070 (u8)((*(p_fw+(frame*128*8+(i/4))) & 0xFF000000)>>24);
1071 }
1072 cx231xx_ep5_bulkout(dev, p_buffer, _buffer_size);
1073 }
1074
1075 p_current_fw = p_fw;
1076 vfree(p_current_fw);
1077 p_current_fw = NULL;
1078 uninitGPIO(dev);
1079 release_firmware(firmware);
1080 dprintk(1, "Firmware upload successful.\n");
1081
1082 retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
1083 IVTV_CMD_HW_BLOCKS_RST);
1084 if (retval < 0) {
1085 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1086 __func__);
1087 return retval;
1088 }
1089 /* F/W power up disturbs the GPIOs, restore state */
1090 retval |= mc417_register_write(dev, 0x9020, gpio_output);
1091 retval |= mc417_register_write(dev, 0x900C, value);
1092
1093 retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
1094 retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
1095
1096 if (retval < 0) {
1097 printk(KERN_ERR "%s: Error with mc417_register_write\n",
1098 __func__);
1099 return retval;
1100 }
1101 return 0;
1102}
1103
1104void cx231xx_417_check_encoder(struct cx231xx *dev)
1105{
1106 u32 status, seq;
1107
1108 status = 0;
1109 seq = 0;
1110 cx231xx_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
1111 dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
1112}
1113
1114static void cx231xx_codec_settings(struct cx231xx *dev)
1115{
1116 dprintk(1, "%s()\n", __func__);
1117
1118 /* assign frame size */
1119 cx231xx_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1120 dev->ts1.height, dev->ts1.width);
1121
1122 dev->mpeg_params.width = dev->ts1.width;
1123 dev->mpeg_params.height = dev->ts1.height;
1124
1125 cx2341x_update(dev, cx231xx_mbox_func, NULL, &dev->mpeg_params);
1126
1127 cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1128 cx231xx_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1129}
1130
1131static int cx231xx_initialize_codec(struct cx231xx *dev)
1132{
1133 int version;
1134 int retval;
1135 u32 i, data[7];
1136 u32 val = 0;
1137
1138 dprintk(1, "%s()\n", __func__);
1139 cx231xx_disable656(dev);
1140 retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1141 if (retval < 0) {
1142 dprintk(2, "%s() PING OK\n", __func__);
1143 retval = cx231xx_load_firmware(dev);
1144 if (retval < 0) {
1145 printk(KERN_ERR "%s() f/w load failed\n", __func__);
1146 return retval;
1147 }
1148 retval = cx231xx_find_mailbox(dev);
1149 if (retval < 0) {
1150 printk(KERN_ERR "%s() mailbox < 0, error\n",
1151 __func__);
1152 return -1;
1153 }
1154 dev->cx23417_mailbox = retval;
1155 retval = cx231xx_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1156 if (retval < 0) {
1157 printk(KERN_ERR
1158 "ERROR: cx23417 firmware ping failed!\n");
1159 return -1;
1160 }
1161 retval = cx231xx_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1162 &version);
1163 if (retval < 0) {
1164 printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1165 "version failed!\n");
1166 return -1;
1167 }
1168 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1169 msleep(200);
1170 }
1171
1172 for (i = 0; i < 1; i++) {
1173 retval = mc417_register_read(dev, 0x20f8, &val);
1174 dprintk(3, "***before enable656() VIM Capture Lines =%d ***\n",
1175 val);
1176 if (retval < 0)
1177 return retval;
1178 }
1179
1180 cx231xx_enable656(dev);
1181 /* stop mpeg capture */
1182 cx231xx_api_cmd(dev, CX2341X_ENC_STOP_CAPTURE,
1183 3, 0, 1, 3, 4);
1184
1185 cx231xx_codec_settings(dev);
1186 msleep(60);
1187
1188/* cx231xx_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1189 CX231xx_FIELD1_SAA7115, CX231xx_FIELD2_SAA7115);
1190 cx231xx_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1191 CX231xx_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1192 0, 0);
1193*/
1194 /* Setup to capture VBI */
1195 data[0] = 0x0001BD00;
1196 data[1] = 1; /* frames per interrupt */
1197 data[2] = 4; /* total bufs */
1198 data[3] = 0x91559155; /* start codes */
1199 data[4] = 0x206080C0; /* stop codes */
1200 data[5] = 6; /* lines */
1201 data[6] = 64; /* BPL */
1202/*
1203 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1204 data[2], data[3], data[4], data[5], data[6]);
1205
1206 for (i = 2; i <= 24; i++) {
1207 int valid;
1208
1209 valid = ((i >= 19) && (i <= 21));
1210 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1211 valid, 0 , 0, 0);
1212 cx231xx_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1213 i | 0x80000000, valid, 0, 0, 0);
1214 }
1215*/
1216/* cx231xx_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX231xx_UNMUTE);
1217 msleep(60);
1218*/
1219 /* initialize the video input */
1220 retval = cx231xx_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1221 if (retval < 0)
1222 return retval;
1223 msleep(60);
1224
1225 /* Enable VIP style pixel invalidation so we work with scaled mode */
1226 mc417_memory_write(dev, 2120, 0x00000080);
1227
1228 /* start capturing to the host interface */
1229 retval = cx231xx_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1230 CX231xx_MPEG_CAPTURE, CX231xx_RAW_BITS_NONE);
1231 if (retval < 0)
1232 return retval;
1233 msleep(10);
1234
1235 for (i = 0; i < 1; i++) {
1236 mc417_register_read(dev, 0x20f8, &val);
1237 dprintk(3, "***VIM Capture Lines =%d ***\n", val);
1238 }
1239
1240 return 0;
1241}
1242
1243/* ------------------------------------------------------------------ */
1244
1245static int bb_buf_setup(struct videobuf_queue *q,
1246 unsigned int *count, unsigned int *size)
1247{
1248 struct cx231xx_fh *fh = q->priv_data;
1249
1250 fh->dev->ts1.ts_packet_size = mpeglinesize;
1251 fh->dev->ts1.ts_packet_count = mpeglines;
1252
1253 *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1254 *count = mpegbufs;
1255
1256 return 0;
1257}
1258static void free_buffer(struct videobuf_queue *vq, struct cx231xx_buffer *buf)
1259{
1260 struct cx231xx_fh *fh = vq->priv_data;
1261 struct cx231xx *dev = fh->dev;
1262 unsigned long flags = 0;
1263
1264 if (in_interrupt())
1265 BUG();
1266
1267 spin_lock_irqsave(&dev->video_mode.slock, flags);
1268 if (dev->USE_ISO) {
1269 if (dev->video_mode.isoc_ctl.buf == buf)
1270 dev->video_mode.isoc_ctl.buf = NULL;
1271 } else {
1272 if (dev->video_mode.bulk_ctl.buf == buf)
1273 dev->video_mode.bulk_ctl.buf = NULL;
1274 }
1275 spin_unlock_irqrestore(&dev->video_mode.slock, flags);
1276 videobuf_waiton(vq, &buf->vb, 0, 0);
1277 videobuf_vmalloc_free(&buf->vb);
1278 buf->vb.state = VIDEOBUF_NEEDS_INIT;
1279}
1280
1281void buffer_copy(struct cx231xx *dev, char *data, int len, struct urb *urb,
1282 struct cx231xx_dmaqueue *dma_q)
1283{
1284 void *vbuf;
1285 struct cx231xx_buffer *buf;
1286 u32 tail_data = 0;
1287 char *p_data;
1288
1289 if (dma_q->mpeg_buffer_done == 0) {
1290 if (list_empty(&dma_q->active))
1291 return;
1292
1293 buf = list_entry(dma_q->active.next,
1294 struct cx231xx_buffer, vb.queue);
1295 dev->video_mode.isoc_ctl.buf = buf;
1296 dma_q->mpeg_buffer_done = 1;
1297 }
1298 /* Fill buffer */
1299 buf = dev->video_mode.isoc_ctl.buf;
1300 vbuf = videobuf_to_vmalloc(&buf->vb);
1301
1302 if ((dma_q->mpeg_buffer_completed+len) <
1303 mpeglines*mpeglinesize) {
1304 if (dma_q->add_ps_package_head ==
1305 CX231XX_NEED_ADD_PS_PACKAGE_HEAD) {
1306 memcpy(vbuf+dma_q->mpeg_buffer_completed,
1307 dma_q->ps_head, 3);
1308 dma_q->mpeg_buffer_completed =
1309 dma_q->mpeg_buffer_completed + 3;
1310 dma_q->add_ps_package_head =
1311 CX231XX_NONEED_PS_PACKAGE_HEAD;
1312 }
1313 memcpy(vbuf+dma_q->mpeg_buffer_completed, data, len);
1314 dma_q->mpeg_buffer_completed =
1315 dma_q->mpeg_buffer_completed + len;
1316 } else {
1317 dma_q->mpeg_buffer_done = 0;
1318
1319 tail_data =
1320 mpeglines*mpeglinesize - dma_q->mpeg_buffer_completed;
1321 memcpy(vbuf+dma_q->mpeg_buffer_completed,
1322 data, tail_data);
1323
1324 buf->vb.state = VIDEOBUF_DONE;
1325 buf->vb.field_count++;
1326 do_gettimeofday(&buf->vb.ts);
1327 list_del(&buf->vb.queue);
1328 wake_up(&buf->vb.done);
1329 dma_q->mpeg_buffer_completed = 0;
1330
1331 if (len - tail_data > 0) {
1332 p_data = data + tail_data;
1333 dma_q->left_data_count = len - tail_data;
1334 memcpy(dma_q->p_left_data,
1335 p_data, len - tail_data);
1336 }
1337
1338 }
1339
1340 return;
1341}
1342
1343void buffer_filled(char *data, int len, struct urb *urb,
1344 struct cx231xx_dmaqueue *dma_q)
1345{
1346 void *vbuf;
1347 struct cx231xx_buffer *buf;
1348
1349 if (list_empty(&dma_q->active))
1350 return;
1351
1352
1353 buf = list_entry(dma_q->active.next,
1354 struct cx231xx_buffer, vb.queue);
1355
1356
1357 /* Fill buffer */
1358 vbuf = videobuf_to_vmalloc(&buf->vb);
1359 memcpy(vbuf, data, len);
1360 buf->vb.state = VIDEOBUF_DONE;
1361 buf->vb.field_count++;
1362 do_gettimeofday(&buf->vb.ts);
1363 list_del(&buf->vb.queue);
1364 wake_up(&buf->vb.done);
1365
1366 return;
1367}
1368static inline int cx231xx_isoc_copy(struct cx231xx *dev, struct urb *urb)
1369{
1370 struct cx231xx_dmaqueue *dma_q = urb->context;
1371 unsigned char *p_buffer;
1372 u32 buffer_size = 0;
1373 u32 i = 0;
1374
1375 for (i = 0; i < urb->number_of_packets; i++) {
1376 if (dma_q->left_data_count > 0) {
1377 buffer_copy(dev, dma_q->p_left_data,
1378 dma_q->left_data_count, urb, dma_q);
1379 dma_q->mpeg_buffer_completed = dma_q->left_data_count;
1380 dma_q->left_data_count = 0;
1381 }
1382
1383 p_buffer = urb->transfer_buffer +
1384 urb->iso_frame_desc[i].offset;
1385 buffer_size = urb->iso_frame_desc[i].actual_length;
1386
1387 if (buffer_size > 0)
1388 buffer_copy(dev, p_buffer, buffer_size, urb, dma_q);
1389 }
1390
1391 return 0;
1392}
1393static inline int cx231xx_bulk_copy(struct cx231xx *dev, struct urb *urb)
1394{
1395
1396 /*char *outp;*/
1397 /*struct cx231xx_buffer *buf;*/
1398 struct cx231xx_dmaqueue *dma_q = urb->context;
1399 unsigned char *p_buffer, *buffer;
1400 u32 buffer_size = 0;
1401
1402 p_buffer = urb->transfer_buffer;
1403 buffer_size = urb->actual_length;
1404
1405 buffer = kmalloc(buffer_size, GFP_ATOMIC);
1406
1407 memcpy(buffer, dma_q->ps_head, 3);
1408 memcpy(buffer+3, p_buffer, buffer_size-3);
1409 memcpy(dma_q->ps_head, p_buffer+buffer_size-3, 3);
1410
1411 p_buffer = buffer;
1412 buffer_filled(p_buffer, buffer_size, urb, dma_q);
1413
1414 kfree(buffer);
1415 return 0;
1416}
1417
1418static int bb_buf_prepare(struct videobuf_queue *q,
1419 struct videobuf_buffer *vb, enum v4l2_field field)
1420{
1421 struct cx231xx_fh *fh = q->priv_data;
1422 struct cx231xx_buffer *buf =
1423 container_of(vb, struct cx231xx_buffer, vb);
1424 struct cx231xx *dev = fh->dev;
1425 int rc = 0, urb_init = 0;
1426 int size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1427
1428 dma_qq = &dev->video_mode.vidq;
1429
1430 if (0 != buf->vb.baddr && buf->vb.bsize < size)
1431 return -EINVAL;
1432 buf->vb.width = fh->dev->ts1.ts_packet_size;
1433 buf->vb.height = fh->dev->ts1.ts_packet_count;
1434 buf->vb.size = size;
1435 buf->vb.field = field;
1436
1437 if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
1438 rc = videobuf_iolock(q, &buf->vb, NULL);
1439 if (rc < 0)
1440 goto fail;
1441 }
1442
1443 if (dev->USE_ISO) {
1444 if (!dev->video_mode.isoc_ctl.num_bufs)
1445 urb_init = 1;
1446 } else {
1447 if (!dev->video_mode.bulk_ctl.num_bufs)
1448 urb_init = 1;
1449 }
1450 /*cx231xx_info("urb_init=%d dev->video_mode.max_pkt_size=%d\n",
1451 urb_init, dev->video_mode.max_pkt_size);*/
1452 dev->mode_tv = 1;
1453
1454 if (urb_init) {
1455 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1456 rc = cx231xx_unmute_audio(dev);
1457 if (dev->USE_ISO) {
1458 cx231xx_set_alt_setting(dev, INDEX_TS1, 4);
1459 rc = cx231xx_init_isoc(dev, mpeglines,
1460 mpegbufs,
1461 dev->ts1_mode.max_pkt_size,
1462 cx231xx_isoc_copy);
1463 } else {
1464 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1465 rc = cx231xx_init_bulk(dev, mpeglines,
1466 mpegbufs,
1467 dev->ts1_mode.max_pkt_size,
1468 cx231xx_bulk_copy);
1469 }
1470 if (rc < 0)
1471 goto fail;
1472 }
1473
1474 buf->vb.state = VIDEOBUF_PREPARED;
1475 return 0;
1476
1477fail:
1478 free_buffer(q, buf);
1479 return rc;
1480}
1481
1482static void bb_buf_queue(struct videobuf_queue *q,
1483 struct videobuf_buffer *vb)
1484{
1485 struct cx231xx_fh *fh = q->priv_data;
1486
1487 struct cx231xx_buffer *buf =
1488 container_of(vb, struct cx231xx_buffer, vb);
1489 struct cx231xx *dev = fh->dev;
1490 struct cx231xx_dmaqueue *vidq = &dev->video_mode.vidq;
1491
1492 buf->vb.state = VIDEOBUF_QUEUED;
1493 list_add_tail(&buf->vb.queue, &vidq->active);
1494
1495}
1496
1497static void bb_buf_release(struct videobuf_queue *q,
1498 struct videobuf_buffer *vb)
1499{
1500 struct cx231xx_buffer *buf =
1501 container_of(vb, struct cx231xx_buffer, vb);
1502 /*struct cx231xx_fh *fh = q->priv_data;*/
1503 /*struct cx231xx *dev = (struct cx231xx *)fh->dev;*/
1504
1505 free_buffer(q, buf);
1506}
1507
1508static struct videobuf_queue_ops cx231xx_qops = {
1509 .buf_setup = bb_buf_setup,
1510 .buf_prepare = bb_buf_prepare,
1511 .buf_queue = bb_buf_queue,
1512 .buf_release = bb_buf_release,
1513};
1514
1515/* ------------------------------------------------------------------ */
1516
1517static const u32 *ctrl_classes[] = {
1518 cx2341x_mpeg_ctrls,
1519 NULL
1520};
1521
1522static int cx231xx_queryctrl(struct cx231xx *dev,
1523 struct v4l2_queryctrl *qctrl)
1524{
1525 qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1526 if (qctrl->id == 0)
1527 return -EINVAL;
1528
1529 /* MPEG V4L2 controls */
1530 if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1531 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1532
1533 return 0;
1534}
1535
1536static int cx231xx_querymenu(struct cx231xx *dev,
1537 struct v4l2_querymenu *qmenu)
1538{
1539 struct v4l2_queryctrl qctrl;
1540
1541 qctrl.id = qmenu->id;
1542 cx231xx_queryctrl(dev, &qctrl);
1543 return v4l2_ctrl_query_menu(qmenu, &qctrl,
1544 cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
1545}
1546
1547static int vidioc_g_std(struct file *file, void *fh0, v4l2_std_id *norm)
1548{
1549 struct cx231xx_fh *fh = file->private_data;
1550 struct cx231xx *dev = fh->dev;
1551
1552 *norm = dev->encodernorm.id;
1553 return 0;
1554}
1555static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
1556{
1557 struct cx231xx_fh *fh = file->private_data;
1558 struct cx231xx *dev = fh->dev;
1559 unsigned int i;
1560
1561 for (i = 0; i < ARRAY_SIZE(cx231xx_tvnorms); i++)
1562 if (*id & cx231xx_tvnorms[i].id)
1563 break;
1564 if (i == ARRAY_SIZE(cx231xx_tvnorms))
1565 return -EINVAL;
1566 dev->encodernorm = cx231xx_tvnorms[i];
1567
1568 if (dev->encodernorm.id & 0xb000) {
1569 dprintk(3, "encodernorm set to NTSC\n");
1570 dev->norm = V4L2_STD_NTSC;
1571 dev->ts1.height = 480;
1572 dev->mpeg_params.is_50hz = 0;
1573 } else {
1574 dprintk(3, "encodernorm set to PAL\n");
1575 dev->norm = V4L2_STD_PAL_B;
1576 dev->ts1.height = 576;
1577 dev->mpeg_params.is_50hz = 1;
1578 }
1579 call_all(dev, core, s_std, dev->norm);
1580 /* do mode control overrides */
1581 cx231xx_do_mode_ctrl_overrides(dev);
1582
1583 dprintk(3, "exit vidioc_s_std() i=0x%x\n", i);
1584 return 0;
1585}
1586static int vidioc_g_audio(struct file *file, void *fh,
1587 struct v4l2_audio *a)
1588{
1589 struct v4l2_audio *vin = a;
1590
1591 int ret = -EINVAL;
1592 if (vin->index > 0)
1593 return ret;
1594 strncpy(vin->name, "VideoGrabber Audio", 14);
1595 vin->capability = V4L2_AUDCAP_STEREO;
1596return 0;
1597}
1598static int vidioc_enumaudio(struct file *file, void *fh,
1599 struct v4l2_audio *a)
1600{
1601 struct v4l2_audio *vin = a;
1602
1603 int ret = -EINVAL;
1604
1605 if (vin->index > 0)
1606 return ret;
1607 strncpy(vin->name, "VideoGrabber Audio", 14);
1608 vin->capability = V4L2_AUDCAP_STEREO;
1609
1610
1611return 0;
1612}
1613static const char *iname[] = {
1614 [CX231XX_VMUX_COMPOSITE1] = "Composite1",
1615 [CX231XX_VMUX_SVIDEO] = "S-Video",
1616 [CX231XX_VMUX_TELEVISION] = "Television",
1617 [CX231XX_VMUX_CABLE] = "Cable TV",
1618 [CX231XX_VMUX_DVB] = "DVB",
1619 [CX231XX_VMUX_DEBUG] = "for debug only",
1620};
1621static int vidioc_enum_input(struct file *file, void *priv,
1622 struct v4l2_input *i)
1623{
1624 struct cx231xx_fh *fh = file->private_data;
1625 struct cx231xx *dev = fh->dev;
1626 struct cx231xx_input *input;
1627 int n;
1628 dprintk(3, "enter vidioc_enum_input()i->index=%d\n", i->index);
1629
1630 if (i->index >= 4)
1631 return -EINVAL;
1632
1633
1634 input = &cx231xx_boards[dev->model].input[i->index];
1635
1636 if (input->type == 0)
1637 return -EINVAL;
1638
1639 /* FIXME
1640 * strcpy(i->name, input->name); */
1641
1642 n = i->index;
1643 strcpy(i->name, iname[INPUT(n)->type]);
1644
1645 if (input->type == CX231XX_VMUX_TELEVISION ||
1646 input->type == CX231XX_VMUX_CABLE)
1647 i->type = V4L2_INPUT_TYPE_TUNER;
1648 else
1649 i->type = V4L2_INPUT_TYPE_CAMERA;
1650
1651
1652 return 0;
1653}
1654
1655static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1656{
1657 *i = 0;
1658 return 0;
1659}
1660
1661static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1662{
1663 struct cx231xx_fh *fh = file->private_data;
1664 struct cx231xx *dev = fh->dev;
1665
1666 dprintk(3, "enter vidioc_s_input() i=%d\n", i);
1667
1668 mutex_lock(&dev->lock);
1669
1670 video_mux(dev, i);
1671
1672 mutex_unlock(&dev->lock);
1673
1674 if (i >= 4)
1675 return -EINVAL;
1676 dev->input = i;
1677 dprintk(3, "exit vidioc_s_input()\n");
1678 return 0;
1679}
1680
1681static int vidioc_g_tuner(struct file *file, void *priv,
1682 struct v4l2_tuner *t)
1683{
1684 return 0;
1685}
1686
1687static int vidioc_s_tuner(struct file *file, void *priv,
1688 struct v4l2_tuner *t)
1689{
1690 return 0;
1691}
1692
1693static int vidioc_g_frequency(struct file *file, void *priv,
1694 struct v4l2_frequency *f)
1695{
1696 return 0;
1697}
1698
1699static int vidioc_s_frequency(struct file *file, void *priv,
1700 struct v4l2_frequency *f)
1701{
1702
1703
1704 return 0;
1705}
1706
1707static int vidioc_s_ctrl(struct file *file, void *priv,
1708 struct v4l2_control *ctl)
1709{
1710 struct cx231xx_fh *fh = file->private_data;
1711 struct cx231xx *dev = fh->dev;
1712 dprintk(3, "enter vidioc_s_ctrl()\n");
1713 /* Update the A/V core */
1714 call_all(dev, core, s_ctrl, ctl);
1715 dprintk(3, "exit vidioc_s_ctrl()\n");
1716 return 0;
1717}
1718static struct v4l2_capability pvr_capability = {
1719 .driver = "cx231xx",
1720 .card = "VideoGrabber",
1721 .bus_info = "usb",
1722 .version = 1,
1723 .capabilities = (V4L2_CAP_VIDEO_CAPTURE |
1724 V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_RADIO |
1725 V4L2_CAP_STREAMING | V4L2_CAP_READWRITE),
1726 .reserved = {0, 0, 0, 0}
1727};
1728static int vidioc_querycap(struct file *file, void *priv,
1729 struct v4l2_capability *cap)
1730{
1731
1732
1733
1734 memcpy(cap, &pvr_capability, sizeof(struct v4l2_capability));
1735 return 0;
1736}
1737
1738static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
1739 struct v4l2_fmtdesc *f)
1740{
1741
1742 if (f->index != 0)
1743 return -EINVAL;
1744
1745 strlcpy(f->description, "MPEG", sizeof(f->description));
1746 f->pixelformat = V4L2_PIX_FMT_MPEG;
1747
1748 return 0;
1749}
1750
1751static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1752 struct v4l2_format *f)
1753{
1754 struct cx231xx_fh *fh = file->private_data;
1755 struct cx231xx *dev = fh->dev;
1756 dprintk(3, "enter vidioc_g_fmt_vid_cap()\n");
1757 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1758 f->fmt.pix.bytesperline = 0;
1759 f->fmt.pix.sizeimage =
1760 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1761 f->fmt.pix.colorspace = 0;
1762 f->fmt.pix.width = dev->ts1.width;
1763 f->fmt.pix.height = dev->ts1.height;
1764 f->fmt.pix.field = fh->vidq.field;
1765 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1766 dev->ts1.width, dev->ts1.height, fh->vidq.field);
1767 dprintk(3, "exit vidioc_g_fmt_vid_cap()\n");
1768 return 0;
1769}
1770
1771static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1772 struct v4l2_format *f)
1773{
1774 struct cx231xx_fh *fh = file->private_data;
1775 struct cx231xx *dev = fh->dev;
1776 dprintk(3, "enter vidioc_try_fmt_vid_cap()\n");
1777 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1778 f->fmt.pix.bytesperline = 0;
1779 f->fmt.pix.sizeimage =
1780 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1781 f->fmt.pix.colorspace = 0;
1782 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1783 dev->ts1.width, dev->ts1.height, fh->vidq.field);
1784 dprintk(3, "exit vidioc_try_fmt_vid_cap()\n");
1785 return 0;
1786}
1787
1788static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1789 struct v4l2_format *f)
1790{
1791
1792 return 0;
1793}
1794
1795static int vidioc_reqbufs(struct file *file, void *priv,
1796 struct v4l2_requestbuffers *p)
1797{
1798 struct cx231xx_fh *fh = file->private_data;
1799
1800 return videobuf_reqbufs(&fh->vidq, p);
1801}
1802
1803static int vidioc_querybuf(struct file *file, void *priv,
1804 struct v4l2_buffer *p)
1805{
1806 struct cx231xx_fh *fh = file->private_data;
1807
1808 return videobuf_querybuf(&fh->vidq, p);
1809}
1810
1811static int vidioc_qbuf(struct file *file, void *priv,
1812 struct v4l2_buffer *p)
1813{
1814 struct cx231xx_fh *fh = file->private_data;
1815
1816 return videobuf_qbuf(&fh->vidq, p);
1817}
1818
1819static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1820{
1821 struct cx231xx_fh *fh = priv;
1822
1823 return videobuf_dqbuf(&fh->vidq, b, file->f_flags & O_NONBLOCK);
1824}
1825
1826
1827static int vidioc_streamon(struct file *file, void *priv,
1828 enum v4l2_buf_type i)
1829{
1830 struct cx231xx_fh *fh = file->private_data;
1831
1832 struct cx231xx *dev = fh->dev;
1833 int rc = 0;
1834 dprintk(3, "enter vidioc_streamon()\n");
1835 cx231xx_set_alt_setting(dev, INDEX_TS1, 0);
1836 rc = cx231xx_set_mode(dev, CX231XX_DIGITAL_MODE);
1837 if (dev->USE_ISO)
1838 rc = cx231xx_init_isoc(dev, CX231XX_NUM_PACKETS,
1839 CX231XX_NUM_BUFS,
1840 dev->video_mode.max_pkt_size,
1841 cx231xx_isoc_copy);
1842 else {
1843 rc = cx231xx_init_bulk(dev, 320,
1844 5,
1845 dev->ts1_mode.max_pkt_size,
1846 cx231xx_bulk_copy);
1847 }
1848 dprintk(3, "exit vidioc_streamon()\n");
1849 return videobuf_streamon(&fh->vidq);
1850}
1851
1852static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1853{
1854 struct cx231xx_fh *fh = file->private_data;
1855
1856 return videobuf_streamoff(&fh->vidq);
1857}
1858
1859static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1860 struct v4l2_ext_controls *f)
1861{
1862 struct cx231xx_fh *fh = priv;
1863 struct cx231xx *dev = fh->dev;
1864 dprintk(3, "enter vidioc_g_ext_ctrls()\n");
1865 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1866 return -EINVAL;
1867 dprintk(3, "exit vidioc_g_ext_ctrls()\n");
1868 return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1869}
1870
1871static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1872 struct v4l2_ext_controls *f)
1873{
1874 struct cx231xx_fh *fh = priv;
1875 struct cx231xx *dev = fh->dev;
1876 struct cx2341x_mpeg_params p;
1877 int err;
1878 dprintk(3, "enter vidioc_s_ext_ctrls()\n");
1879 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1880 return -EINVAL;
1881
1882 p = dev->mpeg_params;
1883 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1884 if (err == 0) {
1885 err = cx2341x_update(dev, cx231xx_mbox_func,
1886 &dev->mpeg_params, &p);
1887 dev->mpeg_params = p;
1888 }
1889
1890 return err;
1891
1892
1893return 0;
1894}
1895
1896static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1897 struct v4l2_ext_controls *f)
1898{
1899 struct cx231xx_fh *fh = priv;
1900 struct cx231xx *dev = fh->dev;
1901 struct cx2341x_mpeg_params p;
1902 int err;
1903 dprintk(3, "enter vidioc_try_ext_ctrls()\n");
1904 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1905 return -EINVAL;
1906
1907 p = dev->mpeg_params;
1908 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1909 dprintk(3, "exit vidioc_try_ext_ctrls() err=%d\n", err);
1910 return err;
1911}
1912
1913static int vidioc_log_status(struct file *file, void *priv)
1914{
1915 struct cx231xx_fh *fh = priv;
1916 struct cx231xx *dev = fh->dev;
1917 char name[32 + 2];
1918
1919 snprintf(name, sizeof(name), "%s/2", dev->name);
1920 dprintk(3,
1921 "%s/2: ============ START LOG STATUS ============\n",
1922 dev->name);
1923 call_all(dev, core, log_status);
1924 cx2341x_log_status(&dev->mpeg_params, name);
1925 dprintk(3,
1926 "%s/2: ============= END LOG STATUS =============\n",
1927 dev->name);
1928 return 0;
1929}
1930
1931static int vidioc_querymenu(struct file *file, void *priv,
1932 struct v4l2_querymenu *a)
1933{
1934 struct cx231xx_fh *fh = priv;
1935 struct cx231xx *dev = fh->dev;
1936 dprintk(3, "enter vidioc_querymenu()\n");
1937 dprintk(3, "exit vidioc_querymenu()\n");
1938 return cx231xx_querymenu(dev, a);
1939}
1940
1941static int vidioc_queryctrl(struct file *file, void *priv,
1942 struct v4l2_queryctrl *c)
1943{
1944 struct cx231xx_fh *fh = priv;
1945 struct cx231xx *dev = fh->dev;
1946 dprintk(3, "enter vidioc_queryctrl()\n");
1947 dprintk(3, "exit vidioc_queryctrl()\n");
1948 return cx231xx_queryctrl(dev, c);
1949}
1950
1951static int mpeg_open(struct file *file)
1952{
1953 int minor = video_devdata(file)->minor;
1954 struct cx231xx *h, *dev = NULL;
1955 /*struct list_head *list;*/
1956 struct cx231xx_fh *fh;
1957 /*u32 value = 0;*/
1958
1959 dprintk(2, "%s()\n", __func__);
1960
1961 list_for_each_entry(h, &cx231xx_devlist, devlist) {
1962 if (h->v4l_device->minor == minor)
1963 dev = h;
1964 }
1965
1966 if (dev == NULL) {
1967 unlock_kernel();
1968 return -ENODEV;
1969 }
1970 mutex_lock(&dev->lock);
1971
1972 /* allocate + initialize per filehandle data */
1973 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1974 if (NULL == fh) {
1975 mutex_unlock(&dev->lock);
1976 return -ENOMEM;
1977 }
1978
1979 file->private_data = fh;
1980 fh->dev = dev;
1981
1982
1983 videobuf_queue_vmalloc_init(&fh->vidq, &cx231xx_qops,
1984 NULL, &dev->video_mode.slock,
1985 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_INTERLACED,
1986 sizeof(struct cx231xx_buffer), fh, NULL);
1987/*
1988 videobuf_queue_sg_init(&fh->vidq, &cx231xx_qops,
1989 &dev->udev->dev, &dev->ts1.slock,
1990 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1991 V4L2_FIELD_INTERLACED,
1992 sizeof(struct cx231xx_buffer),
1993 fh, NULL);
1994*/
1995
1996
1997 cx231xx_set_alt_setting(dev, INDEX_VANC, 1);
1998 cx231xx_set_gpio_value(dev, 2, 0);
1999
2000 cx231xx_initialize_codec(dev);
2001
2002 mutex_unlock(&dev->lock);
2003 cx231xx_start_TS1(dev);
2004
2005 return 0;
2006}
2007
2008static int mpeg_release(struct file *file)
2009{
2010 struct cx231xx_fh *fh = file->private_data;
2011 struct cx231xx *dev = fh->dev;
2012
2013 dprintk(3, "mpeg_release()! dev=0x%x\n", dev);
2014
2015 if (!dev) {
2016 dprintk(3, "abort!!!\n");
2017 return 0;
2018 }
2019
2020 mutex_lock(&dev->lock);
2021
2022 cx231xx_stop_TS1(dev);
2023
2024 /* do this before setting alternate! */
2025 if (dev->USE_ISO)
2026 cx231xx_uninit_isoc(dev);
2027 else
2028 cx231xx_uninit_bulk(dev);
2029 cx231xx_set_mode(dev, CX231XX_SUSPEND);
2030
2031 cx231xx_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
2032 CX231xx_END_NOW, CX231xx_MPEG_CAPTURE,
2033 CX231xx_RAW_BITS_NONE);
2034
2035 /* FIXME: Review this crap */
2036 /* Shut device down on last close */
2037 if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
2038 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
2039 /* stop mpeg capture */
2040
2041 msleep(500);
2042 cx231xx_417_check_encoder(dev);
2043
2044 }
2045 }
2046
2047 if (fh->vidq.streaming)
2048 videobuf_streamoff(&fh->vidq);
2049 if (fh->vidq.reading)
2050 videobuf_read_stop(&fh->vidq);
2051
2052 videobuf_mmap_free(&fh->vidq);
2053 file->private_data = NULL;
2054 kfree(fh);
2055 mutex_unlock(&dev->lock);
2056 return 0;
2057}
2058
2059static ssize_t mpeg_read(struct file *file, char __user *data,
2060 size_t count, loff_t *ppos)
2061{
2062 struct cx231xx_fh *fh = file->private_data;
2063 struct cx231xx *dev = fh->dev;
2064
2065
2066 /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
2067 /* Start mpeg encoder on first read. */
2068 if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
2069 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
2070 if (cx231xx_initialize_codec(dev) < 0)
2071 return -EINVAL;
2072 }
2073 }
2074
2075 return videobuf_read_stream(&fh->vidq, data, count, ppos, 0,
2076 file->f_flags & O_NONBLOCK);
2077}
2078
2079static unsigned int mpeg_poll(struct file *file,
2080 struct poll_table_struct *wait)
2081{
2082 struct cx231xx_fh *fh = file->private_data;
2083 /*struct cx231xx *dev = fh->dev;*/
2084
2085 /*dprintk(2, "%s\n", __func__);*/
2086
2087 return videobuf_poll_stream(file, &fh->vidq, wait);
2088}
2089
2090static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
2091{
2092 struct cx231xx_fh *fh = file->private_data;
2093 struct cx231xx *dev = fh->dev;
2094
2095 dprintk(2, "%s()\n", __func__);
2096
2097 return videobuf_mmap_mapper(&fh->vidq, vma);
2098}
2099
2100static struct v4l2_file_operations mpeg_fops = {
2101 .owner = THIS_MODULE,
2102 .open = mpeg_open,
2103 .release = mpeg_release,
2104 .read = mpeg_read,
2105 .poll = mpeg_poll,
2106 .mmap = mpeg_mmap,
2107 .ioctl = video_ioctl2,
2108};
2109
2110static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
2111 .vidioc_s_std = vidioc_s_std,
2112 .vidioc_g_std = vidioc_g_std,
2113 .vidioc_enum_input = vidioc_enum_input,
2114 .vidioc_enumaudio = vidioc_enumaudio,
2115 .vidioc_g_audio = vidioc_g_audio,
2116 .vidioc_g_input = vidioc_g_input,
2117 .vidioc_s_input = vidioc_s_input,
2118 .vidioc_g_tuner = vidioc_g_tuner,
2119 .vidioc_s_tuner = vidioc_s_tuner,
2120 .vidioc_g_frequency = vidioc_g_frequency,
2121 .vidioc_s_frequency = vidioc_s_frequency,
2122 .vidioc_s_ctrl = vidioc_s_ctrl,
2123 .vidioc_querycap = vidioc_querycap,
2124 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
2125 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
2126 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
2127 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
2128 .vidioc_reqbufs = vidioc_reqbufs,
2129 .vidioc_querybuf = vidioc_querybuf,
2130 .vidioc_qbuf = vidioc_qbuf,
2131 .vidioc_dqbuf = vidioc_dqbuf,
2132 .vidioc_streamon = vidioc_streamon,
2133 .vidioc_streamoff = vidioc_streamoff,
2134 .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
2135 .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls,
2136 .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls,
2137 .vidioc_log_status = vidioc_log_status,
2138 .vidioc_querymenu = vidioc_querymenu,
2139 .vidioc_queryctrl = vidioc_queryctrl,
2140/* .vidioc_g_chip_ident = cx231xx_g_chip_ident,*/
2141#ifdef CONFIG_VIDEO_ADV_DEBUG
2142/* .vidioc_g_register = cx231xx_g_register,*/
2143/* .vidioc_s_register = cx231xx_s_register,*/
2144#endif
2145};
2146
2147static struct video_device cx231xx_mpeg_template = {
2148 .name = "cx231xx",
2149 .fops = &mpeg_fops,
2150 .ioctl_ops = &mpeg_ioctl_ops,
2151 .minor = -1,
2152 .tvnorms = CX231xx_NORMS,
2153 .current_norm = V4L2_STD_NTSC_M,
2154};
2155
2156void cx231xx_417_unregister(struct cx231xx *dev)
2157{
2158 dprintk(1, "%s()\n", __func__);
2159 dprintk(3, "%s()\n", __func__);
2160
2161 if (dev->v4l_device) {
2162 if (-1 != dev->v4l_device->minor)
2163 video_unregister_device(dev->v4l_device);
2164 else
2165 video_device_release(dev->v4l_device);
2166 dev->v4l_device = NULL;
2167 }
2168}
2169
2170static struct video_device *cx231xx_video_dev_alloc(
2171 struct cx231xx *dev,
2172 struct usb_device *usbdev,
2173 struct video_device *template,
2174 char *type)
2175{
2176 struct video_device *vfd;
2177
2178 dprintk(1, "%s()\n", __func__);
2179 vfd = video_device_alloc();
2180 if (NULL == vfd)
2181 return NULL;
2182 *vfd = *template;
2183 vfd->minor = -1;
2184 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
2185 type, cx231xx_boards[dev->model].name);
2186
2187 vfd->v4l2_dev = &dev->v4l2_dev;
2188 vfd->release = video_device_release;
2189
2190 return vfd;
2191
2192}
2193
2194int cx231xx_417_register(struct cx231xx *dev)
2195{
2196 /* FIXME: Port1 hardcoded here */
2197 int err = -ENODEV;
2198 struct cx231xx_tsport *tsport = &dev->ts1;
2199
2200 dprintk(1, "%s()\n", __func__);
2201
2202 /* Set default TV standard */
2203 dev->encodernorm = cx231xx_tvnorms[0];
2204
2205 if (dev->encodernorm.id & V4L2_STD_525_60)
2206 tsport->height = 480;
2207 else
2208 tsport->height = 576;
2209
2210 tsport->width = 720;
2211 cx2341x_fill_defaults(&dev->mpeg_params);
2212 dev->norm = V4L2_STD_NTSC;
2213
2214 dev->mpeg_params.port = CX2341X_PORT_SERIAL;
2215
2216 /* Allocate and initialize V4L video device */
2217 dev->v4l_device = cx231xx_video_dev_alloc(dev,
2218 dev->udev, &cx231xx_mpeg_template, "mpeg");
2219 err = video_register_device(dev->v4l_device,
2220 VFL_TYPE_GRABBER, -1);
2221 if (err < 0) {
2222 dprintk(3, "%s: can't register mpeg device\n", dev->name);
2223 return err;
2224 }
2225
2226 dprintk(3, "%s: registered device video%d [mpeg]\n",
2227 dev->name, dev->v4l_device->num);
2228
2229 return 0;
2230}
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-04 07:14:26 -0500