diff options
Diffstat (limited to 'drivers/media/dvb/frontends/stv0367_regs.h')
| -rw-r--r-- | drivers/media/dvb/frontends/stv0367_regs.h | 3614 |
1 files changed, 0 insertions, 3614 deletions
diff --git a/drivers/media/dvb/frontends/stv0367_regs.h b/drivers/media/dvb/frontends/stv0367_regs.h deleted file mode 100644 index a96fbdc7e25e..000000000000 --- a/drivers/media/dvb/frontends/stv0367_regs.h +++ /dev/null | |||
| @@ -1,3614 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * stv0367_regs.h | ||
| 3 | * | ||
| 4 | * Driver for ST STV0367 DVB-T & DVB-C demodulator IC. | ||
| 5 | * | ||
| 6 | * Copyright (C) ST Microelectronics. | ||
| 7 | * Copyright (C) 2010,2011 NetUP Inc. | ||
| 8 | * Copyright (C) 2010,2011 Igor M. Liplianin <liplianin@netup.ru> | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | * | ||
| 15 | * This program is distributed in the hope that it will be useful, | ||
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 18 | * | ||
| 19 | * GNU General Public License for more details. | ||
| 20 | * | ||
| 21 | * You should have received a copy of the GNU General Public License | ||
| 22 | * along with this program; if not, write to the Free Software | ||
| 23 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
| 24 | */ | ||
| 25 | |||
| 26 | #ifndef STV0367_REGS_H | ||
| 27 | #define STV0367_REGS_H | ||
| 28 | |||
| 29 | /* ID */ | ||
| 30 | #define R367TER_ID 0xf000 | ||
| 31 | #define F367TER_IDENTIFICATIONREG 0xf00000ff | ||
| 32 | |||
| 33 | /* I2CRPT */ | ||
| 34 | #define R367TER_I2CRPT 0xf001 | ||
| 35 | #define F367TER_I2CT_ON 0xf0010080 | ||
| 36 | #define F367TER_ENARPT_LEVEL 0xf0010070 | ||
| 37 | #define F367TER_SCLT_DELAY 0xf0010008 | ||
| 38 | #define F367TER_SCLT_NOD 0xf0010004 | ||
| 39 | #define F367TER_STOP_ENABLE 0xf0010002 | ||
| 40 | #define F367TER_SDAT_NOD 0xf0010001 | ||
| 41 | |||
| 42 | /* TOPCTRL */ | ||
| 43 | #define R367TER_TOPCTRL 0xf002 | ||
| 44 | #define F367TER_STDBY 0xf0020080 | ||
| 45 | #define F367TER_STDBY_FEC 0xf0020040 | ||
| 46 | #define F367TER_STDBY_CORE 0xf0020020 | ||
| 47 | #define F367TER_QAM_COFDM 0xf0020010 | ||
| 48 | #define F367TER_TS_DIS 0xf0020008 | ||
| 49 | #define F367TER_DIR_CLK_216 0xf0020004 | ||
| 50 | #define F367TER_TUNER_BB 0xf0020002 | ||
| 51 | #define F367TER_DVBT_H 0xf0020001 | ||
| 52 | |||
| 53 | /* IOCFG0 */ | ||
| 54 | #define R367TER_IOCFG0 0xf003 | ||
| 55 | #define F367TER_OP0_SD 0xf0030080 | ||
| 56 | #define F367TER_OP0_VAL 0xf0030040 | ||
| 57 | #define F367TER_OP0_OD 0xf0030020 | ||
| 58 | #define F367TER_OP0_INV 0xf0030010 | ||
| 59 | #define F367TER_OP0_DACVALUE_HI 0xf003000f | ||
| 60 | |||
| 61 | /* DAc0R */ | ||
| 62 | #define R367TER_DAC0R 0xf004 | ||
| 63 | #define F367TER_OP0_DACVALUE_LO 0xf00400ff | ||
| 64 | |||
| 65 | /* IOCFG1 */ | ||
| 66 | #define R367TER_IOCFG1 0xf005 | ||
| 67 | #define F367TER_IP0 0xf0050040 | ||
| 68 | #define F367TER_OP1_OD 0xf0050020 | ||
| 69 | #define F367TER_OP1_INV 0xf0050010 | ||
| 70 | #define F367TER_OP1_DACVALUE_HI 0xf005000f | ||
| 71 | |||
| 72 | /* DAC1R */ | ||
| 73 | #define R367TER_DAC1R 0xf006 | ||
| 74 | #define F367TER_OP1_DACVALUE_LO 0xf00600ff | ||
| 75 | |||
| 76 | /* IOCFG2 */ | ||
| 77 | #define R367TER_IOCFG2 0xf007 | ||
| 78 | #define F367TER_OP2_LOCK_CONF 0xf00700e0 | ||
| 79 | #define F367TER_OP2_OD 0xf0070010 | ||
| 80 | #define F367TER_OP2_VAL 0xf0070008 | ||
| 81 | #define F367TER_OP1_LOCK_CONF 0xf0070007 | ||
| 82 | |||
| 83 | /* SDFR */ | ||
| 84 | #define R367TER_SDFR 0xf008 | ||
| 85 | #define F367TER_OP0_FREQ 0xf00800f0 | ||
| 86 | #define F367TER_OP1_FREQ 0xf008000f | ||
| 87 | |||
| 88 | /* STATUS */ | ||
| 89 | #define R367TER_STATUS 0xf009 | ||
| 90 | #define F367TER_TPS_LOCK 0xf0090080 | ||
| 91 | #define F367TER_SYR_LOCK 0xf0090040 | ||
| 92 | #define F367TER_AGC_LOCK 0xf0090020 | ||
| 93 | #define F367TER_PRF 0xf0090010 | ||
| 94 | #define F367TER_LK 0xf0090008 | ||
| 95 | #define F367TER_PR 0xf0090007 | ||
| 96 | |||
| 97 | /* AUX_CLK */ | ||
| 98 | #define R367TER_AUX_CLK 0xf00a | ||
| 99 | #define F367TER_AUXFEC_CTL 0xf00a00c0 | ||
| 100 | #define F367TER_DIS_CKX4 0xf00a0020 | ||
| 101 | #define F367TER_CKSEL 0xf00a0018 | ||
| 102 | #define F367TER_CKDIV_PROG 0xf00a0006 | ||
| 103 | #define F367TER_AUXCLK_ENA 0xf00a0001 | ||
| 104 | |||
| 105 | /* FREESYS1 */ | ||
| 106 | #define R367TER_FREESYS1 0xf00b | ||
| 107 | #define F367TER_FREE_SYS1 0xf00b00ff | ||
| 108 | |||
| 109 | /* FREESYS2 */ | ||
| 110 | #define R367TER_FREESYS2 0xf00c | ||
| 111 | #define F367TER_FREE_SYS2 0xf00c00ff | ||
| 112 | |||
| 113 | /* FREESYS3 */ | ||
| 114 | #define R367TER_FREESYS3 0xf00d | ||
| 115 | #define F367TER_FREE_SYS3 0xf00d00ff | ||
| 116 | |||
| 117 | /* GPIO_CFG */ | ||
| 118 | #define R367TER_GPIO_CFG 0xf00e | ||
| 119 | #define F367TER_GPIO7_NOD 0xf00e0080 | ||
| 120 | #define F367TER_GPIO7_CFG 0xf00e0040 | ||
| 121 | #define F367TER_GPIO6_NOD 0xf00e0020 | ||
| 122 | #define F367TER_GPIO6_CFG 0xf00e0010 | ||
| 123 | #define F367TER_GPIO5_NOD 0xf00e0008 | ||
| 124 | #define F367TER_GPIO5_CFG 0xf00e0004 | ||
| 125 | #define F367TER_GPIO4_NOD 0xf00e0002 | ||
| 126 | #define F367TER_GPIO4_CFG 0xf00e0001 | ||
| 127 | |||
| 128 | /* GPIO_CMD */ | ||
| 129 | #define R367TER_GPIO_CMD 0xf00f | ||
| 130 | #define F367TER_GPIO7_VAL 0xf00f0008 | ||
| 131 | #define F367TER_GPIO6_VAL 0xf00f0004 | ||
| 132 | #define F367TER_GPIO5_VAL 0xf00f0002 | ||
| 133 | #define F367TER_GPIO4_VAL 0xf00f0001 | ||
| 134 | |||
| 135 | /* AGC2MAX */ | ||
| 136 | #define R367TER_AGC2MAX 0xf010 | ||
| 137 | #define F367TER_AGC2_MAX 0xf01000ff | ||
| 138 | |||
| 139 | /* AGC2MIN */ | ||
| 140 | #define R367TER_AGC2MIN 0xf011 | ||
| 141 | #define F367TER_AGC2_MIN 0xf01100ff | ||
| 142 | |||
| 143 | /* AGC1MAX */ | ||
| 144 | #define R367TER_AGC1MAX 0xf012 | ||
| 145 | #define F367TER_AGC1_MAX 0xf01200ff | ||
| 146 | |||
| 147 | /* AGC1MIN */ | ||
| 148 | #define R367TER_AGC1MIN 0xf013 | ||
| 149 | #define F367TER_AGC1_MIN 0xf01300ff | ||
| 150 | |||
| 151 | /* AGCR */ | ||
| 152 | #define R367TER_AGCR 0xf014 | ||
| 153 | #define F367TER_RATIO_A 0xf01400e0 | ||
| 154 | #define F367TER_RATIO_B 0xf0140018 | ||
| 155 | #define F367TER_RATIO_C 0xf0140007 | ||
| 156 | |||
| 157 | /* AGC2TH */ | ||
| 158 | #define R367TER_AGC2TH 0xf015 | ||
| 159 | #define F367TER_AGC2_THRES 0xf01500ff | ||
| 160 | |||
| 161 | /* AGC12c */ | ||
| 162 | #define R367TER_AGC12C 0xf016 | ||
| 163 | #define F367TER_AGC1_IV 0xf0160080 | ||
| 164 | #define F367TER_AGC1_OD 0xf0160040 | ||
| 165 | #define F367TER_AGC1_LOAD 0xf0160020 | ||
| 166 | #define F367TER_AGC2_IV 0xf0160010 | ||
| 167 | #define F367TER_AGC2_OD 0xf0160008 | ||
| 168 | #define F367TER_AGC2_LOAD 0xf0160004 | ||
| 169 | #define F367TER_AGC12_MODE 0xf0160003 | ||
| 170 | |||
| 171 | /* AGCCTRL1 */ | ||
| 172 | #define R367TER_AGCCTRL1 0xf017 | ||
| 173 | #define F367TER_DAGC_ON 0xf0170080 | ||
| 174 | #define F367TER_INVERT_AGC12 0xf0170040 | ||
| 175 | #define F367TER_AGC1_MODE 0xf0170008 | ||
| 176 | #define F367TER_AGC2_MODE 0xf0170007 | ||
| 177 | |||
| 178 | /* AGCCTRL2 */ | ||
| 179 | #define R367TER_AGCCTRL2 0xf018 | ||
| 180 | #define F367TER_FRZ2_CTRL 0xf0180060 | ||
| 181 | #define F367TER_FRZ1_CTRL 0xf0180018 | ||
| 182 | #define F367TER_TIME_CST 0xf0180007 | ||
| 183 | |||
| 184 | /* AGC1VAL1 */ | ||
| 185 | #define R367TER_AGC1VAL1 0xf019 | ||
| 186 | #define F367TER_AGC1_VAL_LO 0xf01900ff | ||
| 187 | |||
| 188 | /* AGC1VAL2 */ | ||
| 189 | #define R367TER_AGC1VAL2 0xf01a | ||
| 190 | #define F367TER_AGC1_VAL_HI 0xf01a000f | ||
| 191 | |||
| 192 | /* AGC2VAL1 */ | ||
| 193 | #define R367TER_AGC2VAL1 0xf01b | ||
| 194 | #define F367TER_AGC2_VAL_LO 0xf01b00ff | ||
| 195 | |||
| 196 | /* AGC2VAL2 */ | ||
| 197 | #define R367TER_AGC2VAL2 0xf01c | ||
| 198 | #define F367TER_AGC2_VAL_HI 0xf01c000f | ||
| 199 | |||
| 200 | /* AGC2PGA */ | ||
| 201 | #define R367TER_AGC2PGA 0xf01d | ||
| 202 | #define F367TER_AGC2_PGA 0xf01d00ff | ||
| 203 | |||
| 204 | /* OVF_RATE1 */ | ||
| 205 | #define R367TER_OVF_RATE1 0xf01e | ||
| 206 | #define F367TER_OVF_RATE_HI 0xf01e000f | ||
| 207 | |||
| 208 | /* OVF_RATE2 */ | ||
| 209 | #define R367TER_OVF_RATE2 0xf01f | ||
| 210 | #define F367TER_OVF_RATE_LO 0xf01f00ff | ||
| 211 | |||
| 212 | /* GAIN_SRC1 */ | ||
| 213 | #define R367TER_GAIN_SRC1 0xf020 | ||
| 214 | #define F367TER_INV_SPECTR 0xf0200080 | ||
| 215 | #define F367TER_IQ_INVERT 0xf0200040 | ||
| 216 | #define F367TER_INR_BYPASS 0xf0200020 | ||
| 217 | #define F367TER_STATUS_INV_SPECRUM 0xf0200010 | ||
| 218 | #define F367TER_GAIN_SRC_HI 0xf020000f | ||
| 219 | |||
| 220 | /* GAIN_SRC2 */ | ||
| 221 | #define R367TER_GAIN_SRC2 0xf021 | ||
| 222 | #define F367TER_GAIN_SRC_LO 0xf02100ff | ||
| 223 | |||
| 224 | /* INC_DEROT1 */ | ||
| 225 | #define R367TER_INC_DEROT1 0xf022 | ||
| 226 | #define F367TER_INC_DEROT_HI 0xf02200ff | ||
| 227 | |||
| 228 | /* INC_DEROT2 */ | ||
| 229 | #define R367TER_INC_DEROT2 0xf023 | ||
| 230 | #define F367TER_INC_DEROT_LO 0xf02300ff | ||
| 231 | |||
| 232 | /* PPM_CPAMP_DIR */ | ||
| 233 | #define R367TER_PPM_CPAMP_DIR 0xf024 | ||
| 234 | #define F367TER_PPM_CPAMP_DIRECT 0xf02400ff | ||
| 235 | |||
| 236 | /* PPM_CPAMP_INV */ | ||
| 237 | #define R367TER_PPM_CPAMP_INV 0xf025 | ||
| 238 | #define F367TER_PPM_CPAMP_INVER 0xf02500ff | ||
| 239 | |||
| 240 | /* FREESTFE_1 */ | ||
| 241 | #define R367TER_FREESTFE_1 0xf026 | ||
| 242 | #define F367TER_SYMBOL_NUMBER_INC 0xf02600c0 | ||
| 243 | #define F367TER_SEL_LSB 0xf0260004 | ||
| 244 | #define F367TER_AVERAGE_ON 0xf0260002 | ||
| 245 | #define F367TER_DC_ADJ 0xf0260001 | ||
| 246 | |||
| 247 | /* FREESTFE_2 */ | ||
| 248 | #define R367TER_FREESTFE_2 0xf027 | ||
| 249 | #define F367TER_SEL_SRCOUT 0xf02700c0 | ||
| 250 | #define F367TER_SEL_SYRTHR 0xf027001f | ||
| 251 | |||
| 252 | /* DCOFFSET */ | ||
| 253 | #define R367TER_DCOFFSET 0xf028 | ||
| 254 | #define F367TER_SELECT_I_Q 0xf0280080 | ||
| 255 | #define F367TER_DC_OFFSET 0xf028007f | ||
| 256 | |||
| 257 | /* EN_PROCESS */ | ||
| 258 | #define R367TER_EN_PROCESS 0xf029 | ||
| 259 | #define F367TER_FREE 0xf02900f0 | ||
| 260 | #define F367TER_ENAB_MANUAL 0xf0290001 | ||
| 261 | |||
| 262 | /* SDI_SMOOTHER */ | ||
| 263 | #define R367TER_SDI_SMOOTHER 0xf02a | ||
| 264 | #define F367TER_DIS_SMOOTH 0xf02a0080 | ||
| 265 | #define F367TER_SDI_INC_SMOOTHER 0xf02a007f | ||
| 266 | |||
| 267 | /* FE_LOOP_OPEN */ | ||
| 268 | #define R367TER_FE_LOOP_OPEN 0xf02b | ||
| 269 | #define F367TER_TRL_LOOP_OP 0xf02b0002 | ||
| 270 | #define F367TER_CRL_LOOP_OP 0xf02b0001 | ||
| 271 | |||
| 272 | /* FREQOFF1 */ | ||
| 273 | #define R367TER_FREQOFF1 0xf02c | ||
| 274 | #define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI 0xf02c00ff | ||
| 275 | |||
| 276 | /* FREQOFF2 */ | ||
| 277 | #define R367TER_FREQOFF2 0xf02d | ||
| 278 | #define F367TER_FREQ_OFFSET_LOOP_OPEN_HI 0xf02d00ff | ||
| 279 | |||
| 280 | /* FREQOFF3 */ | ||
| 281 | #define R367TER_FREQOFF3 0xf02e | ||
| 282 | #define F367TER_FREQ_OFFSET_LOOP_OPEN_LO 0xf02e00ff | ||
| 283 | |||
| 284 | /* TIMOFF1 */ | ||
| 285 | #define R367TER_TIMOFF1 0xf02f | ||
| 286 | #define F367TER_TIM_OFFSET_LOOP_OPEN_HI 0xf02f00ff | ||
| 287 | |||
| 288 | /* TIMOFF2 */ | ||
| 289 | #define R367TER_TIMOFF2 0xf030 | ||
| 290 | #define F367TER_TIM_OFFSET_LOOP_OPEN_LO 0xf03000ff | ||
| 291 | |||
| 292 | /* EPQ */ | ||
| 293 | #define R367TER_EPQ 0xf031 | ||
| 294 | #define F367TER_EPQ1 0xf03100ff | ||
| 295 | |||
| 296 | /* EPQAUTO */ | ||
| 297 | #define R367TER_EPQAUTO 0xf032 | ||
| 298 | #define F367TER_EPQ2 0xf03200ff | ||
| 299 | |||
| 300 | /* SYR_UPDATE */ | ||
| 301 | #define R367TER_SYR_UPDATE 0xf033 | ||
| 302 | #define F367TER_SYR_PROTV 0xf0330080 | ||
| 303 | #define F367TER_SYR_PROTV_GAIN 0xf0330060 | ||
| 304 | #define F367TER_SYR_FILTER 0xf0330010 | ||
| 305 | #define F367TER_SYR_TRACK_THRES 0xf033000c | ||
| 306 | |||
| 307 | /* CHPFREE */ | ||
| 308 | #define R367TER_CHPFREE 0xf034 | ||
| 309 | #define F367TER_CHP_FREE 0xf03400ff | ||
| 310 | |||
| 311 | /* PPM_STATE_MAC */ | ||
| 312 | #define R367TER_PPM_STATE_MAC 0xf035 | ||
| 313 | #define F367TER_PPM_STATE_MACHINE_DECODER 0xf035003f | ||
| 314 | |||
| 315 | /* INR_THRESHOLD */ | ||
| 316 | #define R367TER_INR_THRESHOLD 0xf036 | ||
| 317 | #define F367TER_INR_THRESH 0xf03600ff | ||
| 318 | |||
| 319 | /* EPQ_TPS_ID_CELL */ | ||
| 320 | #define R367TER_EPQ_TPS_ID_CELL 0xf037 | ||
| 321 | #define F367TER_ENABLE_LGTH_TO_CF 0xf0370080 | ||
| 322 | #define F367TER_DIS_TPS_RSVD 0xf0370040 | ||
| 323 | #define F367TER_DIS_BCH 0xf0370020 | ||
| 324 | #define F367TER_DIS_ID_CEL 0xf0370010 | ||
| 325 | #define F367TER_TPS_ADJUST_SYM 0xf037000f | ||
| 326 | |||
| 327 | /* EPQ_CFG */ | ||
| 328 | #define R367TER_EPQ_CFG 0xf038 | ||
| 329 | #define F367TER_EPQ_RANGE 0xf0380002 | ||
| 330 | #define F367TER_EPQ_SOFT 0xf0380001 | ||
| 331 | |||
| 332 | /* EPQ_STATUS */ | ||
| 333 | #define R367TER_EPQ_STATUS 0xf039 | ||
| 334 | #define F367TER_SLOPE_INC 0xf03900fc | ||
| 335 | #define F367TER_TPS_FIELD 0xf0390003 | ||
| 336 | |||
| 337 | /* AUTORELOCK */ | ||
| 338 | #define R367TER_AUTORELOCK 0xf03a | ||
| 339 | #define F367TER_BYPASS_BER_TEMPO 0xf03a0080 | ||
| 340 | #define F367TER_BER_TEMPO 0xf03a0070 | ||
| 341 | #define F367TER_BYPASS_COFDM_TEMPO 0xf03a0008 | ||
| 342 | #define F367TER_COFDM_TEMPO 0xf03a0007 | ||
| 343 | |||
| 344 | /* BER_THR_VMSB */ | ||
| 345 | #define R367TER_BER_THR_VMSB 0xf03b | ||
| 346 | #define F367TER_BER_THRESHOLD_HI 0xf03b00ff | ||
| 347 | |||
| 348 | /* BER_THR_MSB */ | ||
| 349 | #define R367TER_BER_THR_MSB 0xf03c | ||
| 350 | #define F367TER_BER_THRESHOLD_MID 0xf03c00ff | ||
| 351 | |||
| 352 | /* BER_THR_LSB */ | ||
| 353 | #define R367TER_BER_THR_LSB 0xf03d | ||
| 354 | #define F367TER_BER_THRESHOLD_LO 0xf03d00ff | ||
| 355 | |||
| 356 | /* CCD */ | ||
| 357 | #define R367TER_CCD 0xf03e | ||
| 358 | #define F367TER_CCD_DETECTED 0xf03e0080 | ||
| 359 | #define F367TER_CCD_RESET 0xf03e0040 | ||
| 360 | #define F367TER_CCD_THRESHOLD 0xf03e000f | ||
| 361 | |||
| 362 | /* SPECTR_CFG */ | ||
| 363 | #define R367TER_SPECTR_CFG 0xf03f | ||
| 364 | #define F367TER_SPECT_CFG 0xf03f0003 | ||
| 365 | |||
| 366 | /* CONSTMU_MSB */ | ||
| 367 | #define R367TER_CONSTMU_MSB 0xf040 | ||
| 368 | #define F367TER_CONSTMU_FREEZE 0xf0400080 | ||
| 369 | #define F367TER_CONSTNU_FORCE_EN 0xf0400040 | ||
| 370 | #define F367TER_CONST_MU_MSB 0xf040003f | ||
| 371 | |||
| 372 | /* CONSTMU_LSB */ | ||
| 373 | #define R367TER_CONSTMU_LSB 0xf041 | ||
| 374 | #define F367TER_CONST_MU_LSB 0xf04100ff | ||
| 375 | |||
| 376 | /* CONSTMU_MAX_MSB */ | ||
| 377 | #define R367TER_CONSTMU_MAX_MSB 0xf042 | ||
| 378 | #define F367TER_CONST_MU_MAX_MSB 0xf042003f | ||
| 379 | |||
| 380 | /* CONSTMU_MAX_LSB */ | ||
| 381 | #define R367TER_CONSTMU_MAX_LSB 0xf043 | ||
| 382 | #define F367TER_CONST_MU_MAX_LSB 0xf04300ff | ||
| 383 | |||
| 384 | /* ALPHANOISE */ | ||
| 385 | #define R367TER_ALPHANOISE 0xf044 | ||
| 386 | #define F367TER_USE_ALLFILTER 0xf0440080 | ||
| 387 | #define F367TER_INTER_ON 0xf0440040 | ||
| 388 | #define F367TER_ALPHA_NOISE 0xf044001f | ||
| 389 | |||
| 390 | /* MAXGP_MSB */ | ||
| 391 | #define R367TER_MAXGP_MSB 0xf045 | ||
| 392 | #define F367TER_MUFILTER_LENGTH 0xf04500f0 | ||
| 393 | #define F367TER_MAX_GP_MSB 0xf045000f | ||
| 394 | |||
| 395 | /* MAXGP_LSB */ | ||
| 396 | #define R367TER_MAXGP_LSB 0xf046 | ||
| 397 | #define F367TER_MAX_GP_LSB 0xf04600ff | ||
| 398 | |||
| 399 | /* ALPHAMSB */ | ||
| 400 | #define R367TER_ALPHAMSB 0xf047 | ||
| 401 | #define F367TER_CHC_DATARATE 0xf04700c0 | ||
| 402 | #define F367TER_ALPHA_MSB 0xf047003f | ||
| 403 | |||
| 404 | /* ALPHALSB */ | ||
| 405 | #define R367TER_ALPHALSB 0xf048 | ||
| 406 | #define F367TER_ALPHA_LSB 0xf04800ff | ||
| 407 | |||
| 408 | /* PILOT_ACCU */ | ||
| 409 | #define R367TER_PILOT_ACCU 0xf049 | ||
| 410 | #define F367TER_USE_SCAT4ADDAPT 0xf0490080 | ||
| 411 | #define F367TER_PILOT_ACC 0xf049001f | ||
| 412 | |||
| 413 | /* PILOTMU_ACCU */ | ||
| 414 | #define R367TER_PILOTMU_ACCU 0xf04a | ||
| 415 | #define F367TER_DISCARD_BAD_SP 0xf04a0080 | ||
| 416 | #define F367TER_DISCARD_BAD_CP 0xf04a0040 | ||
| 417 | #define F367TER_PILOT_MU_ACCU 0xf04a001f | ||
| 418 | |||
| 419 | /* FILT_CHANNEL_EST */ | ||
| 420 | #define R367TER_FILT_CHANNEL_EST 0xf04b | ||
| 421 | #define F367TER_USE_FILT_PILOT 0xf04b0080 | ||
| 422 | #define F367TER_FILT_CHANNEL 0xf04b007f | ||
| 423 | |||
| 424 | /* ALPHA_NOPISE_FREQ */ | ||
| 425 | #define R367TER_ALPHA_NOPISE_FREQ 0xf04c | ||
| 426 | #define F367TER_NOISE_FREQ_FILT 0xf04c0040 | ||
| 427 | #define F367TER_ALPHA_NOISE_FREQ 0xf04c003f | ||
| 428 | |||
| 429 | /* RATIO_PILOT */ | ||
| 430 | #define R367TER_RATIO_PILOT 0xf04d | ||
| 431 | #define F367TER_RATIO_MEAN_SP 0xf04d00f0 | ||
| 432 | #define F367TER_RATIO_MEAN_CP 0xf04d000f | ||
| 433 | |||
| 434 | /* CHC_CTL */ | ||
| 435 | #define R367TER_CHC_CTL 0xf04e | ||
| 436 | #define F367TER_TRACK_EN 0xf04e0080 | ||
| 437 | #define F367TER_NOISE_NORM_EN 0xf04e0040 | ||
| 438 | #define F367TER_FORCE_CHC_RESET 0xf04e0020 | ||
| 439 | #define F367TER_SHORT_TIME 0xf04e0010 | ||
| 440 | #define F367TER_FORCE_STATE_EN 0xf04e0008 | ||
| 441 | #define F367TER_FORCE_STATE 0xf04e0007 | ||
| 442 | |||
| 443 | /* EPQ_ADJUST */ | ||
| 444 | #define R367TER_EPQ_ADJUST 0xf04f | ||
| 445 | #define F367TER_ADJUST_SCAT_IND 0xf04f00c0 | ||
| 446 | #define F367TER_ONE_SYMBOL 0xf04f0010 | ||
| 447 | #define F367TER_EPQ_DECAY 0xf04f000e | ||
| 448 | #define F367TER_HOLD_SLOPE 0xf04f0001 | ||
| 449 | |||
| 450 | /* EPQ_THRES */ | ||
| 451 | #define R367TER_EPQ_THRES 0xf050 | ||
| 452 | #define F367TER_EPQ_THR 0xf05000ff | ||
| 453 | |||
| 454 | /* OMEGA_CTL */ | ||
| 455 | #define R367TER_OMEGA_CTL 0xf051 | ||
| 456 | #define F367TER_OMEGA_RST 0xf0510080 | ||
| 457 | #define F367TER_FREEZE_OMEGA 0xf0510040 | ||
| 458 | #define F367TER_OMEGA_SEL 0xf051003f | ||
| 459 | |||
| 460 | /* GP_CTL */ | ||
| 461 | #define R367TER_GP_CTL 0xf052 | ||
| 462 | #define F367TER_CHC_STATE 0xf05200e0 | ||
| 463 | #define F367TER_FREEZE_GP 0xf0520010 | ||
| 464 | #define F367TER_GP_SEL 0xf052000f | ||
| 465 | |||
| 466 | /* MUMSB */ | ||
| 467 | #define R367TER_MUMSB 0xf053 | ||
| 468 | #define F367TER_MU_MSB 0xf053007f | ||
| 469 | |||
| 470 | /* MULSB */ | ||
| 471 | #define R367TER_MULSB 0xf054 | ||
| 472 | #define F367TER_MU_LSB 0xf05400ff | ||
| 473 | |||
| 474 | /* GPMSB */ | ||
| 475 | #define R367TER_GPMSB 0xf055 | ||
| 476 | #define F367TER_CSI_THRESHOLD 0xf05500e0 | ||
| 477 | #define F367TER_GP_MSB 0xf055000f | ||
| 478 | |||
| 479 | /* GPLSB */ | ||
| 480 | #define R367TER_GPLSB 0xf056 | ||
| 481 | #define F367TER_GP_LSB 0xf05600ff | ||
| 482 | |||
| 483 | /* OMEGAMSB */ | ||
| 484 | #define R367TER_OMEGAMSB 0xf057 | ||
| 485 | #define F367TER_OMEGA_MSB 0xf057007f | ||
| 486 | |||
| 487 | /* OMEGALSB */ | ||
| 488 | #define R367TER_OMEGALSB 0xf058 | ||
| 489 | #define F367TER_OMEGA_LSB 0xf05800ff | ||
| 490 | |||
| 491 | /* SCAT_NB */ | ||
| 492 | #define R367TER_SCAT_NB 0xf059 | ||
| 493 | #define F367TER_CHC_TEST 0xf05900f8 | ||
| 494 | #define F367TER_SCAT_NUMB 0xf0590003 | ||
| 495 | |||
| 496 | /* CHC_DUMMY */ | ||
| 497 | #define R367TER_CHC_DUMMY 0xf05a | ||
| 498 | #define F367TER_CHC_DUM 0xf05a00ff | ||
| 499 | |||
| 500 | /* INC_CTL */ | ||
| 501 | #define R367TER_INC_CTL 0xf05b | ||
| 502 | #define F367TER_INC_BYPASS 0xf05b0080 | ||
| 503 | #define F367TER_INC_NDEPTH 0xf05b000c | ||
| 504 | #define F367TER_INC_MADEPTH 0xf05b0003 | ||
| 505 | |||
| 506 | /* INCTHRES_COR1 */ | ||
| 507 | #define R367TER_INCTHRES_COR1 0xf05c | ||
| 508 | #define F367TER_INC_THRES_COR1 0xf05c00ff | ||
| 509 | |||
| 510 | /* INCTHRES_COR2 */ | ||
| 511 | #define R367TER_INCTHRES_COR2 0xf05d | ||
| 512 | #define F367TER_INC_THRES_COR2 0xf05d00ff | ||
| 513 | |||
| 514 | /* INCTHRES_DET1 */ | ||
| 515 | #define R367TER_INCTHRES_DET1 0xf05e | ||
| 516 | #define F367TER_INC_THRES_DET1 0xf05e003f | ||
| 517 | |||
| 518 | /* INCTHRES_DET2 */ | ||
| 519 | #define R367TER_INCTHRES_DET2 0xf05f | ||
| 520 | #define F367TER_INC_THRES_DET2 0xf05f003f | ||
| 521 | |||
| 522 | /* IIR_CELLNB */ | ||
| 523 | #define R367TER_IIR_CELLNB 0xf060 | ||
| 524 | #define F367TER_NRST_IIR 0xf0600080 | ||
| 525 | #define F367TER_IIR_CELL_NB 0xf0600007 | ||
| 526 | |||
| 527 | /* IIRCX_COEFF1_MSB */ | ||
| 528 | #define R367TER_IIRCX_COEFF1_MSB 0xf061 | ||
| 529 | #define F367TER_IIR_CX_COEFF1_MSB 0xf06100ff | ||
| 530 | |||
| 531 | /* IIRCX_COEFF1_LSB */ | ||
| 532 | #define R367TER_IIRCX_COEFF1_LSB 0xf062 | ||
| 533 | #define F367TER_IIR_CX_COEFF1_LSB 0xf06200ff | ||
| 534 | |||
| 535 | /* IIRCX_COEFF2_MSB */ | ||
| 536 | #define R367TER_IIRCX_COEFF2_MSB 0xf063 | ||
| 537 | #define F367TER_IIR_CX_COEFF2_MSB 0xf06300ff | ||
| 538 | |||
| 539 | /* IIRCX_COEFF2_LSB */ | ||
| 540 | #define R367TER_IIRCX_COEFF2_LSB 0xf064 | ||
| 541 | #define F367TER_IIR_CX_COEFF2_LSB 0xf06400ff | ||
| 542 | |||
| 543 | /* IIRCX_COEFF3_MSB */ | ||
| 544 | #define R367TER_IIRCX_COEFF3_MSB 0xf065 | ||
| 545 | #define F367TER_IIR_CX_COEFF3_MSB 0xf06500ff | ||
| 546 | |||
| 547 | /* IIRCX_COEFF3_LSB */ | ||
| 548 | #define R367TER_IIRCX_COEFF3_LSB 0xf066 | ||
| 549 | #define F367TER_IIR_CX_COEFF3_LSB 0xf06600ff | ||
| 550 | |||
| 551 | /* IIRCX_COEFF4_MSB */ | ||
| 552 | #define R367TER_IIRCX_COEFF4_MSB 0xf067 | ||
| 553 | #define F367TER_IIR_CX_COEFF4_MSB 0xf06700ff | ||
| 554 | |||
| 555 | /* IIRCX_COEFF4_LSB */ | ||
| 556 | #define R367TER_IIRCX_COEFF4_LSB 0xf068 | ||
| 557 | #define F367TER_IIR_CX_COEFF4_LSB 0xf06800ff | ||
| 558 | |||
| 559 | /* IIRCX_COEFF5_MSB */ | ||
| 560 | #define R367TER_IIRCX_COEFF5_MSB 0xf069 | ||
| 561 | #define F367TER_IIR_CX_COEFF5_MSB 0xf06900ff | ||
| 562 | |||
| 563 | /* IIRCX_COEFF5_LSB */ | ||
| 564 | #define R367TER_IIRCX_COEFF5_LSB 0xf06a | ||
| 565 | #define F367TER_IIR_CX_COEFF5_LSB 0xf06a00ff | ||
| 566 | |||
| 567 | /* FEPATH_CFG */ | ||
| 568 | #define R367TER_FEPATH_CFG 0xf06b | ||
| 569 | #define F367TER_DEMUX_SWAP 0xf06b0004 | ||
| 570 | #define F367TER_DIGAGC_SWAP 0xf06b0002 | ||
| 571 | #define F367TER_LONGPATH_IF 0xf06b0001 | ||
| 572 | |||
| 573 | /* PMC1_FUNC */ | ||
| 574 | #define R367TER_PMC1_FUNC 0xf06c | ||
| 575 | #define F367TER_SOFT_RSTN 0xf06c0080 | ||
| 576 | #define F367TER_PMC1_AVERAGE_TIME 0xf06c0078 | ||
| 577 | #define F367TER_PMC1_WAIT_TIME 0xf06c0006 | ||
| 578 | #define F367TER_PMC1_2N_SEL 0xf06c0001 | ||
| 579 | |||
| 580 | /* PMC1_FOR */ | ||
| 581 | #define R367TER_PMC1_FOR 0xf06d | ||
| 582 | #define F367TER_PMC1_FORCE 0xf06d0080 | ||
| 583 | #define F367TER_PMC1_FORCE_VALUE 0xf06d007c | ||
| 584 | |||
| 585 | /* PMC2_FUNC */ | ||
| 586 | #define R367TER_PMC2_FUNC 0xf06e | ||
| 587 | #define F367TER_PMC2_SOFT_STN 0xf06e0080 | ||
| 588 | #define F367TER_PMC2_ACCU_TIME 0xf06e0070 | ||
| 589 | #define F367TER_PMC2_CMDP_MN 0xf06e0008 | ||
| 590 | #define F367TER_PMC2_SWAP 0xf06e0004 | ||
| 591 | |||
| 592 | /* STATUS_ERR_DA */ | ||
| 593 | #define R367TER_STATUS_ERR_DA 0xf06f | ||
| 594 | #define F367TER_COM_USEGAINTRK 0xf06f0080 | ||
| 595 | #define F367TER_COM_AGCLOCK 0xf06f0040 | ||
| 596 | #define F367TER_AUT_AGCLOCK 0xf06f0020 | ||
| 597 | #define F367TER_MIN_ERR_X_LSB 0xf06f000f | ||
| 598 | |||
| 599 | /* DIG_AGC_R */ | ||
| 600 | #define R367TER_DIG_AGC_R 0xf070 | ||
| 601 | #define F367TER_COM_SOFT_RSTN 0xf0700080 | ||
| 602 | #define F367TER_COM_AGC_ON 0xf0700040 | ||
| 603 | #define F367TER_COM_EARLY 0xf0700020 | ||
| 604 | #define F367TER_AUT_SOFT_RESETN 0xf0700010 | ||
| 605 | #define F367TER_AUT_AGC_ON 0xf0700008 | ||
| 606 | #define F367TER_AUT_EARLY 0xf0700004 | ||
| 607 | #define F367TER_AUT_ROT_EN 0xf0700002 | ||
| 608 | #define F367TER_LOCK_SOFT_RESETN 0xf0700001 | ||
| 609 | |||
| 610 | /* COMAGC_TARMSB */ | ||
| 611 | #define R367TER_COMAGC_TARMSB 0xf071 | ||
| 612 | #define F367TER_COM_AGC_TARGET_MSB 0xf07100ff | ||
| 613 | |||
| 614 | /* COM_AGC_TAR_ENMODE */ | ||
| 615 | #define R367TER_COM_AGC_TAR_ENMODE 0xf072 | ||
| 616 | #define F367TER_COM_AGC_TARGET_LSB 0xf07200f0 | ||
| 617 | #define F367TER_COM_ENMODE 0xf072000f | ||
| 618 | |||
| 619 | /* COM_AGC_CFG */ | ||
| 620 | #define R367TER_COM_AGC_CFG 0xf073 | ||
| 621 | #define F367TER_COM_N 0xf07300f8 | ||
| 622 | #define F367TER_COM_STABMODE 0xf0730006 | ||
| 623 | #define F367TER_ERR_SEL 0xf0730001 | ||
| 624 | |||
| 625 | /* COM_AGC_GAIN1 */ | ||
| 626 | #define R367TER_COM_AGC_GAIN1 0xf074 | ||
| 627 | #define F367TER_COM_GAIN1aCK 0xf07400f0 | ||
| 628 | #define F367TER_COM_GAIN1TRK 0xf074000f | ||
| 629 | |||
| 630 | /* AUT_AGC_TARGETMSB */ | ||
| 631 | #define R367TER_AUT_AGC_TARGETMSB 0xf075 | ||
| 632 | #define F367TER_AUT_AGC_TARGET_MSB 0xf07500ff | ||
| 633 | |||
| 634 | /* LOCK_DET_MSB */ | ||
| 635 | #define R367TER_LOCK_DET_MSB 0xf076 | ||
| 636 | #define F367TER_LOCK_DETECT_MSB 0xf07600ff | ||
| 637 | |||
| 638 | /* AGCTAR_LOCK_LSBS */ | ||
| 639 | #define R367TER_AGCTAR_LOCK_LSBS 0xf077 | ||
| 640 | #define F367TER_AUT_AGC_TARGET_LSB 0xf07700f0 | ||
| 641 | #define F367TER_LOCK_DETECT_LSB 0xf077000f | ||
| 642 | |||
| 643 | /* AUT_GAIN_EN */ | ||
| 644 | #define R367TER_AUT_GAIN_EN 0xf078 | ||
| 645 | #define F367TER_AUT_ENMODE 0xf07800f0 | ||
| 646 | #define F367TER_AUT_GAIN2 0xf078000f | ||
| 647 | |||
| 648 | /* AUT_CFG */ | ||
| 649 | #define R367TER_AUT_CFG 0xf079 | ||
| 650 | #define F367TER_AUT_N 0xf07900f8 | ||
| 651 | #define F367TER_INT_CHOICE 0xf0790006 | ||
| 652 | #define F367TER_INT_LOAD 0xf0790001 | ||
| 653 | |||
| 654 | /* LOCKN */ | ||
| 655 | #define R367TER_LOCKN 0xf07a | ||
| 656 | #define F367TER_LOCK_N 0xf07a00f8 | ||
| 657 | #define F367TER_SEL_IQNTAR 0xf07a0004 | ||
| 658 | #define F367TER_LOCK_DETECT_CHOICE 0xf07a0003 | ||
| 659 | |||
| 660 | /* INT_X_3 */ | ||
| 661 | #define R367TER_INT_X_3 0xf07b | ||
| 662 | #define F367TER_INT_X3 0xf07b00ff | ||
| 663 | |||
| 664 | /* INT_X_2 */ | ||
| 665 | #define R367TER_INT_X_2 0xf07c | ||
| 666 | #define F367TER_INT_X2 0xf07c00ff | ||
| 667 | |||
| 668 | /* INT_X_1 */ | ||
| 669 | #define R367TER_INT_X_1 0xf07d | ||
| 670 | #define F367TER_INT_X1 0xf07d00ff | ||
| 671 | |||
| 672 | /* INT_X_0 */ | ||
| 673 | #define R367TER_INT_X_0 0xf07e | ||
| 674 | #define F367TER_INT_X0 0xf07e00ff | ||
| 675 | |||
| 676 | /* MIN_ERRX_MSB */ | ||
| 677 | #define R367TER_MIN_ERRX_MSB 0xf07f | ||
| 678 | #define F367TER_MIN_ERR_X_MSB 0xf07f00ff | ||
| 679 | |||
| 680 | /* COR_CTL */ | ||
| 681 | #define R367TER_COR_CTL 0xf080 | ||
| 682 | #define F367TER_CORE_ACTIVE 0xf0800020 | ||
| 683 | #define F367TER_HOLD 0xf0800010 | ||
| 684 | #define F367TER_CORE_STATE_CTL 0xf080000f | ||
| 685 | |||
| 686 | /* COR_STAT */ | ||
| 687 | #define R367TER_COR_STAT 0xf081 | ||
| 688 | #define F367TER_SCATT_LOCKED 0xf0810080 | ||
| 689 | #define F367TER_TPS_LOCKED 0xf0810040 | ||
| 690 | #define F367TER_SYR_LOCKED_COR 0xf0810020 | ||
| 691 | #define F367TER_AGC_LOCKED_STAT 0xf0810010 | ||
| 692 | #define F367TER_CORE_STATE_STAT 0xf081000f | ||
| 693 | |||
| 694 | /* COR_INTEN */ | ||
| 695 | #define R367TER_COR_INTEN 0xf082 | ||
| 696 | #define F367TER_INTEN 0xf0820080 | ||
| 697 | #define F367TER_INTEN_SYR 0xf0820020 | ||
| 698 | #define F367TER_INTEN_FFT 0xf0820010 | ||
| 699 | #define F367TER_INTEN_AGC 0xf0820008 | ||
| 700 | #define F367TER_INTEN_TPS1 0xf0820004 | ||
| 701 | #define F367TER_INTEN_TPS2 0xf0820002 | ||
| 702 | #define F367TER_INTEN_TPS3 0xf0820001 | ||
| 703 | |||
| 704 | /* COR_INTSTAT */ | ||
| 705 | #define R367TER_COR_INTSTAT 0xf083 | ||
| 706 | #define F367TER_INTSTAT_SYR 0xf0830020 | ||
| 707 | #define F367TER_INTSTAT_FFT 0xf0830010 | ||
| 708 | #define F367TER_INTSAT_AGC 0xf0830008 | ||
| 709 | #define F367TER_INTSTAT_TPS1 0xf0830004 | ||
| 710 | #define F367TER_INTSTAT_TPS2 0xf0830002 | ||
| 711 | #define F367TER_INTSTAT_TPS3 0xf0830001 | ||
| 712 | |||
| 713 | /* COR_MODEGUARD */ | ||
| 714 | #define R367TER_COR_MODEGUARD 0xf084 | ||
| 715 | #define F367TER_FORCE 0xf0840010 | ||
| 716 | #define F367TER_MODE 0xf084000c | ||
| 717 | #define F367TER_GUARD 0xf0840003 | ||
| 718 | |||
| 719 | /* AGC_CTL */ | ||
| 720 | #define R367TER_AGC_CTL 0xf085 | ||
| 721 | #define F367TER_AGC_TIMING_FACTOR 0xf08500e0 | ||
| 722 | #define F367TER_AGC_LAST 0xf0850010 | ||
| 723 | #define F367TER_AGC_GAIN 0xf085000c | ||
| 724 | #define F367TER_AGC_NEG 0xf0850002 | ||
| 725 | #define F367TER_AGC_SET 0xf0850001 | ||
| 726 | |||
| 727 | /* AGC_MANUAL1 */ | ||
| 728 | #define R367TER_AGC_MANUAL1 0xf086 | ||
| 729 | #define F367TER_AGC_VAL_LO 0xf08600ff | ||
| 730 | |||
| 731 | /* AGC_MANUAL2 */ | ||
| 732 | #define R367TER_AGC_MANUAL2 0xf087 | ||
| 733 | #define F367TER_AGC_VAL_HI 0xf087000f | ||
| 734 | |||
| 735 | /* AGC_TARG */ | ||
| 736 | #define R367TER_AGC_TARG 0xf088 | ||
| 737 | #define F367TER_AGC_TARGET 0xf08800ff | ||
| 738 | |||
| 739 | /* AGC_GAIN1 */ | ||
| 740 | #define R367TER_AGC_GAIN1 0xf089 | ||
| 741 | #define F367TER_AGC_GAIN_LO 0xf08900ff | ||
| 742 | |||
| 743 | /* AGC_GAIN2 */ | ||
| 744 | #define R367TER_AGC_GAIN2 0xf08a | ||
| 745 | #define F367TER_AGC_LOCKED_GAIN2 0xf08a0010 | ||
| 746 | #define F367TER_AGC_GAIN_HI 0xf08a000f | ||
| 747 | |||
| 748 | /* RESERVED_1 */ | ||
| 749 | #define R367TER_RESERVED_1 0xf08b | ||
| 750 | #define F367TER_RESERVED1 0xf08b00ff | ||
| 751 | |||
| 752 | /* RESERVED_2 */ | ||
| 753 | #define R367TER_RESERVED_2 0xf08c | ||
| 754 | #define F367TER_RESERVED2 0xf08c00ff | ||
| 755 | |||
| 756 | /* RESERVED_3 */ | ||
| 757 | #define R367TER_RESERVED_3 0xf08d | ||
| 758 | #define F367TER_RESERVED3 0xf08d00ff | ||
| 759 | |||
| 760 | /* CAS_CTL */ | ||
| 761 | #define R367TER_CAS_CTL 0xf08e | ||
| 762 | #define F367TER_CCS_ENABLE 0xf08e0080 | ||
| 763 | #define F367TER_ACS_DISABLE 0xf08e0040 | ||
| 764 | #define F367TER_DAGC_DIS 0xf08e0020 | ||
| 765 | #define F367TER_DAGC_GAIN 0xf08e0018 | ||
| 766 | #define F367TER_CCSMU 0xf08e0007 | ||
| 767 | |||
| 768 | /* CAS_FREQ */ | ||
| 769 | #define R367TER_CAS_FREQ 0xf08f | ||
| 770 | #define F367TER_CCS_FREQ 0xf08f00ff | ||
| 771 | |||
| 772 | /* CAS_DAGCGAIN */ | ||
| 773 | #define R367TER_CAS_DAGCGAIN 0xf090 | ||
| 774 | #define F367TER_CAS_DAGC_GAIN 0xf09000ff | ||
| 775 | |||
| 776 | /* SYR_CTL */ | ||
| 777 | #define R367TER_SYR_CTL 0xf091 | ||
| 778 | #define F367TER_SICTH_ENABLE 0xf0910080 | ||
| 779 | #define F367TER_LONG_ECHO 0xf0910078 | ||
| 780 | #define F367TER_AUTO_LE_EN 0xf0910004 | ||
| 781 | #define F367TER_SYR_BYPASS 0xf0910002 | ||
| 782 | #define F367TER_SYR_TR_DIS 0xf0910001 | ||
| 783 | |||
| 784 | /* SYR_STAT */ | ||
| 785 | #define R367TER_SYR_STAT 0xf092 | ||
| 786 | #define F367TER_SYR_LOCKED_STAT 0xf0920010 | ||
| 787 | #define F367TER_SYR_MODE 0xf092000c | ||
| 788 | #define F367TER_SYR_GUARD 0xf0920003 | ||
| 789 | |||
| 790 | /* SYR_NCO1 */ | ||
| 791 | #define R367TER_SYR_NCO1 0xf093 | ||
| 792 | #define F367TER_SYR_NCO_LO 0xf09300ff | ||
| 793 | |||
| 794 | /* SYR_NCO2 */ | ||
| 795 | #define R367TER_SYR_NCO2 0xf094 | ||
| 796 | #define F367TER_SYR_NCO_HI 0xf094003f | ||
| 797 | |||
| 798 | /* SYR_OFFSET1 */ | ||
| 799 | #define R367TER_SYR_OFFSET1 0xf095 | ||
| 800 | #define F367TER_SYR_OFFSET_LO 0xf09500ff | ||
| 801 | |||
| 802 | /* SYR_OFFSET2 */ | ||
| 803 | #define R367TER_SYR_OFFSET2 0xf096 | ||
| 804 | #define F367TER_SYR_OFFSET_HI 0xf096003f | ||
| 805 | |||
| 806 | /* FFT_CTL */ | ||
| 807 | #define R367TER_FFT_CTL 0xf097 | ||
| 808 | #define F367TER_SHIFT_FFT_TRIG 0xf0970018 | ||
| 809 | #define F367TER_FFT_TRIGGER 0xf0970004 | ||
| 810 | #define F367TER_FFT_MANUAL 0xf0970002 | ||
| 811 | #define F367TER_IFFT_MODE 0xf0970001 | ||
| 812 | |||
| 813 | /* SCR_CTL */ | ||
| 814 | #define R367TER_SCR_CTL 0xf098 | ||
| 815 | #define F367TER_SYRADJDECAY 0xf0980070 | ||
| 816 | #define F367TER_SCR_CPEDIS 0xf0980002 | ||
| 817 | #define F367TER_SCR_DIS 0xf0980001 | ||
| 818 | |||
| 819 | /* PPM_CTL1 */ | ||
| 820 | #define R367TER_PPM_CTL1 0xf099 | ||
| 821 | #define F367TER_PPM_MAXFREQ 0xf0990030 | ||
| 822 | #define F367TER_PPM_MAXTIM 0xf0990008 | ||
| 823 | #define F367TER_PPM_INVSEL 0xf0990004 | ||
| 824 | #define F367TER_PPM_SCATDIS 0xf0990002 | ||
| 825 | #define F367TER_PPM_BYP 0xf0990001 | ||
| 826 | |||
| 827 | /* TRL_CTL */ | ||
| 828 | #define R367TER_TRL_CTL 0xf09a | ||
| 829 | #define F367TER_TRL_NOMRATE_LSB 0xf09a0080 | ||
| 830 | #define F367TER_TRL_GAIN_FACTOR 0xf09a0078 | ||
| 831 | #define F367TER_TRL_LOOPGAIN 0xf09a0007 | ||
| 832 | |||
| 833 | /* TRL_NOMRATE1 */ | ||
| 834 | #define R367TER_TRL_NOMRATE1 0xf09b | ||
| 835 | #define F367TER_TRL_NOMRATE_LO 0xf09b00ff | ||
| 836 | |||
| 837 | /* TRL_NOMRATE2 */ | ||
| 838 | #define R367TER_TRL_NOMRATE2 0xf09c | ||
| 839 | #define F367TER_TRL_NOMRATE_HI 0xf09c00ff | ||
| 840 | |||
| 841 | /* TRL_TIME1 */ | ||
| 842 | #define R367TER_TRL_TIME1 0xf09d | ||
| 843 | #define F367TER_TRL_TOFFSET_LO 0xf09d00ff | ||
| 844 | |||
| 845 | /* TRL_TIME2 */ | ||
| 846 | #define R367TER_TRL_TIME2 0xf09e | ||
| 847 | #define F367TER_TRL_TOFFSET_HI 0xf09e00ff | ||
| 848 | |||
| 849 | /* CRL_CTL */ | ||
| 850 | #define R367TER_CRL_CTL 0xf09f | ||
| 851 | #define F367TER_CRL_DIS 0xf09f0080 | ||
| 852 | #define F367TER_CRL_GAIN_FACTOR 0xf09f0078 | ||
| 853 | #define F367TER_CRL_LOOPGAIN 0xf09f0007 | ||
| 854 | |||
| 855 | /* CRL_FREQ1 */ | ||
| 856 | #define R367TER_CRL_FREQ1 0xf0a0 | ||
| 857 | #define F367TER_CRL_FOFFSET_LO 0xf0a000ff | ||
| 858 | |||
| 859 | /* CRL_FREQ2 */ | ||
| 860 | #define R367TER_CRL_FREQ2 0xf0a1 | ||
| 861 | #define F367TER_CRL_FOFFSET_HI 0xf0a100ff | ||
| 862 | |||
| 863 | /* CRL_FREQ3 */ | ||
| 864 | #define R367TER_CRL_FREQ3 0xf0a2 | ||
| 865 | #define F367TER_CRL_FOFFSET_VHI 0xf0a200ff | ||
| 866 | |||
| 867 | /* TPS_SFRAME_CTL */ | ||
| 868 | #define R367TER_TPS_SFRAME_CTL 0xf0a3 | ||
| 869 | #define F367TER_TPS_SFRAME_SYNC 0xf0a30001 | ||
| 870 | |||
| 871 | /* CHC_SNR */ | ||
| 872 | #define R367TER_CHC_SNR 0xf0a4 | ||
| 873 | #define F367TER_CHCSNR 0xf0a400ff | ||
| 874 | |||
| 875 | /* BDI_CTL */ | ||
| 876 | #define R367TER_BDI_CTL 0xf0a5 | ||
| 877 | #define F367TER_BDI_LPSEL 0xf0a50002 | ||
| 878 | #define F367TER_BDI_SERIAL 0xf0a50001 | ||
| 879 | |||
| 880 | /* DMP_CTL */ | ||
| 881 | #define R367TER_DMP_CTL 0xf0a6 | ||
| 882 | #define F367TER_DMP_SCALING_FACTOR 0xf0a6001e | ||
| 883 | #define F367TER_DMP_SDDIS 0xf0a60001 | ||
| 884 | |||
| 885 | /* TPS_RCVD1 */ | ||
| 886 | #define R367TER_TPS_RCVD1 0xf0a7 | ||
| 887 | #define F367TER_TPS_CHANGE 0xf0a70040 | ||
| 888 | #define F367TER_BCH_OK 0xf0a70020 | ||
| 889 | #define F367TER_TPS_SYNC 0xf0a70010 | ||
| 890 | #define F367TER_TPS_FRAME 0xf0a70003 | ||
| 891 | |||
| 892 | /* TPS_RCVD2 */ | ||
| 893 | #define R367TER_TPS_RCVD2 0xf0a8 | ||
| 894 | #define F367TER_TPS_HIERMODE 0xf0a80070 | ||
| 895 | #define F367TER_TPS_CONST 0xf0a80003 | ||
| 896 | |||
| 897 | /* TPS_RCVD3 */ | ||
| 898 | #define R367TER_TPS_RCVD3 0xf0a9 | ||
| 899 | #define F367TER_TPS_LPCODE 0xf0a90070 | ||
| 900 | #define F367TER_TPS_HPCODE 0xf0a90007 | ||
| 901 | |||
| 902 | /* TPS_RCVD4 */ | ||
| 903 | #define R367TER_TPS_RCVD4 0xf0aa | ||
| 904 | #define F367TER_TPS_GUARD 0xf0aa0030 | ||
| 905 | #define F367TER_TPS_MODE 0xf0aa0003 | ||
| 906 | |||
| 907 | /* TPS_ID_CELL1 */ | ||
| 908 | #define R367TER_TPS_ID_CELL1 0xf0ab | ||
| 909 | #define F367TER_TPS_ID_CELL_LO 0xf0ab00ff | ||
| 910 | |||
| 911 | /* TPS_ID_CELL2 */ | ||
| 912 | #define R367TER_TPS_ID_CELL2 0xf0ac | ||
| 913 | #define F367TER_TPS_ID_CELL_HI 0xf0ac00ff | ||
| 914 | |||
| 915 | /* TPS_RCVD5_SET1 */ | ||
| 916 | #define R367TER_TPS_RCVD5_SET1 0xf0ad | ||
| 917 | #define F367TER_TPS_NA 0xf0ad00fC | ||
| 918 | #define F367TER_TPS_SETFRAME 0xf0ad0003 | ||
| 919 | |||
| 920 | /* TPS_SET2 */ | ||
| 921 | #define R367TER_TPS_SET2 0xf0ae | ||
| 922 | #define F367TER_TPS_SETHIERMODE 0xf0ae0070 | ||
| 923 | #define F367TER_TPS_SETCONST 0xf0ae0003 | ||
| 924 | |||
| 925 | /* TPS_SET3 */ | ||
| 926 | #define R367TER_TPS_SET3 0xf0af | ||
| 927 | #define F367TER_TPS_SETLPCODE 0xf0af0070 | ||
| 928 | #define F367TER_TPS_SETHPCODE 0xf0af0007 | ||
| 929 | |||
| 930 | /* TPS_CTL */ | ||
| 931 | #define R367TER_TPS_CTL 0xf0b0 | ||
| 932 | #define F367TER_TPS_IMM 0xf0b00004 | ||
| 933 | #define F367TER_TPS_BCHDIS 0xf0b00002 | ||
| 934 | #define F367TER_TPS_UPDDIS 0xf0b00001 | ||
| 935 | |||
| 936 | /* CTL_FFTOSNUM */ | ||
| 937 | #define R367TER_CTL_FFTOSNUM 0xf0b1 | ||
| 938 | #define F367TER_SYMBOL_NUMBER 0xf0b1007f | ||
| 939 | |||
| 940 | /* TESTSELECT */ | ||
| 941 | #define R367TER_TESTSELECT 0xf0b2 | ||
| 942 | #define F367TER_TEST_SELECT 0xf0b2001f | ||
| 943 | |||
| 944 | /* MSC_REV */ | ||
| 945 | #define R367TER_MSC_REV 0xf0b3 | ||
| 946 | #define F367TER_REV_NUMBER 0xf0b300ff | ||
| 947 | |||
| 948 | /* PIR_CTL */ | ||
| 949 | #define R367TER_PIR_CTL 0xf0b4 | ||
| 950 | #define F367TER_FREEZE 0xf0b40001 | ||
| 951 | |||
| 952 | /* SNR_CARRIER1 */ | ||
| 953 | #define R367TER_SNR_CARRIER1 0xf0b5 | ||
| 954 | #define F367TER_SNR_CARRIER_LO 0xf0b500ff | ||
| 955 | |||
| 956 | /* SNR_CARRIER2 */ | ||
| 957 | #define R367TER_SNR_CARRIER2 0xf0b6 | ||
| 958 | #define F367TER_MEAN 0xf0b600c0 | ||
| 959 | #define F367TER_SNR_CARRIER_HI 0xf0b6001f | ||
| 960 | |||
| 961 | /* PPM_CPAMP */ | ||
| 962 | #define R367TER_PPM_CPAMP 0xf0b7 | ||
| 963 | #define F367TER_PPM_CPC 0xf0b700ff | ||
| 964 | |||
| 965 | /* TSM_AP0 */ | ||
| 966 | #define R367TER_TSM_AP0 0xf0b8 | ||
| 967 | #define F367TER_ADDRESS_BYTE_0 0xf0b800ff | ||
| 968 | |||
| 969 | /* TSM_AP1 */ | ||
| 970 | #define R367TER_TSM_AP1 0xf0b9 | ||
| 971 | #define F367TER_ADDRESS_BYTE_1 0xf0b900ff | ||
| 972 | |||
| 973 | /* TSM_AP2 */ | ||
| 974 | #define R367TER_TSM_AP2 0xf0bA | ||
| 975 | #define F367TER_DATA_BYTE_0 0xf0ba00ff | ||
| 976 | |||
| 977 | /* TSM_AP3 */ | ||
| 978 | #define R367TER_TSM_AP3 0xf0bB | ||
| 979 | #define F367TER_DATA_BYTE_1 0xf0bb00ff | ||
| 980 | |||
| 981 | /* TSM_AP4 */ | ||
| 982 | #define R367TER_TSM_AP4 0xf0bC | ||
| 983 | #define F367TER_DATA_BYTE_2 0xf0bc00ff | ||
| 984 | |||
| 985 | /* TSM_AP5 */ | ||
| 986 | #define R367TER_TSM_AP5 0xf0bD | ||
| 987 | #define F367TER_DATA_BYTE_3 0xf0bd00ff | ||
| 988 | |||
| 989 | /* TSM_AP6 */ | ||
| 990 | #define R367TER_TSM_AP6 0xf0bE | ||
| 991 | #define F367TER_TSM_AP_6 0xf0be00ff | ||
| 992 | |||
| 993 | /* TSM_AP7 */ | ||
| 994 | #define R367TER_TSM_AP7 0xf0bF | ||
| 995 | #define F367TER_MEM_SELECT_BYTE 0xf0bf00ff | ||
| 996 | |||
| 997 | /* TSTRES */ | ||
| 998 | #define R367TER_TSTRES 0xf0c0 | ||
| 999 | #define F367TER_FRES_DISPLAY 0xf0c00080 | ||
| 1000 | #define F367TER_FRES_FIFO_AD 0xf0c00020 | ||
| 1001 | #define F367TER_FRESRS 0xf0c00010 | ||
| 1002 | #define F367TER_FRESACS 0xf0c00008 | ||
| 1003 | #define F367TER_FRESFEC 0xf0c00004 | ||
| 1004 | #define F367TER_FRES_PRIF 0xf0c00002 | ||
| 1005 | #define F367TER_FRESCORE 0xf0c00001 | ||
| 1006 | |||
| 1007 | /* ANACTRL */ | ||
| 1008 | #define R367TER_ANACTRL 0xf0c1 | ||
| 1009 | #define F367TER_BYPASS_XTAL 0xf0c10040 | ||
| 1010 | #define F367TER_BYPASS_PLLXN 0xf0c1000c | ||
| 1011 | #define F367TER_DIS_PAD_OSC 0xf0c10002 | ||
| 1012 | #define F367TER_STDBY_PLLXN 0xf0c10001 | ||
| 1013 | |||
| 1014 | /* TSTBUS */ | ||
| 1015 | #define R367TER_TSTBUS 0xf0c2 | ||
| 1016 | #define F367TER_TS_BYTE_CLK_INV 0xf0c20080 | ||
| 1017 | #define F367TER_CFG_IP 0xf0c20070 | ||
| 1018 | #define F367TER_CFG_TST 0xf0c2000f | ||
| 1019 | |||
| 1020 | /* TSTRATE */ | ||
| 1021 | #define R367TER_TSTRATE 0xf0c6 | ||
| 1022 | #define F367TER_FORCEPHA 0xf0c60080 | ||
| 1023 | #define F367TER_FNEWPHA 0xf0c60010 | ||
| 1024 | #define F367TER_FROT90 0xf0c60008 | ||
| 1025 | #define F367TER_FR 0xf0c60007 | ||
| 1026 | |||
| 1027 | /* CONSTMODE */ | ||
| 1028 | #define R367TER_CONSTMODE 0xf0cb | ||
| 1029 | #define F367TER_TST_PRIF 0xf0cb00e0 | ||
| 1030 | #define F367TER_CAR_TYPE 0xf0cb0018 | ||
| 1031 | #define F367TER_CONST_MODE 0xf0cb0003 | ||
| 1032 | |||
| 1033 | /* CONSTCARR1 */ | ||
| 1034 | #define R367TER_CONSTCARR1 0xf0cc | ||
| 1035 | #define F367TER_CONST_CARR_LO 0xf0cc00ff | ||
| 1036 | |||
| 1037 | /* CONSTCARR2 */ | ||
| 1038 | #define R367TER_CONSTCARR2 0xf0cd | ||
| 1039 | #define F367TER_CONST_CARR_HI 0xf0cd001f | ||
| 1040 | |||
| 1041 | /* ICONSTEL */ | ||
| 1042 | #define R367TER_ICONSTEL 0xf0ce | ||
| 1043 | #define F367TER_PICONSTEL 0xf0ce00ff | ||
| 1044 | |||
| 1045 | /* QCONSTEL */ | ||
| 1046 | #define R367TER_QCONSTEL 0xf0cf | ||
| 1047 | #define F367TER_PQCONSTEL 0xf0cf00ff | ||
| 1048 | |||
| 1049 | /* TSTBISTRES0 */ | ||
| 1050 | #define R367TER_TSTBISTRES0 0xf0d0 | ||
| 1051 | #define F367TER_BEND_PPM 0xf0d00080 | ||
| 1052 | #define F367TER_BBAD_PPM 0xf0d00040 | ||
| 1053 | #define F367TER_BEND_FFTW 0xf0d00020 | ||
| 1054 | #define F367TER_BBAD_FFTW 0xf0d00010 | ||
| 1055 | #define F367TER_BEND_FFT_BUF 0xf0d00008 | ||
| 1056 | #define F367TER_BBAD_FFT_BUF 0xf0d00004 | ||
| 1057 | #define F367TER_BEND_SYR 0xf0d00002 | ||
| 1058 | #define F367TER_BBAD_SYR 0xf0d00001 | ||
| 1059 | |||
| 1060 | /* TSTBISTRES1 */ | ||
| 1061 | #define R367TER_TSTBISTRES1 0xf0d1 | ||
| 1062 | #define F367TER_BEND_CHC_CP 0xf0d10080 | ||
| 1063 | #define F367TER_BBAD_CHC_CP 0xf0d10040 | ||
| 1064 | #define F367TER_BEND_CHCI 0xf0d10020 | ||
| 1065 | #define F367TER_BBAD_CHCI 0xf0d10010 | ||
| 1066 | #define F367TER_BEND_BDI 0xf0d10008 | ||
| 1067 | #define F367TER_BBAD_BDI 0xf0d10004 | ||
| 1068 | #define F367TER_BEND_SDI 0xf0d10002 | ||
| 1069 | #define F367TER_BBAD_SDI 0xf0d10001 | ||
| 1070 | |||
| 1071 | /* TSTBISTRES2 */ | ||
| 1072 | #define R367TER_TSTBISTRES2 0xf0d2 | ||
| 1073 | #define F367TER_BEND_CHC_INC 0xf0d20080 | ||
| 1074 | #define F367TER_BBAD_CHC_INC 0xf0d20040 | ||
| 1075 | #define F367TER_BEND_CHC_SPP 0xf0d20020 | ||
| 1076 | #define F367TER_BBAD_CHC_SPP 0xf0d20010 | ||
| 1077 | #define F367TER_BEND_CHC_CPP 0xf0d20008 | ||
| 1078 | #define F367TER_BBAD_CHC_CPP 0xf0d20004 | ||
| 1079 | #define F367TER_BEND_CHC_SP 0xf0d20002 | ||
| 1080 | #define F367TER_BBAD_CHC_SP 0xf0d20001 | ||
| 1081 | |||
| 1082 | /* TSTBISTRES3 */ | ||
| 1083 | #define R367TER_TSTBISTRES3 0xf0d3 | ||
| 1084 | #define F367TER_BEND_QAM 0xf0d30080 | ||
| 1085 | #define F367TER_BBAD_QAM 0xf0d30040 | ||
| 1086 | #define F367TER_BEND_SFEC_VIT 0xf0d30020 | ||
| 1087 | #define F367TER_BBAD_SFEC_VIT 0xf0d30010 | ||
| 1088 | #define F367TER_BEND_SFEC_DLINE 0xf0d30008 | ||
| 1089 | #define F367TER_BBAD_SFEC_DLINE 0xf0d30004 | ||
| 1090 | #define F367TER_BEND_SFEC_HW 0xf0d30002 | ||
| 1091 | #define F367TER_BBAD_SFEC_HW 0xf0d30001 | ||
| 1092 | |||
| 1093 | /* RF_AGC1 */ | ||
| 1094 | #define R367TER_RF_AGC1 0xf0d4 | ||
| 1095 | #define F367TER_RF_AGC1_LEVEL_HI 0xf0d400ff | ||
| 1096 | |||
| 1097 | /* RF_AGC2 */ | ||
| 1098 | #define R367TER_RF_AGC2 0xf0d5 | ||
| 1099 | #define F367TER_REF_ADGP 0xf0d50080 | ||
| 1100 | #define F367TER_STDBY_ADCGP 0xf0d50020 | ||
| 1101 | #define F367TER_CHANNEL_SEL 0xf0d5001c | ||
| 1102 | #define F367TER_RF_AGC1_LEVEL_LO 0xf0d50003 | ||
| 1103 | |||
| 1104 | /* ANADIGCTRL */ | ||
| 1105 | #define R367TER_ANADIGCTRL 0xf0d7 | ||
| 1106 | #define F367TER_SEL_CLKDEM 0xf0d70020 | ||
| 1107 | #define F367TER_EN_BUFFER_Q 0xf0d70010 | ||
| 1108 | #define F367TER_EN_BUFFER_I 0xf0d70008 | ||
| 1109 | #define F367TER_ADC_RIS_EGDE 0xf0d70004 | ||
| 1110 | #define F367TER_SGN_ADC 0xf0d70002 | ||
| 1111 | #define F367TER_SEL_AD12_SYNC 0xf0d70001 | ||
| 1112 | |||
| 1113 | /* PLLMDIV */ | ||
| 1114 | #define R367TER_PLLMDIV 0xf0d8 | ||
| 1115 | #define F367TER_PLL_MDIV 0xf0d800ff | ||
| 1116 | |||
| 1117 | /* PLLNDIV */ | ||
| 1118 | #define R367TER_PLLNDIV 0xf0d9 | ||
| 1119 | #define F367TER_PLL_NDIV 0xf0d900ff | ||
| 1120 | |||
| 1121 | /* PLLSETUP */ | ||
| 1122 | #define R367TER_PLLSETUP 0xf0dA | ||
| 1123 | #define F367TER_PLL_PDIV 0xf0da0070 | ||
| 1124 | #define F367TER_PLL_KDIV 0xf0da000f | ||
| 1125 | |||
| 1126 | /* DUAL_AD12 */ | ||
| 1127 | #define R367TER_DUAL_AD12 0xf0dB | ||
| 1128 | #define F367TER_FS20M 0xf0db0020 | ||
| 1129 | #define F367TER_FS50M 0xf0db0010 | ||
| 1130 | #define F367TER_INMODe0 0xf0db0008 | ||
| 1131 | #define F367TER_POFFQ 0xf0db0004 | ||
| 1132 | #define F367TER_POFFI 0xf0db0002 | ||
| 1133 | #define F367TER_INMODE1 0xf0db0001 | ||
| 1134 | |||
| 1135 | /* TSTBIST */ | ||
| 1136 | #define R367TER_TSTBIST 0xf0dC | ||
| 1137 | #define F367TER_TST_BYP_CLK 0xf0dc0080 | ||
| 1138 | #define F367TER_TST_GCLKENA_STD 0xf0dc0040 | ||
| 1139 | #define F367TER_TST_GCLKENA 0xf0dc0020 | ||
| 1140 | #define F367TER_TST_MEMBIST 0xf0dc001f | ||
| 1141 | |||
| 1142 | /* PAD_COMP_CTRL */ | ||
| 1143 | #define R367TER_PAD_COMP_CTRL 0xf0dD | ||
| 1144 | #define F367TER_COMPTQ 0xf0dd0010 | ||
| 1145 | #define F367TER_COMPEN 0xf0dd0008 | ||
| 1146 | #define F367TER_FREEZE2 0xf0dd0004 | ||
| 1147 | #define F367TER_SLEEP_INHBT 0xf0dd0002 | ||
| 1148 | #define F367TER_CHIP_SLEEP 0xf0dd0001 | ||
| 1149 | |||
| 1150 | /* PAD_COMP_WR */ | ||
| 1151 | #define R367TER_PAD_COMP_WR 0xf0de | ||
| 1152 | #define F367TER_WR_ASRC 0xf0de007f | ||
| 1153 | |||
| 1154 | /* PAD_COMP_RD */ | ||
| 1155 | #define R367TER_PAD_COMP_RD 0xf0df | ||
| 1156 | #define F367TER_COMPOK 0xf0df0080 | ||
| 1157 | #define F367TER_RD_ASRC 0xf0df007f | ||
| 1158 | |||
| 1159 | /* SYR_TARGET_FFTADJT_MSB */ | ||
| 1160 | #define R367TER_SYR_TARGET_FFTADJT_MSB 0xf100 | ||
| 1161 | #define F367TER_SYR_START 0xf1000080 | ||
| 1162 | #define F367TER_SYR_TARGET_FFTADJ_HI 0xf100000f | ||
| 1163 | |||
| 1164 | /* SYR_TARGET_FFTADJT_LSB */ | ||
| 1165 | #define R367TER_SYR_TARGET_FFTADJT_LSB 0xf101 | ||
| 1166 | #define F367TER_SYR_TARGET_FFTADJ_LO 0xf10100ff | ||
| 1167 | |||
| 1168 | /* SYR_TARGET_CHCADJT_MSB */ | ||
| 1169 | #define R367TER_SYR_TARGET_CHCADJT_MSB 0xf102 | ||
| 1170 | #define F367TER_SYR_TARGET_CHCADJ_HI 0xf102000f | ||
| 1171 | |||
| 1172 | /* SYR_TARGET_CHCADJT_LSB */ | ||
| 1173 | #define R367TER_SYR_TARGET_CHCADJT_LSB 0xf103 | ||
| 1174 | #define F367TER_SYR_TARGET_CHCADJ_LO 0xf10300ff | ||
| 1175 | |||
| 1176 | /* SYR_FLAG */ | ||
| 1177 | #define R367TER_SYR_FLAG 0xf104 | ||
| 1178 | #define F367TER_TRIG_FLG1 0xf1040080 | ||
| 1179 | #define F367TER_TRIG_FLG0 0xf1040040 | ||
| 1180 | #define F367TER_FFT_FLG1 0xf1040008 | ||
| 1181 | #define F367TER_FFT_FLG0 0xf1040004 | ||
| 1182 | #define F367TER_CHC_FLG1 0xf1040002 | ||
| 1183 | #define F367TER_CHC_FLG0 0xf1040001 | ||
| 1184 | |||
| 1185 | /* CRL_TARGET1 */ | ||
| 1186 | #define R367TER_CRL_TARGET1 0xf105 | ||
| 1187 | #define F367TER_CRL_START 0xf1050080 | ||
| 1188 | #define F367TER_CRL_TARGET_VHI 0xf105000f | ||
| 1189 | |||
| 1190 | /* CRL_TARGET2 */ | ||
| 1191 | #define R367TER_CRL_TARGET2 0xf106 | ||
| 1192 | #define F367TER_CRL_TARGET_HI 0xf10600ff | ||
| 1193 | |||
| 1194 | /* CRL_TARGET3 */ | ||
| 1195 | #define R367TER_CRL_TARGET3 0xf107 | ||
| 1196 | #define F367TER_CRL_TARGET_LO 0xf10700ff | ||
| 1197 | |||
| 1198 | /* CRL_TARGET4 */ | ||
| 1199 | #define R367TER_CRL_TARGET4 0xf108 | ||
| 1200 | #define F367TER_CRL_TARGET_VLO 0xf10800ff | ||
| 1201 | |||
| 1202 | /* CRL_FLAG */ | ||
| 1203 | #define R367TER_CRL_FLAG 0xf109 | ||
| 1204 | #define F367TER_CRL_FLAG1 0xf1090002 | ||
| 1205 | #define F367TER_CRL_FLAG0 0xf1090001 | ||
| 1206 | |||
| 1207 | /* TRL_TARGET1 */ | ||
| 1208 | #define R367TER_TRL_TARGET1 0xf10a | ||
| 1209 | #define F367TER_TRL_TARGET_HI 0xf10a00ff | ||
| 1210 | |||
| 1211 | /* TRL_TARGET2 */ | ||
| 1212 | #define R367TER_TRL_TARGET2 0xf10b | ||
| 1213 | #define F367TER_TRL_TARGET_LO 0xf10b00ff | ||
| 1214 | |||
| 1215 | /* TRL_CHC */ | ||
| 1216 | #define R367TER_TRL_CHC 0xf10c | ||
| 1217 | #define F367TER_TRL_START 0xf10c0080 | ||
| 1218 | #define F367TER_CHC_START 0xf10c0040 | ||
| 1219 | #define F367TER_TRL_FLAG1 0xf10c0002 | ||
| 1220 | #define F367TER_TRL_FLAG0 0xf10c0001 | ||
| 1221 | |||
| 1222 | /* CHC_SNR_TARG */ | ||
| 1223 | #define R367TER_CHC_SNR_TARG 0xf10d | ||
| 1224 | #define F367TER_CHC_SNR_TARGET 0xf10d00ff | ||
| 1225 | |||
| 1226 | /* TOP_TRACK */ | ||
| 1227 | #define R367TER_TOP_TRACK 0xf10e | ||
| 1228 | #define F367TER_TOP_START 0xf10e0080 | ||
| 1229 | #define F367TER_FIRST_FLAG 0xf10e0070 | ||
| 1230 | #define F367TER_TOP_FLAG1 0xf10e0008 | ||
| 1231 | #define F367TER_TOP_FLAG0 0xf10e0004 | ||
| 1232 | #define F367TER_CHC_FLAG1 0xf10e0002 | ||
| 1233 | #define F367TER_CHC_FLAG0 0xf10e0001 | ||
| 1234 | |||
| 1235 | /* TRACKER_FREE1 */ | ||
| 1236 | #define R367TER_TRACKER_FREE1 0xf10f | ||
| 1237 | #define F367TER_TRACKER_FREE_1 0xf10f00ff | ||
| 1238 | |||
| 1239 | /* ERROR_CRL1 */ | ||
| 1240 | #define R367TER_ERROR_CRL1 0xf110 | ||
| 1241 | #define F367TER_ERROR_CRL_VHI 0xf11000ff | ||
| 1242 | |||
| 1243 | /* ERROR_CRL2 */ | ||
| 1244 | #define R367TER_ERROR_CRL2 0xf111 | ||
| 1245 | #define F367TER_ERROR_CRL_HI 0xf11100ff | ||
| 1246 | |||
| 1247 | /* ERROR_CRL3 */ | ||
| 1248 | #define R367TER_ERROR_CRL3 0xf112 | ||
| 1249 | #define F367TER_ERROR_CRL_LOI 0xf11200ff | ||
| 1250 | |||
| 1251 | /* ERROR_CRL4 */ | ||
| 1252 | #define R367TER_ERROR_CRL4 0xf113 | ||
| 1253 | #define F367TER_ERROR_CRL_VLO 0xf11300ff | ||
| 1254 | |||
| 1255 | /* DEC_NCO1 */ | ||
| 1256 | #define R367TER_DEC_NCO1 0xf114 | ||
| 1257 | #define F367TER_DEC_NCO_VHI 0xf11400ff | ||
| 1258 | |||
| 1259 | /* DEC_NCO2 */ | ||
| 1260 | #define R367TER_DEC_NCO2 0xf115 | ||
| 1261 | #define F367TER_DEC_NCO_HI 0xf11500ff | ||
| 1262 | |||
| 1263 | /* DEC_NCO3 */ | ||
| 1264 | #define R367TER_DEC_NCO3 0xf116 | ||
| 1265 | #define F367TER_DEC_NCO_LO 0xf11600ff | ||
| 1266 | |||
| 1267 | /* SNR */ | ||
| 1268 | #define R367TER_SNR 0xf117 | ||
| 1269 | #define F367TER_SNRATIO 0xf11700ff | ||
| 1270 | |||
| 1271 | /* SYR_FFTADJ1 */ | ||
| 1272 | #define R367TER_SYR_FFTADJ1 0xf118 | ||
| 1273 | #define F367TER_SYR_FFTADJ_HI 0xf11800ff | ||
| 1274 | |||
| 1275 | /* SYR_FFTADJ2 */ | ||
| 1276 | #define R367TER_SYR_FFTADJ2 0xf119 | ||
| 1277 | #define F367TER_SYR_FFTADJ_LO 0xf11900ff | ||
| 1278 | |||
| 1279 | /* SYR_CHCADJ1 */ | ||
| 1280 | #define R367TER_SYR_CHCADJ1 0xf11a | ||
| 1281 | #define F367TER_SYR_CHCADJ_HI 0xf11a00ff | ||
| 1282 | |||
| 1283 | /* SYR_CHCADJ2 */ | ||
| 1284 | #define R367TER_SYR_CHCADJ2 0xf11b | ||
| 1285 | #define F367TER_SYR_CHCADJ_LO 0xf11b00ff | ||
| 1286 | |||
| 1287 | /* SYR_OFF */ | ||
| 1288 | #define R367TER_SYR_OFF 0xf11c | ||
| 1289 | #define F367TER_SYR_OFFSET 0xf11c00ff | ||
| 1290 | |||
| 1291 | /* PPM_OFFSET1 */ | ||
| 1292 | #define R367TER_PPM_OFFSET1 0xf11d | ||
| 1293 | #define F367TER_PPM_OFFSET_HI 0xf11d00ff | ||
| 1294 | |||
| 1295 | /* PPM_OFFSET2 */ | ||
| 1296 | #define R367TER_PPM_OFFSET2 0xf11e | ||
| 1297 | #define F367TER_PPM_OFFSET_LO 0xf11e00ff | ||
| 1298 | |||
| 1299 | /* TRACKER_FREE2 */ | ||
| 1300 | #define R367TER_TRACKER_FREE2 0xf11f | ||
| 1301 | #define F367TER_TRACKER_FREE_2 0xf11f00ff | ||
| 1302 | |||
| 1303 | /* DEBG_LT10 */ | ||
| 1304 | #define R367TER_DEBG_LT10 0xf120 | ||
| 1305 | #define F367TER_DEBUG_LT10 0xf12000ff | ||
| 1306 | |||
| 1307 | /* DEBG_LT11 */ | ||
| 1308 | #define R367TER_DEBG_LT11 0xf121 | ||
| 1309 | #define F367TER_DEBUG_LT11 0xf12100ff | ||
| 1310 | |||
| 1311 | /* DEBG_LT12 */ | ||
| 1312 | #define R367TER_DEBG_LT12 0xf122 | ||
| 1313 | #define F367TER_DEBUG_LT12 0xf12200ff | ||
| 1314 | |||
| 1315 | /* DEBG_LT13 */ | ||
| 1316 | #define R367TER_DEBG_LT13 0xf123 | ||
| 1317 | #define F367TER_DEBUG_LT13 0xf12300ff | ||
| 1318 | |||
| 1319 | /* DEBG_LT14 */ | ||
| 1320 | #define R367TER_DEBG_LT14 0xf124 | ||
| 1321 | #define F367TER_DEBUG_LT14 0xf12400ff | ||
| 1322 | |||
| 1323 | /* DEBG_LT15 */ | ||
| 1324 | #define R367TER_DEBG_LT15 0xf125 | ||
| 1325 | #define F367TER_DEBUG_LT15 0xf12500ff | ||
| 1326 | |||
| 1327 | /* DEBG_LT16 */ | ||
| 1328 | #define R367TER_DEBG_LT16 0xf126 | ||
| 1329 | #define F367TER_DEBUG_LT16 0xf12600ff | ||
| 1330 | |||
| 1331 | /* DEBG_LT17 */ | ||
| 1332 | #define R367TER_DEBG_LT17 0xf127 | ||
| 1333 | #define F367TER_DEBUG_LT17 0xf12700ff | ||
| 1334 | |||
| 1335 | /* DEBG_LT18 */ | ||
| 1336 | #define R367TER_DEBG_LT18 0xf128 | ||
| 1337 | #define F367TER_DEBUG_LT18 0xf12800ff | ||
| 1338 | |||
| 1339 | /* DEBG_LT19 */ | ||
| 1340 | #define R367TER_DEBG_LT19 0xf129 | ||
| 1341 | #define F367TER_DEBUG_LT19 0xf12900ff | ||
| 1342 | |||
| 1343 | /* DEBG_LT1a */ | ||
| 1344 | #define R367TER_DEBG_LT1A 0xf12a | ||
| 1345 | #define F367TER_DEBUG_LT1A 0xf12a00ff | ||
| 1346 | |||
| 1347 | /* DEBG_LT1b */ | ||
| 1348 | #define R367TER_DEBG_LT1B 0xf12b | ||
| 1349 | #define F367TER_DEBUG_LT1B 0xf12b00ff | ||
| 1350 | |||
| 1351 | /* DEBG_LT1c */ | ||
| 1352 | #define R367TER_DEBG_LT1C 0xf12c | ||
| 1353 | #define F367TER_DEBUG_LT1C 0xf12c00ff | ||
| 1354 | |||
| 1355 | /* DEBG_LT1D */ | ||
| 1356 | #define R367TER_DEBG_LT1D 0xf12d | ||
| 1357 | #define F367TER_DEBUG_LT1D 0xf12d00ff | ||
| 1358 | |||
| 1359 | /* DEBG_LT1E */ | ||
| 1360 | #define R367TER_DEBG_LT1E 0xf12e | ||
| 1361 | #define F367TER_DEBUG_LT1E 0xf12e00ff | ||
| 1362 | |||
| 1363 | /* DEBG_LT1F */ | ||
| 1364 | #define R367TER_DEBG_LT1F 0xf12f | ||
| 1365 | #define F367TER_DEBUG_LT1F 0xf12f00ff | ||
| 1366 | |||
| 1367 | /* RCCFGH */ | ||
| 1368 | #define R367TER_RCCFGH 0xf200 | ||
| 1369 | #define F367TER_TSRCFIFO_DVBCI 0xf2000080 | ||
| 1370 | #define F367TER_TSRCFIFO_SERIAL 0xf2000040 | ||
| 1371 | #define F367TER_TSRCFIFO_DISABLE 0xf2000020 | ||
| 1372 | #define F367TER_TSFIFO_2TORC 0xf2000010 | ||
| 1373 | #define F367TER_TSRCFIFO_HSGNLOUT 0xf2000008 | ||
| 1374 | #define F367TER_TSRCFIFO_ERRMODE 0xf2000006 | ||
| 1375 | #define F367TER_RCCFGH_0 0xf2000001 | ||
| 1376 | |||
| 1377 | /* RCCFGM */ | ||
| 1378 | #define R367TER_RCCFGM 0xf201 | ||
| 1379 | #define F367TER_TSRCFIFO_MANSPEED 0xf20100c0 | ||
| 1380 | #define F367TER_TSRCFIFO_PERMDATA 0xf2010020 | ||
| 1381 | #define F367TER_TSRCFIFO_NONEWSGNL 0xf2010010 | ||
| 1382 | #define F367TER_RCBYTE_OVERSAMPLING 0xf201000e | ||
| 1383 | #define F367TER_TSRCFIFO_INVDATA 0xf2010001 | ||
| 1384 | |||
| 1385 | /* RCCFGL */ | ||
| 1386 | #define R367TER_RCCFGL 0xf202 | ||
| 1387 | #define F367TER_TSRCFIFO_BCLKDEL1cK 0xf20200c0 | ||
| 1388 | #define F367TER_RCCFGL_5 0xf2020020 | ||
| 1389 | #define F367TER_TSRCFIFO_DUTY50 0xf2020010 | ||
| 1390 | #define F367TER_TSRCFIFO_NSGNL2dATA 0xf2020008 | ||
| 1391 | #define F367TER_TSRCFIFO_DISSERMUX 0xf2020004 | ||
| 1392 | #define F367TER_RCCFGL_1 0xf2020002 | ||
| 1393 | #define F367TER_TSRCFIFO_STOPCKDIS 0xf2020001 | ||
| 1394 | |||
| 1395 | /* RCINSDELH */ | ||
| 1396 | #define R367TER_RCINSDELH 0xf203 | ||
| 1397 | #define F367TER_TSRCDEL_SYNCBYTE 0xf2030080 | ||
| 1398 | #define F367TER_TSRCDEL_XXHEADER 0xf2030040 | ||
| 1399 | #define F367TER_TSRCDEL_BBHEADER 0xf2030020 | ||
| 1400 | #define F367TER_TSRCDEL_DATAFIELD 0xf2030010 | ||
| 1401 | #define F367TER_TSRCINSDEL_ISCR 0xf2030008 | ||
| 1402 | #define F367TER_TSRCINSDEL_NPD 0xf2030004 | ||
| 1403 | #define F367TER_TSRCINSDEL_RSPARITY 0xf2030002 | ||
| 1404 | #define F367TER_TSRCINSDEL_CRC8 0xf2030001 | ||
| 1405 | |||
| 1406 | /* RCINSDELM */ | ||
| 1407 | #define R367TER_RCINSDELM 0xf204 | ||
| 1408 | #define F367TER_TSRCINS_BBPADDING 0xf2040080 | ||
| 1409 | #define F367TER_TSRCINS_BCHFEC 0xf2040040 | ||
| 1410 | #define F367TER_TSRCINS_LDPCFEC 0xf2040020 | ||
| 1411 | #define F367TER_TSRCINS_EMODCOD 0xf2040010 | ||
| 1412 | #define F367TER_TSRCINS_TOKEN 0xf2040008 | ||
| 1413 | #define F367TER_TSRCINS_XXXERR 0xf2040004 | ||
| 1414 | #define F367TER_TSRCINS_MATYPE 0xf2040002 | ||
| 1415 | #define F367TER_TSRCINS_UPL 0xf2040001 | ||
| 1416 | |||
| 1417 | /* RCINSDELL */ | ||
| 1418 | #define R367TER_RCINSDELL 0xf205 | ||
| 1419 | #define F367TER_TSRCINS_DFL 0xf2050080 | ||
| 1420 | #define F367TER_TSRCINS_SYNCD 0xf2050040 | ||
| 1421 | #define F367TER_TSRCINS_BLOCLEN 0xf2050020 | ||
| 1422 | #define F367TER_TSRCINS_SIGPCOUNT 0xf2050010 | ||
| 1423 | #define F367TER_TSRCINS_FIFO 0xf2050008 | ||
| 1424 | #define F367TER_TSRCINS_REALPACK 0xf2050004 | ||
| 1425 | #define F367TER_TSRCINS_TSCONFIG 0xf2050002 | ||
| 1426 | #define F367TER_TSRCINS_LATENCY 0xf2050001 | ||
| 1427 | |||
| 1428 | /* RCSTATUS */ | ||
| 1429 | #define R367TER_RCSTATUS 0xf206 | ||
| 1430 | #define F367TER_TSRCFIFO_LINEOK 0xf2060080 | ||
| 1431 | #define F367TER_TSRCFIFO_ERROR 0xf2060040 | ||
| 1432 | #define F367TER_TSRCFIFO_DATA7 0xf2060020 | ||
| 1433 | #define F367TER_RCSTATUS_4 0xf2060010 | ||
| 1434 | #define F367TER_TSRCFIFO_DEMODSEL 0xf2060008 | ||
| 1435 | #define F367TER_TSRC1FIFOSPEED_STORE 0xf2060004 | ||
| 1436 | #define F367TER_RCSTATUS_1 0xf2060002 | ||
| 1437 | #define F367TER_TSRCSERIAL_IMPOSSIBLE 0xf2060001 | ||
| 1438 | |||
| 1439 | /* RCSPEED */ | ||
| 1440 | #define R367TER_RCSPEED 0xf207 | ||
| 1441 | #define F367TER_TSRCFIFO_OUTSPEED 0xf20700ff | ||
| 1442 | |||
| 1443 | /* RCDEBUGM */ | ||
| 1444 | #define R367TER_RCDEBUGM 0xf208 | ||
| 1445 | #define F367TER_SD_UNSYNC 0xf2080080 | ||
| 1446 | #define F367TER_ULFLOCK_DETECTM 0xf2080040 | ||
| 1447 | #define F367TER_SUL_SELECTOS 0xf2080020 | ||
| 1448 | #define F367TER_DILUL_NOSCRBLE 0xf2080010 | ||
| 1449 | #define F367TER_NUL_SCRB 0xf2080008 | ||
| 1450 | #define F367TER_UL_SCRB 0xf2080004 | ||
| 1451 | #define F367TER_SCRAULBAD 0xf2080002 | ||
| 1452 | #define F367TER_SCRAUL_UNSYNC 0xf2080001 | ||
| 1453 | |||
| 1454 | /* RCDEBUGL */ | ||
| 1455 | #define R367TER_RCDEBUGL 0xf209 | ||
| 1456 | #define F367TER_RS_ERR 0xf2090080 | ||
| 1457 | #define F367TER_LLFLOCK_DETECTM 0xf2090040 | ||
| 1458 | #define F367TER_NOT_SUL_SELECTOS 0xf2090020 | ||
| 1459 | #define F367TER_DILLL_NOSCRBLE 0xf2090010 | ||
| 1460 | #define F367TER_NLL_SCRB 0xf2090008 | ||
| 1461 | #define F367TER_LL_SCRB 0xf2090004 | ||
| 1462 | #define F367TER_SCRALLBAD 0xf2090002 | ||
| 1463 | #define F367TER_SCRALL_UNSYNC 0xf2090001 | ||
| 1464 | |||
| 1465 | /* RCOBSCFG */ | ||
| 1466 | #define R367TER_RCOBSCFG 0xf20a | ||
| 1467 | #define F367TER_TSRCFIFO_OBSCFG 0xf20a00ff | ||
| 1468 | |||
| 1469 | /* RCOBSM */ | ||
| 1470 | #define R367TER_RCOBSM 0xf20b | ||
| 1471 | #define F367TER_TSRCFIFO_OBSDATA_HI 0xf20b00ff | ||
| 1472 | |||
| 1473 | /* RCOBSL */ | ||
| 1474 | #define R367TER_RCOBSL 0xf20c | ||
| 1475 | #define F367TER_TSRCFIFO_OBSDATA_LO 0xf20c00ff | ||
| 1476 | |||
| 1477 | /* RCFECSPY */ | ||
| 1478 | #define R367TER_RCFECSPY 0xf210 | ||
| 1479 | #define F367TER_SPYRC_ENABLE 0xf2100080 | ||
| 1480 | #define F367TER_RCNO_SYNCBYTE 0xf2100040 | ||
| 1481 | #define F367TER_RCSERIAL_MODE 0xf2100020 | ||
| 1482 | #define F367TER_RCUNUSUAL_PACKET 0xf2100010 | ||
| 1483 | #define F367TER_BERRCMETER_DATAMODE 0xf210000c | ||
| 1484 | #define F367TER_BERRCMETER_LMODE 0xf2100002 | ||
| 1485 | #define F367TER_BERRCMETER_RESET 0xf2100001 | ||
| 1486 | |||
| 1487 | /* RCFSPYCFG */ | ||
| 1488 | #define R367TER_RCFSPYCFG 0xf211 | ||
| 1489 | #define F367TER_FECSPYRC_INPUT 0xf21100c0 | ||
| 1490 | #define F367TER_RCRST_ON_ERROR 0xf2110020 | ||
| 1491 | #define F367TER_RCONE_SHOT 0xf2110010 | ||
| 1492 | #define F367TER_RCI2C_MODE 0xf211000c | ||
| 1493 | #define F367TER_SPYRC_HSTERESIS 0xf2110003 | ||
| 1494 | |||
| 1495 | /* RCFSPYDATA */ | ||
| 1496 | #define R367TER_RCFSPYDATA 0xf212 | ||
| 1497 | #define F367TER_SPYRC_STUFFING 0xf2120080 | ||
| 1498 | #define F367TER_RCNOERR_PKTJITTER 0xf2120040 | ||
| 1499 | #define F367TER_SPYRC_CNULLPKT 0xf2120020 | ||
| 1500 | #define F367TER_SPYRC_OUTDATA_MODE 0xf212001f | ||
| 1501 | |||
| 1502 | /* RCFSPYOUT */ | ||
| 1503 | #define R367TER_RCFSPYOUT 0xf213 | ||
| 1504 | #define F367TER_FSPYRC_DIRECT 0xf2130080 | ||
| 1505 | #define F367TER_RCFSPYOUT_6 0xf2130040 | ||
| 1506 | #define F367TER_SPYRC_OUTDATA_BUS 0xf2130038 | ||
| 1507 | #define F367TER_RCSTUFF_MODE 0xf2130007 | ||
| 1508 | |||
| 1509 | /* RCFSTATUS */ | ||
| 1510 | #define R367TER_RCFSTATUS 0xf214 | ||
| 1511 | #define F367TER_SPYRC_ENDSIM 0xf2140080 | ||
| 1512 | #define F367TER_RCVALID_SIM 0xf2140040 | ||
| 1513 | #define F367TER_RCFOUND_SIGNAL 0xf2140020 | ||
| 1514 | #define F367TER_RCDSS_SYNCBYTE 0xf2140010 | ||
| 1515 | #define F367TER_RCRESULT_STATE 0xf214000f | ||
| 1516 | |||
| 1517 | /* RCFGOODPACK */ | ||
| 1518 | #define R367TER_RCFGOODPACK 0xf215 | ||
| 1519 | #define F367TER_RCGOOD_PACKET 0xf21500ff | ||
| 1520 | |||
| 1521 | /* RCFPACKCNT */ | ||
| 1522 | #define R367TER_RCFPACKCNT 0xf216 | ||
| 1523 | #define F367TER_RCPACKET_COUNTER 0xf21600ff | ||
| 1524 | |||
| 1525 | /* RCFSPYMISC */ | ||
| 1526 | #define R367TER_RCFSPYMISC 0xf217 | ||
| 1527 | #define F367TER_RCLABEL_COUNTER 0xf21700ff | ||
| 1528 | |||
| 1529 | /* RCFBERCPT4 */ | ||
| 1530 | #define R367TER_RCFBERCPT4 0xf218 | ||
| 1531 | #define F367TER_FBERRCMETER_CPT_MMMMSB 0xf21800ff | ||
| 1532 | |||
| 1533 | /* RCFBERCPT3 */ | ||
| 1534 | #define R367TER_RCFBERCPT3 0xf219 | ||
| 1535 | #define F367TER_FBERRCMETER_CPT_MMMSB 0xf21900ff | ||
| 1536 | |||
| 1537 | /* RCFBERCPT2 */ | ||
| 1538 | #define R367TER_RCFBERCPT2 0xf21a | ||
| 1539 | #define F367TER_FBERRCMETER_CPT_MMSB 0xf21a00ff | ||
| 1540 | |||
| 1541 | /* RCFBERCPT1 */ | ||
| 1542 | #define R367TER_RCFBERCPT1 0xf21b | ||
| 1543 | #define F367TER_FBERRCMETER_CPT_MSB 0xf21b00ff | ||
| 1544 | |||
| 1545 | /* RCFBERCPT0 */ | ||
| 1546 | #define R367TER_RCFBERCPT0 0xf21c | ||
| 1547 | #define F367TER_FBERRCMETER_CPT_LSB 0xf21c00ff | ||
| 1548 | |||
| 1549 | /* RCFBERERR2 */ | ||
| 1550 | #define R367TER_RCFBERERR2 0xf21d | ||
| 1551 | #define F367TER_FBERRCMETER_ERR_HI 0xf21d00ff | ||
| 1552 | |||
| 1553 | /* RCFBERERR1 */ | ||
| 1554 | #define R367TER_RCFBERERR1 0xf21e | ||
| 1555 | #define F367TER_FBERRCMETER_ERR 0xf21e00ff | ||
| 1556 | |||
| 1557 | /* RCFBERERR0 */ | ||
| 1558 | #define R367TER_RCFBERERR0 0xf21f | ||
| 1559 | #define F367TER_FBERRCMETER_ERR_LO 0xf21f00ff | ||
| 1560 | |||
| 1561 | /* RCFSTATESM */ | ||
| 1562 | #define R367TER_RCFSTATESM 0xf220 | ||
| 1563 | #define F367TER_RCRSTATE_F 0xf2200080 | ||
| 1564 | #define F367TER_RCRSTATE_E 0xf2200040 | ||
| 1565 | #define F367TER_RCRSTATE_D 0xf2200020 | ||
| 1566 | #define F367TER_RCRSTATE_C 0xf2200010 | ||
| 1567 | #define F367TER_RCRSTATE_B 0xf2200008 | ||
| 1568 | #define F367TER_RCRSTATE_A 0xf2200004 | ||
| 1569 | #define F367TER_RCRSTATE_9 0xf2200002 | ||
| 1570 | #define F367TER_RCRSTATE_8 0xf2200001 | ||
| 1571 | |||
| 1572 | /* RCFSTATESL */ | ||
| 1573 | #define R367TER_RCFSTATESL 0xf221 | ||
| 1574 | #define F367TER_RCRSTATE_7 0xf2210080 | ||
| 1575 | #define F367TER_RCRSTATE_6 0xf2210040 | ||
| 1576 | #define F367TER_RCRSTATE_5 0xf2210020 | ||
| 1577 | #define F367TER_RCRSTATE_4 0xf2210010 | ||
| 1578 | #define F367TER_RCRSTATE_3 0xf2210008 | ||
| 1579 | #define F367TER_RCRSTATE_2 0xf2210004 | ||
| 1580 | #define F367TER_RCRSTATE_1 0xf2210002 | ||
| 1581 | #define F367TER_RCRSTATE_0 0xf2210001 | ||
| 1582 | |||
| 1583 | /* RCFSPYBER */ | ||
| 1584 | #define R367TER_RCFSPYBER 0xf222 | ||
| 1585 | #define F367TER_RCFSPYBER_7 0xf2220080 | ||
| 1586 | #define F367TER_SPYRCOBS_XORREAD 0xf2220040 | ||
| 1587 | #define F367TER_FSPYRCBER_OBSMODE 0xf2220020 | ||
| 1588 | #define F367TER_FSPYRCBER_SYNCBYT 0xf2220010 | ||
| 1589 | #define F367TER_FSPYRCBER_UNSYNC 0xf2220008 | ||
| 1590 | #define F367TER_FSPYRCBER_CTIME 0xf2220007 | ||
| 1591 | |||
| 1592 | /* RCFSPYDISTM */ | ||
| 1593 | #define R367TER_RCFSPYDISTM 0xf223 | ||
| 1594 | #define F367TER_RCPKTTIME_DISTANCE_HI 0xf22300ff | ||
| 1595 | |||
| 1596 | /* RCFSPYDISTL */ | ||
| 1597 | #define R367TER_RCFSPYDISTL 0xf224 | ||
| 1598 | #define F367TER_RCPKTTIME_DISTANCE_LO 0xf22400ff | ||
| 1599 | |||
| 1600 | /* RCFSPYOBS7 */ | ||
| 1601 | #define R367TER_RCFSPYOBS7 0xf228 | ||
| 1602 | #define F367TER_RCSPYOBS_SPYFAIL 0xf2280080 | ||
| 1603 | #define F367TER_RCSPYOBS_SPYFAIL1 0xf2280040 | ||
| 1604 | #define F367TER_RCSPYOBS_ERROR 0xf2280020 | ||
| 1605 | #define F367TER_RCSPYOBS_STROUT 0xf2280010 | ||
| 1606 | #define F367TER_RCSPYOBS_RESULTSTATE1 0xf228000f | ||
| 1607 | |||
| 1608 | /* RCFSPYOBS6 */ | ||
| 1609 | #define R367TER_RCFSPYOBS6 0xf229 | ||
| 1610 | #define F367TER_RCSPYOBS_RESULTSTATe0 0xf22900f0 | ||
| 1611 | #define F367TER_RCSPYOBS_RESULTSTATEM1 0xf229000f | ||
| 1612 | |||
| 1613 | /* RCFSPYOBS5 */ | ||
| 1614 | #define R367TER_RCFSPYOBS5 0xf22a | ||
| 1615 | #define F367TER_RCSPYOBS_BYTEOFPACKET1 0xf22a00ff | ||
| 1616 | |||
| 1617 | /* RCFSPYOBS4 */ | ||
| 1618 | #define R367TER_RCFSPYOBS4 0xf22b | ||
| 1619 | #define F367TER_RCSPYOBS_BYTEVALUE1 0xf22b00ff | ||
| 1620 | |||
| 1621 | /* RCFSPYOBS3 */ | ||
| 1622 | #define R367TER_RCFSPYOBS3 0xf22c | ||
| 1623 | #define F367TER_RCSPYOBS_DATA1 0xf22c00ff | ||
| 1624 | |||
| 1625 | /* RCFSPYOBS2 */ | ||
| 1626 | #define R367TER_RCFSPYOBS2 0xf22d | ||
| 1627 | #define F367TER_RCSPYOBS_DATa0 0xf22d00ff | ||
| 1628 | |||
| 1629 | /* RCFSPYOBS1 */ | ||
| 1630 | #define R367TER_RCFSPYOBS1 0xf22e | ||
| 1631 | #define F367TER_RCSPYOBS_DATAM1 0xf22e00ff | ||
| 1632 | |||
| 1633 | /* RCFSPYOBS0 */ | ||
| 1634 | #define R367TER_RCFSPYOBS0 0xf22f | ||
| 1635 | #define F367TER_RCSPYOBS_DATAM2 0xf22f00ff | ||
| 1636 | |||
| 1637 | /* TSGENERAL */ | ||
| 1638 | #define R367TER_TSGENERAL 0xf230 | ||
| 1639 | #define F367TER_TSGENERAL_7 0xf2300080 | ||
| 1640 | #define F367TER_TSGENERAL_6 0xf2300040 | ||
| 1641 | #define F367TER_TSFIFO_BCLK1aLL 0xf2300020 | ||
| 1642 | #define F367TER_TSGENERAL_4 0xf2300010 | ||
| 1643 | #define F367TER_MUXSTREAM_OUTMODE 0xf2300008 | ||
| 1644 | #define F367TER_TSFIFO_PERMPARAL 0xf2300006 | ||
| 1645 | #define F367TER_RST_REEDSOLO 0xf2300001 | ||
| 1646 | |||
| 1647 | /* RC1SPEED */ | ||
| 1648 | #define R367TER_RC1SPEED 0xf231 | ||
| 1649 | #define F367TER_TSRCFIFO1_OUTSPEED 0xf23100ff | ||
| 1650 | |||
| 1651 | /* TSGSTATUS */ | ||
| 1652 | #define R367TER_TSGSTATUS 0xf232 | ||
| 1653 | #define F367TER_TSGSTATUS_7 0xf2320080 | ||
| 1654 | #define F367TER_TSGSTATUS_6 0xf2320040 | ||
| 1655 | #define F367TER_RSMEM_FULL 0xf2320020 | ||
| 1656 | #define F367TER_RS_MULTCALC 0xf2320010 | ||
| 1657 | #define F367TER_RSIN_OVERTIME 0xf2320008 | ||
| 1658 | #define F367TER_TSFIFO3_DEMODSEL 0xf2320004 | ||
| 1659 | #define F367TER_TSFIFO2_DEMODSEL 0xf2320002 | ||
| 1660 | #define F367TER_TSFIFO1_DEMODSEL 0xf2320001 | ||
| 1661 | |||
| 1662 | |||
| 1663 | /* FECM */ | ||
| 1664 | #define R367TER_FECM 0xf233 | ||
| 1665 | #define F367TER_DSS_DVB 0xf2330080 | ||
| 1666 | #define F367TER_DEMOD_BYPASS 0xf2330040 | ||
| 1667 | #define F367TER_CMP_SLOWMODE 0xf2330020 | ||
| 1668 | #define F367TER_DSS_SRCH 0xf2330010 | ||
| 1669 | #define F367TER_FECM_3 0xf2330008 | ||
| 1670 | #define F367TER_DIFF_MODEVIT 0xf2330004 | ||
| 1671 | #define F367TER_SYNCVIT 0xf2330002 | ||
| 1672 | #define F367TER_I2CSYM 0xf2330001 | ||
| 1673 | |||
| 1674 | /* VTH12 */ | ||
| 1675 | #define R367TER_VTH12 0xf234 | ||
| 1676 | #define F367TER_VTH_12 0xf23400ff | ||
| 1677 | |||
| 1678 | /* VTH23 */ | ||
| 1679 | #define R367TER_VTH23 0xf235 | ||
| 1680 | #define F367TER_VTH_23 0xf23500ff | ||
| 1681 | |||
| 1682 | /* VTH34 */ | ||
| 1683 | #define R367TER_VTH34 0xf236 | ||
| 1684 | #define F367TER_VTH_34 0xf23600ff | ||
| 1685 | |||
| 1686 | /* VTH56 */ | ||
| 1687 | #define R367TER_VTH56 0xf237 | ||
| 1688 | #define F367TER_VTH_56 0xf23700ff | ||
| 1689 | |||
| 1690 | /* VTH67 */ | ||
| 1691 | #define R367TER_VTH67 0xf238 | ||
| 1692 | #define F367TER_VTH_67 0xf23800ff | ||
| 1693 | |||
| 1694 | /* VTH78 */ | ||
| 1695 | #define R367TER_VTH78 0xf239 | ||
| 1696 | #define F367TER_VTH_78 0xf23900ff | ||
| 1697 | |||
| 1698 | /* VITCURPUN */ | ||
| 1699 | #define R367TER_VITCURPUN 0xf23a | ||
| 1700 | #define F367TER_VIT_MAPPING 0xf23a00e0 | ||
| 1701 | #define F367TER_VIT_CURPUN 0xf23a001f | ||
| 1702 | |||
| 1703 | /* VERROR */ | ||
| 1704 | #define R367TER_VERROR 0xf23b | ||
| 1705 | #define F367TER_REGERR_VIT 0xf23b00ff | ||
| 1706 | |||
| 1707 | /* PRVIT */ | ||
| 1708 | #define R367TER_PRVIT 0xf23c | ||
| 1709 | #define F367TER_PRVIT_7 0xf23c0080 | ||
| 1710 | #define F367TER_DIS_VTHLOCK 0xf23c0040 | ||
| 1711 | #define F367TER_E7_8VIT 0xf23c0020 | ||
| 1712 | #define F367TER_E6_7VIT 0xf23c0010 | ||
| 1713 | #define F367TER_E5_6VIT 0xf23c0008 | ||
| 1714 | #define F367TER_E3_4VIT 0xf23c0004 | ||
| 1715 | #define F367TER_E2_3VIT 0xf23c0002 | ||
| 1716 | #define F367TER_E1_2VIT 0xf23c0001 | ||
| 1717 | |||
| 1718 | /* VAVSRVIT */ | ||
| 1719 | #define R367TER_VAVSRVIT 0xf23d | ||
| 1720 | #define F367TER_AMVIT 0xf23d0080 | ||
| 1721 | #define F367TER_FROZENVIT 0xf23d0040 | ||
| 1722 | #define F367TER_SNVIT 0xf23d0030 | ||
| 1723 | #define F367TER_TOVVIT 0xf23d000c | ||
| 1724 | #define F367TER_HYPVIT 0xf23d0003 | ||
| 1725 | |||
| 1726 | /* VSTATUSVIT */ | ||
| 1727 | #define R367TER_VSTATUSVIT 0xf23e | ||
| 1728 | #define F367TER_VITERBI_ON 0xf23e0080 | ||
| 1729 | #define F367TER_END_LOOPVIT 0xf23e0040 | ||
| 1730 | #define F367TER_VITERBI_DEPRF 0xf23e0020 | ||
| 1731 | #define F367TER_PRFVIT 0xf23e0010 | ||
| 1732 | #define F367TER_LOCKEDVIT 0xf23e0008 | ||
| 1733 | #define F367TER_VITERBI_DELOCK 0xf23e0004 | ||
| 1734 | #define F367TER_VIT_DEMODSEL 0xf23e0002 | ||
| 1735 | #define F367TER_VITERBI_COMPOUT 0xf23e0001 | ||
| 1736 | |||
| 1737 | /* VTHINUSE */ | ||
| 1738 | #define R367TER_VTHINUSE 0xf23f | ||
| 1739 | #define F367TER_VIT_INUSE 0xf23f00ff | ||
| 1740 | |||
| 1741 | /* KDIV12 */ | ||
| 1742 | #define R367TER_KDIV12 0xf240 | ||
| 1743 | #define F367TER_KDIV12_MANUAL 0xf2400080 | ||
| 1744 | #define F367TER_K_DIVIDER_12 0xf240007f | ||
| 1745 | |||
| 1746 | /* KDIV23 */ | ||
| 1747 | #define R367TER_KDIV23 0xf241 | ||
| 1748 | #define F367TER_KDIV23_MANUAL 0xf2410080 | ||
| 1749 | #define F367TER_K_DIVIDER_23 0xf241007f | ||
| 1750 | |||
| 1751 | /* KDIV34 */ | ||
| 1752 | #define R367TER_KDIV34 0xf242 | ||
| 1753 | #define F367TER_KDIV34_MANUAL 0xf2420080 | ||
| 1754 | #define F367TER_K_DIVIDER_34 0xf242007f | ||
| 1755 | |||
| 1756 | /* KDIV56 */ | ||
| 1757 | #define R367TER_KDIV56 0xf243 | ||
| 1758 | #define F367TER_KDIV56_MANUAL 0xf2430080 | ||
| 1759 | #define F367TER_K_DIVIDER_56 0xf243007f | ||
| 1760 | |||
| 1761 | /* KDIV67 */ | ||
| 1762 | #define R367TER_KDIV67 0xf244 | ||
| 1763 | #define F367TER_KDIV67_MANUAL 0xf2440080 | ||
| 1764 | #define F367TER_K_DIVIDER_67 0xf244007f | ||
| 1765 | |||
| 1766 | /* KDIV78 */ | ||
| 1767 | #define R367TER_KDIV78 0xf245 | ||
| 1768 | #define F367TER_KDIV78_MANUAL 0xf2450080 | ||
| 1769 | #define F367TER_K_DIVIDER_78 0xf245007f | ||
| 1770 | |||
| 1771 | /* SIGPOWER */ | ||
| 1772 | #define R367TER_SIGPOWER 0xf246 | ||
| 1773 | #define F367TER_SIGPOWER_MANUAL 0xf2460080 | ||
| 1774 | #define F367TER_SIG_POWER 0xf246007f | ||
| 1775 | |||
| 1776 | /* DEMAPVIT */ | ||
| 1777 | #define R367TER_DEMAPVIT 0xf247 | ||
| 1778 | #define F367TER_DEMAPVIT_7 0xf2470080 | ||
| 1779 | #define F367TER_K_DIVIDER_VIT 0xf247007f | ||
| 1780 | |||
| 1781 | /* VITSCALE */ | ||
| 1782 | #define R367TER_VITSCALE 0xf248 | ||
| 1783 | #define F367TER_NVTH_NOSRANGE 0xf2480080 | ||
| 1784 | #define F367TER_VERROR_MAXMODE 0xf2480040 | ||
| 1785 | #define F367TER_KDIV_MODE 0xf2480030 | ||
| 1786 | #define F367TER_NSLOWSN_LOCKED 0xf2480008 | ||
| 1787 | #define F367TER_DELOCK_PRFLOSS 0xf2480004 | ||
| 1788 | #define F367TER_DIS_RSFLOCK 0xf2480002 | ||
| 1789 | #define F367TER_VITSCALE_0 0xf2480001 | ||
| 1790 | |||
| 1791 | /* FFEC1PRG */ | ||
| 1792 | #define R367TER_FFEC1PRG 0xf249 | ||
| 1793 | #define F367TER_FDSS_DVB 0xf2490080 | ||
| 1794 | #define F367TER_FDSS_SRCH 0xf2490040 | ||
| 1795 | #define F367TER_FFECPROG_5 0xf2490020 | ||
| 1796 | #define F367TER_FFECPROG_4 0xf2490010 | ||
| 1797 | #define F367TER_FFECPROG_3 0xf2490008 | ||
| 1798 | #define F367TER_FFECPROG_2 0xf2490004 | ||
| 1799 | #define F367TER_FTS1_DISABLE 0xf2490002 | ||
| 1800 | #define F367TER_FTS2_DISABLE 0xf2490001 | ||
| 1801 | |||
| 1802 | /* FVITCURPUN */ | ||
| 1803 | #define R367TER_FVITCURPUN 0xf24a | ||
| 1804 | #define F367TER_FVIT_MAPPING 0xf24a00e0 | ||
| 1805 | #define F367TER_FVIT_CURPUN 0xf24a001f | ||
| 1806 | |||
| 1807 | /* FVERROR */ | ||
| 1808 | #define R367TER_FVERROR 0xf24b | ||
| 1809 | #define F367TER_FREGERR_VIT 0xf24b00ff | ||
| 1810 | |||
| 1811 | /* FVSTATUSVIT */ | ||
| 1812 | #define R367TER_FVSTATUSVIT 0xf24c | ||
| 1813 | #define F367TER_FVITERBI_ON 0xf24c0080 | ||
| 1814 | #define F367TER_F1END_LOOPVIT 0xf24c0040 | ||
| 1815 | #define F367TER_FVITERBI_DEPRF 0xf24c0020 | ||
| 1816 | #define F367TER_FPRFVIT 0xf24c0010 | ||
| 1817 | #define F367TER_FLOCKEDVIT 0xf24c0008 | ||
| 1818 | #define F367TER_FVITERBI_DELOCK 0xf24c0004 | ||
| 1819 | #define F367TER_FVIT_DEMODSEL 0xf24c0002 | ||
| 1820 | #define F367TER_FVITERBI_COMPOUT 0xf24c0001 | ||
| 1821 | |||
| 1822 | /* DEBUG_LT1 */ | ||
| 1823 | #define R367TER_DEBUG_LT1 0xf24d | ||
| 1824 | #define F367TER_DBG_LT1 0xf24d00ff | ||
| 1825 | |||
| 1826 | /* DEBUG_LT2 */ | ||
| 1827 | #define R367TER_DEBUG_LT2 0xf24e | ||
| 1828 | #define F367TER_DBG_LT2 0xf24e00ff | ||
| 1829 | |||
| 1830 | /* DEBUG_LT3 */ | ||
| 1831 | #define R367TER_DEBUG_LT3 0xf24f | ||
| 1832 | #define F367TER_DBG_LT3 0xf24f00ff | ||
| 1833 | |||
| 1834 | /* TSTSFMET */ | ||
| 1835 | #define R367TER_TSTSFMET 0xf250 | ||
| 1836 | #define F367TER_TSTSFEC_METRIQUES 0xf25000ff | ||
| 1837 | |||
| 1838 | /* SELOUT */ | ||
| 1839 | #define R367TER_SELOUT 0xf252 | ||
| 1840 | #define F367TER_EN_SYNC 0xf2520080 | ||
| 1841 | #define F367TER_EN_TBUSDEMAP 0xf2520040 | ||
| 1842 | #define F367TER_SELOUT_5 0xf2520020 | ||
| 1843 | #define F367TER_SELOUT_4 0xf2520010 | ||
| 1844 | #define F367TER_TSTSYNCHRO_MODE 0xf2520002 | ||
| 1845 | |||
| 1846 | /* TSYNC */ | ||
| 1847 | #define R367TER_TSYNC 0xf253 | ||
| 1848 | #define F367TER_CURPUN_INCMODE 0xf2530080 | ||
| 1849 | #define F367TER_CERR_TSTMODE 0xf2530040 | ||
| 1850 | #define F367TER_SHIFTSOF_MODE 0xf2530030 | ||
| 1851 | #define F367TER_SLOWPHA_MODE 0xf2530008 | ||
| 1852 | #define F367TER_PXX_BYPALL 0xf2530004 | ||
| 1853 | #define F367TER_FROTA45_FIRST 0xf2530002 | ||
| 1854 | #define F367TER_TST_BCHERROR 0xf2530001 | ||
| 1855 | |||
| 1856 | /* TSTERR */ | ||
| 1857 | #define R367TER_TSTERR 0xf254 | ||
| 1858 | #define F367TER_TST_LONGPKT 0xf2540080 | ||
| 1859 | #define F367TER_TST_ISSYION 0xf2540040 | ||
| 1860 | #define F367TER_TST_NPDON 0xf2540020 | ||
| 1861 | #define F367TER_TSTERR_4 0xf2540010 | ||
| 1862 | #define F367TER_TRACEBACK_MODE 0xf2540008 | ||
| 1863 | #define F367TER_TST_RSPARITY 0xf2540004 | ||
| 1864 | #define F367TER_METRIQUE_MODE 0xf2540003 | ||
| 1865 | |||
| 1866 | /* TSFSYNC */ | ||
| 1867 | #define R367TER_TSFSYNC 0xf255 | ||
| 1868 | #define F367TER_EN_SFECSYNC 0xf2550080 | ||
| 1869 | #define F367TER_EN_SFECDEMAP 0xf2550040 | ||
| 1870 | #define F367TER_SFCERR_TSTMODE 0xf2550020 | ||
| 1871 | #define F367TER_SFECPXX_BYPALL 0xf2550010 | ||
| 1872 | #define F367TER_SFECTSTSYNCHRO_MODE 0xf255000f | ||
| 1873 | |||
| 1874 | /* TSTSFERR */ | ||
| 1875 | #define R367TER_TSTSFERR 0xf256 | ||
| 1876 | #define F367TER_TSTSTERR_7 0xf2560080 | ||
| 1877 | #define F367TER_TSTSTERR_6 0xf2560040 | ||
| 1878 | #define F367TER_TSTSTERR_5 0xf2560020 | ||
| 1879 | #define F367TER_TSTSTERR_4 0xf2560010 | ||
| 1880 | #define F367TER_SFECTRACEBACK_MODE 0xf2560008 | ||
| 1881 | #define F367TER_SFEC_NCONVPROG 0xf2560004 | ||
| 1882 | #define F367TER_SFECMETRIQUE_MODE 0xf2560003 | ||
| 1883 | |||
| 1884 | /* TSTTSSF1 */ | ||
| 1885 | #define R367TER_TSTTSSF1 0xf258 | ||
| 1886 | #define F367TER_TSTERSSF 0xf2580080 | ||
| 1887 | #define F367TER_TSTTSSFEN 0xf2580040 | ||
| 1888 | #define F367TER_SFEC_OUTMODE 0xf2580030 | ||
| 1889 | #define F367TER_XLSF_NOFTHRESHOLD 0xf2580008 | ||
| 1890 | #define F367TER_TSTTSSF_STACKSEL 0xf2580007 | ||
| 1891 | |||
| 1892 | /* TSTTSSF2 */ | ||
| 1893 | #define R367TER_TSTTSSF2 0xf259 | ||
| 1894 | #define F367TER_DILSF_DBBHEADER 0xf2590080 | ||
| 1895 | #define F367TER_TSTTSSF_DISBUG 0xf2590040 | ||
| 1896 | #define F367TER_TSTTSSF_NOBADSTART 0xf2590020 | ||
| 1897 | #define F367TER_TSTTSSF_SELECT 0xf259001f | ||
| 1898 | |||
| 1899 | /* TSTTSSF3 */ | ||
| 1900 | #define R367TER_TSTTSSF3 0xf25a | ||
| 1901 | #define F367TER_TSTTSSF3_7 0xf25a0080 | ||
| 1902 | #define F367TER_TSTTSSF3_6 0xf25a0040 | ||
| 1903 | #define F367TER_TSTTSSF3_5 0xf25a0020 | ||
| 1904 | #define F367TER_TSTTSSF3_4 0xf25a0010 | ||
| 1905 | #define F367TER_TSTTSSF3_3 0xf25a0008 | ||
| 1906 | #define F367TER_TSTTSSF3_2 0xf25a0004 | ||
| 1907 | #define F367TER_TSTTSSF3_1 0xf25a0002 | ||
| 1908 | #define F367TER_DISSF_CLKENABLE 0xf25a0001 | ||
| 1909 | |||
| 1910 | /* TSTTS1 */ | ||
| 1911 | #define R367TER_TSTTS1 0xf25c | ||
| 1912 | #define F367TER_TSTERS 0xf25c0080 | ||
| 1913 | #define F367TER_TSFIFO_DSSSYNCB 0xf25c0040 | ||
| 1914 | #define F367TER_TSTTS_FSPYBEFRS 0xf25c0020 | ||
| 1915 | #define F367TER_NFORCE_SYNCBYTE 0xf25c0010 | ||
| 1916 | #define F367TER_XL_NOFTHRESHOLD 0xf25c0008 | ||
| 1917 | #define F367TER_TSTTS_FRFORCEPKT 0xf25c0004 | ||
| 1918 | #define F367TER_DESCR_NOTAUTO 0xf25c0002 | ||
| 1919 | #define F367TER_TSTTSEN 0xf25c0001 | ||
| 1920 | |||
| 1921 | /* TSTTS2 */ | ||
| 1922 | #define R367TER_TSTTS2 0xf25d | ||
| 1923 | #define F367TER_DIL_DBBHEADER 0xf25d0080 | ||
| 1924 | #define F367TER_TSTTS_NOBADXXX 0xf25d0040 | ||
| 1925 | #define F367TER_TSFIFO_DELSPEEDUP 0xf25d0020 | ||
| 1926 | #define F367TER_TSTTS_SELECT 0xf25d001f | ||
| 1927 | |||
| 1928 | /* TSTTS3 */ | ||
| 1929 | #define R367TER_TSTTS3 0xf25e | ||
| 1930 | #define F367TER_TSTTS_NOPKTGAIN 0xf25e0080 | ||
| 1931 | #define F367TER_TSTTS_NOPKTENE 0xf25e0040 | ||
| 1932 | #define F367TER_TSTTS_ISOLATION 0xf25e0020 | ||
| 1933 | #define F367TER_TSTTS_DISBUG 0xf25e0010 | ||
| 1934 | #define F367TER_TSTTS_NOBADSTART 0xf25e0008 | ||
| 1935 | #define F367TER_TSTTS_STACKSEL 0xf25e0007 | ||
| 1936 | |||
| 1937 | /* TSTTS4 */ | ||
| 1938 | #define R367TER_TSTTS4 0xf25f | ||
| 1939 | #define F367TER_TSTTS4_7 0xf25f0080 | ||
| 1940 | #define F367TER_TSTTS4_6 0xf25f0040 | ||
| 1941 | #define F367TER_TSTTS4_5 0xf25f0020 | ||
| 1942 | #define F367TER_TSTTS_DISDSTATE 0xf25f0010 | ||
| 1943 | #define F367TER_TSTTS_FASTNOSYNC 0xf25f0008 | ||
| 1944 | #define F367TER_EXT_FECSPYIN 0xf25f0004 | ||
| 1945 | #define F367TER_TSTTS_NODPZERO 0xf25f0002 | ||
| 1946 | #define F367TER_TSTTS_NODIV3 0xf25f0001 | ||
| 1947 | |||
| 1948 | /* TSTTSRC */ | ||
| 1949 | #define R367TER_TSTTSRC 0xf26c | ||
| 1950 | #define F367TER_TSTTSRC_7 0xf26c0080 | ||
| 1951 | #define F367TER_TSRCFIFO_DSSSYNCB 0xf26c0040 | ||
| 1952 | #define F367TER_TSRCFIFO_DPUNACTIVE 0xf26c0020 | ||
| 1953 | #define F367TER_TSRCFIFO_DELSPEEDUP 0xf26c0010 | ||
| 1954 | #define F367TER_TSTTSRC_NODIV3 0xf26c0008 | ||
| 1955 | #define F367TER_TSTTSRC_FRFORCEPKT 0xf26c0004 | ||
| 1956 | #define F367TER_SAT25_SDDORIGINE 0xf26c0002 | ||
| 1957 | #define F367TER_TSTTSRC_INACTIVE 0xf26c0001 | ||
| 1958 | |||
| 1959 | /* TSTTSRS */ | ||
| 1960 | #define R367TER_TSTTSRS 0xf26d | ||
| 1961 | #define F367TER_TSTTSRS_7 0xf26d0080 | ||
| 1962 | #define F367TER_TSTTSRS_6 0xf26d0040 | ||
| 1963 | #define F367TER_TSTTSRS_5 0xf26d0020 | ||
| 1964 | #define F367TER_TSTTSRS_4 0xf26d0010 | ||
| 1965 | #define F367TER_TSTTSRS_3 0xf26d0008 | ||
| 1966 | #define F367TER_TSTTSRS_2 0xf26d0004 | ||
| 1967 | #define F367TER_TSTRS_DISRS2 0xf26d0002 | ||
| 1968 | #define F367TER_TSTRS_DISRS1 0xf26d0001 | ||
| 1969 | |||
| 1970 | /* TSSTATEM */ | ||
| 1971 | #define R367TER_TSSTATEM 0xf270 | ||
| 1972 | #define F367TER_TSDIL_ON 0xf2700080 | ||
| 1973 | #define F367TER_TSSKIPRS_ON 0xf2700040 | ||
| 1974 | #define F367TER_TSRS_ON 0xf2700020 | ||
| 1975 | #define F367TER_TSDESCRAMB_ON 0xf2700010 | ||
| 1976 | #define F367TER_TSFRAME_MODE 0xf2700008 | ||
| 1977 | #define F367TER_TS_DISABLE 0xf2700004 | ||
| 1978 | #define F367TER_TSACM_MODE 0xf2700002 | ||
| 1979 | #define F367TER_TSOUT_NOSYNC 0xf2700001 | ||
| 1980 | |||
| 1981 | /* TSSTATEL */ | ||
| 1982 | #define R367TER_TSSTATEL 0xf271 | ||
| 1983 | #define F367TER_TSNOSYNCBYTE 0xf2710080 | ||
| 1984 | #define F367TER_TSPARITY_ON 0xf2710040 | ||
| 1985 | #define F367TER_TSSYNCOUTRS_ON 0xf2710020 | ||
| 1986 | #define F367TER_TSDVBS2_MODE 0xf2710010 | ||
| 1987 | #define F367TER_TSISSYI_ON 0xf2710008 | ||
| 1988 | #define F367TER_TSNPD_ON 0xf2710004 | ||
| 1989 | #define F367TER_TSCRC8_ON 0xf2710002 | ||
| 1990 | #define F367TER_TSDSS_PACKET 0xf2710001 | ||
| 1991 | |||
| 1992 | /* TSCFGH */ | ||
| 1993 | #define R367TER_TSCFGH 0xf272 | ||
| 1994 | #define F367TER_TSFIFO_DVBCI 0xf2720080 | ||
| 1995 | #define F367TER_TSFIFO_SERIAL 0xf2720040 | ||
| 1996 | #define F367TER_TSFIFO_TEIUPDATE 0xf2720020 | ||
| 1997 | #define F367TER_TSFIFO_DUTY50 0xf2720010 | ||
| 1998 | #define F367TER_TSFIFO_HSGNLOUT 0xf2720008 | ||
| 1999 | #define F367TER_TSFIFO_ERRMODE 0xf2720006 | ||
| 2000 | #define F367TER_RST_HWARE 0xf2720001 | ||
| 2001 | |||
| 2002 | /* TSCFGM */ | ||
| 2003 | #define R367TER_TSCFGM 0xf273 | ||
| 2004 | #define F367TER_TSFIFO_MANSPEED 0xf27300c0 | ||
| 2005 | #define F367TER_TSFIFO_PERMDATA 0xf2730020 | ||
| 2006 | #define F367TER_TSFIFO_NONEWSGNL 0xf2730010 | ||
| 2007 | #define F367TER_TSFIFO_BITSPEED 0xf2730008 | ||
| 2008 | #define F367TER_NPD_SPECDVBS2 0xf2730004 | ||
| 2009 | #define F367TER_TSFIFO_STOPCKDIS 0xf2730002 | ||
| 2010 | #define F367TER_TSFIFO_INVDATA 0xf2730001 | ||
| 2011 | |||
| 2012 | /* TSCFGL */ | ||
| 2013 | #define R367TER_TSCFGL 0xf274 | ||
| 2014 | #define F367TER_TSFIFO_BCLKDEL1cK 0xf27400c0 | ||
| 2015 | #define F367TER_BCHERROR_MODE 0xf2740030 | ||
| 2016 | #define F367TER_TSFIFO_NSGNL2dATA 0xf2740008 | ||
| 2017 | #define F367TER_TSFIFO_EMBINDVB 0xf2740004 | ||
| 2018 | #define F367TER_TSFIFO_DPUNACT 0xf2740002 | ||
| 2019 | #define F367TER_TSFIFO_NPDOFF 0xf2740001 | ||
| 2020 | |||
| 2021 | /* TSSYNC */ | ||
| 2022 | #define R367TER_TSSYNC 0xf275 | ||
| 2023 | #define F367TER_TSFIFO_PERMUTE 0xf2750080 | ||
| 2024 | #define F367TER_TSFIFO_FISCR3B 0xf2750060 | ||
| 2025 | #define F367TER_TSFIFO_SYNCMODE 0xf2750018 | ||
| 2026 | #define F367TER_TSFIFO_SYNCSEL 0xf2750007 | ||
| 2027 | |||
| 2028 | /* TSINSDELH */ | ||
| 2029 | #define R367TER_TSINSDELH 0xf276 | ||
| 2030 | #define F367TER_TSDEL_SYNCBYTE 0xf2760080 | ||
| 2031 | #define F367TER_TSDEL_XXHEADER 0xf2760040 | ||
| 2032 | #define F367TER_TSDEL_BBHEADER 0xf2760020 | ||
| 2033 | #define F367TER_TSDEL_DATAFIELD 0xf2760010 | ||
| 2034 | #define F367TER_TSINSDEL_ISCR 0xf2760008 | ||
| 2035 | #define F367TER_TSINSDEL_NPD 0xf2760004 | ||
| 2036 | #define F367TER_TSINSDEL_RSPARITY 0xf2760002 | ||
| 2037 | #define F367TER_TSINSDEL_CRC8 0xf2760001 | ||
| 2038 | |||
| 2039 | /* TSINSDELM */ | ||
| 2040 | #define R367TER_TSINSDELM 0xf277 | ||
| 2041 | #define F367TER_TSINS_BBPADDING 0xf2770080 | ||
| 2042 | #define F367TER_TSINS_BCHFEC 0xf2770040 | ||
| 2043 | #define F367TER_TSINS_LDPCFEC 0xf2770020 | ||
| 2044 | #define F367TER_TSINS_EMODCOD 0xf2770010 | ||
| 2045 | #define F367TER_TSINS_TOKEN 0xf2770008 | ||
| 2046 | #define F367TER_TSINS_XXXERR 0xf2770004 | ||
| 2047 | #define F367TER_TSINS_MATYPE 0xf2770002 | ||
| 2048 | #define F367TER_TSINS_UPL 0xf2770001 | ||
| 2049 | |||
| 2050 | /* TSINSDELL */ | ||
| 2051 | #define R367TER_TSINSDELL 0xf278 | ||
| 2052 | #define F367TER_TSINS_DFL 0xf2780080 | ||
| 2053 | #define F367TER_TSINS_SYNCD 0xf2780040 | ||
| 2054 | #define F367TER_TSINS_BLOCLEN 0xf2780020 | ||
| 2055 | #define F367TER_TSINS_SIGPCOUNT 0xf2780010 | ||
| 2056 | #define F367TER_TSINS_FIFO 0xf2780008 | ||
| 2057 | #define F367TER_TSINS_REALPACK 0xf2780004 | ||
| 2058 | #define F367TER_TSINS_TSCONFIG 0xf2780002 | ||
| 2059 | #define F367TER_TSINS_LATENCY 0xf2780001 | ||
| 2060 | |||
| 2061 | /* TSDIVN */ | ||
| 2062 | #define R367TER_TSDIVN 0xf279 | ||
| 2063 | #define F367TER_TSFIFO_LOWSPEED 0xf2790080 | ||
| 2064 | #define F367TER_BYTE_OVERSAMPLING 0xf2790070 | ||
| 2065 | #define F367TER_TSMANUAL_PACKETNBR 0xf279000f | ||
| 2066 | |||
| 2067 | /* TSDIVPM */ | ||
| 2068 | #define R367TER_TSDIVPM 0xf27a | ||
| 2069 | #define F367TER_TSMANUAL_P_HI 0xf27a00ff | ||
| 2070 | |||
| 2071 | /* TSDIVPL */ | ||
| 2072 | #define R367TER_TSDIVPL 0xf27b | ||
| 2073 | #define F367TER_TSMANUAL_P_LO 0xf27b00ff | ||
| 2074 | |||
| 2075 | /* TSDIVQM */ | ||
| 2076 | #define R367TER_TSDIVQM 0xf27c | ||
| 2077 | #define F367TER_TSMANUAL_Q_HI 0xf27c00ff | ||
| 2078 | |||
| 2079 | /* TSDIVQL */ | ||
| 2080 | #define R367TER_TSDIVQL 0xf27d | ||
| 2081 | #define F367TER_TSMANUAL_Q_LO 0xf27d00ff | ||
| 2082 | |||
| 2083 | /* TSDILSTKM */ | ||
| 2084 | #define R367TER_TSDILSTKM 0xf27e | ||
| 2085 | #define F367TER_TSFIFO_DILSTK_HI 0xf27e00ff | ||
| 2086 | |||
| 2087 | /* TSDILSTKL */ | ||
| 2088 | #define R367TER_TSDILSTKL 0xf27f | ||
| 2089 | #define F367TER_TSFIFO_DILSTK_LO 0xf27f00ff | ||
| 2090 | |||
| 2091 | /* TSSPEED */ | ||
| 2092 | #define R367TER_TSSPEED 0xf280 | ||
| 2093 | #define F367TER_TSFIFO_OUTSPEED 0xf28000ff | ||
| 2094 | |||
| 2095 | /* TSSTATUS */ | ||
| 2096 | #define R367TER_TSSTATUS 0xf281 | ||
| 2097 | #define F367TER_TSFIFO_LINEOK 0xf2810080 | ||
| 2098 | #define F367TER_TSFIFO_ERROR 0xf2810040 | ||
| 2099 | #define F367TER_TSFIFO_DATA7 0xf2810020 | ||
| 2100 | #define F367TER_TSFIFO_NOSYNC 0xf2810010 | ||
| 2101 | #define F367TER_ISCR_INITIALIZED 0xf2810008 | ||
| 2102 | #define F367TER_ISCR_UPDATED 0xf2810004 | ||
| 2103 | #define F367TER_SOFFIFO_UNREGUL 0xf2810002 | ||
| 2104 | #define F367TER_DIL_READY 0xf2810001 | ||
| 2105 | |||
| 2106 | /* TSSTATUS2 */ | ||
| 2107 | #define R367TER_TSSTATUS2 0xf282 | ||
| 2108 | #define F367TER_TSFIFO_DEMODSEL 0xf2820080 | ||
| 2109 | #define F367TER_TSFIFOSPEED_STORE 0xf2820040 | ||
| 2110 | #define F367TER_DILXX_RESET 0xf2820020 | ||
| 2111 | #define F367TER_TSSERIAL_IMPOSSIBLE 0xf2820010 | ||
| 2112 | #define F367TER_TSFIFO_UNDERSPEED 0xf2820008 | ||
| 2113 | #define F367TER_BITSPEED_EVENT 0xf2820004 | ||
| 2114 | #define F367TER_UL_SCRAMBDETECT 0xf2820002 | ||
| 2115 | #define F367TER_ULDTV67_FALSELOCK 0xf2820001 | ||
| 2116 | |||
| 2117 | /* TSBITRATEM */ | ||
| 2118 | #define R367TER_TSBITRATEM 0xf283 | ||
| 2119 | #define F367TER_TSFIFO_BITRATE_HI 0xf28300ff | ||
| 2120 | |||
| 2121 | /* TSBITRATEL */ | ||
| 2122 | #define R367TER_TSBITRATEL 0xf284 | ||
| 2123 | #define F367TER_TSFIFO_BITRATE_LO 0xf28400ff | ||
| 2124 | |||
| 2125 | /* TSPACKLENM */ | ||
| 2126 | #define R367TER_TSPACKLENM 0xf285 | ||
| 2127 | #define F367TER_TSFIFO_PACKCPT 0xf28500e0 | ||
| 2128 | #define F367TER_DIL_RPLEN_HI 0xf285001f | ||
| 2129 | |||
| 2130 | /* TSPACKLENL */ | ||
| 2131 | #define R367TER_TSPACKLENL 0xf286 | ||
| 2132 | #define F367TER_DIL_RPLEN_LO 0xf28600ff | ||
| 2133 | |||
| 2134 | /* TSBLOCLENM */ | ||
| 2135 | #define R367TER_TSBLOCLENM 0xf287 | ||
| 2136 | #define F367TER_TSFIFO_PFLEN_HI 0xf28700ff | ||
| 2137 | |||
| 2138 | /* TSBLOCLENL */ | ||
| 2139 | #define R367TER_TSBLOCLENL 0xf288 | ||
| 2140 | #define F367TER_TSFIFO_PFLEN_LO 0xf28800ff | ||
| 2141 | |||
| 2142 | /* TSDLYH */ | ||
| 2143 | #define R367TER_TSDLYH 0xf289 | ||
| 2144 | #define F367TER_SOFFIFO_TSTIMEVALID 0xf2890080 | ||
| 2145 | #define F367TER_SOFFIFO_SPEEDUP 0xf2890040 | ||
| 2146 | #define F367TER_SOFFIFO_STOP 0xf2890020 | ||
| 2147 | #define F367TER_SOFFIFO_REGULATED 0xf2890010 | ||
| 2148 | #define F367TER_SOFFIFO_REALSBOFF_HI 0xf289000f | ||
| 2149 | |||
| 2150 | /* TSDLYM */ | ||
| 2151 | #define R367TER_TSDLYM 0xf28a | ||
| 2152 | #define F367TER_SOFFIFO_REALSBOFF_MED 0xf28a00ff | ||
| 2153 | |||
| 2154 | /* TSDLYL */ | ||
| 2155 | #define R367TER_TSDLYL 0xf28b | ||
| 2156 | #define F367TER_SOFFIFO_REALSBOFF_LO 0xf28b00ff | ||
| 2157 | |||
| 2158 | /* TSNPDAV */ | ||
| 2159 | #define R367TER_TSNPDAV 0xf28c | ||
| 2160 | #define F367TER_TSNPD_AVERAGE 0xf28c00ff | ||
| 2161 | |||
| 2162 | /* TSBUFSTATH */ | ||
| 2163 | #define R367TER_TSBUFSTATH 0xf28d | ||
| 2164 | #define F367TER_TSISCR_3BYTES 0xf28d0080 | ||
| 2165 | #define F367TER_TSISCR_NEWDATA 0xf28d0040 | ||
| 2166 | #define F367TER_TSISCR_BUFSTAT_HI 0xf28d003f | ||
| 2167 | |||
| 2168 | /* TSBUFSTATM */ | ||
| 2169 | #define R367TER_TSBUFSTATM 0xf28e | ||
| 2170 | #define F367TER_TSISCR_BUFSTAT_MED 0xf28e00ff | ||
| 2171 | |||
| 2172 | /* TSBUFSTATL */ | ||
| 2173 | #define R367TER_TSBUFSTATL 0xf28f | ||
| 2174 | #define F367TER_TSISCR_BUFSTAT_LO 0xf28f00ff | ||
| 2175 | |||
| 2176 | /* TSDEBUGM */ | ||
| 2177 | #define R367TER_TSDEBUGM 0xf290 | ||
| 2178 | #define F367TER_TSFIFO_ILLPACKET 0xf2900080 | ||
| 2179 | #define F367TER_DIL_NOSYNC 0xf2900040 | ||
| 2180 | #define F367TER_DIL_ISCR 0xf2900020 | ||
| 2181 | #define F367TER_DILOUT_BSYNCB 0xf2900010 | ||
| 2182 | #define F367TER_TSFIFO_EMPTYPKT 0xf2900008 | ||
| 2183 | #define F367TER_TSFIFO_EMPTYRD 0xf2900004 | ||
| 2184 | #define F367TER_SOFFIFO_STOPM 0xf2900002 | ||
| 2185 | #define F367TER_SOFFIFO_SPEEDUPM 0xf2900001 | ||
| 2186 | |||
| 2187 | /* TSDEBUGL */ | ||
| 2188 | #define R367TER_TSDEBUGL 0xf291 | ||
| 2189 | #define F367TER_TSFIFO_PACKLENFAIL 0xf2910080 | ||
| 2190 | #define F367TER_TSFIFO_SYNCBFAIL 0xf2910040 | ||
| 2191 | #define F367TER_TSFIFO_VITLIBRE 0xf2910020 | ||
| 2192 | #define F367TER_TSFIFO_BOOSTSPEEDM 0xf2910010 | ||
| 2193 | #define F367TER_TSFIFO_UNDERSPEEDM 0xf2910008 | ||
| 2194 | #define F367TER_TSFIFO_ERROR_EVNT 0xf2910004 | ||
| 2195 | #define F367TER_TSFIFO_FULL 0xf2910002 | ||
| 2196 | #define F367TER_TSFIFO_OVERFLOWM 0xf2910001 | ||
| 2197 | |||
| 2198 | /* TSDLYSETH */ | ||
| 2199 | #define R367TER_TSDLYSETH 0xf292 | ||
| 2200 | #define F367TER_SOFFIFO_OFFSET 0xf29200e0 | ||
| 2201 | #define F367TER_SOFFIFO_SYMBOFFSET_HI 0xf292001f | ||
| 2202 | |||
| 2203 | /* TSDLYSETM */ | ||
| 2204 | #define R367TER_TSDLYSETM 0xf293 | ||
| 2205 | #define F367TER_SOFFIFO_SYMBOFFSET_MED 0xf29300ff | ||
| 2206 | |||
| 2207 | /* TSDLYSETL */ | ||
| 2208 | #define R367TER_TSDLYSETL 0xf294 | ||
| 2209 | #define F367TER_SOFFIFO_SYMBOFFSET_LO 0xf29400ff | ||
| 2210 | |||
| 2211 | /* TSOBSCFG */ | ||
| 2212 | #define R367TER_TSOBSCFG 0xf295 | ||
| 2213 | #define F367TER_TSFIFO_OBSCFG 0xf29500ff | ||
| 2214 | |||
| 2215 | /* TSOBSM */ | ||
| 2216 | #define R367TER_TSOBSM 0xf296 | ||
| 2217 | #define F367TER_TSFIFO_OBSDATA_HI 0xf29600ff | ||
| 2218 | |||
| 2219 | /* TSOBSL */ | ||
| 2220 | #define R367TER_TSOBSL 0xf297 | ||
| 2221 | #define F367TER_TSFIFO_OBSDATA_LO 0xf29700ff | ||
| 2222 | |||
| 2223 | /* ERRCTRL1 */ | ||
| 2224 | #define R367TER_ERRCTRL1 0xf298 | ||
| 2225 | #define F367TER_ERR_SRC1 0xf29800f0 | ||
| 2226 | #define F367TER_ERRCTRL1_3 0xf2980008 | ||
| 2227 | #define F367TER_NUM_EVT1 0xf2980007 | ||
| 2228 | |||
| 2229 | /* ERRCNT1H */ | ||
| 2230 | #define R367TER_ERRCNT1H 0xf299 | ||
| 2231 | #define F367TER_ERRCNT1_OLDVALUE 0xf2990080 | ||
| 2232 | #define F367TER_ERR_CNT1 0xf299007f | ||
| 2233 | |||
| 2234 | /* ERRCNT1M */ | ||
| 2235 | #define R367TER_ERRCNT1M 0xf29a | ||
| 2236 | #define F367TER_ERR_CNT1_HI 0xf29a00ff | ||
| 2237 | |||
| 2238 | /* ERRCNT1L */ | ||
| 2239 | #define R367TER_ERRCNT1L 0xf29b | ||
| 2240 | #define F367TER_ERR_CNT1_LO 0xf29b00ff | ||
| 2241 | |||
| 2242 | /* ERRCTRL2 */ | ||
| 2243 | #define R367TER_ERRCTRL2 0xf29c | ||
| 2244 | #define F367TER_ERR_SRC2 0xf29c00f0 | ||
| 2245 | #define F367TER_ERRCTRL2_3 0xf29c0008 | ||
| 2246 | #define F367TER_NUM_EVT2 0xf29c0007 | ||
| 2247 | |||
| 2248 | /* ERRCNT2H */ | ||
| 2249 | #define R367TER_ERRCNT2H 0xf29d | ||
| 2250 | #define F367TER_ERRCNT2_OLDVALUE 0xf29d0080 | ||
| 2251 | #define F367TER_ERR_CNT2_HI 0xf29d007f | ||
| 2252 | |||
| 2253 | /* ERRCNT2M */ | ||
| 2254 | #define R367TER_ERRCNT2M 0xf29e | ||
| 2255 | #define F367TER_ERR_CNT2_MED 0xf29e00ff | ||
| 2256 | |||
| 2257 | /* ERRCNT2L */ | ||
| 2258 | #define R367TER_ERRCNT2L 0xf29f | ||
| 2259 | #define F367TER_ERR_CNT2_LO 0xf29f00ff | ||
| 2260 | |||
| 2261 | /* FECSPY */ | ||
| 2262 | #define R367TER_FECSPY 0xf2a0 | ||
| 2263 | #define F367TER_SPY_ENABLE 0xf2a00080 | ||
| 2264 | #define F367TER_NO_SYNCBYTE 0xf2a00040 | ||
| 2265 | #define F367TER_SERIAL_MODE 0xf2a00020 | ||
| 2266 | #define F367TER_UNUSUAL_PACKET 0xf2a00010 | ||
| 2267 | #define F367TER_BERMETER_DATAMODE 0xf2a0000c | ||
| 2268 | #define F367TER_BERMETER_LMODE 0xf2a00002 | ||
| 2269 | #define F367TER_BERMETER_RESET 0xf2a00001 | ||
| 2270 | |||
| 2271 | /* FSPYCFG */ | ||
| 2272 | #define R367TER_FSPYCFG 0xf2a1 | ||
| 2273 | #define F367TER_FECSPY_INPUT 0xf2a100c0 | ||
| 2274 | #define F367TER_RST_ON_ERROR 0xf2a10020 | ||
| 2275 | #define F367TER_ONE_SHOT 0xf2a10010 | ||
| 2276 | #define F367TER_I2C_MOD 0xf2a1000c | ||
| 2277 | #define F367TER_SPY_HYSTERESIS 0xf2a10003 | ||
| 2278 | |||
| 2279 | /* FSPYDATA */ | ||
| 2280 | #define R367TER_FSPYDATA 0xf2a2 | ||
| 2281 | #define F367TER_SPY_STUFFING 0xf2a20080 | ||
| 2282 | #define F367TER_NOERROR_PKTJITTER 0xf2a20040 | ||
| 2283 | #define F367TER_SPY_CNULLPKT 0xf2a20020 | ||
| 2284 | #define F367TER_SPY_OUTDATA_MODE 0xf2a2001f | ||
| 2285 | |||
| 2286 | /* FSPYOUT */ | ||
| 2287 | #define R367TER_FSPYOUT 0xf2a3 | ||
| 2288 | #define F367TER_FSPY_DIRECT 0xf2a30080 | ||
| 2289 | #define F367TER_FSPYOUT_6 0xf2a30040 | ||
| 2290 | #define F367TER_SPY_OUTDATA_BUS 0xf2a30038 | ||
| 2291 | #define F367TER_STUFF_MODE 0xf2a30007 | ||
| 2292 | |||
| 2293 | /* FSTATUS */ | ||
| 2294 | #define R367TER_FSTATUS 0xf2a4 | ||
| 2295 | #define F367TER_SPY_ENDSIM 0xf2a40080 | ||
| 2296 | #define F367TER_VALID_SIM 0xf2a40040 | ||
| 2297 | #define F367TER_FOUND_SIGNAL 0xf2a40020 | ||
| 2298 | #define F367TER_DSS_SYNCBYTE 0xf2a40010 | ||
| 2299 | #define F367TER_RESULT_STATE 0xf2a4000f | ||
| 2300 | |||
| 2301 | /* FGOODPACK */ | ||
| 2302 | #define R367TER_FGOODPACK 0xf2a5 | ||
| 2303 | #define F367TER_FGOOD_PACKET 0xf2a500ff | ||
| 2304 | |||
| 2305 | /* FPACKCNT */ | ||
| 2306 | #define R367TER_FPACKCNT 0xf2a6 | ||
| 2307 | #define F367TER_FPACKET_COUNTER 0xf2a600ff | ||
| 2308 | |||
| 2309 | /* FSPYMISC */ | ||
| 2310 | #define R367TER_FSPYMISC 0xf2a7 | ||
| 2311 | #define F367TER_FLABEL_COUNTER 0xf2a700ff | ||
| 2312 | |||
| 2313 | /* FBERCPT4 */ | ||
| 2314 | #define R367TER_FBERCPT4 0xf2a8 | ||
| 2315 | #define F367TER_FBERMETER_CPT5 0xf2a800ff | ||
| 2316 | |||
| 2317 | /* FBERCPT3 */ | ||
| 2318 | #define R367TER_FBERCPT3 0xf2a9 | ||
| 2319 | #define F367TER_FBERMETER_CPT4 0xf2a900ff | ||
| 2320 | |||
| 2321 | /* FBERCPT2 */ | ||
| 2322 | #define R367TER_FBERCPT2 0xf2aa | ||
| 2323 | #define F367TER_FBERMETER_CPT3 0xf2aa00ff | ||
| 2324 | |||
| 2325 | /* FBERCPT1 */ | ||
| 2326 | #define R367TER_FBERCPT1 0xf2ab | ||
| 2327 | #define F367TER_FBERMETER_CPT2 0xf2ab00ff | ||
| 2328 | |||
| 2329 | /* FBERCPT0 */ | ||
| 2330 | #define R367TER_FBERCPT0 0xf2ac | ||
| 2331 | #define F367TER_FBERMETER_CPT1 0xf2ac00ff | ||
| 2332 | |||
| 2333 | /* FBERERR2 */ | ||
| 2334 | #define R367TER_FBERERR2 0xf2ad | ||
| 2335 | #define F367TER_FBERMETER_ERR_HI 0xf2ad00ff | ||
| 2336 | |||
| 2337 | /* FBERERR1 */ | ||
| 2338 | #define R367TER_FBERERR1 0xf2ae | ||
| 2339 | #define F367TER_FBERMETER_ERR_MED 0xf2ae00ff | ||
| 2340 | |||
| 2341 | /* FBERERR0 */ | ||
| 2342 | #define R367TER_FBERERR0 0xf2af | ||
| 2343 | #define F367TER_FBERMETER_ERR_LO 0xf2af00ff | ||
| 2344 | |||
| 2345 | /* FSTATESM */ | ||
| 2346 | #define R367TER_FSTATESM 0xf2b0 | ||
| 2347 | #define F367TER_RSTATE_F 0xf2b00080 | ||
| 2348 | #define F367TER_RSTATE_E 0xf2b00040 | ||
| 2349 | #define F367TER_RSTATE_D 0xf2b00020 | ||
| 2350 | #define F367TER_RSTATE_C 0xf2b00010 | ||
| 2351 | #define F367TER_RSTATE_B 0xf2b00008 | ||
| 2352 | #define F367TER_RSTATE_A 0xf2b00004 | ||
| 2353 | #define F367TER_RSTATE_9 0xf2b00002 | ||
| 2354 | #define F367TER_RSTATE_8 0xf2b00001 | ||
| 2355 | |||
| 2356 | /* FSTATESL */ | ||
| 2357 | #define R367TER_FSTATESL 0xf2b1 | ||
| 2358 | #define F367TER_RSTATE_7 0xf2b10080 | ||
| 2359 | #define F367TER_RSTATE_6 0xf2b10040 | ||
| 2360 | #define F367TER_RSTATE_5 0xf2b10020 | ||
| 2361 | #define F367TER_RSTATE_4 0xf2b10010 | ||
| 2362 | #define F367TER_RSTATE_3 0xf2b10008 | ||
| 2363 | #define F367TER_RSTATE_2 0xf2b10004 | ||
| 2364 | #define F367TER_RSTATE_1 0xf2b10002 | ||
| 2365 | #define F367TER_RSTATE_0 0xf2b10001 | ||
| 2366 | |||
| 2367 | /* FSPYBER */ | ||
| 2368 | #define R367TER_FSPYBER 0xf2b2 | ||
| 2369 | #define F367TER_FSPYBER_7 0xf2b20080 | ||
| 2370 | #define F367TER_FSPYOBS_XORREAD 0xf2b20040 | ||
| 2371 | #define F367TER_FSPYBER_OBSMODE 0xf2b20020 | ||
| 2372 | #define F367TER_FSPYBER_SYNCBYTE 0xf2b20010 | ||
| 2373 | #define F367TER_FSPYBER_UNSYNC 0xf2b20008 | ||
| 2374 | #define F367TER_FSPYBER_CTIME 0xf2b20007 | ||
| 2375 | |||
| 2376 | /* FSPYDISTM */ | ||
| 2377 | #define R367TER_FSPYDISTM 0xf2b3 | ||
| 2378 | #define F367TER_PKTTIME_DISTANCE_HI 0xf2b300ff | ||
| 2379 | |||
| 2380 | /* FSPYDISTL */ | ||
| 2381 | #define R367TER_FSPYDISTL 0xf2b4 | ||
| 2382 | #define F367TER_PKTTIME_DISTANCE_LO 0xf2b400ff | ||
| 2383 | |||
| 2384 | /* FSPYOBS7 */ | ||
| 2385 | #define R367TER_FSPYOBS7 0xf2b8 | ||
| 2386 | #define F367TER_FSPYOBS_SPYFAIL 0xf2b80080 | ||
| 2387 | #define F367TER_FSPYOBS_SPYFAIL1 0xf2b80040 | ||
| 2388 | #define F367TER_FSPYOBS_ERROR 0xf2b80020 | ||
| 2389 | #define F367TER_FSPYOBS_STROUT 0xf2b80010 | ||
| 2390 | #define F367TER_FSPYOBS_RESULTSTATE1 0xf2b8000f | ||
| 2391 | |||
| 2392 | /* FSPYOBS6 */ | ||
| 2393 | #define R367TER_FSPYOBS6 0xf2b9 | ||
| 2394 | #define F367TER_FSPYOBS_RESULTSTATe0 0xf2b900f0 | ||
| 2395 | #define F367TER_FSPYOBS_RESULTSTATEM1 0xf2b9000f | ||
| 2396 | |||
| 2397 | /* FSPYOBS5 */ | ||
| 2398 | #define R367TER_FSPYOBS5 0xf2ba | ||
| 2399 | #define F367TER_FSPYOBS_BYTEOFPACKET1 0xf2ba00ff | ||
| 2400 | |||
| 2401 | /* FSPYOBS4 */ | ||
| 2402 | #define R367TER_FSPYOBS4 0xf2bb | ||
| 2403 | #define F367TER_FSPYOBS_BYTEVALUE1 0xf2bb00ff | ||
| 2404 | |||
| 2405 | /* FSPYOBS3 */ | ||
| 2406 | #define R367TER_FSPYOBS3 0xf2bc | ||
| 2407 | #define F367TER_FSPYOBS_DATA1 0xf2bc00ff | ||
| 2408 | |||
| 2409 | /* FSPYOBS2 */ | ||
| 2410 | #define R367TER_FSPYOBS2 0xf2bd | ||
| 2411 | #define F367TER_FSPYOBS_DATa0 0xf2bd00ff | ||
| 2412 | |||
| 2413 | /* FSPYOBS1 */ | ||
| 2414 | #define R367TER_FSPYOBS1 0xf2be | ||
| 2415 | #define F367TER_FSPYOBS_DATAM1 0xf2be00ff | ||
| 2416 | |||
| 2417 | /* FSPYOBS0 */ | ||
| 2418 | #define R367TER_FSPYOBS0 0xf2bf | ||
| 2419 | #define F367TER_FSPYOBS_DATAM2 0xf2bf00ff | ||
| 2420 | |||
| 2421 | /* SFDEMAP */ | ||
| 2422 | #define R367TER_SFDEMAP 0xf2c0 | ||
| 2423 | #define F367TER_SFDEMAP_7 0xf2c00080 | ||
| 2424 | #define F367TER_SFEC_K_DIVIDER_VIT 0xf2c0007f | ||
| 2425 | |||
| 2426 | /* SFERROR */ | ||
| 2427 | #define R367TER_SFERROR 0xf2c1 | ||
| 2428 | #define F367TER_SFEC_REGERR_VIT 0xf2c100ff | ||
| 2429 | |||
| 2430 | /* SFAVSR */ | ||
| 2431 | #define R367TER_SFAVSR 0xf2c2 | ||
| 2432 | #define F367TER_SFEC_SUMERRORS 0xf2c20080 | ||
| 2433 | #define F367TER_SERROR_MAXMODE 0xf2c20040 | ||
| 2434 | #define F367TER_SN_SFEC 0xf2c20030 | ||
| 2435 | #define F367TER_KDIV_MODE_SFEC 0xf2c2000c | ||
| 2436 | #define F367TER_SFAVSR_1 0xf2c20002 | ||
| 2437 | #define F367TER_SFAVSR_0 0xf2c20001 | ||
| 2438 | |||
| 2439 | /* SFECSTATUS */ | ||
| 2440 | #define R367TER_SFECSTATUS 0xf2c3 | ||
| 2441 | #define F367TER_SFEC_ON 0xf2c30080 | ||
| 2442 | #define F367TER_SFSTATUS_6 0xf2c30040 | ||
| 2443 | #define F367TER_SFSTATUS_5 0xf2c30020 | ||
| 2444 | #define F367TER_SFSTATUS_4 0xf2c30010 | ||
| 2445 | #define F367TER_LOCKEDSFEC 0xf2c30008 | ||
| 2446 | #define F367TER_SFEC_DELOCK 0xf2c30004 | ||
| 2447 | #define F367TER_SFEC_DEMODSEL1 0xf2c30002 | ||
| 2448 | #define F367TER_SFEC_OVFON 0xf2c30001 | ||
| 2449 | |||
| 2450 | /* SFKDIV12 */ | ||
| 2451 | #define R367TER_SFKDIV12 0xf2c4 | ||
| 2452 | #define F367TER_SFECKDIV12_MAN 0xf2c40080 | ||
| 2453 | #define F367TER_SFEC_K_DIVIDER_12 0xf2c4007f | ||
| 2454 | |||
| 2455 | /* SFKDIV23 */ | ||
| 2456 | #define R367TER_SFKDIV23 0xf2c5 | ||
| 2457 | #define F367TER_SFECKDIV23_MAN 0xf2c50080 | ||
| 2458 | #define F367TER_SFEC_K_DIVIDER_23 0xf2c5007f | ||
| 2459 | |||
| 2460 | /* SFKDIV34 */ | ||
| 2461 | #define R367TER_SFKDIV34 0xf2c6 | ||
| 2462 | #define F367TER_SFECKDIV34_MAN 0xf2c60080 | ||
| 2463 | #define F367TER_SFEC_K_DIVIDER_34 0xf2c6007f | ||
| 2464 | |||
| 2465 | /* SFKDIV56 */ | ||
| 2466 | #define R367TER_SFKDIV56 0xf2c7 | ||
| 2467 | #define F367TER_SFECKDIV56_MAN 0xf2c70080 | ||
| 2468 | #define F367TER_SFEC_K_DIVIDER_56 0xf2c7007f | ||
| 2469 | |||
| 2470 | /* SFKDIV67 */ | ||
| 2471 | #define R367TER_SFKDIV67 0xf2c8 | ||
| 2472 | #define F367TER_SFECKDIV67_MAN 0xf2c80080 | ||
| 2473 | #define F367TER_SFEC_K_DIVIDER_67 0xf2c8007f | ||
| 2474 | |||
| 2475 | /* SFKDIV78 */ | ||
| 2476 | #define R367TER_SFKDIV78 0xf2c9 | ||
| 2477 | #define F367TER_SFECKDIV78_MAN 0xf2c90080 | ||
| 2478 | #define F367TER_SFEC_K_DIVIDER_78 0xf2c9007f | ||
| 2479 | |||
| 2480 | /* SFDILSTKM */ | ||
| 2481 | #define R367TER_SFDILSTKM 0xf2ca | ||
| 2482 | #define F367TER_SFEC_PACKCPT 0xf2ca00e0 | ||
| 2483 | #define F367TER_SFEC_DILSTK_HI 0xf2ca001f | ||
| 2484 | |||
| 2485 | /* SFDILSTKL */ | ||
| 2486 | #define R367TER_SFDILSTKL 0xf2cb | ||
| 2487 | #define F367TER_SFEC_DILSTK_LO 0xf2cb00ff | ||
| 2488 | |||
| 2489 | /* SFSTATUS */ | ||
| 2490 | #define R367TER_SFSTATUS 0xf2cc | ||
| 2491 | #define F367TER_SFEC_LINEOK 0xf2cc0080 | ||
| 2492 | #define F367TER_SFEC_ERROR 0xf2cc0040 | ||
| 2493 | #define F367TER_SFEC_DATA7 0xf2cc0020 | ||
| 2494 | #define F367TER_SFEC_OVERFLOW 0xf2cc0010 | ||
| 2495 | #define F367TER_SFEC_DEMODSEL2 0xf2cc0008 | ||
| 2496 | #define F367TER_SFEC_NOSYNC 0xf2cc0004 | ||
| 2497 | #define F367TER_SFEC_UNREGULA 0xf2cc0002 | ||
| 2498 | #define F367TER_SFEC_READY 0xf2cc0001 | ||
| 2499 | |||
| 2500 | /* SFDLYH */ | ||
| 2501 | #define R367TER_SFDLYH 0xf2cd | ||
| 2502 | #define F367TER_SFEC_TSTIMEVALID 0xf2cd0080 | ||
| 2503 | #define F367TER_SFEC_SPEEDUP 0xf2cd0040 | ||
| 2504 | #define F367TER_SFEC_STOP 0xf2cd0020 | ||
| 2505 | #define F367TER_SFEC_REGULATED 0xf2cd0010 | ||
| 2506 | #define F367TER_SFEC_REALSYMBOFFSET 0xf2cd000f | ||
| 2507 | |||
| 2508 | /* SFDLYM */ | ||
| 2509 | #define R367TER_SFDLYM 0xf2ce | ||
| 2510 | #define F367TER_SFEC_REALSYMBOFFSET_HI 0xf2ce00ff | ||
| 2511 | |||
| 2512 | /* SFDLYL */ | ||
| 2513 | #define R367TER_SFDLYL 0xf2cf | ||
| 2514 | #define F367TER_SFEC_REALSYMBOFFSET_LO 0xf2cf00ff | ||
| 2515 | |||
| 2516 | /* SFDLYSETH */ | ||
| 2517 | #define R367TER_SFDLYSETH 0xf2d0 | ||
| 2518 | #define F367TER_SFEC_OFFSET 0xf2d000e0 | ||
| 2519 | #define F367TER_SFECDLYSETH_4 0xf2d00010 | ||
| 2520 | #define F367TER_RST_SFEC 0xf2d00008 | ||
| 2521 | #define F367TER_SFECDLYSETH_2 0xf2d00004 | ||
| 2522 | #define F367TER_SFEC_DISABLE 0xf2d00002 | ||
| 2523 | #define F367TER_SFEC_UNREGUL 0xf2d00001 | ||
| 2524 | |||
| 2525 | /* SFDLYSETM */ | ||
| 2526 | #define R367TER_SFDLYSETM 0xf2d1 | ||
| 2527 | #define F367TER_SFECDLYSETM_7 0xf2d10080 | ||
| 2528 | #define F367TER_SFEC_SYMBOFFSET_HI 0xf2d1007f | ||
| 2529 | |||
| 2530 | /* SFDLYSETL */ | ||
| 2531 | #define R367TER_SFDLYSETL 0xf2d2 | ||
| 2532 | #define F367TER_SFEC_SYMBOFFSET_LO 0xf2d200ff | ||
| 2533 | |||
| 2534 | /* SFOBSCFG */ | ||
| 2535 | #define R367TER_SFOBSCFG 0xf2d3 | ||
| 2536 | #define F367TER_SFEC_OBSCFG 0xf2d300ff | ||
| 2537 | |||
| 2538 | /* SFOBSM */ | ||
| 2539 | #define R367TER_SFOBSM 0xf2d4 | ||
| 2540 | #define F367TER_SFEC_OBSDATA_HI 0xf2d400ff | ||
| 2541 | |||
| 2542 | /* SFOBSL */ | ||
| 2543 | #define R367TER_SFOBSL 0xf2d5 | ||
| 2544 | #define F367TER_SFEC_OBSDATA_LO 0xf2d500ff | ||
| 2545 | |||
| 2546 | /* SFECINFO */ | ||
| 2547 | #define R367TER_SFECINFO 0xf2d6 | ||
| 2548 | #define F367TER_SFECINFO_7 0xf2d60080 | ||
| 2549 | #define F367TER_SFEC_SYNCDLSB 0xf2d60070 | ||
| 2550 | #define F367TER_SFCE_S1cPHASE 0xf2d6000f | ||
| 2551 | |||
| 2552 | /* SFERRCTRL */ | ||
| 2553 | #define R367TER_SFERRCTRL 0xf2d8 | ||
| 2554 | #define F367TER_SFEC_ERR_SOURCE 0xf2d800f0 | ||
| 2555 | #define F367TER_SFERRCTRL_3 0xf2d80008 | ||
| 2556 | #define F367TER_SFEC_NUM_EVENT 0xf2d80007 | ||
| 2557 | |||
| 2558 | /* SFERRCNTH */ | ||
| 2559 | #define R367TER_SFERRCNTH 0xf2d9 | ||
| 2560 | #define F367TER_SFERRC_OLDVALUE 0xf2d90080 | ||
| 2561 | #define F367TER_SFEC_ERR_CNT 0xf2d9007f | ||
| 2562 | |||
| 2563 | /* SFERRCNTM */ | ||
| 2564 | #define R367TER_SFERRCNTM 0xf2da | ||
| 2565 | #define F367TER_SFEC_ERR_CNT_HI 0xf2da00ff | ||
| 2566 | |||
| 2567 | /* SFERRCNTL */ | ||
| 2568 | #define R367TER_SFERRCNTL 0xf2db | ||
| 2569 | #define F367TER_SFEC_ERR_CNT_LO 0xf2db00ff | ||
| 2570 | |||
| 2571 | /* SYMBRATEM */ | ||
| 2572 | #define R367TER_SYMBRATEM 0xf2e0 | ||
| 2573 | #define F367TER_DEFGEN_SYMBRATE_HI 0xf2e000ff | ||
| 2574 | |||
| 2575 | /* SYMBRATEL */ | ||
| 2576 | #define R367TER_SYMBRATEL 0xf2e1 | ||
| 2577 | #define F367TER_DEFGEN_SYMBRATE_LO 0xf2e100ff | ||
| 2578 | |||
| 2579 | /* SYMBSTATUS */ | ||
| 2580 | #define R367TER_SYMBSTATUS 0xf2e2 | ||
| 2581 | #define F367TER_SYMBDLINE2_OFF 0xf2e20080 | ||
| 2582 | #define F367TER_SDDL_REINIT1 0xf2e20040 | ||
| 2583 | #define F367TER_SDD_REINIT1 0xf2e20020 | ||
| 2584 | #define F367TER_TOKENID_ERROR 0xf2e20010 | ||
| 2585 | #define F367TER_SYMBRATE_OVERFLOW 0xf2e20008 | ||
| 2586 | #define F367TER_SYMBRATE_UNDERFLOW 0xf2e20004 | ||
| 2587 | #define F367TER_TOKENID_RSTEVENT 0xf2e20002 | ||
| 2588 | #define F367TER_TOKENID_RESET1 0xf2e20001 | ||
| 2589 | |||
| 2590 | /* SYMBCFG */ | ||
| 2591 | #define R367TER_SYMBCFG 0xf2e3 | ||
| 2592 | #define F367TER_SYMBCFG_7 0xf2e30080 | ||
| 2593 | #define F367TER_SYMBCFG_6 0xf2e30040 | ||
| 2594 | #define F367TER_SYMBCFG_5 0xf2e30020 | ||
| 2595 | #define F367TER_SYMBCFG_4 0xf2e30010 | ||
| 2596 | #define F367TER_SYMRATE_FSPEED 0xf2e3000c | ||
| 2597 | #define F367TER_SYMRATE_SSPEED 0xf2e30003 | ||
| 2598 | |||
| 2599 | /* SYMBFIFOM */ | ||
| 2600 | #define R367TER_SYMBFIFOM 0xf2e4 | ||
| 2601 | #define F367TER_SYMBFIFOM_7 0xf2e40080 | ||
| 2602 | #define F367TER_SYMBFIFOM_6 0xf2e40040 | ||
| 2603 | #define F367TER_DEFGEN_SYMFIFO_HI 0xf2e4003f | ||
| 2604 | |||
| 2605 | /* SYMBFIFOL */ | ||
| 2606 | #define R367TER_SYMBFIFOL 0xf2e5 | ||
| 2607 | #define F367TER_DEFGEN_SYMFIFO_LO 0xf2e500ff | ||
| 2608 | |||
| 2609 | /* SYMBOFFSM */ | ||
| 2610 | #define R367TER_SYMBOFFSM 0xf2e6 | ||
| 2611 | #define F367TER_TOKENID_RESET2 0xf2e60080 | ||
| 2612 | #define F367TER_SDDL_REINIT2 0xf2e60040 | ||
| 2613 | #define F367TER_SDD_REINIT2 0xf2e60020 | ||
| 2614 | #define F367TER_SYMBOFFSM_4 0xf2e60010 | ||
| 2615 | #define F367TER_SYMBOFFSM_3 0xf2e60008 | ||
| 2616 | #define F367TER_DEFGEN_SYMBOFFSET_HI 0xf2e60007 | ||
| 2617 | |||
| 2618 | /* SYMBOFFSL */ | ||
| 2619 | #define R367TER_SYMBOFFSL 0xf2e7 | ||
| 2620 | #define F367TER_DEFGEN_SYMBOFFSET_LO 0xf2e700ff | ||
| 2621 | |||
| 2622 | /* DEBUG_LT4 */ | ||
| 2623 | #define R367TER_DEBUG_LT4 0xf400 | ||
| 2624 | #define F367TER_F_DEBUG_LT4 0xf40000ff | ||
| 2625 | |||
| 2626 | /* DEBUG_LT5 */ | ||
| 2627 | #define R367TER_DEBUG_LT5 0xf401 | ||
| 2628 | #define F367TER_F_DEBUG_LT5 0xf40100ff | ||
| 2629 | |||
| 2630 | /* DEBUG_LT6 */ | ||
| 2631 | #define R367TER_DEBUG_LT6 0xf402 | ||
| 2632 | #define F367TER_F_DEBUG_LT6 0xf40200ff | ||
| 2633 | |||
| 2634 | /* DEBUG_LT7 */ | ||
| 2635 | #define R367TER_DEBUG_LT7 0xf403 | ||
| 2636 | #define F367TER_F_DEBUG_LT7 0xf40300ff | ||
| 2637 | |||
| 2638 | /* DEBUG_LT8 */ | ||
| 2639 | #define R367TER_DEBUG_LT8 0xf404 | ||
| 2640 | #define F367TER_F_DEBUG_LT8 0xf40400ff | ||
| 2641 | |||
| 2642 | /* DEBUG_LT9 */ | ||
| 2643 | #define R367TER_DEBUG_LT9 0xf405 | ||
| 2644 | #define F367TER_F_DEBUG_LT9 0xf40500ff | ||
| 2645 | |||
| 2646 | #define STV0367TER_NBREGS 445 | ||
| 2647 | |||
| 2648 | /* ID */ | ||
| 2649 | #define R367CAB_ID 0xf000 | ||
| 2650 | #define F367CAB_IDENTIFICATIONREGISTER 0xf00000ff | ||
| 2651 | |||
| 2652 | /* I2CRPT */ | ||
| 2653 | #define R367CAB_I2CRPT 0xf001 | ||
| 2654 | #define F367CAB_I2CT_ON 0xf0010080 | ||
| 2655 | #define F367CAB_ENARPT_LEVEL 0xf0010070 | ||
| 2656 | #define F367CAB_SCLT_DELAY 0xf0010008 | ||
| 2657 | #define F367CAB_SCLT_NOD 0xf0010004 | ||
| 2658 | #define F367CAB_STOP_ENABLE 0xf0010002 | ||
| 2659 | #define F367CAB_SDAT_NOD 0xf0010001 | ||
| 2660 | |||
| 2661 | /* TOPCTRL */ | ||
| 2662 | #define R367CAB_TOPCTRL 0xf002 | ||
| 2663 | #define F367CAB_STDBY 0xf0020080 | ||
| 2664 | #define F367CAB_STDBY_CORE 0xf0020020 | ||
| 2665 | #define F367CAB_QAM_COFDM 0xf0020010 | ||
| 2666 | #define F367CAB_TS_DIS 0xf0020008 | ||
| 2667 | #define F367CAB_DIR_CLK_216 0xf0020004 | ||
| 2668 | |||
| 2669 | /* IOCFG0 */ | ||
| 2670 | #define R367CAB_IOCFG0 0xf003 | ||
| 2671 | #define F367CAB_OP0_SD 0xf0030080 | ||
| 2672 | #define F367CAB_OP0_VAL 0xf0030040 | ||
| 2673 | #define F367CAB_OP0_OD 0xf0030020 | ||
| 2674 | #define F367CAB_OP0_INV 0xf0030010 | ||
| 2675 | #define F367CAB_OP0_DACVALUE_HI 0xf003000f | ||
| 2676 | |||
| 2677 | /* DAc0R */ | ||
| 2678 | #define R367CAB_DAC0R 0xf004 | ||
| 2679 | #define F367CAB_OP0_DACVALUE_LO 0xf00400ff | ||
| 2680 | |||
| 2681 | /* IOCFG1 */ | ||
| 2682 | #define R367CAB_IOCFG1 0xf005 | ||
| 2683 | #define F367CAB_IP0 0xf0050040 | ||
| 2684 | #define F367CAB_OP1_OD 0xf0050020 | ||
| 2685 | #define F367CAB_OP1_INV 0xf0050010 | ||
| 2686 | #define F367CAB_OP1_DACVALUE_HI 0xf005000f | ||
| 2687 | |||
| 2688 | /* DAC1R */ | ||
| 2689 | #define R367CAB_DAC1R 0xf006 | ||
| 2690 | #define F367CAB_OP1_DACVALUE_LO 0xf00600ff | ||
| 2691 | |||
| 2692 | /* IOCFG2 */ | ||
| 2693 | #define R367CAB_IOCFG2 0xf007 | ||
| 2694 | #define F367CAB_OP2_LOCK_CONF 0xf00700e0 | ||
| 2695 | #define F367CAB_OP2_OD 0xf0070010 | ||
| 2696 | #define F367CAB_OP2_VAL 0xf0070008 | ||
| 2697 | #define F367CAB_OP1_LOCK_CONF 0xf0070007 | ||
| 2698 | |||
| 2699 | /* SDFR */ | ||
| 2700 | #define R367CAB_SDFR 0xf008 | ||
| 2701 | #define F367CAB_OP0_FREQ 0xf00800f0 | ||
| 2702 | #define F367CAB_OP1_FREQ 0xf008000f | ||
| 2703 | |||
| 2704 | /* AUX_CLK */ | ||
| 2705 | #define R367CAB_AUX_CLK 0xf00a | ||
| 2706 | #define F367CAB_AUXFEC_CTL 0xf00a00c0 | ||
| 2707 | #define F367CAB_DIS_CKX4 0xf00a0020 | ||
| 2708 | #define F367CAB_CKSEL 0xf00a0018 | ||
| 2709 | #define F367CAB_CKDIV_PROG 0xf00a0006 | ||
| 2710 | #define F367CAB_AUXCLK_ENA 0xf00a0001 | ||
| 2711 | |||
| 2712 | /* FREESYS1 */ | ||
| 2713 | #define R367CAB_FREESYS1 0xf00b | ||
| 2714 | #define F367CAB_FREESYS_1 0xf00b00ff | ||
| 2715 | |||
| 2716 | /* FREESYS2 */ | ||
| 2717 | #define R367CAB_FREESYS2 0xf00c | ||
| 2718 | #define F367CAB_FREESYS_2 0xf00c00ff | ||
| 2719 | |||
| 2720 | /* FREESYS3 */ | ||
| 2721 | #define R367CAB_FREESYS3 0xf00d | ||
| 2722 | #define F367CAB_FREESYS_3 0xf00d00ff | ||
| 2723 | |||
| 2724 | /* GPIO_CFG */ | ||
| 2725 | #define R367CAB_GPIO_CFG 0xf00e | ||
| 2726 | #define F367CAB_GPIO7_OD 0xf00e0080 | ||
| 2727 | #define F367CAB_GPIO7_CFG 0xf00e0040 | ||
| 2728 | #define F367CAB_GPIO6_OD 0xf00e0020 | ||
| 2729 | #define F367CAB_GPIO6_CFG 0xf00e0010 | ||
| 2730 | #define F367CAB_GPIO5_OD 0xf00e0008 | ||
| 2731 | #define F367CAB_GPIO5_CFG 0xf00e0004 | ||
| 2732 | #define F367CAB_GPIO4_OD 0xf00e0002 | ||
| 2733 | #define F367CAB_GPIO4_CFG 0xf00e0001 | ||
| 2734 | |||
| 2735 | /* GPIO_CMD */ | ||
| 2736 | #define R367CAB_GPIO_CMD 0xf00f | ||
| 2737 | #define F367CAB_GPIO7_VAL 0xf00f0008 | ||
| 2738 | #define F367CAB_GPIO6_VAL 0xf00f0004 | ||
| 2739 | #define F367CAB_GPIO5_VAL 0xf00f0002 | ||
| 2740 | #define F367CAB_GPIO4_VAL 0xf00f0001 | ||
| 2741 | |||
| 2742 | /* TSTRES */ | ||
| 2743 | #define R367CAB_TSTRES 0xf0c0 | ||
| 2744 | #define F367CAB_FRES_DISPLAY 0xf0c00080 | ||
| 2745 | #define F367CAB_FRES_FIFO_AD 0xf0c00020 | ||
| 2746 | #define F367CAB_FRESRS 0xf0c00010 | ||
| 2747 | #define F367CAB_FRESACS 0xf0c00008 | ||
| 2748 | #define F367CAB_FRESFEC 0xf0c00004 | ||
| 2749 | #define F367CAB_FRES_PRIF 0xf0c00002 | ||
| 2750 | #define F367CAB_FRESCORE 0xf0c00001 | ||
| 2751 | |||
| 2752 | /* ANACTRL */ | ||
| 2753 | #define R367CAB_ANACTRL 0xf0c1 | ||
| 2754 | #define F367CAB_BYPASS_XTAL 0xf0c10040 | ||
| 2755 | #define F367CAB_BYPASS_PLLXN 0xf0c1000c | ||
| 2756 | #define F367CAB_DIS_PAD_OSC 0xf0c10002 | ||
| 2757 | #define F367CAB_STDBY_PLLXN 0xf0c10001 | ||
| 2758 | |||
| 2759 | /* TSTBUS */ | ||
| 2760 | #define R367CAB_TSTBUS 0xf0c2 | ||
| 2761 | #define F367CAB_TS_BYTE_CLK_INV 0xf0c20080 | ||
| 2762 | #define F367CAB_CFG_IP 0xf0c20070 | ||
| 2763 | #define F367CAB_CFG_TST 0xf0c2000f | ||
| 2764 | |||
| 2765 | /* RF_AGC1 */ | ||
| 2766 | #define R367CAB_RF_AGC1 0xf0d4 | ||
| 2767 | #define F367CAB_RF_AGC1_LEVEL_HI 0xf0d400ff | ||
| 2768 | |||
| 2769 | /* RF_AGC2 */ | ||
| 2770 | #define R367CAB_RF_AGC2 0xf0d5 | ||
| 2771 | #define F367CAB_REF_ADGP 0xf0d50080 | ||
| 2772 | #define F367CAB_STDBY_ADCGP 0xf0d50020 | ||
| 2773 | #define F367CAB_RF_AGC1_LEVEL_LO 0xf0d50003 | ||
| 2774 | |||
| 2775 | /* ANADIGCTRL */ | ||
| 2776 | #define R367CAB_ANADIGCTRL 0xf0d7 | ||
| 2777 | #define F367CAB_SEL_CLKDEM 0xf0d70020 | ||
| 2778 | #define F367CAB_EN_BUFFER_Q 0xf0d70010 | ||
| 2779 | #define F367CAB_EN_BUFFER_I 0xf0d70008 | ||
| 2780 | #define F367CAB_ADC_RIS_EGDE 0xf0d70004 | ||
| 2781 | #define F367CAB_SGN_ADC 0xf0d70002 | ||
| 2782 | #define F367CAB_SEL_AD12_SYNC 0xf0d70001 | ||
| 2783 | |||
| 2784 | /* PLLMDIV */ | ||
| 2785 | #define R367CAB_PLLMDIV 0xf0d8 | ||
| 2786 | #define F367CAB_PLL_MDIV 0xf0d800ff | ||
| 2787 | |||
| 2788 | /* PLLNDIV */ | ||
| 2789 | #define R367CAB_PLLNDIV 0xf0d9 | ||
| 2790 | #define F367CAB_PLL_NDIV 0xf0d900ff | ||
| 2791 | |||
| 2792 | /* PLLSETUP */ | ||
| 2793 | #define R367CAB_PLLSETUP 0xf0da | ||
| 2794 | #define F367CAB_PLL_PDIV 0xf0da0070 | ||
| 2795 | #define F367CAB_PLL_KDIV 0xf0da000f | ||
| 2796 | |||
| 2797 | /* DUAL_AD12 */ | ||
| 2798 | #define R367CAB_DUAL_AD12 0xf0db | ||
| 2799 | #define F367CAB_FS20M 0xf0db0020 | ||
| 2800 | #define F367CAB_FS50M 0xf0db0010 | ||
| 2801 | #define F367CAB_INMODe0 0xf0db0008 | ||
| 2802 | #define F367CAB_POFFQ 0xf0db0004 | ||
| 2803 | #define F367CAB_POFFI 0xf0db0002 | ||
| 2804 | #define F367CAB_INMODE1 0xf0db0001 | ||
| 2805 | |||
| 2806 | /* TSTBIST */ | ||
| 2807 | #define R367CAB_TSTBIST 0xf0dc | ||
| 2808 | #define F367CAB_TST_BYP_CLK 0xf0dc0080 | ||
| 2809 | #define F367CAB_TST_GCLKENA_STD 0xf0dc0040 | ||
| 2810 | #define F367CAB_TST_GCLKENA 0xf0dc0020 | ||
| 2811 | #define F367CAB_TST_MEMBIST 0xf0dc001f | ||
| 2812 | |||
| 2813 | /* CTRL_1 */ | ||
| 2814 | #define R367CAB_CTRL_1 0xf402 | ||
| 2815 | #define F367CAB_SOFT_RST 0xf4020080 | ||
| 2816 | #define F367CAB_EQU_RST 0xf4020008 | ||
| 2817 | #define F367CAB_CRL_RST 0xf4020004 | ||
| 2818 | #define F367CAB_TRL_RST 0xf4020002 | ||
| 2819 | #define F367CAB_AGC_RST 0xf4020001 | ||
| 2820 | |||
| 2821 | /* CTRL_2 */ | ||
| 2822 | #define R367CAB_CTRL_2 0xf403 | ||
| 2823 | #define F367CAB_DEINT_RST 0xf4030008 | ||
| 2824 | #define F367CAB_RS_RST 0xf4030004 | ||
| 2825 | |||
| 2826 | /* IT_STATUS1 */ | ||
| 2827 | #define R367CAB_IT_STATUS1 0xf408 | ||
| 2828 | #define F367CAB_SWEEP_OUT 0xf4080080 | ||
| 2829 | #define F367CAB_FSM_CRL 0xf4080040 | ||
| 2830 | #define F367CAB_CRL_LOCK 0xf4080020 | ||
| 2831 | #define F367CAB_MFSM 0xf4080010 | ||
| 2832 | #define F367CAB_TRL_LOCK 0xf4080008 | ||
| 2833 | #define F367CAB_TRL_AGC_LIMIT 0xf4080004 | ||
| 2834 | #define F367CAB_ADJ_AGC_LOCK 0xf4080002 | ||
| 2835 | #define F367CAB_AGC_QAM_LOCK 0xf4080001 | ||
| 2836 | |||
| 2837 | /* IT_STATUS2 */ | ||
| 2838 | #define R367CAB_IT_STATUS2 0xf409 | ||
| 2839 | #define F367CAB_TSMF_CNT 0xf4090080 | ||
| 2840 | #define F367CAB_TSMF_EOF 0xf4090040 | ||
| 2841 | #define F367CAB_TSMF_RDY 0xf4090020 | ||
| 2842 | #define F367CAB_FEC_NOCORR 0xf4090010 | ||
| 2843 | #define F367CAB_SYNCSTATE 0xf4090008 | ||
| 2844 | #define F367CAB_DEINT_LOCK 0xf4090004 | ||
| 2845 | #define F367CAB_FADDING_FRZ 0xf4090002 | ||
| 2846 | #define F367CAB_TAPMON_ALARM 0xf4090001 | ||
| 2847 | |||
| 2848 | /* IT_EN1 */ | ||
| 2849 | #define R367CAB_IT_EN1 0xf40a | ||
| 2850 | #define F367CAB_SWEEP_OUTE 0xf40a0080 | ||
| 2851 | #define F367CAB_FSM_CRLE 0xf40a0040 | ||
| 2852 | #define F367CAB_CRL_LOCKE 0xf40a0020 | ||
| 2853 | #define F367CAB_MFSME 0xf40a0010 | ||
| 2854 | #define F367CAB_TRL_LOCKE 0xf40a0008 | ||
| 2855 | #define F367CAB_TRL_AGC_LIMITE 0xf40a0004 | ||
| 2856 | #define F367CAB_ADJ_AGC_LOCKE 0xf40a0002 | ||
| 2857 | #define F367CAB_AGC_LOCKE 0xf40a0001 | ||
| 2858 | |||
| 2859 | /* IT_EN2 */ | ||
| 2860 | #define R367CAB_IT_EN2 0xf40b | ||
| 2861 | #define F367CAB_TSMF_CNTE 0xf40b0080 | ||
| 2862 | #define F367CAB_TSMF_EOFE 0xf40b0040 | ||
| 2863 | #define F367CAB_TSMF_RDYE 0xf40b0020 | ||
| 2864 | #define F367CAB_FEC_NOCORRE 0xf40b0010 | ||
| 2865 | #define F367CAB_SYNCSTATEE 0xf40b0008 | ||
| 2866 | #define F367CAB_DEINT_LOCKE 0xf40b0004 | ||
| 2867 | #define F367CAB_FADDING_FRZE 0xf40b0002 | ||
| 2868 | #define F367CAB_TAPMON_ALARME 0xf40b0001 | ||
| 2869 | |||
| 2870 | /* CTRL_STATUS */ | ||
| 2871 | #define R367CAB_CTRL_STATUS 0xf40c | ||
| 2872 | #define F367CAB_QAMFEC_LOCK 0xf40c0004 | ||
| 2873 | #define F367CAB_TSMF_LOCK 0xf40c0002 | ||
| 2874 | #define F367CAB_TSMF_ERROR 0xf40c0001 | ||
| 2875 | |||
| 2876 | /* TEST_CTL */ | ||
| 2877 | #define R367CAB_TEST_CTL 0xf40f | ||
| 2878 | #define F367CAB_TST_BLK_SEL 0xf40f0060 | ||
| 2879 | #define F367CAB_TST_BUS_SEL 0xf40f001f | ||
| 2880 | |||
| 2881 | /* AGC_CTL */ | ||
| 2882 | #define R367CAB_AGC_CTL 0xf410 | ||
| 2883 | #define F367CAB_AGC_LCK_TH 0xf41000f0 | ||
| 2884 | #define F367CAB_AGC_ACCUMRSTSEL 0xf4100007 | ||
| 2885 | |||
| 2886 | /* AGC_IF_CFG */ | ||
| 2887 | #define R367CAB_AGC_IF_CFG 0xf411 | ||
| 2888 | #define F367CAB_AGC_IF_BWSEL 0xf41100f0 | ||
| 2889 | #define F367CAB_AGC_IF_FREEZE 0xf4110002 | ||
| 2890 | |||
| 2891 | /* AGC_RF_CFG */ | ||
| 2892 | #define R367CAB_AGC_RF_CFG 0xf412 | ||
| 2893 | #define F367CAB_AGC_RF_BWSEL 0xf4120070 | ||
| 2894 | #define F367CAB_AGC_RF_FREEZE 0xf4120002 | ||
| 2895 | |||
| 2896 | /* AGC_PWM_CFG */ | ||
| 2897 | #define R367CAB_AGC_PWM_CFG 0xf413 | ||
| 2898 | #define F367CAB_AGC_RF_PWM_TST 0xf4130080 | ||
| 2899 | #define F367CAB_AGC_RF_PWM_INV 0xf4130040 | ||
| 2900 | #define F367CAB_AGC_IF_PWM_TST 0xf4130008 | ||
| 2901 | #define F367CAB_AGC_IF_PWM_INV 0xf4130004 | ||
| 2902 | #define F367CAB_AGC_PWM_CLKDIV 0xf4130003 | ||
| 2903 | |||
| 2904 | /* AGC_PWR_REF_L */ | ||
| 2905 | #define R367CAB_AGC_PWR_REF_L 0xf414 | ||
| 2906 | #define F367CAB_AGC_PWRREF_LO 0xf41400ff | ||
| 2907 | |||
| 2908 | /* AGC_PWR_REF_H */ | ||
| 2909 | #define R367CAB_AGC_PWR_REF_H 0xf415 | ||
| 2910 | #define F367CAB_AGC_PWRREF_HI 0xf4150003 | ||
| 2911 | |||
| 2912 | /* AGC_RF_TH_L */ | ||
| 2913 | #define R367CAB_AGC_RF_TH_L 0xf416 | ||
| 2914 | #define F367CAB_AGC_RF_TH_LO 0xf41600ff | ||
| 2915 | |||
| 2916 | /* AGC_RF_TH_H */ | ||
| 2917 | #define R367CAB_AGC_RF_TH_H 0xf417 | ||
| 2918 | #define F367CAB_AGC_RF_TH_HI 0xf417000f | ||
| 2919 | |||
| 2920 | /* AGC_IF_LTH_L */ | ||
| 2921 | #define R367CAB_AGC_IF_LTH_L 0xf418 | ||
| 2922 | #define F367CAB_AGC_IF_THLO_LO 0xf41800ff | ||
| 2923 | |||
| 2924 | /* AGC_IF_LTH_H */ | ||
| 2925 | #define R367CAB_AGC_IF_LTH_H 0xf419 | ||
| 2926 | #define F367CAB_AGC_IF_THLO_HI 0xf419000f | ||
| 2927 | |||
| 2928 | /* AGC_IF_HTH_L */ | ||
| 2929 | #define R367CAB_AGC_IF_HTH_L 0xf41a | ||
| 2930 | #define F367CAB_AGC_IF_THHI_LO 0xf41a00ff | ||
| 2931 | |||
| 2932 | /* AGC_IF_HTH_H */ | ||
| 2933 | #define R367CAB_AGC_IF_HTH_H 0xf41b | ||
| 2934 | #define F367CAB_AGC_IF_THHI_HI 0xf41b000f | ||
| 2935 | |||
| 2936 | /* AGC_PWR_RD_L */ | ||
| 2937 | #define R367CAB_AGC_PWR_RD_L 0xf41c | ||
| 2938 | #define F367CAB_AGC_PWR_WORD_LO 0xf41c00ff | ||
| 2939 | |||
| 2940 | /* AGC_PWR_RD_M */ | ||
| 2941 | #define R367CAB_AGC_PWR_RD_M 0xf41d | ||
| 2942 | #define F367CAB_AGC_PWR_WORD_ME 0xf41d00ff | ||
| 2943 | |||
| 2944 | /* AGC_PWR_RD_H */ | ||
| 2945 | #define R367CAB_AGC_PWR_RD_H 0xf41e | ||
| 2946 | #define F367CAB_AGC_PWR_WORD_HI 0xf41e0003 | ||
| 2947 | |||
| 2948 | /* AGC_PWM_IFCMD_L */ | ||
| 2949 | #define R367CAB_AGC_PWM_IFCMD_L 0xf420 | ||
| 2950 | #define F367CAB_AGC_IF_PWMCMD_LO 0xf42000ff | ||
| 2951 | |||
| 2952 | /* AGC_PWM_IFCMD_H */ | ||
| 2953 | #define R367CAB_AGC_PWM_IFCMD_H 0xf421 | ||
| 2954 | #define F367CAB_AGC_IF_PWMCMD_HI 0xf421000f | ||
| 2955 | |||
| 2956 | /* AGC_PWM_RFCMD_L */ | ||
| 2957 | #define R367CAB_AGC_PWM_RFCMD_L 0xf422 | ||
| 2958 | #define F367CAB_AGC_RF_PWMCMD_LO 0xf42200ff | ||
| 2959 | |||
| 2960 | /* AGC_PWM_RFCMD_H */ | ||
| 2961 | #define R367CAB_AGC_PWM_RFCMD_H 0xf423 | ||
| 2962 | #define F367CAB_AGC_RF_PWMCMD_HI 0xf423000f | ||
| 2963 | |||
| 2964 | /* IQDEM_CFG */ | ||
| 2965 | #define R367CAB_IQDEM_CFG 0xf424 | ||
| 2966 | #define F367CAB_IQDEM_CLK_SEL 0xf4240004 | ||
| 2967 | #define F367CAB_IQDEM_INVIQ 0xf4240002 | ||
| 2968 | #define F367CAB_IQDEM_A2dTYPE 0xf4240001 | ||
| 2969 | |||
| 2970 | /* MIX_NCO_LL */ | ||
| 2971 | #define R367CAB_MIX_NCO_LL 0xf425 | ||
| 2972 | #define F367CAB_MIX_NCO_INC_LL 0xf42500ff | ||
| 2973 | |||
| 2974 | /* MIX_NCO_HL */ | ||
| 2975 | #define R367CAB_MIX_NCO_HL 0xf426 | ||
| 2976 | #define F367CAB_MIX_NCO_INC_HL 0xf42600ff | ||
| 2977 | |||
| 2978 | /* MIX_NCO_HH */ | ||
| 2979 | #define R367CAB_MIX_NCO_HH 0xf427 | ||
| 2980 | #define F367CAB_MIX_NCO_INVCNST 0xf4270080 | ||
| 2981 | #define F367CAB_MIX_NCO_INC_HH 0xf427007f | ||
| 2982 | |||
| 2983 | /* SRC_NCO_LL */ | ||
| 2984 | #define R367CAB_SRC_NCO_LL 0xf428 | ||
| 2985 | #define F367CAB_SRC_NCO_INC_LL 0xf42800ff | ||
| 2986 | |||
| 2987 | /* SRC_NCO_LH */ | ||
| 2988 | #define R367CAB_SRC_NCO_LH 0xf429 | ||
| 2989 | #define F367CAB_SRC_NCO_INC_LH 0xf42900ff | ||
| 2990 | |||
| 2991 | /* SRC_NCO_HL */ | ||
| 2992 | #define R367CAB_SRC_NCO_HL 0xf42a | ||
| 2993 | #define F367CAB_SRC_NCO_INC_HL 0xf42a00ff | ||
| 2994 | |||
| 2995 | /* SRC_NCO_HH */ | ||
| 2996 | #define R367CAB_SRC_NCO_HH 0xf42b | ||
| 2997 | #define F367CAB_SRC_NCO_INC_HH 0xf42b007f | ||
| 2998 | |||
| 2999 | /* IQDEM_GAIN_SRC_L */ | ||
| 3000 | #define R367CAB_IQDEM_GAIN_SRC_L 0xf42c | ||
| 3001 | #define F367CAB_GAIN_SRC_LO 0xf42c00ff | ||
| 3002 | |||
| 3003 | /* IQDEM_GAIN_SRC_H */ | ||
| 3004 | #define R367CAB_IQDEM_GAIN_SRC_H 0xf42d | ||
| 3005 | #define F367CAB_GAIN_SRC_HI 0xf42d0003 | ||
| 3006 | |||
| 3007 | /* IQDEM_DCRM_CFG_LL */ | ||
| 3008 | #define R367CAB_IQDEM_DCRM_CFG_LL 0xf430 | ||
| 3009 | #define F367CAB_DCRM0_DCIN_L 0xf43000ff | ||
| 3010 | |||
| 3011 | /* IQDEM_DCRM_CFG_LH */ | ||
| 3012 | #define R367CAB_IQDEM_DCRM_CFG_LH 0xf431 | ||
| 3013 | #define F367CAB_DCRM1_I_DCIN_L 0xf43100fc | ||
| 3014 | #define F367CAB_DCRM0_DCIN_H 0xf4310003 | ||
| 3015 | |||
| 3016 | /* IQDEM_DCRM_CFG_HL */ | ||
| 3017 | #define R367CAB_IQDEM_DCRM_CFG_HL 0xf432 | ||
| 3018 | #define F367CAB_DCRM1_Q_DCIN_L 0xf43200f0 | ||
| 3019 | #define F367CAB_DCRM1_I_DCIN_H 0xf432000f | ||
| 3020 | |||
| 3021 | /* IQDEM_DCRM_CFG_HH */ | ||
| 3022 | #define R367CAB_IQDEM_DCRM_CFG_HH 0xf433 | ||
| 3023 | #define F367CAB_DCRM1_FRZ 0xf4330080 | ||
| 3024 | #define F367CAB_DCRM0_FRZ 0xf4330040 | ||
| 3025 | #define F367CAB_DCRM1_Q_DCIN_H 0xf433003f | ||
| 3026 | |||
| 3027 | /* IQDEM_ADJ_COEFf0 */ | ||
| 3028 | #define R367CAB_IQDEM_ADJ_COEFF0 0xf434 | ||
| 3029 | #define F367CAB_ADJIIR_COEFF10_L 0xf43400ff | ||
| 3030 | |||
| 3031 | /* IQDEM_ADJ_COEFF1 */ | ||
| 3032 | #define R367CAB_IQDEM_ADJ_COEFF1 0xf435 | ||
| 3033 | #define F367CAB_ADJIIR_COEFF11_L 0xf43500fc | ||
| 3034 | #define F367CAB_ADJIIR_COEFF10_H 0xf4350003 | ||
| 3035 | |||
| 3036 | /* IQDEM_ADJ_COEFF2 */ | ||
| 3037 | #define R367CAB_IQDEM_ADJ_COEFF2 0xf436 | ||
| 3038 | #define F367CAB_ADJIIR_COEFF12_L 0xf43600f0 | ||
| 3039 | #define F367CAB_ADJIIR_COEFF11_H 0xf436000f | ||
| 3040 | |||
| 3041 | /* IQDEM_ADJ_COEFF3 */ | ||
| 3042 | #define R367CAB_IQDEM_ADJ_COEFF3 0xf437 | ||
| 3043 | #define F367CAB_ADJIIR_COEFF20_L 0xf43700c0 | ||
| 3044 | #define F367CAB_ADJIIR_COEFF12_H 0xf437003f | ||
| 3045 | |||
| 3046 | /* IQDEM_ADJ_COEFF4 */ | ||
| 3047 | #define R367CAB_IQDEM_ADJ_COEFF4 0xf438 | ||
| 3048 | #define F367CAB_ADJIIR_COEFF20_H 0xf43800ff | ||
| 3049 | |||
| 3050 | /* IQDEM_ADJ_COEFF5 */ | ||
| 3051 | #define R367CAB_IQDEM_ADJ_COEFF5 0xf439 | ||
| 3052 | #define F367CAB_ADJIIR_COEFF21_L 0xf43900ff | ||
| 3053 | |||
| 3054 | /* IQDEM_ADJ_COEFF6 */ | ||
| 3055 | #define R367CAB_IQDEM_ADJ_COEFF6 0xf43a | ||
| 3056 | #define F367CAB_ADJIIR_COEFF22_L 0xf43a00fc | ||
| 3057 | #define F367CAB_ADJIIR_COEFF21_H 0xf43a0003 | ||
| 3058 | |||
| 3059 | /* IQDEM_ADJ_COEFF7 */ | ||
| 3060 | #define R367CAB_IQDEM_ADJ_COEFF7 0xf43b | ||
| 3061 | #define F367CAB_ADJIIR_COEFF22_H 0xf43b000f | ||
| 3062 | |||
| 3063 | /* IQDEM_ADJ_EN */ | ||
| 3064 | #define R367CAB_IQDEM_ADJ_EN 0xf43c | ||
| 3065 | #define F367CAB_ALLPASSFILT_EN 0xf43c0008 | ||
| 3066 | #define F367CAB_ADJ_AGC_EN 0xf43c0004 | ||
| 3067 | #define F367CAB_ADJ_COEFF_FRZ 0xf43c0002 | ||
| 3068 | #define F367CAB_ADJ_EN 0xf43c0001 | ||
| 3069 | |||
| 3070 | /* IQDEM_ADJ_AGC_REF */ | ||
| 3071 | #define R367CAB_IQDEM_ADJ_AGC_REF 0xf43d | ||
| 3072 | #define F367CAB_ADJ_AGC_REF 0xf43d00ff | ||
| 3073 | |||
| 3074 | /* ALLPASSFILT1 */ | ||
| 3075 | #define R367CAB_ALLPASSFILT1 0xf440 | ||
| 3076 | #define F367CAB_ALLPASSFILT_COEFF1_LO 0xf44000ff | ||
| 3077 | |||
| 3078 | /* ALLPASSFILT2 */ | ||
| 3079 | #define R367CAB_ALLPASSFILT2 0xf441 | ||
| 3080 | #define F367CAB_ALLPASSFILT_COEFF1_ME 0xf44100ff | ||
| 3081 | |||
| 3082 | /* ALLPASSFILT3 */ | ||
| 3083 | #define R367CAB_ALLPASSFILT3 0xf442 | ||
| 3084 | #define F367CAB_ALLPASSFILT_COEFF2_LO 0xf44200c0 | ||
| 3085 | #define F367CAB_ALLPASSFILT_COEFF1_HI 0xf442003f | ||
| 3086 | |||
| 3087 | /* ALLPASSFILT4 */ | ||
| 3088 | #define R367CAB_ALLPASSFILT4 0xf443 | ||
| 3089 | #define F367CAB_ALLPASSFILT_COEFF2_MEL 0xf44300ff | ||
| 3090 | |||
| 3091 | /* ALLPASSFILT5 */ | ||
| 3092 | #define R367CAB_ALLPASSFILT5 0xf444 | ||
| 3093 | #define F367CAB_ALLPASSFILT_COEFF2_MEH 0xf44400ff | ||
| 3094 | |||
| 3095 | /* ALLPASSFILT6 */ | ||
| 3096 | #define R367CAB_ALLPASSFILT6 0xf445 | ||
| 3097 | #define F367CAB_ALLPASSFILT_COEFF3_LO 0xf44500f0 | ||
| 3098 | #define F367CAB_ALLPASSFILT_COEFF2_HI 0xf445000f | ||
| 3099 | |||
| 3100 | /* ALLPASSFILT7 */ | ||
| 3101 | #define R367CAB_ALLPASSFILT7 0xf446 | ||
| 3102 | #define F367CAB_ALLPASSFILT_COEFF3_MEL 0xf44600ff | ||
| 3103 | |||
| 3104 | /* ALLPASSFILT8 */ | ||
| 3105 | #define R367CAB_ALLPASSFILT8 0xf447 | ||
| 3106 | #define F367CAB_ALLPASSFILT_COEFF3_MEH 0xf44700ff | ||
| 3107 | |||
| 3108 | /* ALLPASSFILT9 */ | ||
| 3109 | #define R367CAB_ALLPASSFILT9 0xf448 | ||
| 3110 | #define F367CAB_ALLPASSFILT_COEFF4_LO 0xf44800fc | ||
| 3111 | #define F367CAB_ALLPASSFILT_COEFF3_HI 0xf4480003 | ||
| 3112 | |||
| 3113 | /* ALLPASSFILT10 */ | ||
| 3114 | #define R367CAB_ALLPASSFILT10 0xf449 | ||
| 3115 | #define F367CAB_ALLPASSFILT_COEFF4_ME 0xf44900ff | ||
| 3116 | |||
| 3117 | /* ALLPASSFILT11 */ | ||
| 3118 | #define R367CAB_ALLPASSFILT11 0xf44a | ||
| 3119 | #define F367CAB_ALLPASSFILT_COEFF4_HI 0xf44a00ff | ||
| 3120 | |||
| 3121 | /* TRL_AGC_CFG */ | ||
| 3122 | #define R367CAB_TRL_AGC_CFG 0xf450 | ||
| 3123 | #define F367CAB_TRL_AGC_FREEZE 0xf4500080 | ||
| 3124 | #define F367CAB_TRL_AGC_REF 0xf450007f | ||
| 3125 | |||
| 3126 | /* TRL_LPF_CFG */ | ||
| 3127 | #define R367CAB_TRL_LPF_CFG 0xf454 | ||
| 3128 | #define F367CAB_NYQPOINT_INV 0xf4540040 | ||
| 3129 | #define F367CAB_TRL_SHIFT 0xf4540030 | ||
| 3130 | #define F367CAB_NYQ_COEFF_SEL 0xf454000c | ||
| 3131 | #define F367CAB_TRL_LPF_FREEZE 0xf4540002 | ||
| 3132 | #define F367CAB_TRL_LPF_CRT 0xf4540001 | ||
| 3133 | |||
| 3134 | /* TRL_LPF_ACQ_GAIN */ | ||
| 3135 | #define R367CAB_TRL_LPF_ACQ_GAIN 0xf455 | ||
| 3136 | #define F367CAB_TRL_GDIR_ACQ 0xf4550070 | ||
| 3137 | #define F367CAB_TRL_GINT_ACQ 0xf4550007 | ||
| 3138 | |||
| 3139 | /* TRL_LPF_TRK_GAIN */ | ||
| 3140 | #define R367CAB_TRL_LPF_TRK_GAIN 0xf456 | ||
| 3141 | #define F367CAB_TRL_GDIR_TRK 0xf4560070 | ||
| 3142 | #define F367CAB_TRL_GINT_TRK 0xf4560007 | ||
| 3143 | |||
| 3144 | /* TRL_LPF_OUT_GAIN */ | ||
| 3145 | #define R367CAB_TRL_LPF_OUT_GAIN 0xf457 | ||
| 3146 | #define F367CAB_TRL_GAIN_OUT 0xf4570007 | ||
| 3147 | |||
| 3148 | /* TRL_LOCKDET_LTH */ | ||
| 3149 | #define R367CAB_TRL_LOCKDET_LTH 0xf458 | ||
| 3150 | #define F367CAB_TRL_LCK_THLO 0xf4580007 | ||
| 3151 | |||
| 3152 | /* TRL_LOCKDET_HTH */ | ||
| 3153 | #define R367CAB_TRL_LOCKDET_HTH 0xf459 | ||
| 3154 | #define F367CAB_TRL_LCK_THHI 0xf45900ff | ||
| 3155 | |||
| 3156 | /* TRL_LOCKDET_TRGVAL */ | ||
| 3157 | #define R367CAB_TRL_LOCKDET_TRGVAL 0xf45a | ||
| 3158 | #define F367CAB_TRL_LCK_TRG 0xf45a00ff | ||
| 3159 | |||
| 3160 | /* IQ_QAM */ | ||
| 3161 | #define R367CAB_IQ_QAM 0xf45c | ||
| 3162 | #define F367CAB_IQ_INPUT 0xf45c0008 | ||
| 3163 | #define F367CAB_DETECT_MODE 0xf45c0007 | ||
| 3164 | |||
| 3165 | /* FSM_STATE */ | ||
| 3166 | #define R367CAB_FSM_STATE 0xf460 | ||
| 3167 | #define F367CAB_CRL_DFE 0xf4600080 | ||
| 3168 | #define F367CAB_DFE_START 0xf4600040 | ||
| 3169 | #define F367CAB_CTRLG_START 0xf4600030 | ||
| 3170 | #define F367CAB_FSM_FORCESTATE 0xf460000f | ||
| 3171 | |||
| 3172 | /* FSM_CTL */ | ||
| 3173 | #define R367CAB_FSM_CTL 0xf461 | ||
| 3174 | #define F367CAB_FEC2_EN 0xf4610040 | ||
| 3175 | #define F367CAB_SIT_EN 0xf4610020 | ||
| 3176 | #define F367CAB_TRL_AHEAD 0xf4610010 | ||
| 3177 | #define F367CAB_TRL2_EN 0xf4610008 | ||
| 3178 | #define F367CAB_FSM_EQA1_EN 0xf4610004 | ||
| 3179 | #define F367CAB_FSM_BKP_DIS 0xf4610002 | ||
| 3180 | #define F367CAB_FSM_FORCE_EN 0xf4610001 | ||
| 3181 | |||
| 3182 | /* FSM_STS */ | ||
| 3183 | #define R367CAB_FSM_STS 0xf462 | ||
| 3184 | #define F367CAB_FSM_STATUS 0xf462000f | ||
| 3185 | |||
| 3186 | /* FSM_SNR0_HTH */ | ||
| 3187 | #define R367CAB_FSM_SNR0_HTH 0xf463 | ||
| 3188 | #define F367CAB_SNR0_HTH 0xf46300ff | ||
| 3189 | |||
| 3190 | /* FSM_SNR1_HTH */ | ||
| 3191 | #define R367CAB_FSM_SNR1_HTH 0xf464 | ||
| 3192 | #define F367CAB_SNR1_HTH 0xf46400ff | ||
| 3193 | |||
| 3194 | /* FSM_SNR2_HTH */ | ||
| 3195 | #define R367CAB_FSM_SNR2_HTH 0xf465 | ||
| 3196 | #define F367CAB_SNR2_HTH 0xf46500ff | ||
| 3197 | |||
| 3198 | /* FSM_SNR0_LTH */ | ||
| 3199 | #define R367CAB_FSM_SNR0_LTH 0xf466 | ||
| 3200 | #define F367CAB_SNR0_LTH 0xf46600ff | ||
| 3201 | |||
| 3202 | /* FSM_SNR1_LTH */ | ||
| 3203 | #define R367CAB_FSM_SNR1_LTH 0xf467 | ||
| 3204 | #define F367CAB_SNR1_LTH 0xf46700ff | ||
| 3205 | |||
| 3206 | /* FSM_EQA1_HTH */ | ||
| 3207 | #define R367CAB_FSM_EQA1_HTH 0xf468 | ||
| 3208 | #define F367CAB_SNR3_HTH_LO 0xf46800f0 | ||
| 3209 | #define F367CAB_EQA1_HTH 0xf468000f | ||
| 3210 | |||
| 3211 | /* FSM_TEMPO */ | ||
| 3212 | #define R367CAB_FSM_TEMPO 0xf469 | ||
| 3213 | #define F367CAB_SIT 0xf46900c0 | ||
| 3214 | #define F367CAB_WST 0xf4690038 | ||
| 3215 | #define F367CAB_ELT 0xf4690006 | ||
| 3216 | #define F367CAB_SNR3_HTH_HI 0xf4690001 | ||
| 3217 | |||
| 3218 | /* FSM_CONFIG */ | ||
| 3219 | #define R367CAB_FSM_CONFIG 0xf46a | ||
| 3220 | #define F367CAB_FEC2_DFEOFF 0xf46a0004 | ||
| 3221 | #define F367CAB_PRIT_STATE 0xf46a0002 | ||
| 3222 | #define F367CAB_MODMAP_STATE 0xf46a0001 | ||
| 3223 | |||
| 3224 | /* EQU_I_TESTTAP_L */ | ||
| 3225 | #define R367CAB_EQU_I_TESTTAP_L 0xf474 | ||
| 3226 | #define F367CAB_I_TEST_TAP_L 0xf47400ff | ||
| 3227 | |||
| 3228 | /* EQU_I_TESTTAP_M */ | ||
| 3229 | #define R367CAB_EQU_I_TESTTAP_M 0xf475 | ||
| 3230 | #define F367CAB_I_TEST_TAP_M 0xf47500ff | ||
| 3231 | |||
| 3232 | /* EQU_I_TESTTAP_H */ | ||
| 3233 | #define R367CAB_EQU_I_TESTTAP_H 0xf476 | ||
| 3234 | #define F367CAB_I_TEST_TAP_H 0xf476001f | ||
| 3235 | |||
| 3236 | /* EQU_TESTAP_CFG */ | ||
| 3237 | #define R367CAB_EQU_TESTAP_CFG 0xf477 | ||
| 3238 | #define F367CAB_TEST_FFE_DFE_SEL 0xf4770040 | ||
| 3239 | #define F367CAB_TEST_TAP_SELECT 0xf477003f | ||
| 3240 | |||
| 3241 | /* EQU_Q_TESTTAP_L */ | ||
| 3242 | #define R367CAB_EQU_Q_TESTTAP_L 0xf478 | ||
| 3243 | #define F367CAB_Q_TEST_TAP_L 0xf47800ff | ||
| 3244 | |||
| 3245 | /* EQU_Q_TESTTAP_M */ | ||
| 3246 | #define R367CAB_EQU_Q_TESTTAP_M 0xf479 | ||
| 3247 | #define F367CAB_Q_TEST_TAP_M 0xf47900ff | ||
| 3248 | |||
| 3249 | /* EQU_Q_TESTTAP_H */ | ||
| 3250 | #define R367CAB_EQU_Q_TESTTAP_H 0xf47a | ||
| 3251 | #define F367CAB_Q_TEST_TAP_H 0xf47a001f | ||
| 3252 | |||
| 3253 | /* EQU_TAP_CTRL */ | ||
| 3254 | #define R367CAB_EQU_TAP_CTRL 0xf47b | ||
| 3255 | #define F367CAB_MTAP_FRZ 0xf47b0010 | ||
| 3256 | #define F367CAB_PRE_FREEZE 0xf47b0008 | ||
| 3257 | #define F367CAB_DFE_TAPMON_EN 0xf47b0004 | ||
| 3258 | #define F367CAB_FFE_TAPMON_EN 0xf47b0002 | ||
| 3259 | #define F367CAB_MTAP_ONLY 0xf47b0001 | ||
| 3260 | |||
| 3261 | /* EQU_CTR_CRL_CONTROL_L */ | ||
| 3262 | #define R367CAB_EQU_CTR_CRL_CONTROL_L 0xf47c | ||
| 3263 | #define F367CAB_EQU_CTR_CRL_CONTROL_LO 0xf47c00ff | ||
| 3264 | |||
| 3265 | /* EQU_CTR_CRL_CONTROL_H */ | ||
| 3266 | #define R367CAB_EQU_CTR_CRL_CONTROL_H 0xf47d | ||
| 3267 | #define F367CAB_EQU_CTR_CRL_CONTROL_HI 0xf47d00ff | ||
| 3268 | |||
| 3269 | /* EQU_CTR_HIPOW_L */ | ||
| 3270 | #define R367CAB_EQU_CTR_HIPOW_L 0xf47e | ||
| 3271 | #define F367CAB_CTR_HIPOW_L 0xf47e00ff | ||
| 3272 | |||
| 3273 | /* EQU_CTR_HIPOW_H */ | ||
| 3274 | #define R367CAB_EQU_CTR_HIPOW_H 0xf47f | ||
| 3275 | #define F367CAB_CTR_HIPOW_H 0xf47f00ff | ||
| 3276 | |||
| 3277 | /* EQU_I_EQU_LO */ | ||
| 3278 | #define R367CAB_EQU_I_EQU_LO 0xf480 | ||
| 3279 | #define F367CAB_EQU_I_EQU_L 0xf48000ff | ||
| 3280 | |||
| 3281 | /* EQU_I_EQU_HI */ | ||
| 3282 | #define R367CAB_EQU_I_EQU_HI 0xf481 | ||
| 3283 | #define F367CAB_EQU_I_EQU_H 0xf4810003 | ||
| 3284 | |||
| 3285 | /* EQU_Q_EQU_LO */ | ||
| 3286 | #define R367CAB_EQU_Q_EQU_LO 0xf482 | ||
| 3287 | #define F367CAB_EQU_Q_EQU_L 0xf48200ff | ||
| 3288 | |||
| 3289 | /* EQU_Q_EQU_HI */ | ||
| 3290 | #define R367CAB_EQU_Q_EQU_HI 0xf483 | ||
| 3291 | #define F367CAB_EQU_Q_EQU_H 0xf4830003 | ||
| 3292 | |||
| 3293 | /* EQU_MAPPER */ | ||
| 3294 | #define R367CAB_EQU_MAPPER 0xf484 | ||
| 3295 | #define F367CAB_QUAD_AUTO 0xf4840080 | ||
| 3296 | #define F367CAB_QUAD_INV 0xf4840040 | ||
| 3297 | #define F367CAB_QAM_MODE 0xf4840007 | ||
| 3298 | |||
| 3299 | /* EQU_SWEEP_RATE */ | ||
| 3300 | #define R367CAB_EQU_SWEEP_RATE 0xf485 | ||
| 3301 | #define F367CAB_SNR_PER 0xf48500c0 | ||
| 3302 | #define F367CAB_SWEEP_RATE 0xf485003f | ||
| 3303 | |||
| 3304 | /* EQU_SNR_LO */ | ||
| 3305 | #define R367CAB_EQU_SNR_LO 0xf486 | ||
| 3306 | #define F367CAB_SNR_LO 0xf48600ff | ||
| 3307 | |||
| 3308 | /* EQU_SNR_HI */ | ||
| 3309 | #define R367CAB_EQU_SNR_HI 0xf487 | ||
| 3310 | #define F367CAB_SNR_HI 0xf48700ff | ||
| 3311 | |||
| 3312 | /* EQU_GAMMA_LO */ | ||
| 3313 | #define R367CAB_EQU_GAMMA_LO 0xf488 | ||
| 3314 | #define F367CAB_GAMMA_LO 0xf48800ff | ||
| 3315 | |||
| 3316 | /* EQU_GAMMA_HI */ | ||
| 3317 | #define R367CAB_EQU_GAMMA_HI 0xf489 | ||
| 3318 | #define F367CAB_GAMMA_ME 0xf48900ff | ||
| 3319 | |||
| 3320 | /* EQU_ERR_GAIN */ | ||
| 3321 | #define R367CAB_EQU_ERR_GAIN 0xf48a | ||
| 3322 | #define F367CAB_EQA1MU 0xf48a0070 | ||
| 3323 | #define F367CAB_CRL2MU 0xf48a000e | ||
| 3324 | #define F367CAB_GAMMA_HI 0xf48a0001 | ||
| 3325 | |||
| 3326 | /* EQU_RADIUS */ | ||
| 3327 | #define R367CAB_EQU_RADIUS 0xf48b | ||
| 3328 | #define F367CAB_RADIUS 0xf48b00ff | ||
| 3329 | |||
| 3330 | /* EQU_FFE_MAINTAP */ | ||
| 3331 | #define R367CAB_EQU_FFE_MAINTAP 0xf48c | ||
| 3332 | #define F367CAB_FFE_MAINTAP_INIT 0xf48c00ff | ||
| 3333 | |||
| 3334 | /* EQU_FFE_LEAKAGE */ | ||
| 3335 | #define R367CAB_EQU_FFE_LEAKAGE 0xf48e | ||
| 3336 | #define F367CAB_LEAK_PER 0xf48e00f0 | ||
| 3337 | #define F367CAB_EQU_OUTSEL 0xf48e0002 | ||
| 3338 | #define F367CAB_PNT2dFE 0xf48e0001 | ||
| 3339 | |||
| 3340 | /* EQU_FFE_MAINTAP_POS */ | ||
| 3341 | #define R367CAB_EQU_FFE_MAINTAP_POS 0xf48f | ||
| 3342 | #define F367CAB_FFE_LEAK_EN 0xf48f0080 | ||
| 3343 | #define F367CAB_DFE_LEAK_EN 0xf48f0040 | ||
| 3344 | #define F367CAB_FFE_MAINTAP_POS 0xf48f003f | ||
| 3345 | |||
| 3346 | /* EQU_GAIN_WIDE */ | ||
| 3347 | #define R367CAB_EQU_GAIN_WIDE 0xf490 | ||
| 3348 | #define F367CAB_DFE_GAIN_WIDE 0xf49000f0 | ||
| 3349 | #define F367CAB_FFE_GAIN_WIDE 0xf490000f | ||
| 3350 | |||
| 3351 | /* EQU_GAIN_NARROW */ | ||
| 3352 | #define R367CAB_EQU_GAIN_NARROW 0xf491 | ||
| 3353 | #define F367CAB_DFE_GAIN_NARROW 0xf49100f0 | ||
| 3354 | #define F367CAB_FFE_GAIN_NARROW 0xf491000f | ||
| 3355 | |||
| 3356 | /* EQU_CTR_LPF_GAIN */ | ||
| 3357 | #define R367CAB_EQU_CTR_LPF_GAIN 0xf492 | ||
| 3358 | #define F367CAB_CTR_GTO 0xf4920080 | ||
| 3359 | #define F367CAB_CTR_GDIR 0xf4920070 | ||
| 3360 | #define F367CAB_SWEEP_EN 0xf4920008 | ||
| 3361 | #define F367CAB_CTR_GINT 0xf4920007 | ||
| 3362 | |||
| 3363 | /* EQU_CRL_LPF_GAIN */ | ||
| 3364 | #define R367CAB_EQU_CRL_LPF_GAIN 0xf493 | ||
| 3365 | #define F367CAB_CRL_GTO 0xf4930080 | ||
| 3366 | #define F367CAB_CRL_GDIR 0xf4930070 | ||
| 3367 | #define F367CAB_SWEEP_DIR 0xf4930008 | ||
| 3368 | #define F367CAB_CRL_GINT 0xf4930007 | ||
| 3369 | |||
| 3370 | /* EQU_GLOBAL_GAIN */ | ||
| 3371 | #define R367CAB_EQU_GLOBAL_GAIN 0xf494 | ||
| 3372 | #define F367CAB_CRL_GAIN 0xf49400f8 | ||
| 3373 | #define F367CAB_CTR_INC_GAIN 0xf4940004 | ||
| 3374 | #define F367CAB_CTR_FRAC 0xf4940003 | ||
| 3375 | |||
| 3376 | /* EQU_CRL_LD_SEN */ | ||
| 3377 | #define R367CAB_EQU_CRL_LD_SEN 0xf495 | ||
| 3378 | #define F367CAB_CTR_BADPOINT_EN 0xf4950080 | ||
| 3379 | #define F367CAB_CTR_GAIN 0xf4950070 | ||
| 3380 | #define F367CAB_LIMANEN 0xf4950008 | ||
| 3381 | #define F367CAB_CRL_LD_SEN 0xf4950007 | ||
| 3382 | |||
| 3383 | /* EQU_CRL_LD_VAL */ | ||
| 3384 | #define R367CAB_EQU_CRL_LD_VAL 0xf496 | ||
| 3385 | #define F367CAB_CRL_BISTH_LIMIT 0xf4960080 | ||
| 3386 | #define F367CAB_CARE_EN 0xf4960040 | ||
| 3387 | #define F367CAB_CRL_LD_PER 0xf4960030 | ||
| 3388 | #define F367CAB_CRL_LD_WST 0xf496000c | ||
| 3389 | #define F367CAB_CRL_LD_TFS 0xf4960003 | ||
| 3390 | |||
| 3391 | /* EQU_CRL_TFR */ | ||
| 3392 | #define R367CAB_EQU_CRL_TFR 0xf497 | ||
| 3393 | #define F367CAB_CRL_LD_TFR 0xf49700ff | ||
| 3394 | |||
| 3395 | /* EQU_CRL_BISTH_LO */ | ||
| 3396 | #define R367CAB_EQU_CRL_BISTH_LO 0xf498 | ||
| 3397 | #define F367CAB_CRL_BISTH_LO 0xf49800ff | ||
| 3398 | |||
| 3399 | /* EQU_CRL_BISTH_HI */ | ||
| 3400 | #define R367CAB_EQU_CRL_BISTH_HI 0xf499 | ||
| 3401 | #define F367CAB_CRL_BISTH_HI 0xf49900ff | ||
| 3402 | |||
| 3403 | /* EQU_SWEEP_RANGE_LO */ | ||
| 3404 | #define R367CAB_EQU_SWEEP_RANGE_LO 0xf49a | ||
| 3405 | #define F367CAB_SWEEP_RANGE_LO 0xf49a00ff | ||
| 3406 | |||
| 3407 | /* EQU_SWEEP_RANGE_HI */ | ||
| 3408 | #define R367CAB_EQU_SWEEP_RANGE_HI 0xf49b | ||
| 3409 | #define F367CAB_SWEEP_RANGE_HI 0xf49b00ff | ||
| 3410 | |||
| 3411 | /* EQU_CRL_LIMITER */ | ||
| 3412 | #define R367CAB_EQU_CRL_LIMITER 0xf49c | ||
| 3413 | #define F367CAB_BISECTOR_EN 0xf49c0080 | ||
| 3414 | #define F367CAB_PHEST128_EN 0xf49c0040 | ||
| 3415 | #define F367CAB_CRL_LIM 0xf49c003f | ||
| 3416 | |||
| 3417 | /* EQU_MODULUS_MAP */ | ||
| 3418 | #define R367CAB_EQU_MODULUS_MAP 0xf49d | ||
| 3419 | #define F367CAB_PNT_DEPTH 0xf49d00e0 | ||
| 3420 | #define F367CAB_MODULUS_CMP 0xf49d001f | ||
| 3421 | |||
| 3422 | /* EQU_PNT_GAIN */ | ||
| 3423 | #define R367CAB_EQU_PNT_GAIN 0xf49e | ||
| 3424 | #define F367CAB_PNT_EN 0xf49e0080 | ||
| 3425 | #define F367CAB_MODULUSMAP_EN 0xf49e0040 | ||
| 3426 | #define F367CAB_PNT_GAIN 0xf49e003f | ||
| 3427 | |||
| 3428 | /* FEC_AC_CTR_0 */ | ||
| 3429 | #define R367CAB_FEC_AC_CTR_0 0xf4a8 | ||
| 3430 | #define F367CAB_BE_BYPASS 0xf4a80020 | ||
| 3431 | #define F367CAB_REFRESH47 0xf4a80010 | ||
| 3432 | #define F367CAB_CT_NBST 0xf4a80008 | ||
| 3433 | #define F367CAB_TEI_ENA 0xf4a80004 | ||
| 3434 | #define F367CAB_DS_ENA 0xf4a80002 | ||
| 3435 | #define F367CAB_TSMF_EN 0xf4a80001 | ||
| 3436 | |||
| 3437 | /* FEC_AC_CTR_1 */ | ||
| 3438 | #define R367CAB_FEC_AC_CTR_1 0xf4a9 | ||
| 3439 | #define F367CAB_DEINT_DEPTH 0xf4a900ff | ||
| 3440 | |||
| 3441 | /* FEC_AC_CTR_2 */ | ||
| 3442 | #define R367CAB_FEC_AC_CTR_2 0xf4aa | ||
| 3443 | #define F367CAB_DEINT_M 0xf4aa00f8 | ||
| 3444 | #define F367CAB_DIS_UNLOCK 0xf4aa0004 | ||
| 3445 | #define F367CAB_DESCR_MODE 0xf4aa0003 | ||
| 3446 | |||
| 3447 | /* FEC_AC_CTR_3 */ | ||
| 3448 | #define R367CAB_FEC_AC_CTR_3 0xf4ab | ||
| 3449 | #define F367CAB_DI_UNLOCK 0xf4ab0080 | ||
| 3450 | #define F367CAB_DI_FREEZE 0xf4ab0040 | ||
| 3451 | #define F367CAB_MISMATCH 0xf4ab0030 | ||
| 3452 | #define F367CAB_ACQ_MODE 0xf4ab000c | ||
| 3453 | #define F367CAB_TRK_MODE 0xf4ab0003 | ||
| 3454 | |||
| 3455 | /* FEC_STATUS */ | ||
| 3456 | #define R367CAB_FEC_STATUS 0xf4ac | ||
| 3457 | #define F367CAB_DEINT_SMCNTR 0xf4ac00e0 | ||
| 3458 | #define F367CAB_DEINT_SYNCSTATE 0xf4ac0018 | ||
| 3459 | #define F367CAB_DEINT_SYNLOST 0xf4ac0004 | ||
| 3460 | #define F367CAB_DESCR_SYNCSTATE 0xf4ac0002 | ||
| 3461 | |||
| 3462 | /* RS_COUNTER_0 */ | ||
| 3463 | #define R367CAB_RS_COUNTER_0 0xf4ae | ||
| 3464 | #define F367CAB_BK_CT_L 0xf4ae00ff | ||
| 3465 | |||
| 3466 | /* RS_COUNTER_1 */ | ||
| 3467 | #define R367CAB_RS_COUNTER_1 0xf4af | ||
| 3468 | #define F367CAB_BK_CT_H 0xf4af00ff | ||
| 3469 | |||
| 3470 | /* RS_COUNTER_2 */ | ||
| 3471 | #define R367CAB_RS_COUNTER_2 0xf4b0 | ||
| 3472 | #define F367CAB_CORR_CT_L 0xf4b000ff | ||
| 3473 | |||
| 3474 | /* RS_COUNTER_3 */ | ||
| 3475 | #define R367CAB_RS_COUNTER_3 0xf4b1 | ||
| 3476 | #define F367CAB_CORR_CT_H 0xf4b100ff | ||
| 3477 | |||
| 3478 | /* RS_COUNTER_4 */ | ||
| 3479 | #define R367CAB_RS_COUNTER_4 0xf4b2 | ||
| 3480 | #define F367CAB_UNCORR_CT_L 0xf4b200ff | ||
| 3481 | |||
| 3482 | /* RS_COUNTER_5 */ | ||
| 3483 | #define R367CAB_RS_COUNTER_5 0xf4b3 | ||
| 3484 | #define F367CAB_UNCORR_CT_H 0xf4b300ff | ||
| 3485 | |||
| 3486 | /* BERT_0 */ | ||
| 3487 | #define R367CAB_BERT_0 0xf4b4 | ||
| 3488 | #define F367CAB_RS_NOCORR 0xf4b40004 | ||
| 3489 | #define F367CAB_CT_HOLD 0xf4b40002 | ||
| 3490 | #define F367CAB_CT_CLEAR 0xf4b40001 | ||
| 3491 | |||
| 3492 | /* BERT_1 */ | ||
| 3493 | #define R367CAB_BERT_1 0xf4b5 | ||
| 3494 | #define F367CAB_BERT_ON 0xf4b50020 | ||
| 3495 | #define F367CAB_BERT_ERR_SRC 0xf4b50010 | ||
| 3496 | #define F367CAB_BERT_ERR_MODE 0xf4b50008 | ||
| 3497 | #define F367CAB_BERT_NBYTE 0xf4b50007 | ||
| 3498 | |||
| 3499 | /* BERT_2 */ | ||
| 3500 | #define R367CAB_BERT_2 0xf4b6 | ||
| 3501 | #define F367CAB_BERT_ERRCOUNT_L 0xf4b600ff | ||
| 3502 | |||
| 3503 | /* BERT_3 */ | ||
| 3504 | #define R367CAB_BERT_3 0xf4b7 | ||
| 3505 | #define F367CAB_BERT_ERRCOUNT_H 0xf4b700ff | ||
| 3506 | |||
| 3507 | /* OUTFORMAT_0 */ | ||
| 3508 | #define R367CAB_OUTFORMAT_0 0xf4b8 | ||
| 3509 | #define F367CAB_CLK_POLARITY 0xf4b80080 | ||
| 3510 | #define F367CAB_FEC_TYPE 0xf4b80040 | ||
| 3511 | #define F367CAB_SYNC_STRIP 0xf4b80008 | ||
| 3512 | #define F367CAB_TS_SWAP 0xf4b80004 | ||
| 3513 | #define F367CAB_OUTFORMAT 0xf4b80003 | ||
| 3514 | |||
| 3515 | /* OUTFORMAT_1 */ | ||
| 3516 | #define R367CAB_OUTFORMAT_1 0xf4b9 | ||
| 3517 | #define F367CAB_CI_DIVRANGE 0xf4b900ff | ||
| 3518 | |||
| 3519 | /* SMOOTHER_2 */ | ||
| 3520 | #define R367CAB_SMOOTHER_2 0xf4be | ||
| 3521 | #define F367CAB_FIFO_BYPASS 0xf4be0020 | ||
| 3522 | |||
| 3523 | /* TSMF_CTRL_0 */ | ||
| 3524 | #define R367CAB_TSMF_CTRL_0 0xf4c0 | ||
| 3525 | #define F367CAB_TS_NUMBER 0xf4c0001e | ||
| 3526 | #define F367CAB_SEL_MODE 0xf4c00001 | ||
| 3527 | |||
| 3528 | /* TSMF_CTRL_1 */ | ||
| 3529 | #define R367CAB_TSMF_CTRL_1 0xf4c1 | ||
| 3530 | #define F367CAB_CHECK_ERROR_BIT 0xf4c10080 | ||
| 3531 | #define F367CAB_CHCK_F_SYNC 0xf4c10040 | ||
| 3532 | #define F367CAB_H_MODE 0xf4c10008 | ||
| 3533 | #define F367CAB_D_V_MODE 0xf4c10004 | ||
| 3534 | #define F367CAB_MODE 0xf4c10003 | ||
| 3535 | |||
| 3536 | /* TSMF_CTRL_3 */ | ||
| 3537 | #define R367CAB_TSMF_CTRL_3 0xf4c3 | ||
| 3538 | #define F367CAB_SYNC_IN_COUNT 0xf4c300f0 | ||
| 3539 | #define F367CAB_SYNC_OUT_COUNT 0xf4c3000f | ||
| 3540 | |||
| 3541 | /* TS_ON_ID_0 */ | ||
| 3542 | #define R367CAB_TS_ON_ID_0 0xf4c4 | ||
| 3543 | #define F367CAB_TS_ID_L 0xf4c400ff | ||
| 3544 | |||
| 3545 | /* TS_ON_ID_1 */ | ||
| 3546 | #define R367CAB_TS_ON_ID_1 0xf4c5 | ||
| 3547 | #define F367CAB_TS_ID_H 0xf4c500ff | ||
| 3548 | |||
| 3549 | /* TS_ON_ID_2 */ | ||
| 3550 | #define R367CAB_TS_ON_ID_2 0xf4c6 | ||
| 3551 | #define F367CAB_ON_ID_L 0xf4c600ff | ||
| 3552 | |||
| 3553 | /* TS_ON_ID_3 */ | ||
| 3554 | #define R367CAB_TS_ON_ID_3 0xf4c7 | ||
| 3555 | #define F367CAB_ON_ID_H 0xf4c700ff | ||
| 3556 | |||
| 3557 | /* RE_STATUS_0 */ | ||
| 3558 | #define R367CAB_RE_STATUS_0 0xf4c8 | ||
| 3559 | #define F367CAB_RECEIVE_STATUS_L 0xf4c800ff | ||
| 3560 | |||
| 3561 | /* RE_STATUS_1 */ | ||
| 3562 | #define R367CAB_RE_STATUS_1 0xf4c9 | ||
| 3563 | #define F367CAB_RECEIVE_STATUS_LH 0xf4c900ff | ||
| 3564 | |||
| 3565 | /* RE_STATUS_2 */ | ||
| 3566 | #define R367CAB_RE_STATUS_2 0xf4ca | ||
| 3567 | #define F367CAB_RECEIVE_STATUS_HL 0xf4ca00ff | ||
| 3568 | |||
| 3569 | /* RE_STATUS_3 */ | ||
| 3570 | #define R367CAB_RE_STATUS_3 0xf4cb | ||
| 3571 | #define F367CAB_RECEIVE_STATUS_HH 0xf4cb003f | ||
| 3572 | |||
| 3573 | /* TS_STATUS_0 */ | ||
| 3574 | #define R367CAB_TS_STATUS_0 0xf4cc | ||
| 3575 | #define F367CAB_TS_STATUS_L 0xf4cc00ff | ||
| 3576 | |||
| 3577 | /* TS_STATUS_1 */ | ||
| 3578 | #define R367CAB_TS_STATUS_1 0xf4cd | ||
| 3579 | #define F367CAB_TS_STATUS_H 0xf4cd007f | ||
| 3580 | |||
| 3581 | /* TS_STATUS_2 */ | ||
| 3582 | #define R367CAB_TS_STATUS_2 0xf4ce | ||
| 3583 | #define F367CAB_ERROR 0xf4ce0080 | ||
| 3584 | #define F367CAB_EMERGENCY 0xf4ce0040 | ||
| 3585 | #define F367CAB_CRE_TS 0xf4ce0030 | ||
| 3586 | #define F367CAB_VER 0xf4ce000e | ||
| 3587 | #define F367CAB_M_LOCK 0xf4ce0001 | ||
| 3588 | |||
| 3589 | /* TS_STATUS_3 */ | ||
| 3590 | #define R367CAB_TS_STATUS_3 0xf4cf | ||
| 3591 | #define F367CAB_UPDATE_READY 0xf4cf0080 | ||
| 3592 | #define F367CAB_END_FRAME_HEADER 0xf4cf0040 | ||
| 3593 | #define F367CAB_CONTCNT 0xf4cf0020 | ||
| 3594 | #define F367CAB_TS_IDENTIFIER_SEL 0xf4cf000f | ||
| 3595 | |||
| 3596 | /* T_O_ID_0 */ | ||
| 3597 | #define R367CAB_T_O_ID_0 0xf4d0 | ||
| 3598 | #define F367CAB_ON_ID_I_L 0xf4d000ff | ||
| 3599 | |||
| 3600 | /* T_O_ID_1 */ | ||
| 3601 | #define R367CAB_T_O_ID_1 0xf4d1 | ||
| 3602 | #define F367CAB_ON_ID_I_H 0xf4d100ff | ||
| 3603 | |||
| 3604 | /* T_O_ID_2 */ | ||
| 3605 | #define R367CAB_T_O_ID_2 0xf4d2 | ||
| 3606 | #define F367CAB_TS_ID_I_L 0xf4d200ff | ||
| 3607 | |||
| 3608 | /* T_O_ID_3 */ | ||
| 3609 | #define R367CAB_T_O_ID_3 0xf4d3 | ||
| 3610 | #define F367CAB_TS_ID_I_H 0xf4d300ff | ||
| 3611 | |||
| 3612 | #define STV0367CAB_NBREGS 187 | ||
| 3613 | |||
| 3614 | #endif | ||