diff options
Diffstat (limited to 'drivers/media/dvb/frontends/drxk_hard.c')
-rw-r--r-- | drivers/media/dvb/frontends/drxk_hard.c | 314 |
1 files changed, 148 insertions, 166 deletions
diff --git a/drivers/media/dvb/frontends/drxk_hard.c b/drivers/media/dvb/frontends/drxk_hard.c index f6431ef827dc..6980ed7b8786 100644 --- a/drivers/media/dvb/frontends/drxk_hard.c +++ b/drivers/media/dvb/frontends/drxk_hard.c | |||
@@ -368,10 +368,10 @@ static int i2c_read(struct i2c_adapter *adap, | |||
368 | } | 368 | } |
369 | if (debug > 2) { | 369 | if (debug > 2) { |
370 | int i; | 370 | int i; |
371 | dprintk(2, ": read from "); | 371 | dprintk(2, ": read from"); |
372 | for (i = 0; i < len; i++) | 372 | for (i = 0; i < len; i++) |
373 | printk(KERN_CONT " %02x", msg[i]); | 373 | printk(KERN_CONT " %02x", msg[i]); |
374 | printk(KERN_CONT "Value = "); | 374 | printk(KERN_CONT ", value = "); |
375 | for (i = 0; i < alen; i++) | 375 | for (i = 0; i < alen; i++) |
376 | printk(KERN_CONT " %02x", answ[i]); | 376 | printk(KERN_CONT " %02x", answ[i]); |
377 | printk(KERN_CONT "\n"); | 377 | printk(KERN_CONT "\n"); |
@@ -660,7 +660,6 @@ static int init_state(struct drxk_state *state) | |||
660 | /* io_pad_cfg_mode output mode is drive always */ | 660 | /* io_pad_cfg_mode output mode is drive always */ |
661 | /* io_pad_cfg_drive is set to power 2 (23 mA) */ | 661 | /* io_pad_cfg_drive is set to power 2 (23 mA) */ |
662 | u32 ulGPIOCfg = 0x0113; | 662 | u32 ulGPIOCfg = 0x0113; |
663 | u32 ulSerialMode = 1; | ||
664 | u32 ulInvertTSClock = 0; | 663 | u32 ulInvertTSClock = 0; |
665 | u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; | 664 | u32 ulTSDataStrength = DRXK_MPEG_SERIAL_OUTPUT_PIN_DRIVE_STRENGTH; |
666 | u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; | 665 | u32 ulTSClockkStrength = DRXK_MPEG_OUTPUT_CLK_DRIVE_STRENGTH; |
@@ -681,7 +680,8 @@ static int init_state(struct drxk_state *state) | |||
681 | state->m_hasOOB = false; | 680 | state->m_hasOOB = false; |
682 | state->m_hasAudio = false; | 681 | state->m_hasAudio = false; |
683 | 682 | ||
684 | state->m_ChunkSize = 124; | 683 | if (!state->m_ChunkSize) |
684 | state->m_ChunkSize = 124; | ||
685 | 685 | ||
686 | state->m_oscClockFreq = 0; | 686 | state->m_oscClockFreq = 0; |
687 | state->m_smartAntInverted = false; | 687 | state->m_smartAntInverted = false; |
@@ -810,8 +810,6 @@ static int init_state(struct drxk_state *state) | |||
810 | /* MPEG output configuration */ | 810 | /* MPEG output configuration */ |
811 | state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ | 811 | state->m_enableMPEGOutput = true; /* If TRUE; enable MPEG ouput */ |
812 | state->m_insertRSByte = false; /* If TRUE; insert RS byte */ | 812 | state->m_insertRSByte = false; /* If TRUE; insert RS byte */ |
813 | state->m_enableParallel = true; /* If TRUE; | ||
814 | parallel out otherwise serial */ | ||
815 | state->m_invertDATA = false; /* If TRUE; invert DATA signals */ | 813 | state->m_invertDATA = false; /* If TRUE; invert DATA signals */ |
816 | state->m_invertERR = false; /* If TRUE; invert ERR signal */ | 814 | state->m_invertERR = false; /* If TRUE; invert ERR signal */ |
817 | state->m_invertSTR = false; /* If TRUE; invert STR signals */ | 815 | state->m_invertSTR = false; /* If TRUE; invert STR signals */ |
@@ -856,8 +854,6 @@ static int init_state(struct drxk_state *state) | |||
856 | state->m_bPowerDown = false; | 854 | state->m_bPowerDown = false; |
857 | state->m_currentPowerMode = DRX_POWER_DOWN; | 855 | state->m_currentPowerMode = DRX_POWER_DOWN; |
858 | 856 | ||
859 | state->m_enableParallel = (ulSerialMode == 0); | ||
860 | |||
861 | state->m_rfmirror = (ulRfMirror == 0); | 857 | state->m_rfmirror = (ulRfMirror == 0); |
862 | state->m_IfAgcPol = false; | 858 | state->m_IfAgcPol = false; |
863 | return 0; | 859 | return 0; |
@@ -946,6 +942,9 @@ static int GetDeviceCapabilities(struct drxk_state *state) | |||
946 | status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); | 942 | status = read32(state, SIO_TOP_JTAGID_LO__A, &sioTopJtagidLo); |
947 | if (status < 0) | 943 | if (status < 0) |
948 | goto error; | 944 | goto error; |
945 | |||
946 | printk(KERN_ERR "drxk: status = 0x%08x\n", sioTopJtagidLo); | ||
947 | |||
949 | /* driver 0.9.0 */ | 948 | /* driver 0.9.0 */ |
950 | switch ((sioTopJtagidLo >> 29) & 0xF) { | 949 | switch ((sioTopJtagidLo >> 29) & 0xF) { |
951 | case 0: | 950 | case 0: |
@@ -963,7 +962,8 @@ static int GetDeviceCapabilities(struct drxk_state *state) | |||
963 | default: | 962 | default: |
964 | state->m_deviceSpin = DRXK_SPIN_UNKNOWN; | 963 | state->m_deviceSpin = DRXK_SPIN_UNKNOWN; |
965 | status = -EINVAL; | 964 | status = -EINVAL; |
966 | printk(KERN_ERR "drxk: Spin unknown\n"); | 965 | printk(KERN_ERR "drxk: Spin %d unknown\n", |
966 | (sioTopJtagidLo >> 29) & 0xF); | ||
967 | goto error2; | 967 | goto error2; |
968 | } | 968 | } |
969 | switch ((sioTopJtagidLo >> 12) & 0xFF) { | 969 | switch ((sioTopJtagidLo >> 12) & 0xFF) { |
@@ -1190,7 +1190,9 @@ static int MPEGTSConfigurePins(struct drxk_state *state, bool mpegEnable) | |||
1190 | u16 sioPdrMclkCfg = 0; | 1190 | u16 sioPdrMclkCfg = 0; |
1191 | u16 sioPdrMdxCfg = 0; | 1191 | u16 sioPdrMdxCfg = 0; |
1192 | 1192 | ||
1193 | dprintk(1, "\n"); | 1193 | dprintk(1, ": mpeg %s, %s mode\n", |
1194 | mpegEnable ? "enable" : "disable", | ||
1195 | state->m_enableParallel ? "parallel" : "serial"); | ||
1194 | 1196 | ||
1195 | /* stop lock indicator process */ | 1197 | /* stop lock indicator process */ |
1196 | status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); | 1198 | status = write16(state, SCU_RAM_GPIO__A, SCU_RAM_GPIO_HW_LOCK_IND_DISABLE); |
@@ -1846,6 +1848,7 @@ static int SetOperationMode(struct drxk_state *state, | |||
1846 | */ | 1848 | */ |
1847 | switch (oMode) { | 1849 | switch (oMode) { |
1848 | case OM_DVBT: | 1850 | case OM_DVBT: |
1851 | dprintk(1, ": DVB-T\n"); | ||
1849 | state->m_OperationMode = oMode; | 1852 | state->m_OperationMode = oMode; |
1850 | status = SetDVBTStandard(state, oMode); | 1853 | status = SetDVBTStandard(state, oMode); |
1851 | if (status < 0) | 1854 | if (status < 0) |
@@ -1853,6 +1856,8 @@ static int SetOperationMode(struct drxk_state *state, | |||
1853 | break; | 1856 | break; |
1854 | case OM_QAM_ITU_A: /* fallthrough */ | 1857 | case OM_QAM_ITU_A: /* fallthrough */ |
1855 | case OM_QAM_ITU_C: | 1858 | case OM_QAM_ITU_C: |
1859 | dprintk(1, ": DVB-C Annex %c\n", | ||
1860 | (state->m_OperationMode == OM_QAM_ITU_A) ? 'A' : 'C'); | ||
1856 | state->m_OperationMode = oMode; | 1861 | state->m_OperationMode = oMode; |
1857 | status = SetQAMStandard(state, oMode); | 1862 | status = SetQAMStandard(state, oMode); |
1858 | if (status < 0) | 1863 | if (status < 0) |
@@ -1881,7 +1886,7 @@ static int Start(struct drxk_state *state, s32 offsetFreq, | |||
1881 | state->m_DrxkState != DRXK_DTV_STARTED) | 1886 | state->m_DrxkState != DRXK_DTV_STARTED) |
1882 | goto error; | 1887 | goto error; |
1883 | 1888 | ||
1884 | state->m_bMirrorFreqSpect = (state->param.inversion == INVERSION_ON); | 1889 | state->m_bMirrorFreqSpect = (state->props.inversion == INVERSION_ON); |
1885 | 1890 | ||
1886 | if (IntermediateFrequency < 0) { | 1891 | if (IntermediateFrequency < 0) { |
1887 | state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; | 1892 | state->m_bMirrorFreqSpect = !state->m_bMirrorFreqSpect; |
@@ -2503,7 +2508,7 @@ static int GetQAMSignalToNoise(struct drxk_state *state, | |||
2503 | u16 qamSlErrPower = 0; /* accum. error between | 2508 | u16 qamSlErrPower = 0; /* accum. error between |
2504 | raw and sliced symbols */ | 2509 | raw and sliced symbols */ |
2505 | u32 qamSlSigPower = 0; /* used for MER, depends of | 2510 | u32 qamSlSigPower = 0; /* used for MER, depends of |
2506 | QAM constellation */ | 2511 | QAM modulation */ |
2507 | u32 qamSlMer = 0; /* QAM MER */ | 2512 | u32 qamSlMer = 0; /* QAM MER */ |
2508 | 2513 | ||
2509 | dprintk(1, "\n"); | 2514 | dprintk(1, "\n"); |
@@ -2517,7 +2522,7 @@ static int GetQAMSignalToNoise(struct drxk_state *state, | |||
2517 | return -EINVAL; | 2522 | return -EINVAL; |
2518 | } | 2523 | } |
2519 | 2524 | ||
2520 | switch (state->param.u.qam.modulation) { | 2525 | switch (state->props.modulation) { |
2521 | case QAM_16: | 2526 | case QAM_16: |
2522 | qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; | 2527 | qamSlSigPower = DRXK_QAM_SL_SIG_POWER_QAM16 << 2; |
2523 | break; | 2528 | break; |
@@ -2748,7 +2753,7 @@ static int GetDVBCQuality(struct drxk_state *state, s32 *pQuality) | |||
2748 | if (status < 0) | 2753 | if (status < 0) |
2749 | break; | 2754 | break; |
2750 | 2755 | ||
2751 | switch (state->param.u.qam.modulation) { | 2756 | switch (state->props.modulation) { |
2752 | case QAM_16: | 2757 | case QAM_16: |
2753 | SignalToNoiseRel = SignalToNoise - 200; | 2758 | SignalToNoiseRel = SignalToNoise - 200; |
2754 | break; | 2759 | break; |
@@ -3813,7 +3818,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
3813 | /*== Write channel settings to device =====================================*/ | 3818 | /*== Write channel settings to device =====================================*/ |
3814 | 3819 | ||
3815 | /* mode */ | 3820 | /* mode */ |
3816 | switch (state->param.u.ofdm.transmission_mode) { | 3821 | switch (state->props.transmission_mode) { |
3817 | case TRANSMISSION_MODE_AUTO: | 3822 | case TRANSMISSION_MODE_AUTO: |
3818 | default: | 3823 | default: |
3819 | operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; | 3824 | operationMode |= OFDM_SC_RA_RAM_OP_AUTO_MODE__M; |
@@ -3827,7 +3832,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
3827 | } | 3832 | } |
3828 | 3833 | ||
3829 | /* guard */ | 3834 | /* guard */ |
3830 | switch (state->param.u.ofdm.guard_interval) { | 3835 | switch (state->props.guard_interval) { |
3831 | default: | 3836 | default: |
3832 | case GUARD_INTERVAL_AUTO: | 3837 | case GUARD_INTERVAL_AUTO: |
3833 | operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; | 3838 | operationMode |= OFDM_SC_RA_RAM_OP_AUTO_GUARD__M; |
@@ -3847,7 +3852,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
3847 | } | 3852 | } |
3848 | 3853 | ||
3849 | /* hierarchy */ | 3854 | /* hierarchy */ |
3850 | switch (state->param.u.ofdm.hierarchy_information) { | 3855 | switch (state->props.hierarchy) { |
3851 | case HIERARCHY_AUTO: | 3856 | case HIERARCHY_AUTO: |
3852 | case HIERARCHY_NONE: | 3857 | case HIERARCHY_NONE: |
3853 | default: | 3858 | default: |
@@ -3867,8 +3872,8 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
3867 | } | 3872 | } |
3868 | 3873 | ||
3869 | 3874 | ||
3870 | /* constellation */ | 3875 | /* modulation */ |
3871 | switch (state->param.u.ofdm.constellation) { | 3876 | switch (state->props.modulation) { |
3872 | case QAM_AUTO: | 3877 | case QAM_AUTO: |
3873 | default: | 3878 | default: |
3874 | operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; | 3879 | operationMode |= OFDM_SC_RA_RAM_OP_AUTO_CONST__M; |
@@ -3911,7 +3916,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
3911 | #endif | 3916 | #endif |
3912 | 3917 | ||
3913 | /* coderate */ | 3918 | /* coderate */ |
3914 | switch (state->param.u.ofdm.code_rate_HP) { | 3919 | switch (state->props.code_rate_HP) { |
3915 | case FEC_AUTO: | 3920 | case FEC_AUTO: |
3916 | default: | 3921 | default: |
3917 | operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; | 3922 | operationMode |= OFDM_SC_RA_RAM_OP_AUTO_RATE__M; |
@@ -3940,9 +3945,11 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
3940 | /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed | 3945 | /* Also set parameters for EC_OC fix, note EC_OC_REG_TMD_HIL_MAR is changed |
3941 | by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC | 3946 | by SC for fix for some 8K,1/8 guard but is restored by InitEC and ResetEC |
3942 | functions */ | 3947 | functions */ |
3943 | switch (state->param.u.ofdm.bandwidth) { | 3948 | switch (state->props.bandwidth_hz) { |
3944 | case BANDWIDTH_AUTO: | 3949 | case 0: |
3945 | case BANDWIDTH_8_MHZ: | 3950 | state->props.bandwidth_hz = 8000000; |
3951 | /* fall though */ | ||
3952 | case 8000000: | ||
3946 | bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; | 3953 | bandwidth = DRXK_BANDWIDTH_8MHZ_IN_HZ; |
3947 | status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); | 3954 | status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3052); |
3948 | if (status < 0) | 3955 | if (status < 0) |
@@ -3961,7 +3968,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
3961 | if (status < 0) | 3968 | if (status < 0) |
3962 | goto error; | 3969 | goto error; |
3963 | break; | 3970 | break; |
3964 | case BANDWIDTH_7_MHZ: | 3971 | case 7000000: |
3965 | bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; | 3972 | bandwidth = DRXK_BANDWIDTH_7MHZ_IN_HZ; |
3966 | status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); | 3973 | status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 3491); |
3967 | if (status < 0) | 3974 | if (status < 0) |
@@ -3980,7 +3987,7 @@ static int SetDVBT(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
3980 | if (status < 0) | 3987 | if (status < 0) |
3981 | goto error; | 3988 | goto error; |
3982 | break; | 3989 | break; |
3983 | case BANDWIDTH_6_MHZ: | 3990 | case 6000000: |
3984 | bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; | 3991 | bandwidth = DRXK_BANDWIDTH_6MHZ_IN_HZ; |
3985 | status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); | 3992 | status = write16(state, OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A, 4073); |
3986 | if (status < 0) | 3993 | if (status < 0) |
@@ -4187,7 +4194,7 @@ error: | |||
4187 | /** | 4194 | /** |
4188 | * \brief Setup of the QAM Measurement intervals for signal quality | 4195 | * \brief Setup of the QAM Measurement intervals for signal quality |
4189 | * \param demod instance of demod. | 4196 | * \param demod instance of demod. |
4190 | * \param constellation current constellation. | 4197 | * \param modulation current modulation. |
4191 | * \return DRXStatus_t. | 4198 | * \return DRXStatus_t. |
4192 | * | 4199 | * |
4193 | * NOTE: | 4200 | * NOTE: |
@@ -4196,7 +4203,7 @@ error: | |||
4196 | * | 4203 | * |
4197 | */ | 4204 | */ |
4198 | static int SetQAMMeasurement(struct drxk_state *state, | 4205 | static int SetQAMMeasurement(struct drxk_state *state, |
4199 | enum EDrxkConstellation constellation, | 4206 | enum EDrxkConstellation modulation, |
4200 | u32 symbolRate) | 4207 | u32 symbolRate) |
4201 | { | 4208 | { |
4202 | u32 fecBitsDesired = 0; /* BER accounting period */ | 4209 | u32 fecBitsDesired = 0; /* BER accounting period */ |
@@ -4210,11 +4217,11 @@ static int SetQAMMeasurement(struct drxk_state *state, | |||
4210 | fecRsPrescale = 1; | 4217 | fecRsPrescale = 1; |
4211 | /* fecBitsDesired = symbolRate [kHz] * | 4218 | /* fecBitsDesired = symbolRate [kHz] * |
4212 | FrameLenght [ms] * | 4219 | FrameLenght [ms] * |
4213 | (constellation + 1) * | 4220 | (modulation + 1) * |
4214 | SyncLoss (== 1) * | 4221 | SyncLoss (== 1) * |
4215 | ViterbiLoss (==1) | 4222 | ViterbiLoss (==1) |
4216 | */ | 4223 | */ |
4217 | switch (constellation) { | 4224 | switch (modulation) { |
4218 | case DRX_CONSTELLATION_QAM16: | 4225 | case DRX_CONSTELLATION_QAM16: |
4219 | fecBitsDesired = 4 * symbolRate; | 4226 | fecBitsDesired = 4 * symbolRate; |
4220 | break; | 4227 | break; |
@@ -5281,12 +5288,12 @@ static int QAMSetSymbolrate(struct drxk_state *state) | |||
5281 | /* Select & calculate correct IQM rate */ | 5288 | /* Select & calculate correct IQM rate */ |
5282 | adcFrequency = (state->m_sysClockFreq * 1000) / 3; | 5289 | adcFrequency = (state->m_sysClockFreq * 1000) / 3; |
5283 | ratesel = 0; | 5290 | ratesel = 0; |
5284 | /* printk(KERN_DEBUG "drxk: SR %d\n", state->param.u.qam.symbol_rate); */ | 5291 | /* printk(KERN_DEBUG "drxk: SR %d\n", state->props.symbol_rate); */ |
5285 | if (state->param.u.qam.symbol_rate <= 1188750) | 5292 | if (state->props.symbol_rate <= 1188750) |
5286 | ratesel = 3; | 5293 | ratesel = 3; |
5287 | else if (state->param.u.qam.symbol_rate <= 2377500) | 5294 | else if (state->props.symbol_rate <= 2377500) |
5288 | ratesel = 2; | 5295 | ratesel = 2; |
5289 | else if (state->param.u.qam.symbol_rate <= 4755000) | 5296 | else if (state->props.symbol_rate <= 4755000) |
5290 | ratesel = 1; | 5297 | ratesel = 1; |
5291 | status = write16(state, IQM_FD_RATESEL__A, ratesel); | 5298 | status = write16(state, IQM_FD_RATESEL__A, ratesel); |
5292 | if (status < 0) | 5299 | if (status < 0) |
@@ -5295,7 +5302,7 @@ static int QAMSetSymbolrate(struct drxk_state *state) | |||
5295 | /* | 5302 | /* |
5296 | IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) | 5303 | IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) |
5297 | */ | 5304 | */ |
5298 | symbFreq = state->param.u.qam.symbol_rate * (1 << ratesel); | 5305 | symbFreq = state->props.symbol_rate * (1 << ratesel); |
5299 | if (symbFreq == 0) { | 5306 | if (symbFreq == 0) { |
5300 | /* Divide by zero */ | 5307 | /* Divide by zero */ |
5301 | status = -EINVAL; | 5308 | status = -EINVAL; |
@@ -5311,7 +5318,7 @@ static int QAMSetSymbolrate(struct drxk_state *state) | |||
5311 | /* | 5318 | /* |
5312 | LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) | 5319 | LcSymbFreq = round (.125 * symbolrate / adcFreq * (1<<15)) |
5313 | */ | 5320 | */ |
5314 | symbFreq = state->param.u.qam.symbol_rate; | 5321 | symbFreq = state->props.symbol_rate; |
5315 | if (adcFrequency == 0) { | 5322 | if (adcFrequency == 0) { |
5316 | /* Divide by zero */ | 5323 | /* Divide by zero */ |
5317 | status = -EINVAL; | 5324 | status = -EINVAL; |
@@ -5412,7 +5419,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
5412 | goto error; | 5419 | goto error; |
5413 | 5420 | ||
5414 | /* Set params */ | 5421 | /* Set params */ |
5415 | switch (state->param.u.qam.modulation) { | 5422 | switch (state->props.modulation) { |
5416 | case QAM_256: | 5423 | case QAM_256: |
5417 | state->m_Constellation = DRX_CONSTELLATION_QAM256; | 5424 | state->m_Constellation = DRX_CONSTELLATION_QAM256; |
5418 | break; | 5425 | break; |
@@ -5435,7 +5442,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
5435 | } | 5442 | } |
5436 | if (status < 0) | 5443 | if (status < 0) |
5437 | goto error; | 5444 | goto error; |
5438 | setParamParameters[0] = state->m_Constellation; /* constellation */ | 5445 | setParamParameters[0] = state->m_Constellation; /* modulation */ |
5439 | setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ | 5446 | setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ |
5440 | if (state->m_OperationMode == OM_QAM_ITU_C) | 5447 | if (state->m_OperationMode == OM_QAM_ITU_C) |
5441 | setParamParameters[2] = QAM_TOP_ANNEX_C; | 5448 | setParamParameters[2] = QAM_TOP_ANNEX_C; |
@@ -5457,7 +5464,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
5457 | if (status < 0) | 5464 | if (status < 0) |
5458 | goto error; | 5465 | goto error; |
5459 | 5466 | ||
5460 | setParamParameters[0] = state->m_Constellation; /* constellation */ | 5467 | setParamParameters[0] = state->m_Constellation; /* modulation */ |
5461 | setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ | 5468 | setParamParameters[1] = DRXK_QAM_I12_J17; /* interleave mode */ |
5462 | status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult); | 5469 | status = scu_command(state, SCU_RAM_COMMAND_STANDARD_QAM | SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM, 2, setParamParameters, 1, &cmdResult); |
5463 | } | 5470 | } |
@@ -5466,7 +5473,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
5466 | 5473 | ||
5467 | /* | 5474 | /* |
5468 | * STEP 3: enable the system in a mode where the ADC provides valid | 5475 | * STEP 3: enable the system in a mode where the ADC provides valid |
5469 | * signal setup constellation independent registers | 5476 | * signal setup modulation independent registers |
5470 | */ | 5477 | */ |
5471 | #if 0 | 5478 | #if 0 |
5472 | status = SetFrequency(channel, tunerFreqOffset)); | 5479 | status = SetFrequency(channel, tunerFreqOffset)); |
@@ -5478,7 +5485,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
5478 | goto error; | 5485 | goto error; |
5479 | 5486 | ||
5480 | /* Setup BER measurement */ | 5487 | /* Setup BER measurement */ |
5481 | status = SetQAMMeasurement(state, state->m_Constellation, state->param.u. qam.symbol_rate); | 5488 | status = SetQAMMeasurement(state, state->m_Constellation, state->props.symbol_rate); |
5482 | if (status < 0) | 5489 | if (status < 0) |
5483 | goto error; | 5490 | goto error; |
5484 | 5491 | ||
@@ -5560,8 +5567,8 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
5560 | if (status < 0) | 5567 | if (status < 0) |
5561 | goto error; | 5568 | goto error; |
5562 | 5569 | ||
5563 | /* STEP 4: constellation specific setup */ | 5570 | /* STEP 4: modulation specific setup */ |
5564 | switch (state->param.u.qam.modulation) { | 5571 | switch (state->props.modulation) { |
5565 | case QAM_16: | 5572 | case QAM_16: |
5566 | status = SetQAM16(state); | 5573 | status = SetQAM16(state); |
5567 | break; | 5574 | break; |
@@ -5591,7 +5598,7 @@ static int SetQAM(struct drxk_state *state, u16 IntermediateFreqkHz, | |||
5591 | goto error; | 5598 | goto error; |
5592 | 5599 | ||
5593 | /* Re-configure MPEG output, requires knowledge of channel bitrate */ | 5600 | /* Re-configure MPEG output, requires knowledge of channel bitrate */ |
5594 | /* extAttr->currentChannel.constellation = channel->constellation; */ | 5601 | /* extAttr->currentChannel.modulation = channel->modulation; */ |
5595 | /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ | 5602 | /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ |
5596 | status = MPEGTSDtoSetup(state, state->m_OperationMode); | 5603 | status = MPEGTSDtoSetup(state, state->m_OperationMode); |
5597 | if (status < 0) | 5604 | if (status < 0) |
@@ -6167,7 +6174,7 @@ error: | |||
6167 | return status; | 6174 | return status; |
6168 | } | 6175 | } |
6169 | 6176 | ||
6170 | static void drxk_c_release(struct dvb_frontend *fe) | 6177 | static void drxk_release(struct dvb_frontend *fe) |
6171 | { | 6178 | { |
6172 | struct drxk_state *state = fe->demodulator_priv; | 6179 | struct drxk_state *state = fe->demodulator_priv; |
6173 | 6180 | ||
@@ -6175,24 +6182,12 @@ static void drxk_c_release(struct dvb_frontend *fe) | |||
6175 | kfree(state); | 6182 | kfree(state); |
6176 | } | 6183 | } |
6177 | 6184 | ||
6178 | static int drxk_c_init(struct dvb_frontend *fe) | 6185 | static int drxk_sleep(struct dvb_frontend *fe) |
6179 | { | ||
6180 | struct drxk_state *state = fe->demodulator_priv; | ||
6181 | |||
6182 | dprintk(1, "\n"); | ||
6183 | if (mutex_trylock(&state->ctlock) == 0) | ||
6184 | return -EBUSY; | ||
6185 | SetOperationMode(state, OM_QAM_ITU_A); | ||
6186 | return 0; | ||
6187 | } | ||
6188 | |||
6189 | static int drxk_c_sleep(struct dvb_frontend *fe) | ||
6190 | { | 6186 | { |
6191 | struct drxk_state *state = fe->demodulator_priv; | 6187 | struct drxk_state *state = fe->demodulator_priv; |
6192 | 6188 | ||
6193 | dprintk(1, "\n"); | 6189 | dprintk(1, "\n"); |
6194 | ShutDown(state); | 6190 | ShutDown(state); |
6195 | mutex_unlock(&state->ctlock); | ||
6196 | return 0; | 6191 | return 0; |
6197 | } | 6192 | } |
6198 | 6193 | ||
@@ -6204,9 +6199,10 @@ static int drxk_gate_ctrl(struct dvb_frontend *fe, int enable) | |||
6204 | return ConfigureI2CBridge(state, enable ? true : false); | 6199 | return ConfigureI2CBridge(state, enable ? true : false); |
6205 | } | 6200 | } |
6206 | 6201 | ||
6207 | static int drxk_set_parameters(struct dvb_frontend *fe, | 6202 | static int drxk_set_parameters(struct dvb_frontend *fe) |
6208 | struct dvb_frontend_parameters *p) | ||
6209 | { | 6203 | { |
6204 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; | ||
6205 | u32 delsys = p->delivery_system, old_delsys; | ||
6210 | struct drxk_state *state = fe->demodulator_priv; | 6206 | struct drxk_state *state = fe->demodulator_priv; |
6211 | u32 IF; | 6207 | u32 IF; |
6212 | 6208 | ||
@@ -6218,14 +6214,39 @@ static int drxk_set_parameters(struct dvb_frontend *fe, | |||
6218 | return -EINVAL; | 6214 | return -EINVAL; |
6219 | } | 6215 | } |
6220 | 6216 | ||
6221 | |||
6222 | if (fe->ops.i2c_gate_ctrl) | 6217 | if (fe->ops.i2c_gate_ctrl) |
6223 | fe->ops.i2c_gate_ctrl(fe, 1); | 6218 | fe->ops.i2c_gate_ctrl(fe, 1); |
6224 | if (fe->ops.tuner_ops.set_params) | 6219 | if (fe->ops.tuner_ops.set_params) |
6225 | fe->ops.tuner_ops.set_params(fe, p); | 6220 | fe->ops.tuner_ops.set_params(fe); |
6226 | if (fe->ops.i2c_gate_ctrl) | 6221 | if (fe->ops.i2c_gate_ctrl) |
6227 | fe->ops.i2c_gate_ctrl(fe, 0); | 6222 | fe->ops.i2c_gate_ctrl(fe, 0); |
6228 | state->param = *p; | 6223 | |
6224 | old_delsys = state->props.delivery_system; | ||
6225 | state->props = *p; | ||
6226 | |||
6227 | if (old_delsys != delsys) { | ||
6228 | ShutDown(state); | ||
6229 | switch (delsys) { | ||
6230 | case SYS_DVBC_ANNEX_A: | ||
6231 | case SYS_DVBC_ANNEX_C: | ||
6232 | if (!state->m_hasDVBC) | ||
6233 | return -EINVAL; | ||
6234 | state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? true : false; | ||
6235 | if (state->m_itut_annex_c) | ||
6236 | SetOperationMode(state, OM_QAM_ITU_C); | ||
6237 | else | ||
6238 | SetOperationMode(state, OM_QAM_ITU_A); | ||
6239 | break; | ||
6240 | case SYS_DVBT: | ||
6241 | if (!state->m_hasDVBT) | ||
6242 | return -EINVAL; | ||
6243 | SetOperationMode(state, OM_DVBT); | ||
6244 | break; | ||
6245 | default: | ||
6246 | return -EINVAL; | ||
6247 | } | ||
6248 | } | ||
6249 | |||
6229 | fe->ops.tuner_ops.get_if_frequency(fe, &IF); | 6250 | fe->ops.tuner_ops.get_if_frequency(fe, &IF); |
6230 | Start(state, 0, IF); | 6251 | Start(state, 0, IF); |
6231 | 6252 | ||
@@ -6234,13 +6255,6 @@ static int drxk_set_parameters(struct dvb_frontend *fe, | |||
6234 | return 0; | 6255 | return 0; |
6235 | } | 6256 | } |
6236 | 6257 | ||
6237 | static int drxk_c_get_frontend(struct dvb_frontend *fe, | ||
6238 | struct dvb_frontend_parameters *p) | ||
6239 | { | ||
6240 | dprintk(1, "\n"); | ||
6241 | return 0; | ||
6242 | } | ||
6243 | |||
6244 | static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) | 6258 | static int drxk_read_status(struct dvb_frontend *fe, fe_status_t *status) |
6245 | { | 6259 | { |
6246 | struct drxk_state *state = fe->demodulator_priv; | 6260 | struct drxk_state *state = fe->demodulator_priv; |
@@ -6300,102 +6314,54 @@ static int drxk_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks) | |||
6300 | return 0; | 6314 | return 0; |
6301 | } | 6315 | } |
6302 | 6316 | ||
6303 | static int drxk_c_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings | 6317 | static int drxk_get_tune_settings(struct dvb_frontend *fe, struct dvb_frontend_tune_settings |
6304 | *sets) | 6318 | *sets) |
6305 | { | 6319 | { |
6306 | dprintk(1, "\n"); | 6320 | struct dtv_frontend_properties *p = &fe->dtv_property_cache; |
6307 | sets->min_delay_ms = 3000; | ||
6308 | sets->max_drift = 0; | ||
6309 | sets->step_size = 0; | ||
6310 | return 0; | ||
6311 | } | ||
6312 | |||
6313 | static void drxk_t_release(struct dvb_frontend *fe) | ||
6314 | { | ||
6315 | /* | ||
6316 | * There's nothing to release here, as the state struct | ||
6317 | * is already freed by drxk_c_release. | ||
6318 | */ | ||
6319 | } | ||
6320 | |||
6321 | static int drxk_t_init(struct dvb_frontend *fe) | ||
6322 | { | ||
6323 | struct drxk_state *state = fe->demodulator_priv; | ||
6324 | 6321 | ||
6325 | dprintk(1, "\n"); | 6322 | dprintk(1, "\n"); |
6326 | if (mutex_trylock(&state->ctlock) == 0) | 6323 | switch (p->delivery_system) { |
6327 | return -EBUSY; | 6324 | case SYS_DVBC_ANNEX_A: |
6328 | SetOperationMode(state, OM_DVBT); | 6325 | case SYS_DVBC_ANNEX_C: |
6329 | return 0; | 6326 | sets->min_delay_ms = 3000; |
6330 | } | 6327 | sets->max_drift = 0; |
6331 | 6328 | sets->step_size = 0; | |
6332 | static int drxk_t_sleep(struct dvb_frontend *fe) | 6329 | return 0; |
6333 | { | 6330 | default: |
6334 | struct drxk_state *state = fe->demodulator_priv; | 6331 | /* |
6335 | 6332 | * For DVB-T, let it use the default DVB core way, that is: | |
6336 | dprintk(1, "\n"); | 6333 | * fepriv->step_size = fe->ops.info.frequency_stepsize * 2 |
6337 | mutex_unlock(&state->ctlock); | 6334 | */ |
6338 | return 0; | 6335 | return -EINVAL; |
6339 | } | 6336 | } |
6340 | |||
6341 | static int drxk_t_get_frontend(struct dvb_frontend *fe, | ||
6342 | struct dvb_frontend_parameters *p) | ||
6343 | { | ||
6344 | dprintk(1, "\n"); | ||
6345 | |||
6346 | return 0; | ||
6347 | } | 6337 | } |
6348 | 6338 | ||
6349 | static struct dvb_frontend_ops drxk_c_ops = { | 6339 | static struct dvb_frontend_ops drxk_ops = { |
6340 | /* .delsys will be filled dynamically */ | ||
6350 | .info = { | 6341 | .info = { |
6351 | .name = "DRXK DVB-C", | 6342 | .name = "DRXK", |
6352 | .type = FE_QAM, | 6343 | .frequency_min = 47000000, |
6353 | .frequency_stepsize = 62500, | 6344 | .frequency_max = 865000000, |
6354 | .frequency_min = 47000000, | 6345 | /* For DVB-C */ |
6355 | .frequency_max = 862000000, | 6346 | .symbol_rate_min = 870000, |
6356 | .symbol_rate_min = 870000, | 6347 | .symbol_rate_max = 11700000, |
6357 | .symbol_rate_max = 11700000, | 6348 | /* For DVB-T */ |
6358 | .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | | 6349 | .frequency_stepsize = 166667, |
6359 | FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO}, | 6350 | |
6360 | .release = drxk_c_release, | 6351 | .caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 | |
6361 | .init = drxk_c_init, | 6352 | FE_CAN_QAM_128 | FE_CAN_QAM_256 | FE_CAN_FEC_AUTO | |
6362 | .sleep = drxk_c_sleep, | 6353 | FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | |
6354 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_MUTE_TS | | ||
6355 | FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_RECOVER | | ||
6356 | FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_HIERARCHY_AUTO | ||
6357 | }, | ||
6358 | |||
6359 | .release = drxk_release, | ||
6360 | .sleep = drxk_sleep, | ||
6363 | .i2c_gate_ctrl = drxk_gate_ctrl, | 6361 | .i2c_gate_ctrl = drxk_gate_ctrl, |
6364 | 6362 | ||
6365 | .set_frontend = drxk_set_parameters, | 6363 | .set_frontend = drxk_set_parameters, |
6366 | .get_frontend = drxk_c_get_frontend, | 6364 | .get_tune_settings = drxk_get_tune_settings, |
6367 | .get_tune_settings = drxk_c_get_tune_settings, | ||
6368 | |||
6369 | .read_status = drxk_read_status, | ||
6370 | .read_ber = drxk_read_ber, | ||
6371 | .read_signal_strength = drxk_read_signal_strength, | ||
6372 | .read_snr = drxk_read_snr, | ||
6373 | .read_ucblocks = drxk_read_ucblocks, | ||
6374 | }; | ||
6375 | |||
6376 | static struct dvb_frontend_ops drxk_t_ops = { | ||
6377 | .info = { | ||
6378 | .name = "DRXK DVB-T", | ||
6379 | .type = FE_OFDM, | ||
6380 | .frequency_min = 47125000, | ||
6381 | .frequency_max = 865000000, | ||
6382 | .frequency_stepsize = 166667, | ||
6383 | .frequency_tolerance = 0, | ||
6384 | .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | | ||
6385 | FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | | ||
6386 | FE_CAN_FEC_AUTO | | ||
6387 | FE_CAN_QAM_16 | FE_CAN_QAM_64 | | ||
6388 | FE_CAN_QAM_AUTO | | ||
6389 | FE_CAN_TRANSMISSION_MODE_AUTO | | ||
6390 | FE_CAN_GUARD_INTERVAL_AUTO | | ||
6391 | FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS}, | ||
6392 | .release = drxk_t_release, | ||
6393 | .init = drxk_t_init, | ||
6394 | .sleep = drxk_t_sleep, | ||
6395 | .i2c_gate_ctrl = drxk_gate_ctrl, | ||
6396 | |||
6397 | .set_frontend = drxk_set_parameters, | ||
6398 | .get_frontend = drxk_t_get_frontend, | ||
6399 | 6365 | ||
6400 | .read_status = drxk_read_status, | 6366 | .read_status = drxk_read_status, |
6401 | .read_ber = drxk_read_ber, | 6367 | .read_ber = drxk_read_ber, |
@@ -6405,9 +6371,10 @@ static struct dvb_frontend_ops drxk_t_ops = { | |||
6405 | }; | 6371 | }; |
6406 | 6372 | ||
6407 | struct dvb_frontend *drxk_attach(const struct drxk_config *config, | 6373 | struct dvb_frontend *drxk_attach(const struct drxk_config *config, |
6408 | struct i2c_adapter *i2c, | 6374 | struct i2c_adapter *i2c) |
6409 | struct dvb_frontend **fe_t) | ||
6410 | { | 6375 | { |
6376 | int n; | ||
6377 | |||
6411 | struct drxk_state *state = NULL; | 6378 | struct drxk_state *state = NULL; |
6412 | u8 adr = config->adr; | 6379 | u8 adr = config->adr; |
6413 | 6380 | ||
@@ -6423,6 +6390,12 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, | |||
6423 | state->no_i2c_bridge = config->no_i2c_bridge; | 6390 | state->no_i2c_bridge = config->no_i2c_bridge; |
6424 | state->antenna_gpio = config->antenna_gpio; | 6391 | state->antenna_gpio = config->antenna_gpio; |
6425 | state->antenna_dvbt = config->antenna_dvbt; | 6392 | state->antenna_dvbt = config->antenna_dvbt; |
6393 | state->m_ChunkSize = config->chunk_size; | ||
6394 | |||
6395 | if (config->parallel_ts) | ||
6396 | state->m_enableParallel = true; | ||
6397 | else | ||
6398 | state->m_enableParallel = false; | ||
6426 | 6399 | ||
6427 | /* NOTE: as more UIO bits will be used, add them to the mask */ | 6400 | /* NOTE: as more UIO bits will be used, add them to the mask */ |
6428 | state->UIO_mask = config->antenna_gpio; | 6401 | state->UIO_mask = config->antenna_gpio; |
@@ -6434,21 +6407,30 @@ struct dvb_frontend *drxk_attach(const struct drxk_config *config, | |||
6434 | state->m_GPIO &= ~state->antenna_gpio; | 6407 | state->m_GPIO &= ~state->antenna_gpio; |
6435 | 6408 | ||
6436 | mutex_init(&state->mutex); | 6409 | mutex_init(&state->mutex); |
6437 | mutex_init(&state->ctlock); | ||
6438 | 6410 | ||
6439 | memcpy(&state->c_frontend.ops, &drxk_c_ops, | 6411 | memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); |
6440 | sizeof(struct dvb_frontend_ops)); | 6412 | state->frontend.demodulator_priv = state; |
6441 | memcpy(&state->t_frontend.ops, &drxk_t_ops, | ||
6442 | sizeof(struct dvb_frontend_ops)); | ||
6443 | state->c_frontend.demodulator_priv = state; | ||
6444 | state->t_frontend.demodulator_priv = state; | ||
6445 | 6413 | ||
6446 | init_state(state); | 6414 | init_state(state); |
6447 | if (init_drxk(state) < 0) | 6415 | if (init_drxk(state) < 0) |
6448 | goto error; | 6416 | goto error; |
6449 | *fe_t = &state->t_frontend; | ||
6450 | 6417 | ||
6451 | return &state->c_frontend; | 6418 | /* Initialize the supported delivery systems */ |
6419 | n = 0; | ||
6420 | if (state->m_hasDVBC) { | ||
6421 | state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; | ||
6422 | state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; | ||
6423 | strlcat(state->frontend.ops.info.name, " DVB-C", | ||
6424 | sizeof(state->frontend.ops.info.name)); | ||
6425 | } | ||
6426 | if (state->m_hasDVBT) { | ||
6427 | state->frontend.ops.delsys[n++] = SYS_DVBT; | ||
6428 | strlcat(state->frontend.ops.info.name, " DVB-T", | ||
6429 | sizeof(state->frontend.ops.info.name)); | ||
6430 | } | ||
6431 | |||
6432 | printk(KERN_INFO "drxk: frontend initialized.\n"); | ||
6433 | return &state->frontend; | ||
6452 | 6434 | ||
6453 | error: | 6435 | error: |
6454 | printk(KERN_ERR "drxk: not found\n"); | 6436 | printk(KERN_ERR "drxk: not found\n"); |