33 files changed, 344 insertions, 76 deletions

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index aee83fa178f6..9214119c0154 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -605,6 +605,9 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
                 case FBC_NOT_TILED:
                         seq_printf(m, "scanout buffer not tiled");
                         break;
+                case FBC_MULTIPLE_PIPES:
+                        seq_printf(m, "multiple pipes are enabled");
+                        break;
                 default:
                         seq_printf(m, "unknown reason");
                 }
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index f00c5ae9556c..2305a1234f1e 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1300,7 +1300,7 @@ static void i915_cleanup_compression(struct drm_device *dev)
         struct drm_i915_private *dev_priv = dev->dev_private;
 
         drm_mm_put_block(dev_priv->compressed_fb);
-        if (!IS_GM45(dev))
+        if (dev_priv->compressed_llb)
                 drm_mm_put_block(dev_priv->compressed_llb);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d147ab2f5bfc..2e1744d37ad5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -215,6 +215,7 @@ enum no_fbc_reason {
         FBC_MODE_TOO_LARGE, /* mode too large for compression */
         FBC_BAD_PLANE, /* fbc not supported on plane */
         FBC_NOT_TILED, /* buffer not tiled */
+        FBC_MULTIPLE_PIPES, /* more than one pipe active */
 };
 
 enum intel_pch {
@@ -222,6 +223,8 @@ enum intel_pch {
         PCH_CPT,        /* Cougarpoint PCH */
 };
 
+#define QUIRK_PIPEA_FORCE (1<<0)
+
 struct intel_fbdev;
 
 typedef struct drm_i915_private {
@@ -337,6 +340,8 @@ typedef struct drm_i915_private {
         /* PCH chipset type */
         enum intel_pch pch_type;
 
+        unsigned long quirks;
+
         /* Register state */
         bool modeset_on_lid;
         u8 saveLBB;
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 074385882ccf..5aa747fc25a9 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2241,6 +2241,7 @@ i915_gem_object_get_pages(struct drm_gem_object *obj,
                 page = read_cache_page_gfp(mapping, i,
                                            GFP_HIGHUSER |
                                            __GFP_COLD |
+                                           __GFP_RECLAIMABLE |
                                            gfpmask);
                 if (IS_ERR(page))
                         goto err_pages;
@@ -3646,6 +3647,7 @@ i915_gem_wait_for_pending_flip(struct drm_device *dev,
         return ret;
 }
 
+
 int
 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                        struct drm_file *file_priv,
@@ -3793,7 +3795,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
                                 unsigned long long total_size = 0;
                                 int num_fences = 0;
                                 for (i = 0; i < args->buffer_count; i++) {
-                                        obj_priv = object_list[i]->driver_private;
+                                        obj_priv = to_intel_bo(object_list[i]);
 
                                         total_size += object_list[i]->size;
                                         num_fences +=
@@ -4741,6 +4743,16 @@ i915_gem_load(struct drm_device *dev)
         list_add(&dev_priv->mm.shrink_list, &shrink_list);
         spin_unlock(&shrink_list_lock);
 
+        /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
+        if (IS_GEN3(dev)) {
+                u32 tmp = I915_READ(MI_ARB_STATE);
+                if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
+                        /* arb state is a masked write, so set bit + bit in mask */
+                        tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
+                        I915_WRITE(MI_ARB_STATE, tmp);
+                }
+        }
+
         /* Old X drivers will take 0-2 for front, back, depth buffers */
         if (!drm_core_check_feature(dev, DRIVER_MODESET))
                 dev_priv->fence_reg_start = 3;
@@ -4977,7 +4989,7 @@ i915_gpu_is_active(struct drm_device *dev)
 }
 
 static int
-i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
+i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
 {
         drm_i915_private_t *dev_priv, *next_dev;
         struct drm_i915_gem_object *obj_priv, *next_obj;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 150400f40534..cf41c672defe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -359,6 +359,70 @@
 #define LM_BURST_LENGTH     0x00000700
 #define LM_FIFO_WATERMARK   0x0000001F
 #define MI_ARB_STATE    0x020e4 /* 915+ only */
+#define   MI_ARB_MASK_SHIFT       16    /* shift for enable bits */
+
+/* Make render/texture TLB fetches lower priorty than associated data
+ *   fetches. This is not turned on by default
+ */
+#define   MI_ARB_RENDER_TLB_LOW_PRIORITY        (1 << 15)
+
+/* Isoch request wait on GTT enable (Display A/B/C streams).
+ * Make isoch requests stall on the TLB update. May cause
+ * display underruns (test mode only)
+ */
+#define   MI_ARB_ISOCH_WAIT_GTT                 (1 << 14)
+
+/* Block grant count for isoch requests when block count is
+ * set to a finite value.
+ */
+#define   MI_ARB_BLOCK_GRANT_MASK               (3 << 12)
+#define   MI_ARB_BLOCK_GRANT_8                  (0 << 12)       /* for 3 display planes */
+#define   MI_ARB_BLOCK_GRANT_4                  (1 << 12)       /* for 2 display planes */
+#define   MI_ARB_BLOCK_GRANT_2                  (2 << 12)       /* for 1 display plane */
+#define   MI_ARB_BLOCK_GRANT_0                  (3 << 12)       /* don't use */
+
+/* Enable render writes to complete in C2/C3/C4 power states.
+ * If this isn't enabled, render writes are prevented in low
+ * power states. That seems bad to me.
+ */
+#define   MI_ARB_C3_LP_WRITE_ENABLE             (1 << 11)
+
+/* This acknowledges an async flip immediately instead
+ * of waiting for 2TLB fetches.
+ */
+#define   MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE       (1 << 10)
+
+/* Enables non-sequential data reads through arbiter
+ */
+#define   MI_ARB_DUAL_DATA_PHASE_DISABLE        (1 << 9)
+
+/* Disable FSB snooping of cacheable write cycles from binner/render
+ * command stream
+ */
+#define   MI_ARB_CACHE_SNOOP_DISABLE            (1 << 8)
+
+/* Arbiter time slice for non-isoch streams */
+#define   MI_ARB_TIME_SLICE_MASK                (7 << 5)
+#define   MI_ARB_TIME_SLICE_1                   (0 << 5)
+#define   MI_ARB_TIME_SLICE_2                   (1 << 5)
+#define   MI_ARB_TIME_SLICE_4                   (2 << 5)
+#define   MI_ARB_TIME_SLICE_6                   (3 << 5)
+#define   MI_ARB_TIME_SLICE_8                   (4 << 5)
+#define   MI_ARB_TIME_SLICE_10                  (5 << 5)
+#define   MI_ARB_TIME_SLICE_14                  (6 << 5)
+#define   MI_ARB_TIME_SLICE_16                  (7 << 5)
+
+/* Low priority grace period page size */
+#define   MI_ARB_LOW_PRIORITY_GRACE_4KB         (0 << 4)        /* default */
+#define   MI_ARB_LOW_PRIORITY_GRACE_8KB         (1 << 4)
+
+/* Disable display A/B trickle feed */
+#define   MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE   (1 << 2)
+
+/* Set display plane priority */
+#define   MI_ARB_DISPLAY_PRIORITY_A_B           (0 << 0)        /* display A > display B */
+#define   MI_ARB_DISPLAY_PRIORITY_B_A           (1 << 0)        /* display B > display A */
+
 #define CACHE_MODE_0    0x02120 /* 915+ only */
 #define   CM0_MASK_SHIFT          16
 #define   CM0_IZ_OPT_DISABLE      (1<<6)
@@ -2805,6 +2869,7 @@
 
 #define PCH_PP_STATUS           0xc7200
 #define PCH_PP_CONTROL          0xc7204
+#define  PANEL_UNLOCK_REGS      (0xabcd << 16)
 #define  EDP_FORCE_VDD          (1 << 3)
 #define  EDP_BLC_ENABLE         (1 << 2)
 #define  PANEL_POWER_RESET      (1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 68dcf36e2793..5e21b3119824 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -862,8 +862,8 @@ intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
         intel_clock_t clock;
         int max_n;
         bool found;
-        /* approximately equals target * 0.00488 */
-        int err_most = (target >> 8) + (target >> 10);
+        /* approximately equals target * 0.00585 */
+        int err_most = (target >> 8) + (target >> 9);
         found = false;
 
         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
@@ -1180,8 +1180,12 @@ static void intel_update_fbc(struct drm_crtc *crtc,
         struct drm_framebuffer *fb = crtc->fb;
         struct intel_framebuffer *intel_fb;
         struct drm_i915_gem_object *obj_priv;
+        struct drm_crtc *tmp_crtc;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         int plane = intel_crtc->plane;
+        int crtcs_enabled = 0;
+
+        DRM_DEBUG_KMS("\n");
 
         if (!i915_powersave)
                 return;
@@ -1199,10 +1203,21 @@ static void intel_update_fbc(struct drm_crtc *crtc,
          * If FBC is already on, we just have to verify that we can
          * keep it that way...
          * Need to disable if:
+         *   - more than one pipe is active
          *   - changing FBC params (stride, fence, mode)
          *   - new fb is too large to fit in compressed buffer
          *   - going to an unsupported config (interlace, pixel multiply, etc.)
          */
+        list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
+                if (tmp_crtc->enabled)
+                        crtcs_enabled++;
+        }
+        DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled);
+        if (crtcs_enabled > 1) {
+                DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
+                dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
+                goto out_disable;
+        }
         if (intel_fb->obj->size > dev_priv->cfb_size) {
                 DRM_DEBUG_KMS("framebuffer too large, disabling "
                                 "compression\n");
@@ -1255,7 +1270,7 @@ out_disable:
         }
 }
 
-static int
+int
 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
 {
         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
@@ -2255,6 +2270,11 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                         intel_wait_for_vblank(dev);
                 }
 
+                /* Don't disable pipe A or pipe A PLLs if needed */
+                if (pipeconf_reg == PIPEACONF &&
+                    (dev_priv->quirks & QUIRK_PIPEA_FORCE))
+                        goto skip_pipe_off;
+
                 /* Next, disable display pipes */
                 temp = I915_READ(pipeconf_reg);
                 if ((temp & PIPEACONF_ENABLE) != 0) {
@@ -2270,7 +2290,7 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
                         I915_READ(dpll_reg);
                 }
-
+        skip_pipe_off:
                 /* Wait for the clocks to turn off. */
                 udelay(150);
                 break;
@@ -2356,8 +2376,6 @@ static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
                 if (mode->clock * 3 > 27000 * 4)
                         return MODE_CLOCK_HIGH;
         }
-
-        drm_mode_set_crtcinfo(adjusted_mode, 0);
         return true;
 }
 
@@ -3736,6 +3754,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
                         if (dev_priv->lvds_dither) {
                                 if (HAS_PCH_SPLIT(dev)) {
                                         pipeconf |= PIPE_ENABLE_DITHER;
+                                        pipeconf &= ~PIPE_DITHER_TYPE_MASK;
                                         pipeconf |= PIPE_DITHER_TYPE_ST01;
                                 } else
                                         lvds |= LVDS_ENABLE_DITHER;
@@ -4412,7 +4431,8 @@ static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
 
                 /* Unlock panel regs */
-                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                           PANEL_UNLOCK_REGS);
 
                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
                 I915_WRITE(dpll_reg, dpll);
@@ -4455,7 +4475,8 @@ static void intel_decrease_pllclock(struct drm_crtc *crtc)
                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
 
                 /* Unlock panel regs */
-                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
+                I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
+                           PANEL_UNLOCK_REGS);
 
                 dpll |= DISPLAY_RATE_SELECT_FPA1;
                 I915_WRITE(dpll_reg, dpll);
@@ -4695,7 +4716,7 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
         struct drm_gem_object *obj;
         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
         struct intel_unpin_work *work;
-        unsigned long flags;
+        unsigned long flags, offset;
         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
         int ret, pipesrc;
         u32 flip_mask;
@@ -4762,19 +4783,23 @@ static int intel_crtc_page_flip(struct drm_crtc *crtc,
                 while (I915_READ(ISR) & flip_mask)
                         ;
 
+        /* Offset into the new buffer for cases of shared fbs between CRTCs */
+        offset = obj_priv->gtt_offset;
+        offset += (crtc->y * fb->pitch) + (crtc->x * (fb->bits_per_pixel) / 8);
+
         BEGIN_LP_RING(4);
         if (IS_I965G(dev)) {
                 OUT_RING(MI_DISPLAY_FLIP |
                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                 OUT_RING(fb->pitch);
-                OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
+                OUT_RING(offset | obj_priv->tiling_mode);
                 pipesrc = I915_READ(pipesrc_reg); 
                 OUT_RING(pipesrc & 0x0fff0fff);
         } else {
                 OUT_RING(MI_DISPLAY_FLIP_I915 |
                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
                 OUT_RING(fb->pitch);
-                OUT_RING(obj_priv->gtt_offset);
+                OUT_RING(offset);
                 OUT_RING(MI_NOOP);
         }
         ADVANCE_LP_RING();
@@ -5506,6 +5531,66 @@ static void intel_init_display(struct drm_device *dev)
         }
 }
 
+/*
+ * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
+ * resume, or other times.  This quirk makes sure that's the case for
+ * affected systems.
+ */
+static void quirk_pipea_force (struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+
+        dev_priv->quirks |= QUIRK_PIPEA_FORCE;
+        DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
+}
+
+struct intel_quirk {
+        int device;
+        int subsystem_vendor;
+        int subsystem_device;
+        void (*hook)(struct drm_device *dev);
+};
+
+struct intel_quirk intel_quirks[] = {
+        /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
+        { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
+        /* HP Mini needs pipe A force quirk (LP: #322104) */
+        { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
+
+        /* Thinkpad R31 needs pipe A force quirk */
+        { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
+        /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
+        { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
+
+        /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
+        { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
+        /* ThinkPad X40 needs pipe A force quirk */
+
+        /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
+        { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
+
+        /* 855 & before need to leave pipe A & dpll A up */
+        { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+        { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
+};
+
+static void intel_init_quirks(struct drm_device *dev)
+{
+        struct pci_dev *d = dev->pdev;
+        int i;
+
+        for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
+                struct intel_quirk *q = &intel_quirks[i];
+
+                if (d->device == q->device &&
+                    (d->subsystem_vendor == q->subsystem_vendor ||
+                     q->subsystem_vendor == PCI_ANY_ID) &&
+                    (d->subsystem_device == q->subsystem_device ||
+                     q->subsystem_device == PCI_ANY_ID))
+                        q->hook(dev);
+        }
+}
+
 void intel_modeset_init(struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -5518,6 +5603,8 @@ void intel_modeset_init(struct drm_device *dev)
 
         dev->mode_config.funcs = (void *)&intel_mode_funcs;
 
+        intel_init_quirks(dev);
+
         intel_init_display(dev);
 
         if (IS_I965G(dev)) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 1aac59e83bff..5dde80f9e652 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -717,6 +717,51 @@ intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
         }
 }
 
+static void ironlake_edp_panel_on (struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+        u32 pp, pp_status;
+
+        pp_status = I915_READ(PCH_PP_STATUS);
+        if (pp_status & PP_ON)
+                return;
+
+        pp = I915_READ(PCH_PP_CONTROL);
+        pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
+        I915_WRITE(PCH_PP_CONTROL, pp);
+        do {
+                pp_status = I915_READ(PCH_PP_STATUS);
+        } while (((pp_status & PP_ON) == 0) && !time_after(jiffies, timeout));
+
+        if (time_after(jiffies, timeout))
+                DRM_DEBUG_KMS("panel on wait timed out: 0x%08x\n", pp_status);
+
+        pp &= ~(PANEL_UNLOCK_REGS | EDP_FORCE_VDD);
+        I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
+static void ironlake_edp_panel_off (struct drm_device *dev)
+{
+        struct drm_i915_private *dev_priv = dev->dev_private;
+        unsigned long timeout = jiffies + msecs_to_jiffies(5000);
+        u32 pp, pp_status;
+
+        pp = I915_READ(PCH_PP_CONTROL);
+        pp &= ~POWER_TARGET_ON;
+        I915_WRITE(PCH_PP_CONTROL, pp);
+        do {
+                pp_status = I915_READ(PCH_PP_STATUS);
+        } while ((pp_status & PP_ON) && !time_after(jiffies, timeout));
+
+        if (time_after(jiffies, timeout))
+                DRM_DEBUG_KMS("panel off wait timed out\n");
+
+        /* Make sure VDD is enabled so DP AUX will work */
+        pp |= EDP_FORCE_VDD;
+        I915_WRITE(PCH_PP_CONTROL, pp);
+}
+
 static void ironlake_edp_backlight_on (struct drm_device *dev)
 {
         struct drm_i915_private *dev_priv = dev->dev_private;
@@ -751,14 +796,18 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
         if (mode != DRM_MODE_DPMS_ON) {
                 if (dp_reg & DP_PORT_EN) {
                         intel_dp_link_down(intel_encoder, dp_priv->DP);
-                        if (IS_eDP(intel_encoder))
+                        if (IS_eDP(intel_encoder)) {
                                 ironlake_edp_backlight_off(dev);
+                                ironlake_edp_panel_off(dev);
+                        }
                 }
         } else {
                 if (!(dp_reg & DP_PORT_EN)) {
                         intel_dp_link_train(intel_encoder, dp_priv->DP, dp_priv->link_configuration);
-                        if (IS_eDP(intel_encoder))
+                        if (IS_eDP(intel_encoder)) {
+                                ironlake_edp_panel_on(dev);
                                 ironlake_edp_backlight_on(dev);
+                        }
                 }
         }
         dp_priv->dpms_mode = mode;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 72206f37c4fb..2f7970be9051 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -215,6 +215,9 @@ extern void intel_init_clock_gating(struct drm_device *dev);
 extern void ironlake_enable_drps(struct drm_device *dev);
 extern void ironlake_disable_drps(struct drm_device *dev);
 
+extern int intel_pin_and_fence_fb_obj(struct drm_device *dev,
+                                      struct drm_gem_object *obj);
+
 extern int intel_framebuffer_init(struct drm_device *dev,
                                   struct intel_framebuffer *ifb,
                                   struct drm_mode_fb_cmd *mode_cmd,
diff --git a/drivers/gpu/drm/i915/intel_fb.c b/drivers/gpu/drm/i915/intel_fb.c
index c3c505244e07..3e18c9e7729b 100644
--- a/drivers/gpu/drm/i915/intel_fb.c
+++ b/drivers/gpu/drm/i915/intel_fb.c
@@ -98,7 +98,7 @@ static int intelfb_create(struct intel_fbdev *ifbdev,
 
         mutex_lock(&dev->struct_mutex);
 
-        ret = i915_gem_object_pin(fbo, 64*1024);
+        ret = intel_pin_and_fence_fb_obj(dev, fbo);
         if (ret) {
                 DRM_ERROR("failed to pin fb: %d\n", ret);
                 goto out_unref;
@@ -236,7 +236,7 @@ int intel_fbdev_destroy(struct drm_device *dev,
 
         drm_framebuffer_cleanup(&ifb->base);
         if (ifb->obj)
-                drm_gem_object_unreference_unlocked(ifb->obj);
+                drm_gem_object_unreference(ifb->obj);
 
         return 0;
 }
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index 31df55f0a0a7..0eab8df5bf7e 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -599,6 +599,26 @@ static int intel_lvds_get_modes(struct drm_connector *connector)
         return 0;
 }
 
+static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
+{
+        DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident);
+        return 1;
+}
+
+/* The GPU hangs up on these systems if modeset is performed on LID open */
+static const struct dmi_system_id intel_no_modeset_on_lid[] = {
+        {
+                .callback = intel_no_modeset_on_lid_dmi_callback,
+                .ident = "Toshiba Tecra A11",
+                .matches = {
+                        DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
+                },
+        },
+
+        { }     /* terminating entry */
+};
+
 /*
  * Lid events. Note the use of 'modeset_on_lid':
  *  - we set it on lid close, and reset it on open
@@ -622,6 +642,9 @@ static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
          */
         if (connector)
                 connector->status = connector->funcs->detect(connector);
+        /* Don't force modeset on machines where it causes a GPU lockup */
+        if (dmi_check_system(intel_no_modeset_on_lid))
+                return NOTIFY_OK;
         if (!acpi_lid_open()) {
                 dev_priv->modeset_on_lid = 1;
                 return NOTIFY_OK;
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index fc924b649195..e492919faf44 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -203,36 +203,26 @@ struct methods {
         const bool rw;
 };
 
-static struct methods nv04_methods[] = {
-        { "PROM", load_vbios_prom, false },
-        { "PRAMIN", load_vbios_pramin, true },
-        { "PCIROM", load_vbios_pci, true },
-};
-
-static struct methods nv50_methods[] = {
-        { "ACPI", load_vbios_acpi, true },
+static struct methods shadow_methods[] = {
         { "PRAMIN", load_vbios_pramin, true },
         { "PROM", load_vbios_prom, false },
         { "PCIROM", load_vbios_pci, true },
+        { "ACPI", load_vbios_acpi, true },
 };
 
-#define METHODCNT 3
-
 static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
 {
-        struct drm_nouveau_private *dev_priv = dev->dev_private;
-        struct methods *methods;
-        int i;
+        const int nr_methods = ARRAY_SIZE(shadow_methods);
+        struct methods *methods = shadow_methods;
         int testscore = 3;
-        int scores[METHODCNT];
+        int scores[nr_methods], i;
 
         if (nouveau_vbios) {
-                methods = nv04_methods;
-                for (i = 0; i < METHODCNT; i++)
+                for (i = 0; i < nr_methods; i++)
                         if (!strcasecmp(nouveau_vbios, methods[i].desc))
                                 break;
 
-                if (i < METHODCNT) {
+                if (i < nr_methods) {
                         NV_INFO(dev, "Attempting to use BIOS image from %s\n",
                                 methods[i].desc);
 
@@ -244,12 +234,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
                 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
         }
 
-        if (dev_priv->card_type < NV_50)
-                methods = nv04_methods;
-        else
-                methods = nv50_methods;
-
-        for (i = 0; i < METHODCNT; i++) {
+        for (i = 0; i < nr_methods; i++) {
                 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
                          methods[i].desc);
                 data[0] = data[1] = 0;  /* avoid reuse of previous image */
@@ -260,7 +245,7 @@ static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
         }
 
         while (--testscore > 0) {
-                for (i = 0; i < METHODCNT; i++) {
+                for (i = 0; i < nr_methods; i++) {
                         if (scores[i] == testscore) {
                                 NV_TRACE(dev, "Using BIOS image from %s\n",
                                          methods[i].desc);
diff --git a/drivers/gpu/drm/nouveau/nouveau_fbcon.c b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
index c9a4a0d2a115..257ea130ae13 100644
--- a/drivers/gpu/drm/nouveau/nouveau_fbcon.c
+++ b/drivers/gpu/drm/nouveau/nouveau_fbcon.c
@@ -387,7 +387,8 @@ int nouveau_fbcon_init(struct drm_device *dev)
         dev_priv->nfbdev = nfbdev;
         nfbdev->helper.funcs = &nouveau_fbcon_helper_funcs;
 
-        ret = drm_fb_helper_init(dev, &nfbdev->helper, 2, 4);
+        ret = drm_fb_helper_init(dev, &nfbdev->helper,
+                                 nv_two_heads(dev) ? 2 : 1, 4);
         if (ret) {
                 kfree(nfbdev);
                 return ret;
diff --git a/drivers/gpu/drm/radeon/evergreen_cs.c b/drivers/gpu/drm/radeon/evergreen_cs.c
index 010963d4570f..345a75a03c96 100644
--- a/drivers/gpu/drm/radeon/evergreen_cs.c
+++ b/drivers/gpu/drm/radeon/evergreen_cs.c
@@ -333,7 +333,6 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
         reg = CP_PACKET0_GET_REG(header);
-        mutex_lock(&p->rdev->ddev->mode_config.mutex);
         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
         if (!obj) {
                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -368,7 +367,6 @@ static int evergreen_cs_packet_parse_vline(struct radeon_cs_parser *p)
                 }
         }
 out:
-        mutex_unlock(&p->rdev->ddev->mode_config.mutex);
         return r;
 }
 
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 3970e62eaab8..a89a15ab524d 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1230,7 +1230,6 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 5);
         reg = CP_PACKET0_GET_REG(header);
-        mutex_lock(&p->rdev->ddev->mode_config.mutex);
         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
         if (!obj) {
                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -1264,7 +1263,6 @@ int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
         }
 out:
-        mutex_unlock(&p->rdev->ddev->mode_config.mutex);
         return r;
 }
 
@@ -2354,6 +2352,7 @@ void r100_mc_init(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_IGP)
                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = 0;
         if (!(rdev->flags & RADEON_IS_AGP))
                 radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 7e81db5eb804..19a7ef7ee344 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -481,6 +481,7 @@ void r300_mc_init(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_IGP)
                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = 0;
         if (!(rdev->flags & RADEON_IS_AGP))
                 radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
@@ -1176,6 +1177,8 @@ int r300_cs_parse(struct radeon_cs_parser *p)
         int r;
 
         track = kzalloc(sizeof(*track), GFP_KERNEL);
+        if (track == NULL)
+                return -ENOMEM;
         r100_cs_track_clear(p->rdev, track);
         p->track = track;
         do {
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index 34330df28483..694af7cc23ac 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -125,6 +125,7 @@ void r520_mc_init(struct radeon_device *rdev)
         r520_vram_get_type(rdev);
         r100_vram_init_sizes(rdev);
         radeon_vram_location(rdev, &rdev->mc, 0);
+        rdev->mc.gtt_base_align = 0;
         if (!(rdev->flags & RADEON_IS_AGP))
                 radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 3d6645ce2151..e100f69faeec 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1179,6 +1179,7 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
                 if (rdev->flags & RADEON_IS_IGP)
                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
                 radeon_vram_location(rdev, &rdev->mc, base);
+                rdev->mc.gtt_base_align = 0;
                 radeon_gtt_location(rdev, mc);
         }
 }
diff --git a/drivers/gpu/drm/radeon/r600_blit.c b/drivers/gpu/drm/radeon/r600_blit.c
index f4fb88ece2bb..ca5c29f70779 100644
--- a/drivers/gpu/drm/radeon/r600_blit.c
+++ b/drivers/gpu/drm/radeon/r600_blit.c
@@ -538,9 +538,12 @@ int
 r600_prepare_blit_copy(struct drm_device *dev, struct drm_file *file_priv)
 {
         drm_radeon_private_t *dev_priv = dev->dev_private;
+        int ret;
         DRM_DEBUG("\n");
 
-        r600_nomm_get_vb(dev);
+        ret = r600_nomm_get_vb(dev);
+        if (ret)
+                return ret;
 
         dev_priv->blit_vb->file_priv = file_priv;
 
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index c39c1bc13016..144c32d37136 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -585,7 +585,7 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
         header = radeon_get_ib_value(p, h_idx);
         crtc_id = radeon_get_ib_value(p, h_idx + 2 + 7 + 1);
         reg = CP_PACKET0_GET_REG(header);
-        mutex_lock(&p->rdev->ddev->mode_config.mutex);
+
         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
         if (!obj) {
                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
@@ -620,7 +620,6 @@ static int r600_cs_packet_parse_vline(struct radeon_cs_parser *p)
                 ib[h_idx + 4] = AVIVO_D2MODE_VLINE_STATUS >> 2;
         }
 out:
-        mutex_unlock(&p->rdev->ddev->mode_config.mutex);
         return r;
 }
 
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index ab61aaa887bb..2f94dc66c183 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -351,6 +351,7 @@ struct radeon_mc {
         int                     vram_mtrr;
         bool                    vram_is_ddr;
         bool                    igp_sideport_enabled;
+        u64                     gtt_base_align;
 };
 
 bool radeon_combios_sideport_present(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 99bd8a9c56b3..10673ae59cfa 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -280,6 +280,15 @@ static bool radeon_atom_apply_quirks(struct drm_device *dev,
                 }
         }
 
+        /* ASUS HD 3600 board lists the DVI port as HDMI */
+        if ((dev->pdev->device == 0x9598) &&
+            (dev->pdev->subsystem_vendor == 0x1043) &&
+            (dev->pdev->subsystem_device == 0x01e4)) {
+                if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
+                        *connector_type = DRM_MODE_CONNECTOR_DVII;
+                }
+        }
+
         /* ASUS HD 3450 board lists the DVI port as HDMI */
         if ((dev->pdev->device == 0x95C5) &&
             (dev->pdev->subsystem_vendor == 0x1043) &&
@@ -1029,8 +1038,15 @@ bool radeon_atombios_sideport_present(struct radeon_device *rdev)
                                       data_offset);
                 switch (crev) {
                 case 1:
-                        if (igp_info->info.ucMemoryType & 0xf0)
-                                return true;
+                        /* AMD IGPS */
+                        if ((rdev->family == CHIP_RS690) ||
+                            (rdev->family == CHIP_RS740)) {
+                                if (igp_info->info.ulBootUpMemoryClock)
+                                        return true;
+                        } else {
+                                if (igp_info->info.ucMemoryType & 0xf0)
+                                        return true;
+                        }
                         break;
                 case 2:
                         if (igp_info->info_2.ucMemoryType & 0x0f)
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index d1c1d8dd93ce..2417d7b06fdb 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -3050,6 +3050,14 @@ void radeon_combios_asic_init(struct drm_device *dev)
             rdev->pdev->subsystem_device == 0x308b)
                 return;
 
+        /* quirk for rs4xx HP dv5000 laptop to make it resume
+         * - it hangs on resume inside the dynclk 1 table.
+         */
+        if (rdev->family == CHIP_RS480 &&
+            rdev->pdev->subsystem_vendor == 0x103c &&
+            rdev->pdev->subsystem_device == 0x30a4)
+                return;
+
         /* DYN CLK 1 */
         table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE);
         if (table)
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index f58f8bd8f77b..adccbc2c202c 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -771,14 +771,14 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
                         } else
                                 ret = connector_status_connected;
 
-                        /* multiple connectors on the same encoder with the same ddc line
-                         * This tends to be HDMI and DVI on the same encoder with the
-                         * same ddc line.  If the edid says HDMI, consider the HDMI port
-                         * connected and the DVI port disconnected.  If the edid doesn't
-                         * say HDMI, vice versa.
+                        /* This gets complicated.  We have boards with VGA + HDMI with a
+                         * shared DDC line and we have boards with DVI-D + HDMI with a shared
+                         * DDC line.  The latter is more complex because with DVI<->HDMI adapters
+                         * you don't really know what's connected to which port as both are digital.
                          */
                         if (radeon_connector->shared_ddc && (ret == connector_status_connected)) {
                                 struct drm_device *dev = connector->dev;
+                                struct radeon_device *rdev = dev->dev_private;
                                 struct drm_connector *list_connector;
                                 struct radeon_connector *list_radeon_connector;
                                 list_for_each_entry(list_connector, &dev->mode_config.connector_list, head) {
@@ -788,15 +788,10 @@ static enum drm_connector_status radeon_dvi_detect(struct drm_connector *connect
                                         if (list_radeon_connector->shared_ddc &&
                                             (list_radeon_connector->ddc_bus->rec.i2c_id ==
                                              radeon_connector->ddc_bus->rec.i2c_id)) {
-                                                if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
-                                                        if (connector->connector_type == DRM_MODE_CONNECTOR_DVID) {
-                                                                kfree(radeon_connector->edid);
-                                                                radeon_connector->edid = NULL;
-                                                                ret = connector_status_disconnected;
-                                                        }
-                                                } else {
-                                                        if ((connector->connector_type == DRM_MODE_CONNECTOR_HDMIA) ||
-                                                            (connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)) {
+                                                /* cases where both connectors are digital */
+                                                if (list_connector->connector_type != DRM_MODE_CONNECTOR_VGA) {
+                                                        /* hpd is our only option in this case */
+                                                        if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
                                                                 kfree(radeon_connector->edid);
                                                                 radeon_connector->edid = NULL;
                                                                 ret = connector_status_disconnected;
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 5f317317aba2..dd279da90546 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -226,20 +226,20 @@ void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 {
         u64 size_af, size_bf;
 
-        size_af = 0xFFFFFFFF - mc->vram_end;
-        size_bf = mc->vram_start;
+        size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
+        size_bf = mc->vram_start & ~mc->gtt_base_align;
         if (size_bf > size_af) {
                 if (mc->gtt_size > size_bf) {
                         dev_warn(rdev->dev, "limiting GTT\n");
                         mc->gtt_size = size_bf;
                 }
-                mc->gtt_start = mc->vram_start - mc->gtt_size;
+                mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
         } else {
                 if (mc->gtt_size > size_af) {
                         dev_warn(rdev->dev, "limiting GTT\n");
                         mc->gtt_size = size_af;
                 }
-                mc->gtt_start = mc->vram_end + 1;
+                mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
         }
         mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
         dev_info(rdev->dev, "GTT: %lluM 0x%08llX - 0x%08llX\n",
diff --git a/drivers/gpu/drm/radeon/radeon_kms.c b/drivers/gpu/drm/radeon/radeon_kms.c
index 6a70c0dc7f92..ab389f89fa8d 100644
--- a/drivers/gpu/drm/radeon/radeon_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_kms.c
@@ -128,7 +128,8 @@ int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
                         crtc = (struct drm_crtc *)minfo->crtcs[i];
                         if (crtc && crtc->base.id == value) {
-                                value = i;
+                                struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+                                value = radeon_crtc->crtc_id;
                                 found = 1;
                                 break;
                         }
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
index bad77f40a9da..5688a0cf6bbe 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
@@ -108,6 +108,7 @@ static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
                 udelay(panel_pwr_delay * 1000);
                 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
+                udelay(panel_pwr_delay * 1000);
                 break;
         }
 
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_tv.c b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
index f2ed27c8055b..032040397743 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_tv.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_tv.c
@@ -642,8 +642,8 @@ void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
         }
         flicker_removal = (tmp + 500) / 1000;
 
-        if (flicker_removal < 2)
-                flicker_removal = 2;
+        if (flicker_removal < 3)
+                flicker_removal = 3;
         for (i = 0; i < ARRAY_SIZE(SLOPE_limit); ++i) {
                 if (flicker_removal == SLOPE_limit[i])
                         break;
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 9e4240b3bf0b..f454c9a5e7f2 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -57,7 +57,9 @@ void rs400_gart_adjust_size(struct radeon_device *rdev)
         }
         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
                 /* FIXME: RS400 & RS480 seems to have issue with GART size
-                 * if 4G of system memory (needs more testing) */
+                 * if 4G of system memory (needs more testing)
+                 */
+                /* XXX is this still an issue with proper alignment? */
                 rdev->mc.gtt_size = 32 * 1024 * 1024;
                 DRM_ERROR("Forcing to 32M GART size (because of ASIC bug ?)\n");
         }
@@ -263,6 +265,7 @@ void rs400_mc_init(struct radeon_device *rdev)
         r100_vram_init_sizes(rdev);
         base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
         radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
 }
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 7bb4c3e52f3b..6dc15ea8ba33 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -698,6 +698,7 @@ void rs600_mc_init(struct radeon_device *rdev)
         base = G_000004_MC_FB_START(base) << 16;
         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = 0;
         radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
 }
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index f4f0a61bcdce..ce4ecbe10816 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -162,6 +162,7 @@ void rs690_mc_init(struct radeon_device *rdev)
         rs690_pm_info(rdev);
         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
         radeon_vram_location(rdev, &rdev->mc, base);
+        rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
         radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
 }
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index 7d9a7b0a180a..0c9c169a6852 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -195,6 +195,7 @@ void rv515_mc_init(struct radeon_device *rdev)
         rv515_vram_get_type(rdev);
         r100_vram_init_sizes(rdev);
         radeon_vram_location(rdev, &rdev->mc, 0);
+        rdev->mc.gtt_base_align = 0;
         if (!(rdev->flags & RADEON_IS_AGP))
                 radeon_gtt_location(rdev, &rdev->mc);
         radeon_update_bandwidth_info(rdev);
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index b1d67dc973dc..ca904799f018 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -40,11 +40,13 @@
 #include <linux/slab.h>
 
 #include <asm/atomic.h>
-#include <asm/agp.h>
 
 #include "ttm/ttm_bo_driver.h"
 #include "ttm/ttm_page_alloc.h"
 
+#ifdef TTM_HAS_AGP
+#include <asm/agp.h>
+#endif
 
 #define NUM_PAGES_TO_ALLOC              (PAGE_SIZE/sizeof(struct page *))
 #define SMALL_ALLOCATION                16
@@ -392,7 +394,7 @@ static int ttm_pool_get_num_unused_pages(void)
 /**
  * Callback for mm to request pool to reduce number of page held.
  */
-static int ttm_pool_mm_shrink(int shrink_pages, gfp_t gfp_mask)
+static int ttm_pool_mm_shrink(struct shrinker *shrink, int shrink_pages, gfp_t gfp_mask)
 {
         static atomic_t start_pool = ATOMIC_INIT(0);
         unsigned i;
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
index f1d626112415..437ac786277a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_kms.c
@@ -972,6 +972,7 @@ int vmw_kms_update_layout_ioctl(struct drm_device *dev, void *data,
         ret = copy_from_user(rects, user_rects, rects_size);
         if (unlikely(ret != 0)) {
                 DRM_ERROR("Failed to get rects.\n");
+                ret = -EFAULT;
                 goto out_free;
         }