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-rw-r--r--drivers/gpu/drm/nouveau/nv50_graph.c1
-rw-r--r--drivers/gpu/drm/sis/sis_drv.h4
2 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index e25cbb46789a..40680f2b4231 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -31,7 +31,6 @@
31#include "nouveau_grctx.h" 31#include "nouveau_grctx.h"
32#include "nouveau_dma.h" 32#include "nouveau_dma.h"
33#include "nouveau_vm.h" 33#include "nouveau_vm.h"
34#include "nouveau_ramht.h"
35#include "nv50_evo.h" 34#include "nv50_evo.h"
36 35
37struct nv50_graph_engine { 36struct nv50_graph_engine {
diff --git a/drivers/gpu/drm/sis/sis_drv.h b/drivers/gpu/drm/sis/sis_drv.h
index ef940bad63f7..194303c177ad 100644
--- a/drivers/gpu/drm/sis/sis_drv.h
+++ b/drivers/gpu/drm/sis/sis_drv.h
@@ -48,8 +48,8 @@ enum sis_family {
48 48
49 49
50#define SIS_BASE (dev_priv->mmio) 50#define SIS_BASE (dev_priv->mmio)
51#define SIS_READ(reg) DRM_READ32(SIS_BASE, reg); 51#define SIS_READ(reg) DRM_READ32(SIS_BASE, reg)
52#define SIS_WRITE(reg, val) DRM_WRITE32(SIS_BASE, reg, val); 52#define SIS_WRITE(reg, val) DRM_WRITE32(SIS_BASE, reg, val)
53 53
54typedef struct drm_sis_private { 54typedef struct drm_sis_private {
55 drm_local_map_t *mmio; 55 drm_local_map_t *mmio;