1 files changed, 231 insertions, 45 deletions
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
index 96949b93d920..13afddc1f034 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_drv.c
@@ -82,16 +82,27 @@
 #define DRM_IOCTL_VMW_EXECBUF                                   \
        DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF,             \
                struct drm_vmw_execbuf_arg)
-#define DRM_IOCTL_VMW_FIFO_DEBUG                                \
+#define DRM_IOCTL_VMW_GET_3D_CAP                                \
-        DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FIFO_DEBUG,         \
+        DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP,          \
-                 struct drm_vmw_fifo_debug_arg)
+                 struct drm_vmw_get_3d_cap_arg)
 #define DRM_IOCTL_VMW_FENCE_WAIT                                \
        DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT,         \
                 struct drm_vmw_fence_wait_arg)
-#define DRM_IOCTL_VMW_UPDATE_LAYOUT                             \
+#define DRM_IOCTL_VMW_FENCE_SIGNALED                            \
-        DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT,      \
+        DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED,     \
-                 struct drm_vmw_update_layout_arg)
+                 struct drm_vmw_fence_signaled_arg)
+#define DRM_IOCTL_VMW_FENCE_UNREF                               \
+        DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF,         \
+                 struct drm_vmw_fence_arg)
+#define DRM_IOCTL_VMW_FENCE_EVENT                               \
+        DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT,         \
+                 struct drm_vmw_fence_event_arg)
+#define DRM_IOCTL_VMW_PRESENT                                   \
+        DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT,             \
+                 struct drm_vmw_present_arg)
+#define DRM_IOCTL_VMW_PRESENT_READBACK                          \
+        DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK,    \
+                 struct drm_vmw_present_readback_arg)
 /**
 * The core DRM version of this macro doesn't account for
@@ -135,12 +146,25 @@ static struct drm_ioctl_desc vmw_ioctls[] = {
                      DRM_AUTH | DRM_UNLOCKED),
        VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl,
                      DRM_AUTH | DRM_UNLOCKED),
-        VMW_IOCTL_DEF(VMW_FIFO_DEBUG, vmw_fifo_debug_ioctl,
+        VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl,
-                      DRM_AUTH | DRM_ROOT_ONLY | DRM_MASTER | DRM_UNLOCKED),
+                      DRM_AUTH | DRM_UNLOCKED),
-        VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_wait_ioctl,
+        VMW_IOCTL_DEF(VMW_FENCE_SIGNALED,
+                      vmw_fence_obj_signaled_ioctl,
+                      DRM_AUTH | DRM_UNLOCKED),
+        VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl,
+                      DRM_AUTH | DRM_UNLOCKED),
+        VMW_IOCTL_DEF(VMW_FENCE_EVENT,
+                      vmw_fence_event_ioctl,
+                      DRM_AUTH | DRM_UNLOCKED),
+        VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl,
                      DRM_AUTH | DRM_UNLOCKED),
-        VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, vmw_kms_update_layout_ioctl,
-                      DRM_MASTER | DRM_CONTROL_ALLOW | DRM_UNLOCKED)
+        /* these allow direct access to the framebuffers mark as master only */
+        VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl,
+                      DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
+        VMW_IOCTL_DEF(VMW_PRESENT_READBACK,
+                      vmw_present_readback_ioctl,
+                      DRM_MASTER | DRM_AUTH | DRM_UNLOCKED),
 };
 static struct pci_device_id vmw_pci_id_list[] = {
@@ -189,8 +213,78 @@ static void vmw_print_capabilities(uint32_t capabilities)
                DRM_INFO("  GMR.\n");
        if (capabilities & SVGA_CAP_TRACES)
                DRM_INFO("  Traces.\n");
+        if (capabilities & SVGA_CAP_GMR2)
+                DRM_INFO("  GMR2.\n");
+        if (capabilities & SVGA_CAP_SCREEN_OBJECT_2)
+                DRM_INFO("  Screen Object 2.\n");
+}
+/**
+ * vmw_execbuf_prepare_dummy_query - Initialize a query result structure at
+ * the start of a buffer object.
+ *
+ * @dev_priv: The device private structure.
+ *
+ * This function will idle the buffer using an uninterruptible wait, then
+ * map the first page and initialize a pending occlusion query result structure,
+ * Finally it will unmap the buffer.
+ *
+ * TODO: Since we're only mapping a single page, we should optimize the map
+ * to use kmap_atomic / iomap_atomic.
+ */
+static void vmw_dummy_query_bo_prepare(struct vmw_private *dev_priv)
+{
+        struct ttm_bo_kmap_obj map;
+        volatile SVGA3dQueryResult *result;
+        bool dummy;
+        int ret;
+        struct ttm_bo_device *bdev = &dev_priv->bdev;
+        struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
+        ttm_bo_reserve(bo, false, false, false, 0);
+        spin_lock(&bdev->fence_lock);
+        ret = ttm_bo_wait(bo, false, false, false);
+        spin_unlock(&bdev->fence_lock);
+        if (unlikely(ret != 0))
+                (void) vmw_fallback_wait(dev_priv, false, true, 0, false,
+                                         10*HZ);
+        ret = ttm_bo_kmap(bo, 0, 1, &map);
+        if (likely(ret == 0)) {
+                result = ttm_kmap_obj_virtual(&map, &dummy);
+                result->totalSize = sizeof(*result);
+                result->state = SVGA3D_QUERYSTATE_PENDING;
+                result->result32 = 0xff;
+                ttm_bo_kunmap(&map);
+        } else
+                DRM_ERROR("Dummy query buffer map failed.\n");
+        ttm_bo_unreserve(bo);
+}
+/**
+ * vmw_dummy_query_bo_create - create a bo to hold a dummy query result
+ *
+ * @dev_priv: A device private structure.
+ *
+ * This function creates a small buffer object that holds the query
+ * result for dummy queries emitted as query barriers.
+ * No interruptible waits are done within this function.
+ *
+ * Returns an error if bo creation fails.
+ */
+static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv)
+{
+        return ttm_bo_create(&dev_priv->bdev,
+                             PAGE_SIZE,
+                             ttm_bo_type_device,
+                             &vmw_vram_sys_placement,
+                             0, 0, false, NULL,
+                             &dev_priv->dummy_query_bo);
 }
 static int vmw_request_device(struct vmw_private *dev_priv)
 {
        int ret;
@@ -200,16 +294,42 @@ static int vmw_request_device(struct vmw_private *dev_priv)
                DRM_ERROR("Unable to initialize FIFO.\n");
                return ret;
        }
+        vmw_fence_fifo_up(dev_priv->fman);
+        ret = vmw_dummy_query_bo_create(dev_priv);
+        if (unlikely(ret != 0))
+                goto out_no_query_bo;
+        vmw_dummy_query_bo_prepare(dev_priv);
        return 0;
+out_no_query_bo:
+        vmw_fence_fifo_down(dev_priv->fman);
+        vmw_fifo_release(dev_priv, &dev_priv->fifo);
+        return ret;
 }
 static void vmw_release_device(struct vmw_private *dev_priv)
 {
+        /*
+         * Previous destructions should've released
+         * the pinned bo.
+         */
+        BUG_ON(dev_priv->pinned_bo != NULL);
+        ttm_bo_unref(&dev_priv->dummy_query_bo);
+        vmw_fence_fifo_down(dev_priv->fman);
        vmw_fifo_release(dev_priv, &dev_priv->fifo);
 }
-int vmw_3d_resource_inc(struct vmw_private *dev_priv)
+/**
+ * Increase the 3d resource refcount.
+ * If the count was prevously zero, initialize the fifo, switching to svga
+ * mode. Note that the master holds a ref as well, and may request an
+ * explicit switch to svga mode if fb is not running, using @unhide_svga.
+ */
+int vmw_3d_resource_inc(struct vmw_private *dev_priv,
+                        bool unhide_svga)
 {
        int ret = 0;
@@ -218,19 +338,42 @@ int vmw_3d_resource_inc(struct vmw_private *dev_priv)
                ret = vmw_request_device(dev_priv);
                if (unlikely(ret != 0))
                        --dev_priv->num_3d_resources;
+        } else if (unhide_svga) {
+                mutex_lock(&dev_priv->hw_mutex);
+                vmw_write(dev_priv, SVGA_REG_ENABLE,
+                          vmw_read(dev_priv, SVGA_REG_ENABLE) &
+                          ~SVGA_REG_ENABLE_HIDE);
+                mutex_unlock(&dev_priv->hw_mutex);
        }
        mutex_unlock(&dev_priv->release_mutex);
        return ret;
 }
+/**
-void vmw_3d_resource_dec(struct vmw_private *dev_priv)
+ * Decrease the 3d resource refcount.
+ * If the count reaches zero, disable the fifo, switching to vga mode.
+ * Note that the master holds a refcount as well, and may request an
+ * explicit switch to vga mode when it releases its refcount to account
+ * for the situation of an X server vt switch to VGA with 3d resources
+ * active.
+ */
+void vmw_3d_resource_dec(struct vmw_private *dev_priv,
+                         bool hide_svga)
 {
        int32_t n3d;
        mutex_lock(&dev_priv->release_mutex);
        if (unlikely(--dev_priv->num_3d_resources == 0))
                vmw_release_device(dev_priv);
+        else if (hide_svga) {
+                mutex_lock(&dev_priv->hw_mutex);
+                vmw_write(dev_priv, SVGA_REG_ENABLE,
+                          vmw_read(dev_priv, SVGA_REG_ENABLE) |
+                          SVGA_REG_ENABLE_HIDE);
+                mutex_unlock(&dev_priv->hw_mutex);
+        }
        n3d = (int32_t) dev_priv->num_3d_resources;
        mutex_unlock(&dev_priv->release_mutex);
@@ -252,7 +395,7 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
        dev_priv->dev = dev;
        dev_priv->vmw_chipset = chipset;
-        dev_priv->last_read_sequence = (uint32_t) -100;
+        dev_priv->last_read_seqno = (uint32_t) -100;
        mutex_init(&dev_priv->hw_mutex);
        mutex_init(&dev_priv->cmdbuf_mutex);
        mutex_init(&dev_priv->release_mutex);
@@ -263,8 +406,10 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
        mutex_init(&dev_priv->init_mutex);
        init_waitqueue_head(&dev_priv->fence_queue);
        init_waitqueue_head(&dev_priv->fifo_queue);
-        atomic_set(&dev_priv->fence_queue_waiters, 0);
+        dev_priv->fence_queue_waiters = 0;
        atomic_set(&dev_priv->fifo_queue_waiters, 0);
+        INIT_LIST_HEAD(&dev_priv->surface_lru);
+        dev_priv->used_memory_size = 0;
        dev_priv->io_start = pci_resource_start(dev->pdev, 0);
        dev_priv->vram_start = pci_resource_start(dev->pdev, 1);
@@ -285,6 +430,10 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
        dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES);
+        dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
+        dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
+        dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
+        dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
        if (dev_priv->capabilities & SVGA_CAP_GMR) {
                dev_priv->max_gmr_descriptors =
                        vmw_read(dev_priv,
@@ -292,11 +441,19 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
                dev_priv->max_gmr_ids =
                        vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS);
        }
+        if (dev_priv->capabilities & SVGA_CAP_GMR2) {
-        dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE);
+                dev_priv->max_gmr_pages =
-        dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE);
+                        vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES);
-        dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH);
+                dev_priv->memory_size =
-        dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT);
+                        vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE);
+                dev_priv->memory_size -= dev_priv->vram_size;
+        } else {
+                /*
+                 * An arbitrary limit of 512MiB on surface
+                 * memory. But all HWV8 hardware supports GMR2.
+                 */
+                dev_priv->memory_size = 512*1024*1024;
+        }
        mutex_unlock(&dev_priv->hw_mutex);
@@ -308,6 +465,12 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
                DRM_INFO("Max GMR descriptors is %u\n",
                         (unsigned)dev_priv->max_gmr_descriptors);
        }
+        if (dev_priv->capabilities & SVGA_CAP_GMR2) {
+                DRM_INFO("Max number of GMR pages is %u\n",
+                         (unsigned)dev_priv->max_gmr_pages);
+                DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n",
+                         (unsigned)dev_priv->memory_size / 1024);
+        }
        DRM_INFO("VRAM at 0x%08x size is %u kiB\n",
                 dev_priv->vram_start, dev_priv->vram_size / 1024);
        DRM_INFO("MMIO at 0x%08x size is %u kiB\n",
@@ -394,22 +557,34 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
                        goto out_no_device;
                }
        }
+        dev_priv->fman = vmw_fence_manager_init(dev_priv);
+        if (unlikely(dev_priv->fman == NULL))
+                goto out_no_fman;
+        /* Need to start the fifo to check if we can do screen objects */
+        ret = vmw_3d_resource_inc(dev_priv, true);
+        if (unlikely(ret != 0))
+                goto out_no_fifo;
+        vmw_kms_save_vga(dev_priv);
+        /* Start kms and overlay systems, needs fifo. */
        ret = vmw_kms_init(dev_priv);
        if (unlikely(ret != 0))
                goto out_no_kms;
        vmw_overlay_init(dev_priv);
+        /* 3D Depends on Screen Objects being used. */
+        DRM_INFO("Detected %sdevice 3D availability.\n",
+                 vmw_fifo_have_3d(dev_priv) ?
+                 "" : "no ");
+        /* We might be done with the fifo now */
        if (dev_priv->enable_fb) {
-                ret = vmw_3d_resource_inc(dev_priv);
-                if (unlikely(ret != 0))
-                        goto out_no_fifo;
-                vmw_kms_save_vga(dev_priv);
                vmw_fb_init(dev_priv);
-                DRM_INFO("%s", vmw_fifo_have_3d(dev_priv) ?
-                         "Detected device 3D availability.\n" :
-                         "Detected no device 3D availability.\n");
        } else {
-                DRM_INFO("Delayed 3D detection since we're not "
+                vmw_kms_restore_vga(dev_priv);
-                         "running the device in SVGA mode yet.\n");
+                vmw_3d_resource_dec(dev_priv, true);
        }
        if (dev_priv->capabilities & SVGA_CAP_IRQMASK) {
@@ -426,15 +601,19 @@ static int vmw_driver_load(struct drm_device *dev, unsigned long chipset)
        return 0;
 out_no_irq:
-        if (dev_priv->enable_fb) {
+        if (dev_priv->enable_fb)
                vmw_fb_close(dev_priv);
-                vmw_kms_restore_vga(dev_priv);
-                vmw_3d_resource_dec(dev_priv);
-        }
-out_no_fifo:
        vmw_overlay_close(dev_priv);
        vmw_kms_close(dev_priv);
 out_no_kms:
+        /* We still have a 3D resource reference held */
+        if (dev_priv->enable_fb) {
+                vmw_kms_restore_vga(dev_priv);
+                vmw_3d_resource_dec(dev_priv, false);
+        }
+out_no_fifo:
+        vmw_fence_manager_takedown(dev_priv->fman);
+out_no_fman:
        if (dev_priv->stealth)
                pci_release_region(dev->pdev, 2);
        else
@@ -467,15 +646,18 @@ static int vmw_driver_unload(struct drm_device *dev)
        unregister_pm_notifier(&dev_priv->pm_nb);
+        if (dev_priv->ctx.cmd_bounce)
+                vfree(dev_priv->ctx.cmd_bounce);
        if (dev_priv->capabilities & SVGA_CAP_IRQMASK)
                drm_irq_uninstall(dev_priv->dev);
        if (dev_priv->enable_fb) {
                vmw_fb_close(dev_priv);
                vmw_kms_restore_vga(dev_priv);
-                vmw_3d_resource_dec(dev_priv);
+                vmw_3d_resource_dec(dev_priv, false);
        }
        vmw_kms_close(dev_priv);
        vmw_overlay_close(dev_priv);
+        vmw_fence_manager_takedown(dev_priv->fman);
        if (dev_priv->stealth)
                pci_release_region(dev->pdev, 2);
        else
@@ -646,7 +828,7 @@ static int vmw_master_set(struct drm_device *dev,
        int ret = 0;
        if (!dev_priv->enable_fb) {
-                ret = vmw_3d_resource_inc(dev_priv);
+                ret = vmw_3d_resource_inc(dev_priv, true);
                if (unlikely(ret != 0))
                        return ret;
                vmw_kms_save_vga(dev_priv);
@@ -688,7 +870,7 @@ out_no_active_lock:
                vmw_write(dev_priv, SVGA_REG_TRACES, 1);
                mutex_unlock(&dev_priv->hw_mutex);
                vmw_kms_restore_vga(dev_priv);
-                vmw_3d_resource_dec(dev_priv);
+                vmw_3d_resource_dec(dev_priv, true);
        }
        return ret;
 }
@@ -709,7 +891,7 @@ static void vmw_master_drop(struct drm_device *dev,
        vmw_fp->locked_master = drm_master_get(file_priv->master);
        ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
-        vmw_kms_idle_workqueues(vmaster);
+        vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
        if (unlikely((ret != 0))) {
                DRM_ERROR("Unable to lock TTM at VT switch.\n");
@@ -726,7 +908,7 @@ static void vmw_master_drop(struct drm_device *dev,
                vmw_write(dev_priv, SVGA_REG_TRACES, 1);
                mutex_unlock(&dev_priv->hw_mutex);
                vmw_kms_restore_vga(dev_priv);
-                vmw_3d_resource_dec(dev_priv);
+                vmw_3d_resource_dec(dev_priv, true);
        }
        dev_priv->active_master = &dev_priv->fbdev_master;
@@ -761,6 +943,7 @@ static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val,
                 * This empties VRAM and unbinds all GMR bindings.
                 * Buffer contents is moved to swappable memory.
                 */
+                vmw_execbuf_release_pinned_bo(dev_priv, false, 0);
                ttm_bo_swapout_all(&dev_priv->bdev);
                break;
@@ -835,7 +1018,7 @@ static int vmw_pm_prepare(struct device *kdev)
         */
        dev_priv->suspended = true;
        if (dev_priv->enable_fb)
-                vmw_3d_resource_dec(dev_priv);
+                        vmw_3d_resource_dec(dev_priv, true);
        if (dev_priv->num_3d_resources != 0) {
@@ -843,7 +1026,7 @@ static int vmw_pm_prepare(struct device *kdev)
                         "while 3D resources are active.\n");
                if (dev_priv->enable_fb)
-                        vmw_3d_resource_inc(dev_priv);
+                        vmw_3d_resource_inc(dev_priv, true);
                dev_priv->suspended = false;
                return -EBUSY;
        }
@@ -862,7 +1045,7 @@ static void vmw_pm_complete(struct device *kdev)
         * start fifo.
         */
        if (dev_priv->enable_fb)
-                vmw_3d_resource_inc(dev_priv);
+                        vmw_3d_resource_inc(dev_priv, false);
        dev_priv->suspended = false;
 }
@@ -886,6 +1069,8 @@ static struct drm_driver driver = {
        .irq_uninstall = vmw_irq_uninstall,
        .irq_handler = vmw_irq_handler,
        .get_vblank_counter = vmw_get_vblank_counter,
+        .enable_vblank = vmw_enable_vblank,
+        .disable_vblank = vmw_disable_vblank,
        .reclaim_buffers_locked = NULL,
        .ioctls = vmw_ioctls,
        .num_ioctls = DRM_ARRAY_SIZE(vmw_ioctls),
@@ -902,7 +1087,8 @@ static struct drm_driver driver = {
                 .release = drm_release,
                 .unlocked_ioctl = vmw_unlocked_ioctl,
                 .mmap = vmw_mmap,
-                 .poll = drm_poll,
+                 .poll = vmw_fops_poll,
+                 .read = vmw_fops_read,
                 .fasync = drm_fasync,
 #if defined(CONFIG_COMPAT)
                 .compat_ioctl = drm_compat_ioctl,