9 files changed, 275 insertions, 148 deletions

diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index f4d4505fe831..e721e3087b99 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -258,7 +258,6 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
                 radeon_crtc->enabled = true;
                 /* adjust pm to dpms changes BEFORE enabling crtcs */
                 radeon_pm_compute_clocks(rdev);
-                /* disable crtc pair power gating before programming */
                 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
                         atombios_powergate_crtc(crtc, ATOM_DISABLE);
                 atombios_enable_crtc(crtc, ATOM_ENABLE);
@@ -278,25 +277,8 @@ void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
                 atombios_enable_crtc(crtc, ATOM_DISABLE);
                 radeon_crtc->enabled = false;
-                /* power gating is per-pair */
-                if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set) {
-                        struct drm_crtc *other_crtc;
-                        struct radeon_crtc *other_radeon_crtc;
-                        list_for_each_entry(other_crtc, &rdev->ddev->mode_config.crtc_list, head) {
-                                other_radeon_crtc = to_radeon_crtc(other_crtc);
-                                if (((radeon_crtc->crtc_id == 0) && (other_radeon_crtc->crtc_id == 1)) ||
-                                    ((radeon_crtc->crtc_id == 1) && (other_radeon_crtc->crtc_id == 0)) ||
-                                    ((radeon_crtc->crtc_id == 2) && (other_radeon_crtc->crtc_id == 3)) ||
-                                    ((radeon_crtc->crtc_id == 3) && (other_radeon_crtc->crtc_id == 2)) ||
-                                    ((radeon_crtc->crtc_id == 4) && (other_radeon_crtc->crtc_id == 5)) ||
-                                    ((radeon_crtc->crtc_id == 5) && (other_radeon_crtc->crtc_id == 4))) {
-                                        /* if both crtcs in the pair are off, enable power gating */
-                                        if (other_radeon_crtc->enabled == false)
-                                                atombios_powergate_crtc(crtc, ATOM_ENABLE);
-                                        break;
-                                }
-                        }
-                }
+                if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
+                        atombios_powergate_crtc(crtc, ATOM_ENABLE);
                 /* adjust pm to dpms changes AFTER disabling crtcs */
                 radeon_pm_compute_clocks(rdev);
                 break;
@@ -1497,14 +1479,98 @@ static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
         }
 }
 
+/**
+ * radeon_get_pll_use_mask - look up a mask of which pplls are in use
+ *
+ * @crtc: drm crtc
+ *
+ * Returns the mask of which PPLLs (Pixel PLLs) are in use.
+ */
+static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_crtc *test_crtc;
+        struct radeon_crtc *radeon_test_crtc;
+        u32 pll_in_use = 0;
+
+        list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
+                if (crtc == test_crtc)
+                        continue;
+
+                radeon_test_crtc = to_radeon_crtc(test_crtc);
+                if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
+                        pll_in_use |= (1 << radeon_test_crtc->pll_id);
+        }
+        return pll_in_use;
+}
+
+/**
+ * radeon_get_shared_dp_ppll - return the PPLL used by another crtc for DP
+ *
+ * @crtc: drm crtc
+ *
+ * Returns the PPLL (Pixel PLL) used by another crtc/encoder which is
+ * also in DP mode.  For DP, a single PPLL can be used for all DP
+ * crtcs/encoders.
+ */
+static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
+{
+        struct drm_device *dev = crtc->dev;
+        struct drm_encoder *test_encoder;
+        struct radeon_crtc *radeon_test_crtc;
+
+        list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
+                if (test_encoder->crtc && (test_encoder->crtc != crtc)) {
+                        if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
+                                /* for DP use the same PLL for all */
+                                radeon_test_crtc = to_radeon_crtc(test_encoder->crtc);
+                                if (radeon_test_crtc->pll_id != ATOM_PPLL_INVALID)
+                                        return radeon_test_crtc->pll_id;
+                        }
+                }
+        }
+        return ATOM_PPLL_INVALID;
+}
+
+/**
+ * radeon_atom_pick_pll - Allocate a PPLL for use by the crtc.
+ *
+ * @crtc: drm crtc
+ *
+ * Returns the PPLL (Pixel PLL) to be used by the crtc.  For DP monitors
+ * a single PPLL can be used for all DP crtcs/encoders.  For non-DP
+ * monitors a dedicated PPLL must be used.  If a particular board has
+ * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
+ * as there is no need to program the PLL itself.  If we are not able to
+ * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
+ * avoid messing up an existing monitor.
+ *
+ * Asic specific PLL information
+ *
+ * DCE 6.1
+ * - PPLL2 is only available to UNIPHYA (both DP and non-DP)
+ * - PPLL0, PPLL1 are available for UNIPHYB/C/D/E/F (both DP and non-DP)
+ *
+ * DCE 6.0
+ * - PPLL0 is available to all UNIPHY (DP only)
+ * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
+ *
+ * DCE 5.0
+ * - DCPLL is available to all UNIPHY (DP only)
+ * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
+ *
+ * DCE 3.0/4.0/4.1
+ * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
+ *
+ */
 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 {
         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
         struct drm_device *dev = crtc->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct drm_encoder *test_encoder;
-        struct drm_crtc *test_crtc;
-        uint32_t pll_in_use = 0;
+        u32 pll_in_use;
+        int pll;
 
         if (ASIC_IS_DCE61(rdev)) {
                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
@@ -1516,32 +1582,40 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 
                                 if ((test_radeon_encoder->encoder_id ==
                                      ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
-                                    (dig->linkb == false)) /* UNIPHY A uses PPLL2 */
+                                    (dig->linkb == false))
+                                        /* UNIPHY A uses PPLL2 */
                                         return ATOM_PPLL2;
+                                else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
+                                        /* UNIPHY B/C/D/E/F */
+                                        if (rdev->clock.dp_extclk)
+                                                /* skip PPLL programming if using ext clock */
+                                                return ATOM_PPLL_INVALID;
+                                        else {
+                                                /* use the same PPLL for all DP monitors */
+                                                pll = radeon_get_shared_dp_ppll(crtc);
+                                                if (pll != ATOM_PPLL_INVALID)
+                                                        return pll;
+                                        }
+                                }
+                                break;
                         }
                 }
                 /* UNIPHY B/C/D/E/F */
-                list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
-                        struct radeon_crtc *radeon_test_crtc;
-
-                        if (crtc == test_crtc)
-                                continue;
-
-                        radeon_test_crtc = to_radeon_crtc(test_crtc);
-                        if ((radeon_test_crtc->pll_id == ATOM_PPLL0) ||
-                            (radeon_test_crtc->pll_id == ATOM_PPLL1))
-                                pll_in_use |= (1 << radeon_test_crtc->pll_id);
-                }
-                if (!(pll_in_use & 4))
+                pll_in_use = radeon_get_pll_use_mask(crtc);
+                if (!(pll_in_use & (1 << ATOM_PPLL0)))
                         return ATOM_PPLL0;
-                return ATOM_PPLL1;
+                if (!(pll_in_use & (1 << ATOM_PPLL1)))
+                        return ATOM_PPLL1;
+                DRM_ERROR("unable to allocate a PPLL\n");
+                return ATOM_PPLL_INVALID;
         } else if (ASIC_IS_DCE4(rdev)) {
                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
                                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
                                  * depending on the asic:
                                  * DCE4: PPLL or ext clock
-                                 * DCE5: DCPLL or ext clock
+                                 * DCE5: PPLL, DCPLL, or ext clock
+                                 * DCE6: PPLL, PPLL0, or ext clock
                                  *
                                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
                                  * PPLL/DCPLL programming and only program the DP DTO for the
@@ -1549,31 +1623,34 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
                                  */
                                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
                                         if (rdev->clock.dp_extclk)
+                                                /* skip PPLL programming if using ext clock */
                                                 return ATOM_PPLL_INVALID;
                                         else if (ASIC_IS_DCE6(rdev))
+                                                /* use PPLL0 for all DP */
                                                 return ATOM_PPLL0;
                                         else if (ASIC_IS_DCE5(rdev))
+                                                /* use DCPLL for all DP */
                                                 return ATOM_DCPLL;
+                                        else {
+                                                /* use the same PPLL for all DP monitors */
+                                                pll = radeon_get_shared_dp_ppll(crtc);
+                                                if (pll != ATOM_PPLL_INVALID)
+                                                        return pll;
+                                        }
                                 }
+                                break;
                         }
                 }
-
-                /* otherwise, pick one of the plls */
-                list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
-                        struct radeon_crtc *radeon_test_crtc;
-
-                        if (crtc == test_crtc)
-                                continue;
-
-                        radeon_test_crtc = to_radeon_crtc(test_crtc);
-                        if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
-                            (radeon_test_crtc->pll_id <= ATOM_PPLL2))
-                                pll_in_use |= (1 << radeon_test_crtc->pll_id);
-                }
-                if (!(pll_in_use & 1))
+                /* all other cases */
+                pll_in_use = radeon_get_pll_use_mask(crtc);
+                if (!(pll_in_use & (1 << ATOM_PPLL2)))
+                        return ATOM_PPLL2;
+                if (!(pll_in_use & (1 << ATOM_PPLL1)))
                         return ATOM_PPLL1;
-                return ATOM_PPLL2;
+                DRM_ERROR("unable to allocate a PPLL\n");
+                return ATOM_PPLL_INVALID;
         } else
+                /* use PPLL1 or PPLL2 */
                 return radeon_crtc->crtc_id;
 
 }
@@ -1682,9 +1759,22 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
         struct drm_device *dev = crtc->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_atom_ss ss;
+        int i;
 
         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 
+        for (i = 0; i < rdev->num_crtc; i++) {
+                if (rdev->mode_info.crtcs[i] &&
+                    rdev->mode_info.crtcs[i]->enabled &&
+                    i != radeon_crtc->crtc_id &&
+                    radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
+                        /* one other crtc is using this pll don't turn
+                         * off the pll
+                         */
+                        goto done;
+                }
+        }
+
         switch (radeon_crtc->pll_id) {
         case ATOM_PPLL1:
         case ATOM_PPLL2:
@@ -1701,7 +1791,8 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
         default:
                 break;
         }
-        radeon_crtc->pll_id = -1;
+done:
+        radeon_crtc->pll_id = ATOM_PPLL_INVALID;
 }
 
 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
@@ -1750,6 +1841,6 @@ void radeon_atombios_init_crtc(struct drm_device *dev,
                 else
                         radeon_crtc->crtc_offset = 0;
         }
-        radeon_crtc->pll_id = -1;
+        radeon_crtc->pll_id = ATOM_PPLL_INVALID;
         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
 }
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 7712cf5ab33b..3623b98ed3fe 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -577,30 +577,25 @@ int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
         int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+        u16 dp_bridge = radeon_connector_encoder_get_dp_bridge_encoder_id(connector);
+        u8 tmp;
 
         if (!ASIC_IS_DCE4(rdev))
                 return panel_mode;
 
-        if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
-            ENCODER_OBJECT_ID_NUTMEG)
-                panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
-        else if (radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
-                 ENCODER_OBJECT_ID_TRAVIS) {
-                u8 id[6];
-                int i;
-                for (i = 0; i < 6; i++)
-                        id[i] = radeon_read_dpcd_reg(radeon_connector, 0x503 + i);
-                if (id[0] == 0x73 &&
-                    id[1] == 0x69 &&
-                    id[2] == 0x76 &&
-                    id[3] == 0x61 &&
-                    id[4] == 0x72 &&
-                    id[5] == 0x54)
+        if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
+                /* DP bridge chips */
+                tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
+                if (tmp & 1)
+                        panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+                else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
+                         (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
                         panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
                 else
-                        panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
+                        panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
         } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
-                u8 tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
+                /* eDP */
+                tmp = radeon_read_dpcd_reg(radeon_connector, DP_EDP_CONFIGURATION_CAP);
                 if (tmp & 1)
                         panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
         }
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index f9bc27fe269a..6e8803a1170c 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -1379,6 +1379,8 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
         struct drm_device *dev = encoder->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+        struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
+        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
         struct radeon_connector *radeon_connector = NULL;
         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
@@ -1390,19 +1392,37 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
 
         switch (mode) {
         case DRM_MODE_DPMS_ON:
-                /* some early dce3.2 boards have a bug in their transmitter control table */
-                if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) ||
-                    ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
-                        if (ASIC_IS_DCE6(rdev)) {
-                                /* It seems we need to call ATOM_ENCODER_CMD_SETUP again
-                                 * before reenabling encoder on DPMS ON, otherwise we never
-                                 * get picture
-                                 */
-                                atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
+                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
+                        if (!connector)
+                                dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+                        else
+                                dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
+
+                        /* setup and enable the encoder */
+                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
+                        atombios_dig_encoder_setup(encoder,
+                                                   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
+                                                   dig->panel_mode);
+                        if (ext_encoder) {
+                                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
+                                        atombios_external_encoder_setup(encoder, ext_encoder,
+                                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
                         }
                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
-                } else {
+                } else if (ASIC_IS_DCE4(rdev)) {
+                        /* setup and enable the encoder */
+                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
+                        /* enable the transmitter */
+                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
+                } else {
+                        /* setup and enable the encoder and transmitter */
+                        atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
+                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
+                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
+                        /* some early dce3.2 boards have a bug in their transmitter control table */
+                        if ((rdev->family != CHIP_RV710) || (rdev->family != CHIP_RV730))
+                                atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
                 }
                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
@@ -1420,10 +1440,19 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
         case DRM_MODE_DPMS_STANDBY:
         case DRM_MODE_DPMS_SUSPEND:
         case DRM_MODE_DPMS_OFF:
-                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
+                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
+                        /* disable the transmitter */
                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-                else
+                } else if (ASIC_IS_DCE4(rdev)) {
+                        /* disable the transmitter */
+                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
+                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
+                } else {
+                        /* disable the encoder and transmitter */
                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
+                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
+                        atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
+                }
                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
                         if (ASIC_IS_DCE4(rdev))
                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
@@ -1740,13 +1769,34 @@ static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct drm_encoder *test_encoder;
-        struct radeon_encoder_atom_dig *dig;
+        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
         uint32_t dig_enc_in_use = 0;
 
-        /* DCE4/5 */
-        if (ASIC_IS_DCE4(rdev)) {
-                dig = radeon_encoder->enc_priv;
-                if (ASIC_IS_DCE41(rdev)) {
+        if (ASIC_IS_DCE6(rdev)) {
+                /* DCE6 */
+                switch (radeon_encoder->encoder_id) {
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+                        if (dig->linkb)
+                                return 1;
+                        else
+                                return 0;
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+                        if (dig->linkb)
+                                return 3;
+                        else
+                                return 2;
+                        break;
+                case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+                        if (dig->linkb)
+                                return 5;
+                        else
+                                return 4;
+                        break;
+                }
+        } else if (ASIC_IS_DCE4(rdev)) {
+                /* DCE4/5 */
+                if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
                         /* ontario follows DCE4 */
                         if (rdev->family == CHIP_PALM) {
                                 if (dig->linkb)
@@ -1848,10 +1898,12 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
         struct drm_device *dev = encoder->dev;
         struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
-        struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
 
         radeon_encoder->pixel_clock = adjusted_mode->clock;
 
+        /* need to call this here rather than in prepare() since we need some crtc info */
+        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
+
         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
                         atombios_yuv_setup(encoder, true);
@@ -1870,38 +1922,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
-                        struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
-                        struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
-
-                        if (!connector)
-                                dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
-                        else
-                                dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
-
-                        /* setup and enable the encoder */
-                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
-                        atombios_dig_encoder_setup(encoder,
-                                                   ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
-                                                   dig->panel_mode);
-                } else if (ASIC_IS_DCE4(rdev)) {
-                        /* disable the transmitter */
-                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-                        /* setup and enable the encoder */
-                        atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
-
-                        /* enable the transmitter */
-                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
-                } else {
-                        /* disable the encoder and transmitter */
-                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-                        atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
-
-                        /* setup and enable the encoder and transmitter */
-                        atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
-                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
-                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
-                }
+                /* handled in dpms */
                 break;
         case ENCODER_OBJECT_ID_INTERNAL_DDI:
         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
@@ -1922,14 +1943,6 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
                 break;
         }
 
-        if (ext_encoder) {
-                if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
-                        atombios_external_encoder_setup(encoder, ext_encoder,
-                                                        EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
-                else
-                        atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
-        }
-
         atombios_apply_encoder_quirks(encoder, adjusted_mode);
 
         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
@@ -2116,7 +2129,6 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
         }
 
         radeon_atom_output_lock(encoder, true);
-        radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
 
         if (connector) {
                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -2137,6 +2149,7 @@ static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
 
 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
 {
+        /* need to call this here as we need the crtc set up */
         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
         radeon_atom_output_lock(encoder, false);
 }
@@ -2177,14 +2190,7 @@ static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
-                if (ASIC_IS_DCE4(rdev))
-                        /* disable the transmitter */
-                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-                else {
-                        /* disable the encoder and transmitter */
-                        atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
-                        atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
-                }
+                /* handled in dpms */
                 break;
         case ENCODER_OBJECT_ID_INTERNAL_DDI:
         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index ab74e6b149e7..f37676d7f217 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -63,6 +63,7 @@ struct r600_cs_track {
         u32                     cb_color_size_idx[8]; /* unused */
         u32                     cb_target_mask;
         u32                     cb_shader_mask;  /* unused */
+        bool                    is_resolve;
         u32                     cb_color_size[8];
         u32                     vgt_strmout_en;
         u32                     vgt_strmout_buffer_en;
@@ -315,7 +316,15 @@ static void r600_cs_track_init(struct r600_cs_track *track)
                 track->cb_color_bo[i] = NULL;
                 track->cb_color_bo_offset[i] = 0xFFFFFFFF;
                 track->cb_color_bo_mc[i] = 0xFFFFFFFF;
-        }
+                track->cb_color_frag_bo[i] = NULL;
+                track->cb_color_frag_offset[i] = 0xFFFFFFFF;
+                track->cb_color_tile_bo[i] = NULL;
+                track->cb_color_tile_offset[i] = 0xFFFFFFFF;
+                track->cb_color_mask[i] = 0xFFFFFFFF;
+        }
+        track->is_resolve = false;
+        track->nsamples = 16;
+        track->log_nsamples = 4;
         track->cb_target_mask = 0xFFFFFFFF;
         track->cb_shader_mask = 0xFFFFFFFF;
         track->cb_dirty = true;
@@ -352,6 +361,8 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
         volatile u32 *ib = p->ib.ptr;
         unsigned array_mode;
         u32 format;
+        /* When resolve is used, the second colorbuffer has always 1 sample. */
+        unsigned nsamples = track->is_resolve && i == 1 ? 1 : track->nsamples;
 
         size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
         format = G_0280A0_FORMAT(track->cb_color_info[i]);
@@ -375,7 +386,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
         array_check.group_size = track->group_size;
         array_check.nbanks = track->nbanks;
         array_check.npipes = track->npipes;
-        array_check.nsamples = track->nsamples;
+        array_check.nsamples = nsamples;
         array_check.blocksize = r600_fmt_get_blocksize(format);
         if (r600_get_array_mode_alignment(&array_check,
                                           &pitch_align, &height_align, &depth_align, &base_align)) {
@@ -421,7 +432,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
 
         /* check offset */
         tmp = r600_fmt_get_nblocksy(format, height) * r600_fmt_get_nblocksx(format, pitch) *
-              r600_fmt_get_blocksize(format) * track->nsamples;
+              r600_fmt_get_blocksize(format) * nsamples;
         switch (array_mode) {
         default:
         case V_0280A0_ARRAY_LINEAR_GENERAL:
@@ -792,6 +803,12 @@ static int r600_cs_track_check(struct radeon_cs_parser *p)
          */
         if (track->cb_dirty) {
                 tmp = track->cb_target_mask;
+
+                /* We must check both colorbuffers for RESOLVE. */
+                if (track->is_resolve) {
+                        tmp |= 0xff;
+                }
+
                 for (i = 0; i < 8; i++) {
                         if ((tmp >> (i * 4)) & 0xF) {
                                 /* at least one component is enabled */
@@ -1281,6 +1298,11 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
                 track->nsamples = 1 << tmp;
                 track->cb_dirty = true;
                 break;
+        case R_028808_CB_COLOR_CONTROL:
+                tmp = G_028808_SPECIAL_OP(radeon_get_ib_value(p, idx));
+                track->is_resolve = tmp == V_028808_SPECIAL_RESOLVE_BOX;
+                track->cb_dirty = true;
+                break;
         case R_0280A0_CB_COLOR0_INFO:
         case R_0280A4_CB_COLOR1_INFO:
         case R_0280A8_CB_COLOR2_INFO:
@@ -1416,7 +1438,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
         case R_028118_CB_COLOR6_MASK:
         case R_02811C_CB_COLOR7_MASK:
                 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
-                track->cb_color_mask[tmp] = ib[idx];
+                track->cb_color_mask[tmp] = radeon_get_ib_value(p, idx);
                 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
                         track->cb_dirty = true;
                 }
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index bdb69a63062f..fa6f37099ba9 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -66,6 +66,14 @@
 #define CC_RB_BACKEND_DISABLE                           0x98F4
 #define         BACKEND_DISABLE(x)                              ((x) << 16)
 
+#define R_028808_CB_COLOR_CONTROL                       0x28808
+#define   S_028808_SPECIAL_OP(x)                       (((x) & 0x7) << 4)
+#define   G_028808_SPECIAL_OP(x)                       (((x) >> 4) & 0x7)
+#define   C_028808_SPECIAL_OP                          0xFFFFFF8F
+#define     V_028808_SPECIAL_NORMAL                     0x00
+#define     V_028808_SPECIAL_DISABLE                    0x01
+#define     V_028808_SPECIAL_RESOLVE_BOX                0x07
+
 #define CB_COLOR0_BASE                                  0x28040
 #define CB_COLOR1_BASE                                  0x28044
 #define CB_COLOR2_BASE                                  0x28048
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index d2e243867ac6..7a3daebd732d 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1051,7 +1051,7 @@ int radeon_device_init(struct radeon_device *rdev,
         if (rdev->flags & RADEON_IS_AGP)
                 rdev->need_dma32 = true;
         if ((rdev->flags & RADEON_IS_PCI) &&
-            (rdev->family < CHIP_RS400))
+            (rdev->family <= CHIP_RS740))
                 rdev->need_dma32 = true;
 
         dma_bits = rdev->need_dma32 ? 32 : 40;
@@ -1346,12 +1346,15 @@ retry:
                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
                         radeon_ring_restore(rdev, &rdev->ring[i],
                                             ring_sizes[i], ring_data[i]);
+                        ring_sizes[i] = 0;
+                        ring_data[i] = NULL;
                 }
 
                 r = radeon_ib_ring_tests(rdev);
                 if (r) {
                         dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
                         if (saved) {
+                                saved = false;
                                 radeon_suspend(rdev);
                                 goto retry;
                         }
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 27d22d709c90..8c593ea82c41 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -63,9 +63,10 @@
  *   2.19.0 - r600-eg: MSAA textures
  *   2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
  *   2.21.0 - r600-r700: FMASK and CMASK
+ *   2.22.0 - r600 only: RESOLVE_BOX allowed
  */
 #define KMS_DRIVER_MAJOR        2
-#define KMS_DRIVER_MINOR        21
+#define KMS_DRIVER_MINOR        22
 #define KMS_DRIVER_PATCHLEVEL   0
 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
 int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 7b737b9339ad..2a59375dbe52 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -131,7 +131,7 @@ int radeon_fence_emit(struct radeon_device *rdev,
  */
 void radeon_fence_process(struct radeon_device *rdev, int ring)
 {
-        uint64_t seq, last_seq;
+        uint64_t seq, last_seq, last_emitted;
         unsigned count_loop = 0;
         bool wake = false;
 
@@ -158,13 +158,15 @@ void radeon_fence_process(struct radeon_device *rdev, int ring)
          */
         last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
         do {
+                last_emitted = rdev->fence_drv[ring].sync_seq[ring];
                 seq = radeon_fence_read(rdev, ring);
                 seq |= last_seq & 0xffffffff00000000LL;
                 if (seq < last_seq) {
-                        seq += 0x100000000LL;
+                        seq &= 0xffffffff;
+                        seq |= last_emitted & 0xffffffff00000000LL;
                 }
 
-                if (seq == last_seq) {
+                if (seq <= last_seq || seq > last_emitted) {
                         break;
                 }
                 /* If we loop over we don't want to return without
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index f93e45d869f4..20bfbda7b3f1 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -744,7 +744,6 @@ r600 0x9400
 0x00028C38 CB_CLRCMP_DST
 0x00028C3C CB_CLRCMP_MSK
 0x00028C34 CB_CLRCMP_SRC
-0x00028808 CB_COLOR_CONTROL
 0x0002842C CB_FOG_BLUE
 0x00028428 CB_FOG_GREEN
 0x00028424 CB_FOG_RED