1 files changed, 76 insertions, 37 deletions

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index d883cae56378..f79633a036c3 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -1806,13 +1806,14 @@ void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
 #endif
                           (ib->gpu_addr & 0xFFFFFFFC));
         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
-        radeon_ring_write(ring, ib->length_dw | (ib->vm_id << 24));
+        radeon_ring_write(ring, ib->length_dw |
+                          (ib->vm ? (ib->vm->id << 24) : 0));
 
         if (!ib->is_const_ib) {
                 /* flush read cache over gart for this vmid */
                 radeon_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
                 radeon_ring_write(ring, (CP_COHER_CNTL2 - PACKET3_SET_CONFIG_REG_START) >> 2);
-                radeon_ring_write(ring, ib->vm_id);
+                radeon_ring_write(ring, ib->vm ? ib->vm->id : 0);
                 radeon_ring_write(ring, PACKET3(PACKET3_SURFACE_SYNC, 3));
                 radeon_ring_write(ring, PACKET3_TCL1_ACTION_ENA |
                                   PACKET3_TC_ACTION_ENA |
@@ -2363,7 +2364,7 @@ void si_pcie_gart_tlb_flush(struct radeon_device *rdev)
         WREG32(VM_INVALIDATE_REQUEST, 1);
 }
 
-int si_pcie_gart_enable(struct radeon_device *rdev)
+static int si_pcie_gart_enable(struct radeon_device *rdev)
 {
         int r, i;
 
@@ -2425,7 +2426,7 @@ int si_pcie_gart_enable(struct radeon_device *rdev)
         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
                (u32)(rdev->dummy_page.addr >> 12));
         WREG32(VM_CONTEXT1_CNTL2, 0);
-        WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
+        WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 
         si_pcie_gart_tlb_flush(rdev);
@@ -2436,7 +2437,7 @@ int si_pcie_gart_enable(struct radeon_device *rdev)
         return 0;
 }
 
-void si_pcie_gart_disable(struct radeon_device *rdev)
+static void si_pcie_gart_disable(struct radeon_device *rdev)
 {
         /* Disable all tables */
         WREG32(VM_CONTEXT0_CNTL, 0);
@@ -2455,7 +2456,7 @@ void si_pcie_gart_disable(struct radeon_device *rdev)
         radeon_gart_table_vram_unpin(rdev);
 }
 
-void si_pcie_gart_fini(struct radeon_device *rdev)
+static void si_pcie_gart_fini(struct radeon_device *rdev)
 {
         si_pcie_gart_disable(rdev);
         radeon_gart_table_vram_free(rdev);
@@ -2788,41 +2789,84 @@ void si_vm_fini(struct radeon_device *rdev)
 {
 }
 
-int si_vm_bind(struct radeon_device *rdev, struct radeon_vm *vm, int id)
+/**
+ * si_vm_set_page - update the page tables using the CP
+ *
+ * @rdev: radeon_device pointer
+ * @pe: addr of the page entry
+ * @addr: dst addr to write into pe
+ * @count: number of page entries to update
+ * @incr: increase next addr by incr bytes
+ * @flags: access flags
+ *
+ * Update the page tables using the CP (cayman-si).
+ */
+void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
+                    uint64_t addr, unsigned count,
+                    uint32_t incr, uint32_t flags)
 {
-        if (id < 8)
-                WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (id << 2), vm->pt_gpu_addr >> 12);
-        else
-                WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((id - 8) << 2),
-                       vm->pt_gpu_addr >> 12);
-        /* flush hdp cache */
-        WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
-        /* bits 0-15 are the VM contexts0-15 */
-        WREG32(VM_INVALIDATE_REQUEST, 1 << id);
-        return 0;
+        struct radeon_ring *ring = &rdev->ring[rdev->asic->vm.pt_ring_index];
+        uint32_t r600_flags = cayman_vm_page_flags(rdev, flags);
+        int i;
+        uint64_t value;
+
+        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 2 + count * 2));
+        radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+                                 WRITE_DATA_DST_SEL(1)));
+        radeon_ring_write(ring, pe);
+        radeon_ring_write(ring, upper_32_bits(pe));
+        for (i = 0; i < count; ++i) {
+                if (flags & RADEON_VM_PAGE_SYSTEM) {
+                        value = radeon_vm_map_gart(rdev, addr);
+                        value &= 0xFFFFFFFFFFFFF000ULL;
+                } else if (flags & RADEON_VM_PAGE_VALID)
+                        value = addr;
+                else
+                        value = 0;
+                addr += incr;
+                value |= r600_flags;
+                radeon_ring_write(ring, value);
+                radeon_ring_write(ring, upper_32_bits(value));
+        }
 }
 
-void si_vm_unbind(struct radeon_device *rdev, struct radeon_vm *vm)
+void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
 {
-        if (vm->id < 8)
-                WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2), 0);
-        else
-                WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2), 0);
-        /* flush hdp cache */
-        WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
-        /* bits 0-15 are the VM contexts0-15 */
-        WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
-}
+        struct radeon_ring *ring = &rdev->ring[ridx];
 
-void si_vm_tlb_flush(struct radeon_device *rdev, struct radeon_vm *vm)
-{
-        if (vm->id == -1)
+        if (vm == NULL)
                 return;
 
+        /* write new base address */
+        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+        radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+                                 WRITE_DATA_DST_SEL(0)));
+
+        if (vm->id < 8) {
+                radeon_ring_write(ring,
+                                  (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
+        } else {
+                radeon_ring_write(ring,
+                                  (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
+        }
+        radeon_ring_write(ring, 0);
+        radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
+
         /* flush hdp cache */
-        WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
+        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+        radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+                                 WRITE_DATA_DST_SEL(0)));
+        radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
+        radeon_ring_write(ring, 0);
+        radeon_ring_write(ring, 0x1);
+
         /* bits 0-15 are the VM contexts0-15 */
-        WREG32(VM_INVALIDATE_REQUEST, 1 << vm->id);
+        radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+        radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
+                                 WRITE_DATA_DST_SEL(0)));
+        radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
+        radeon_ring_write(ring, 0);
+        radeon_ring_write(ring, 1 << vm->id);
 }
 
 /*
@@ -3199,10 +3243,6 @@ int si_irq_set(struct radeon_device *rdev)
                 DRM_DEBUG("si_irq_set: hpd 6\n");
                 hpd6 |= DC_HPDx_INT_EN;
         }
-        if (rdev->irq.gui_idle) {
-                DRM_DEBUG("gui idle\n");
-                grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
-        }
 
         WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
         WREG32(CP_INT_CNTL_RING1, cp_int_cntl1);
@@ -3658,7 +3698,6 @@ restart_ih:
                         break;
                 case 233: /* GUI IDLE */
                         DRM_DEBUG("IH: GUI idle\n");
-                        wake_up(&rdev->irq.idle_queue);
                         break;
                 default:
                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);