aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/radeon_atombios.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_atombios.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_atombios.c126
1 files changed, 86 insertions, 40 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
index 08d0b94332e6..fecd705a1a5f 100644
--- a/drivers/gpu/drm/radeon/radeon_atombios.c
+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
@@ -85,6 +85,18 @@ static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rd
85 for (i = 0; i < num_indices; i++) { 85 for (i = 0; i < num_indices; i++) {
86 gpio = &i2c_info->asGPIO_Info[i]; 86 gpio = &i2c_info->asGPIO_Info[i];
87 87
88 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
89 if ((rdev->family == CHIP_R420) ||
90 (rdev->family == CHIP_R423) ||
91 (rdev->family == CHIP_RV410)) {
92 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
93 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
94 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
95 gpio->ucClkMaskShift = 0x19;
96 gpio->ucDataMaskShift = 0x18;
97 }
98 }
99
88 /* some evergreen boards have bad data for this entry */ 100 /* some evergreen boards have bad data for this entry */
89 if (ASIC_IS_DCE4(rdev)) { 101 if (ASIC_IS_DCE4(rdev)) {
90 if ((i == 7) && 102 if ((i == 7) &&
@@ -1996,10 +2008,14 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
1996 return state_index; 2008 return state_index;
1997 /* last mode is usually default, array is low to high */ 2009 /* last mode is usually default, array is low to high */
1998 for (i = 0; i < num_modes; i++) { 2010 for (i = 0; i < num_modes; i++) {
2011 rdev->pm.power_state[state_index].clock_info =
2012 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2013 if (!rdev->pm.power_state[state_index].clock_info)
2014 return state_index;
2015 rdev->pm.power_state[state_index].num_clock_modes = 1;
1999 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2016 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2000 switch (frev) { 2017 switch (frev) {
2001 case 1: 2018 case 1:
2002 rdev->pm.power_state[state_index].num_clock_modes = 1;
2003 rdev->pm.power_state[state_index].clock_info[0].mclk = 2019 rdev->pm.power_state[state_index].clock_info[0].mclk =
2004 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock); 2020 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2005 rdev->pm.power_state[state_index].clock_info[0].sclk = 2021 rdev->pm.power_state[state_index].clock_info[0].sclk =
@@ -2035,7 +2051,6 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2035 state_index++; 2051 state_index++;
2036 break; 2052 break;
2037 case 2: 2053 case 2:
2038 rdev->pm.power_state[state_index].num_clock_modes = 1;
2039 rdev->pm.power_state[state_index].clock_info[0].mclk = 2054 rdev->pm.power_state[state_index].clock_info[0].mclk =
2040 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock); 2055 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2041 rdev->pm.power_state[state_index].clock_info[0].sclk = 2056 rdev->pm.power_state[state_index].clock_info[0].sclk =
@@ -2072,7 +2087,6 @@ static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2072 state_index++; 2087 state_index++;
2073 break; 2088 break;
2074 case 3: 2089 case 3:
2075 rdev->pm.power_state[state_index].num_clock_modes = 1;
2076 rdev->pm.power_state[state_index].clock_info[0].mclk = 2090 rdev->pm.power_state[state_index].clock_info[0].mclk =
2077 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock); 2091 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2078 rdev->pm.power_state[state_index].clock_info[0].sclk = 2092 rdev->pm.power_state[state_index].clock_info[0].sclk =
@@ -2257,7 +2271,7 @@ static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rde
2257 rdev->pm.default_power_state_index = state_index; 2271 rdev->pm.default_power_state_index = state_index;
2258 rdev->pm.power_state[state_index].default_clock_mode = 2272 rdev->pm.power_state[state_index].default_clock_mode =
2259 &rdev->pm.power_state[state_index].clock_info[mode_index - 1]; 2273 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2260 if (ASIC_IS_DCE5(rdev)) { 2274 if (ASIC_IS_DCE5(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2261 /* NI chips post without MC ucode, so default clocks are strobe mode only */ 2275 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2262 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk; 2276 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2263 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk; 2277 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
@@ -2377,17 +2391,31 @@ static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2377 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) + 2391 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2378 (power_state->v1.ucNonClockStateIndex * 2392 (power_state->v1.ucNonClockStateIndex *
2379 power_info->pplib.ucNonClockSize)); 2393 power_info->pplib.ucNonClockSize));
2380 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) { 2394 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2381 clock_info = (union pplib_clock_info *) 2395 ((power_info->pplib.ucStateEntrySize - 1) ?
2382 (mode_info->atom_context->bios + data_offset + 2396 (power_info->pplib.ucStateEntrySize - 1) : 1),
2383 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) + 2397 GFP_KERNEL);
2384 (power_state->v1.ucClockStateIndices[j] * 2398 if (!rdev->pm.power_state[i].clock_info)
2385 power_info->pplib.ucClockInfoSize)); 2399 return state_index;
2386 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2400 if (power_info->pplib.ucStateEntrySize - 1) {
2387 state_index, mode_index, 2401 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2388 clock_info); 2402 clock_info = (union pplib_clock_info *)
2389 if (valid) 2403 (mode_info->atom_context->bios + data_offset +
2390 mode_index++; 2404 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2405 (power_state->v1.ucClockStateIndices[j] *
2406 power_info->pplib.ucClockInfoSize));
2407 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2408 state_index, mode_index,
2409 clock_info);
2410 if (valid)
2411 mode_index++;
2412 }
2413 } else {
2414 rdev->pm.power_state[state_index].clock_info[0].mclk =
2415 rdev->clock.default_mclk;
2416 rdev->pm.power_state[state_index].clock_info[0].sclk =
2417 rdev->clock.default_sclk;
2418 mode_index++;
2391 } 2419 }
2392 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2420 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2393 if (mode_index) { 2421 if (mode_index) {
@@ -2456,18 +2484,32 @@ static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2456 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */ 2484 non_clock_array_index = i; /* power_state->v2.nonClockInfoIndex */
2457 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 2485 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2458 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 2486 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2459 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 2487 rdev->pm.power_state[i].clock_info = kzalloc(sizeof(struct radeon_pm_clock_info) *
2460 clock_array_index = power_state->v2.clockInfoIndex[j]; 2488 (power_state->v2.ucNumDPMLevels ?
2461 /* XXX this might be an inagua bug... */ 2489 power_state->v2.ucNumDPMLevels : 1),
2462 if (clock_array_index >= clock_info_array->ucNumEntries) 2490 GFP_KERNEL);
2463 continue; 2491 if (!rdev->pm.power_state[i].clock_info)
2464 clock_info = (union pplib_clock_info *) 2492 return state_index;
2465 &clock_info_array->clockInfo[clock_array_index]; 2493 if (power_state->v2.ucNumDPMLevels) {
2466 valid = radeon_atombios_parse_pplib_clock_info(rdev, 2494 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2467 state_index, mode_index, 2495 clock_array_index = power_state->v2.clockInfoIndex[j];
2468 clock_info); 2496 /* XXX this might be an inagua bug... */
2469 if (valid) 2497 if (clock_array_index >= clock_info_array->ucNumEntries)
2470 mode_index++; 2498 continue;
2499 clock_info = (union pplib_clock_info *)
2500 &clock_info_array->clockInfo[clock_array_index];
2501 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2502 state_index, mode_index,
2503 clock_info);
2504 if (valid)
2505 mode_index++;
2506 }
2507 } else {
2508 rdev->pm.power_state[state_index].clock_info[0].mclk =
2509 rdev->clock.default_mclk;
2510 rdev->pm.power_state[state_index].clock_info[0].sclk =
2511 rdev->clock.default_sclk;
2512 mode_index++;
2471 } 2513 }
2472 rdev->pm.power_state[state_index].num_clock_modes = mode_index; 2514 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2473 if (mode_index) { 2515 if (mode_index) {
@@ -2524,19 +2566,23 @@ void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2524 } else { 2566 } else {
2525 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL); 2567 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2526 if (rdev->pm.power_state) { 2568 if (rdev->pm.power_state) {
2527 /* add the default mode */ 2569 rdev->pm.power_state[0].clock_info =
2528 rdev->pm.power_state[state_index].type = 2570 kzalloc(sizeof(struct radeon_pm_clock_info) * 1, GFP_KERNEL);
2529 POWER_STATE_TYPE_DEFAULT; 2571 if (rdev->pm.power_state[0].clock_info) {
2530 rdev->pm.power_state[state_index].num_clock_modes = 1; 2572 /* add the default mode */
2531 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2573 rdev->pm.power_state[state_index].type =
2532 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2574 POWER_STATE_TYPE_DEFAULT;
2533 rdev->pm.power_state[state_index].default_clock_mode = 2575 rdev->pm.power_state[state_index].num_clock_modes = 1;
2534 &rdev->pm.power_state[state_index].clock_info[0]; 2576 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2535 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2577 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2536 rdev->pm.power_state[state_index].pcie_lanes = 16; 2578 rdev->pm.power_state[state_index].default_clock_mode =
2537 rdev->pm.default_power_state_index = state_index; 2579 &rdev->pm.power_state[state_index].clock_info[0];
2538 rdev->pm.power_state[state_index].flags = 0; 2580 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2539 state_index++; 2581 rdev->pm.power_state[state_index].pcie_lanes = 16;
2582 rdev->pm.default_power_state_index = state_index;
2583 rdev->pm.power_state[state_index].flags = 0;
2584 state_index++;
2585 }
2540 } 2586 }
2541 } 2587 }
2542 2588
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-07 13:20:46 -0500