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path: root/drivers/gpu/drm/radeon/r600_blit_kms.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r600_blit_kms.c')
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c13
1 files changed, 2 insertions, 11 deletions
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index 446b765ac72a..de8bbbcfe117 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -403,8 +403,6 @@ set_default_state(struct radeon_device *rdev)
403 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); 403 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF);
404 radeon_ring_write(rdev, dwords); 404 radeon_ring_write(rdev, dwords);
405 405
406 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
407 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
408 /* SQ config */ 406 /* SQ config */
409 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); 407 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6));
410 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 408 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
@@ -578,9 +576,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
578 ring_size = num_loops * dwords_per_loop; 576 ring_size = num_loops * dwords_per_loop;
579 /* set default + shaders */ 577 /* set default + shaders */
580 ring_size += 40; /* shaders + def state */ 578 ring_size += 40; /* shaders + def state */
581 ring_size += 7; /* fence emit for VB IB */ 579 ring_size += 10; /* fence emit for VB IB */
582 ring_size += 5; /* done copy */ 580 ring_size += 5; /* done copy */
583 ring_size += 7; /* fence emit for done copy */ 581 ring_size += 10; /* fence emit for done copy */
584 r = radeon_ring_lock(rdev, ring_size); 582 r = radeon_ring_lock(rdev, ring_size);
585 if (r) 583 if (r)
586 return r; 584 return r;
@@ -594,13 +592,6 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
594{ 592{
595 int r; 593 int r;
596 594
597 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
598 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
599 /* wait for 3D idle clean */
600 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
601 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
602 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
603
604 if (rdev->r600_blit.vb_ib) 595 if (rdev->r600_blit.vb_ib)
605 r600_vb_ib_put(rdev); 596 r600_vb_ib_put(rdev);
606 597