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path: root/drivers/gpu/drm/nouveau/nvc0_graph.fuc
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Diffstat (limited to 'drivers/gpu/drm/nouveau/nvc0_graph.fuc')
-rw-r--r--drivers/gpu/drm/nouveau/nvc0_graph.fuc56
1 files changed, 28 insertions, 28 deletions
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.fuc b/drivers/gpu/drm/nouveau/nvc0_graph.fuc
index 2a4b6dc8f9de..e6b228844a32 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.fuc
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.fuc
@@ -71,9 +71,9 @@ queue_put:
71 ld b32 $r9 D[$r13 + 0x4] // PUT 71 ld b32 $r9 D[$r13 + 0x4] // PUT
72 xor $r8 8 72 xor $r8 8
73 cmpu b32 $r8 $r9 73 cmpu b32 $r8 $r9
74 bra ne queue_put_next 74 bra ne #queue_put_next
75 mov $r15 E_CMD_OVERFLOW 75 mov $r15 E_CMD_OVERFLOW
76 call error 76 call #error
77 ret 77 ret
78 78
79 // store cmd/data on queue 79 // store cmd/data on queue
@@ -104,7 +104,7 @@ queue_get:
104 ld b32 $r8 D[$r13 + 0x0] // GET 104 ld b32 $r8 D[$r13 + 0x0] // GET
105 ld b32 $r9 D[$r13 + 0x4] // PUT 105 ld b32 $r9 D[$r13 + 0x4] // PUT
106 cmpu b32 $r8 $r9 106 cmpu b32 $r8 $r9
107 bra e queue_get_done 107 bra e #queue_get_done
108 // fetch first cmd/data pair 108 // fetch first cmd/data pair
109 and $r9 $r8 7 109 and $r9 $r8 7
110 shl b32 $r9 3 110 shl b32 $r9 3
@@ -135,9 +135,9 @@ nv_rd32:
135 nv_rd32_wait: 135 nv_rd32_wait:
136 iord $r12 I[$r11 + 0x000] 136 iord $r12 I[$r11 + 0x000]
137 xbit $r12 $r12 31 137 xbit $r12 $r12 31
138 bra ne nv_rd32_wait 138 bra ne #nv_rd32_wait
139 mov $r10 6 // DONE_MMIO_RD 139 mov $r10 6 // DONE_MMIO_RD
140 call wait_doneo 140 call #wait_doneo
141 iord $r15 I[$r11 + 0x100] // MMIO_RDVAL 141 iord $r15 I[$r11 + 0x100] // MMIO_RDVAL
142 ret 142 ret
143 143
@@ -157,7 +157,7 @@ nv_wr32:
157 nv_wr32_wait: 157 nv_wr32_wait:
158 iord $r12 I[$r11 + 0x000] 158 iord $r12 I[$r11 + 0x000]
159 xbit $r12 $r12 31 159 xbit $r12 $r12 31
160 bra ne nv_wr32_wait 160 bra ne #nv_wr32_wait
161 ret 161 ret
162 162
163// (re)set watchdog timer 163// (re)set watchdog timer
@@ -193,7 +193,7 @@ $1:
193 shl b32 $r8 6 193 shl b32 $r8 6
194 iord $r8 I[$r8 + 0x000] // DONE 194 iord $r8 I[$r8 + 0x000] // DONE
195 xbit $r8 $r8 $r10 195 xbit $r8 $r8 $r10
196 bra $2 wait_done_$1 196 bra $2 #wait_done_$1
197 trace_clr(T_WAIT) 197 trace_clr(T_WAIT)
198 ret 198 ret
199') 199')
@@ -216,7 +216,7 @@ mmctx_size:
216 add b32 $r9 $r8 216 add b32 $r9 $r8
217 add b32 $r14 4 217 add b32 $r14 4
218 cmpu b32 $r14 $r15 218 cmpu b32 $r14 $r15
219 bra ne nv_mmctx_size_loop 219 bra ne #nv_mmctx_size_loop
220 mov b32 $r15 $r9 220 mov b32 $r15 $r9
221 ret 221 ret
222 222
@@ -238,12 +238,12 @@ mmctx_xfer:
238 shl b32 $r8 6 238 shl b32 $r8 6
239 clear b32 $r9 239 clear b32 $r9
240 or $r11 $r11 240 or $r11 $r11
241 bra e mmctx_base_disabled 241 bra e #mmctx_base_disabled
242 iowr I[$r8 + 0x000] $r11 // MMCTX_BASE 242 iowr I[$r8 + 0x000] $r11 // MMCTX_BASE
243 bset $r9 0 // BASE_EN 243 bset $r9 0 // BASE_EN
244 mmctx_base_disabled: 244 mmctx_base_disabled:
245 or $r14 $r14 245 or $r14 $r14
246 bra e mmctx_multi_disabled 246 bra e #mmctx_multi_disabled
247 iowr I[$r8 + 0x200] $r14 // MMCTX_MULTI_STRIDE 247 iowr I[$r8 + 0x200] $r14 // MMCTX_MULTI_STRIDE
248 iowr I[$r8 + 0x300] $r15 // MMCTX_MULTI_MASK 248 iowr I[$r8 + 0x300] $r15 // MMCTX_MULTI_MASK
249 bset $r9 1 // MULTI_EN 249 bset $r9 1 // MULTI_EN
@@ -264,7 +264,7 @@ mmctx_xfer:
264 mmctx_wait_free: 264 mmctx_wait_free:
265 iord $r14 I[$r8 + 0x000] // MMCTX_CTRL 265 iord $r14 I[$r8 + 0x000] // MMCTX_CTRL
266 and $r14 0x1f 266 and $r14 0x1f
267 bra e mmctx_wait_free 267 bra e #mmctx_wait_free
268 268
269 // queue up an entry 269 // queue up an entry
270 ld b32 $r14 D[$r12] 270 ld b32 $r14 D[$r12]
@@ -272,19 +272,19 @@ mmctx_xfer:
272 iowr I[$r8 + 0x300] $r14 272 iowr I[$r8 + 0x300] $r14
273 add b32 $r12 4 273 add b32 $r12 4
274 cmpu b32 $r12 $r13 274 cmpu b32 $r12 $r13
275 bra ne mmctx_exec_loop 275 bra ne #mmctx_exec_loop
276 276
277 xbit $r11 $r10 2 277 xbit $r11 $r10 2
278 bra ne mmctx_stop 278 bra ne #mmctx_stop
279 // wait for queue to empty 279 // wait for queue to empty
280 mmctx_fini_wait: 280 mmctx_fini_wait:
281 iord $r11 I[$r8 + 0x000] // MMCTX_CTRL 281 iord $r11 I[$r8 + 0x000] // MMCTX_CTRL
282 and $r11 0x1f 282 and $r11 0x1f
283 cmpu b32 $r11 0x10 283 cmpu b32 $r11 0x10
284 bra ne mmctx_fini_wait 284 bra ne #mmctx_fini_wait
285 mov $r10 2 // DONE_MMCTX 285 mov $r10 2 // DONE_MMCTX
286 call wait_donez 286 call #wait_donez
287 bra mmctx_done 287 bra #mmctx_done
288 mmctx_stop: 288 mmctx_stop:
289 xbit $r11 $r10 0 289 xbit $r11 $r10 0
290 shl b32 $r11 16 // DIR 290 shl b32 $r11 16 // DIR
@@ -295,7 +295,7 @@ mmctx_xfer:
295 // wait for STOP_TRIGGER to clear 295 // wait for STOP_TRIGGER to clear
296 iord $r11 I[$r8 + 0x000] // MMCTX_CTRL 296 iord $r11 I[$r8 + 0x000] // MMCTX_CTRL
297 xbit $r11 $r11 18 297 xbit $r11 $r11 18
298 bra ne mmctx_stop_wait 298 bra ne #mmctx_stop_wait
299 mmctx_done: 299 mmctx_done:
300 trace_clr(T_MMCTX) 300 trace_clr(T_MMCTX)
301 ret 301 ret
@@ -305,7 +305,7 @@ mmctx_xfer:
305strand_wait: 305strand_wait:
306 push $r10 306 push $r10
307 mov $r10 2 307 mov $r10 2
308 call wait_donez 308 call #wait_donez
309 pop $r10 309 pop $r10
310 ret 310 ret
311 311
@@ -316,7 +316,7 @@ strand_pre:
316 sethi $r8 0x20000 316 sethi $r8 0x20000
317 mov $r9 0xc 317 mov $r9 0xc
318 iowr I[$r8] $r9 318 iowr I[$r8] $r9
319 call strand_wait 319 call #strand_wait
320 ret 320 ret
321 321
322// unknown - call after issuing strand commands 322// unknown - call after issuing strand commands
@@ -326,7 +326,7 @@ strand_post:
326 sethi $r8 0x20000 326 sethi $r8 0x20000
327 mov $r9 0xd 327 mov $r9 0xd
328 iowr I[$r8] $r9 328 iowr I[$r8] $r9
329 call strand_wait 329 call #strand_wait
330 ret 330 ret
331 331
332// Selects strand set?! 332// Selects strand set?!
@@ -341,11 +341,11 @@ strand_set:
341 iowr I[$r10 + 0x000] $r12 // 0x93c = 0xf 341 iowr I[$r10 + 0x000] $r12 // 0x93c = 0xf
342 mov $r12 0xb 342 mov $r12 0xb
343 iowr I[$r11 + 0x000] $r12 // 0x928 = 0xb 343 iowr I[$r11 + 0x000] $r12 // 0x928 = 0xb
344 call strand_wait 344 call #strand_wait
345 iowr I[$r10 + 0x000] $r14 // 0x93c = <id> 345 iowr I[$r10 + 0x000] $r14 // 0x93c = <id>
346 mov $r12 0xa 346 mov $r12 0xa
347 iowr I[$r11 + 0x000] $r12 // 0x928 = 0xa 347 iowr I[$r11 + 0x000] $r12 // 0x928 = 0xa
348 call strand_wait 348 call #strand_wait
349 ret 349 ret
350 350
351// Initialise strand context data 351// Initialise strand context data
@@ -357,22 +357,22 @@ strand_set:
357// 357//
358strand_ctx_init: 358strand_ctx_init:
359 trace_set(T_STRINIT) 359 trace_set(T_STRINIT)
360 call strand_pre 360 call #strand_pre
361 mov $r14 3 361 mov $r14 3
362 call strand_set 362 call #strand_set
363 mov $r10 0x46fc 363 mov $r10 0x46fc
364 sethi $r10 0x20000 364 sethi $r10 0x20000
365 add b32 $r11 $r10 0x400 365 add b32 $r11 $r10 0x400
366 iowr I[$r10 + 0x100] $r0 // STRAND_FIRST_GENE = 0 366 iowr I[$r10 + 0x100] $r0 // STRAND_FIRST_GENE = 0
367 mov $r12 1 367 mov $r12 1
368 iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_FIRST_GENE 368 iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_FIRST_GENE
369 call strand_wait 369 call #strand_wait
370 sub b32 $r12 $r0 1 370 sub b32 $r12 $r0 1
371 iowr I[$r10 + 0x000] $r12 // STRAND_GENE_CNT = 0xffffffff 371 iowr I[$r10 + 0x000] $r12 // STRAND_GENE_CNT = 0xffffffff
372 mov $r12 2 372 mov $r12 2
373 iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_GENE_CNT 373 iowr I[$r11 + 0x000] $r12 // STRAND_CMD = LATCH_GENE_CNT
374 call strand_wait 374 call #strand_wait
375 call strand_post 375 call #strand_post
376 376
377 // read the size of each strand, poke the context offset of 377 // read the size of each strand, poke the context offset of
378 // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry 378 // each into STRAND_{SAVE,LOAD}_SWBASE now, no need to worry
@@ -391,7 +391,7 @@ strand_ctx_init:
391 add b32 $r14 $r10 391 add b32 $r14 $r10
392 add b32 $r8 4 392 add b32 $r8 4
393 sub b32 $r9 1 393 sub b32 $r9 1
394 bra ne ctx_init_strand_loop 394 bra ne #ctx_init_strand_loop
395 395
396 shl b32 $r14 8 396 shl b32 $r14 8
397 sub b32 $r15 $r14 $r15 397 sub b32 $r15 $r14 $r15