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-rw-r--r--drivers/gpu/drm/i915/i915_drv.c31
-rw-r--r--drivers/gpu/drm/i915/i915_gem_context.c1
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c20
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c3
-rw-r--r--drivers/gpu/drm/i915/i915_sysfs.c12
-rw-r--r--drivers/gpu/drm/i915/intel_display.c12
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c14
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h20
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c10
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c15
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c6
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c48
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c5
13 files changed, 122 insertions, 75 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index ed22612bc847..a24ffbe97c01 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -346,11 +346,40 @@ static const struct pci_device_id pciidlist[] = { /* aka */
346 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ 346 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
347 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */ 347 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
348 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */ 348 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
349 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
349 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */ 350 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
350 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */ 351 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
352 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
351 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */ 353 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
352 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */ 354 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
353 INTEL_VGA_DEVICE(0x0c16, &intel_haswell_d_info), /* SDV */ 355 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
356 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
357 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
358 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
359 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
360 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
361 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
362 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
363 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
364 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
365 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
366 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
367 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
368 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
369 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
370 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
371 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
372 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
373 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
374 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT1 desktop */
375 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
376 INTEL_VGA_DEVICE(0x0D32, &intel_haswell_d_info), /* CRW GT2 desktop */
377 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT1 server */
378 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
379 INTEL_VGA_DEVICE(0x0D3A, &intel_haswell_d_info), /* CRW GT2 server */
380 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT1 mobile */
381 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
382 INTEL_VGA_DEVICE(0x0D36, &intel_haswell_m_info), /* CRW GT2 mobile */
354 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info), 383 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
355 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info), 384 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
356 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info), 385 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index da8b01fb1bf8..a9d58d72bb4d 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -451,7 +451,6 @@ int i915_switch_context(struct intel_ring_buffer *ring,
451 struct drm_i915_file_private *file_priv = NULL; 451 struct drm_i915_file_private *file_priv = NULL;
452 struct i915_hw_context *to; 452 struct i915_hw_context *to;
453 struct drm_i915_gem_object *from_obj = ring->last_context_obj; 453 struct drm_i915_gem_object *from_obj = ring->last_context_obj;
454 int ret;
455 454
456 if (dev_priv->hw_contexts_disabled) 455 if (dev_priv->hw_contexts_disabled)
457 return 0; 456 return 0;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 5af631e788c8..ff2819ea0813 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -291,6 +291,16 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
291 target_i915_obj = to_intel_bo(target_obj); 291 target_i915_obj = to_intel_bo(target_obj);
292 target_offset = target_i915_obj->gtt_offset; 292 target_offset = target_i915_obj->gtt_offset;
293 293
294 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
295 * pipe_control writes because the gpu doesn't properly redirect them
296 * through the ppgtt for non_secure batchbuffers. */
297 if (unlikely(IS_GEN6(dev) &&
298 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
299 !target_i915_obj->has_global_gtt_mapping)) {
300 i915_gem_gtt_bind_object(target_i915_obj,
301 target_i915_obj->cache_level);
302 }
303
294 /* The target buffer should have appeared before us in the 304 /* The target buffer should have appeared before us in the
295 * exec_object list, so it should have a GTT space bound by now. 305 * exec_object list, so it should have a GTT space bound by now.
296 */ 306 */
@@ -399,16 +409,6 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
399 io_mapping_unmap_atomic(reloc_page); 409 io_mapping_unmap_atomic(reloc_page);
400 } 410 }
401 411
402 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
403 * pipe_control writes because the gpu doesn't properly redirect them
404 * through the ppgtt for non_secure batchbuffers. */
405 if (unlikely(IS_GEN6(dev) &&
406 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
407 !target_i915_obj->has_global_gtt_mapping)) {
408 i915_gem_gtt_bind_object(target_i915_obj,
409 target_i915_obj->cache_level);
410 }
411
412 /* and update the user's relocation entry */ 412 /* and update the user's relocation entry */
413 reloc->presumed_offset = target_offset; 413 reloc->presumed_offset = target_offset;
414 414
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 9fd25a435536..ee9b68f6bc36 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -361,7 +361,8 @@ int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj)
361 struct drm_device *dev = obj->base.dev; 361 struct drm_device *dev = obj->base.dev;
362 struct drm_i915_private *dev_priv = dev->dev_private; 362 struct drm_i915_private *dev_priv = dev->dev_private;
363 363
364 if (dev_priv->mm.gtt->needs_dmar) 364 /* don't map imported dma buf objects */
365 if (dev_priv->mm.gtt->needs_dmar && !obj->sg_table)
365 return intel_gtt_map_memory(obj->pages, 366 return intel_gtt_map_memory(obj->pages,
366 obj->base.size >> PAGE_SHIFT, 367 obj->base.size >> PAGE_SHIFT,
367 &obj->sg_list, 368 &obj->sg_list,
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 2f5388af8df9..7631807a2788 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -32,6 +32,7 @@
32#include "intel_drv.h" 32#include "intel_drv.h"
33#include "i915_drv.h" 33#include "i915_drv.h"
34 34
35#ifdef CONFIG_PM
35static u32 calc_residency(struct drm_device *dev, const u32 reg) 36static u32 calc_residency(struct drm_device *dev, const u32 reg)
36{ 37{
37 struct drm_i915_private *dev_priv = dev->dev_private; 38 struct drm_i915_private *dev_priv = dev->dev_private;
@@ -224,3 +225,14 @@ void i915_teardown_sysfs(struct drm_device *dev)
224 device_remove_bin_file(&dev->primary->kdev, &dpf_attrs); 225 device_remove_bin_file(&dev->primary->kdev, &dpf_attrs);
225 sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group); 226 sysfs_unmerge_group(&dev->primary->kdev.kobj, &rc6_attr_group);
226} 227}
228#else
229void i915_setup_sysfs(struct drm_device *dev)
230{
231 return;
232}
233
234void i915_teardown_sysfs(struct drm_device *dev)
235{
236 return;
237}
238#endif /* CONFIG_PM */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f6159765f1eb..a69a3d0d3acf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -869,6 +869,7 @@ intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
869 unsigned long bestppm, ppm, absppm; 869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag; 870 int dotclk, flag;
871 871
872 flag = 0;
872 dotclk = target * 1000; 873 dotclk = target * 1000;
873 bestppm = 1000000; 874 bestppm = 1000000;
874 ppm = absppm = 0; 875 ppm = absppm = 0;
@@ -3753,17 +3754,6 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3753 continue; 3754 continue;
3754 } 3755 }
3755 3756
3756 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3757 /* Use VBT settings if we have an eDP panel */
3758 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3759
3760 if (edp_bpc < display_bpc) {
3761 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
3762 display_bpc = edp_bpc;
3763 }
3764 continue;
3765 }
3766
3767 /* Not one of the known troublemakers, check the EDID */ 3757 /* Not one of the known troublemakers, check the EDID */
3768 list_for_each_entry(connector, &dev->mode_config.connector_list, 3758 list_for_each_entry(connector, &dev->mode_config.connector_list,
3769 head) { 3759 head) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0a56b9ab0f58..a6c426afaa7a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1174,10 +1174,14 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1174 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); 1174 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1175 1175
1176 pp = ironlake_get_pp_control(dev_priv); 1176 pp = ironlake_get_pp_control(dev_priv);
1177 pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE); 1177 /* We need to switch off panel power _and_ force vdd, for otherwise some
1178 * panels get very unhappy and cease to work. */
1179 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1178 I915_WRITE(PCH_PP_CONTROL, pp); 1180 I915_WRITE(PCH_PP_CONTROL, pp);
1179 POSTING_READ(PCH_PP_CONTROL); 1181 POSTING_READ(PCH_PP_CONTROL);
1180 1182
1183 intel_dp->want_panel_vdd = false;
1184
1181 ironlake_wait_panel_off(intel_dp); 1185 ironlake_wait_panel_off(intel_dp);
1182} 1186}
1183 1187
@@ -1287,11 +1291,9 @@ static void intel_dp_prepare(struct drm_encoder *encoder)
1287 * ensure that we have vdd while we switch off the panel. */ 1291 * ensure that we have vdd while we switch off the panel. */
1288 ironlake_edp_panel_vdd_on(intel_dp); 1292 ironlake_edp_panel_vdd_on(intel_dp);
1289 ironlake_edp_backlight_off(intel_dp); 1293 ironlake_edp_backlight_off(intel_dp);
1290 ironlake_edp_panel_off(intel_dp);
1291
1292 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 1294 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1295 ironlake_edp_panel_off(intel_dp);
1293 intel_dp_link_down(intel_dp); 1296 intel_dp_link_down(intel_dp);
1294 ironlake_edp_panel_vdd_off(intel_dp, false);
1295} 1297}
1296 1298
1297static void intel_dp_commit(struct drm_encoder *encoder) 1299static void intel_dp_commit(struct drm_encoder *encoder)
@@ -1326,11 +1328,9 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
1326 /* Switching the panel off requires vdd. */ 1328 /* Switching the panel off requires vdd. */
1327 ironlake_edp_panel_vdd_on(intel_dp); 1329 ironlake_edp_panel_vdd_on(intel_dp);
1328 ironlake_edp_backlight_off(intel_dp); 1330 ironlake_edp_backlight_off(intel_dp);
1329 ironlake_edp_panel_off(intel_dp);
1330
1331 intel_dp_sink_dpms(intel_dp, mode); 1331 intel_dp_sink_dpms(intel_dp, mode);
1332 ironlake_edp_panel_off(intel_dp);
1332 intel_dp_link_down(intel_dp); 1333 intel_dp_link_down(intel_dp);
1333 ironlake_edp_panel_vdd_off(intel_dp, false);
1334 1334
1335 if (is_cpu_edp(intel_dp)) 1335 if (is_cpu_edp(intel_dp))
1336 ironlake_edp_pll_off(encoder); 1336 ironlake_edp_pll_off(encoder);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 84353559441c..132ab511b90c 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -46,15 +46,16 @@
46}) 46})
47 47
48#define wait_for_atomic_us(COND, US) ({ \ 48#define wait_for_atomic_us(COND, US) ({ \
49 int i, ret__ = -ETIMEDOUT; \ 49 unsigned long timeout__ = jiffies + usecs_to_jiffies(US); \
50 for (i = 0; i < (US); i++) { \ 50 int ret__ = 0; \
51 if ((COND)) { \ 51 while (!(COND)) { \
52 ret__ = 0; \ 52 if (time_after(jiffies, timeout__)) { \
53 break; \ 53 ret__ = -ETIMEDOUT; \
54 } \ 54 break; \
55 udelay(1); \ 55 } \
56 } \ 56 cpu_relax(); \
57 ret__; \ 57 } \
58 ret__; \
58}) 59})
59 60
60#define wait_for(COND, MS) _wait_for(COND, MS, 1) 61#define wait_for(COND, MS) _wait_for(COND, MS, 1)
@@ -380,7 +381,6 @@ extern void intel_pch_panel_fitting(struct drm_device *dev,
380 const struct drm_display_mode *mode, 381 const struct drm_display_mode *mode,
381 struct drm_display_mode *adjusted_mode); 382 struct drm_display_mode *adjusted_mode);
382extern u32 intel_panel_get_max_backlight(struct drm_device *dev); 383extern u32 intel_panel_get_max_backlight(struct drm_device *dev);
383extern u32 intel_panel_get_backlight(struct drm_device *dev);
384extern void intel_panel_set_backlight(struct drm_device *dev, u32 level); 384extern void intel_panel_set_backlight(struct drm_device *dev, u32 level);
385extern int intel_panel_setup_backlight(struct drm_device *dev); 385extern int intel_panel_setup_backlight(struct drm_device *dev);
386extern void intel_panel_enable_backlight(struct drm_device *dev, 386extern void intel_panel_enable_backlight(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 1991a4408cf9..b9755f6378d8 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -486,9 +486,6 @@ int intel_setup_gmbus(struct drm_device *dev)
486 bus->dev_priv = dev_priv; 486 bus->dev_priv = dev_priv;
487 487
488 bus->adapter.algo = &gmbus_algorithm; 488 bus->adapter.algo = &gmbus_algorithm;
489 ret = i2c_add_adapter(&bus->adapter);
490 if (ret)
491 goto err;
492 489
493 /* By default use a conservative clock rate */ 490 /* By default use a conservative clock rate */
494 bus->reg0 = port | GMBUS_RATE_100KHZ; 491 bus->reg0 = port | GMBUS_RATE_100KHZ;
@@ -498,6 +495,10 @@ int intel_setup_gmbus(struct drm_device *dev)
498 bus->force_bit = true; 495 bus->force_bit = true;
499 496
500 intel_gpio_setup(bus, port); 497 intel_gpio_setup(bus, port);
498
499 ret = i2c_add_adapter(&bus->adapter);
500 if (ret)
501 goto err;
501 } 502 }
502 503
503 intel_i2c_reset(dev_priv->dev); 504 intel_i2c_reset(dev_priv->dev);
@@ -540,9 +541,6 @@ void intel_teardown_gmbus(struct drm_device *dev)
540 struct drm_i915_private *dev_priv = dev->dev_private; 541 struct drm_i915_private *dev_priv = dev->dev_private;
541 int i; 542 int i;
542 543
543 if (dev_priv->gmbus == NULL)
544 return;
545
546 for (i = 0; i < GMBUS_NUM_PORTS; i++) { 544 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
547 struct intel_gmbus *bus = &dev_priv->gmbus[i]; 545 struct intel_gmbus *bus = &dev_priv->gmbus[i];
548 i2c_del_adapter(&bus->adapter); 546 i2c_del_adapter(&bus->adapter);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 10c7d39034e1..3df4f5fa892a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -213,7 +213,7 @@ static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
213 return val; 213 return val;
214} 214}
215 215
216u32 intel_panel_get_backlight(struct drm_device *dev) 216static u32 intel_panel_get_backlight(struct drm_device *dev)
217{ 217{
218 struct drm_i915_private *dev_priv = dev->dev_private; 218 struct drm_i915_private *dev_priv = dev->dev_private;
219 u32 val; 219 u32 val;
@@ -311,9 +311,6 @@ void intel_panel_enable_backlight(struct drm_device *dev,
311 if (dev_priv->backlight_level == 0) 311 if (dev_priv->backlight_level == 0)
312 dev_priv->backlight_level = intel_panel_get_max_backlight(dev); 312 dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
313 313
314 dev_priv->backlight_enabled = true;
315 intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
316
317 if (INTEL_INFO(dev)->gen >= 4) { 314 if (INTEL_INFO(dev)->gen >= 4) {
318 uint32_t reg, tmp; 315 uint32_t reg, tmp;
319 316
@@ -326,7 +323,7 @@ void intel_panel_enable_backlight(struct drm_device *dev,
326 * we don't track the backlight dpms state, hence check whether 323 * we don't track the backlight dpms state, hence check whether
327 * we have to do anything first. */ 324 * we have to do anything first. */
328 if (tmp & BLM_PWM_ENABLE) 325 if (tmp & BLM_PWM_ENABLE)
329 return; 326 goto set_level;
330 327
331 if (dev_priv->num_pipe == 3) 328 if (dev_priv->num_pipe == 3)
332 tmp &= ~BLM_PIPE_SELECT_IVB; 329 tmp &= ~BLM_PIPE_SELECT_IVB;
@@ -347,6 +344,14 @@ void intel_panel_enable_backlight(struct drm_device *dev,
347 I915_WRITE(BLC_PWM_PCH_CTL1, tmp); 344 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
348 } 345 }
349 } 346 }
347
348set_level:
349 /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
350 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
351 * registers are set.
352 */
353 dev_priv->backlight_enabled = true;
354 intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
350} 355}
351 356
352static void intel_panel_init_backlight(struct drm_device *dev) 357static void intel_panel_init_backlight(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 94aabcaa3a67..58c07cdafb7e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3963,6 +3963,7 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
3963 DRM_ERROR("Force wake wait timed out\n"); 3963 DRM_ERROR("Force wake wait timed out\n");
3964 3964
3965 I915_WRITE_NOTRACE(FORCEWAKE, 1); 3965 I915_WRITE_NOTRACE(FORCEWAKE, 1);
3966 POSTING_READ(FORCEWAKE);
3966 3967
3967 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500)) 3968 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
3968 DRM_ERROR("Force wake wait timed out\n"); 3969 DRM_ERROR("Force wake wait timed out\n");
@@ -3983,6 +3984,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
3983 DRM_ERROR("Force wake wait timed out\n"); 3984 DRM_ERROR("Force wake wait timed out\n");
3984 3985
3985 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1)); 3986 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(1));
3987 POSTING_READ(FORCEWAKE_MT);
3986 3988
3987 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500)) 3989 if (wait_for_atomic_us((I915_READ_NOTRACE(forcewake_ack) & 1), 500))
3988 DRM_ERROR("Force wake wait timed out\n"); 3990 DRM_ERROR("Force wake wait timed out\n");
@@ -4018,14 +4020,14 @@ void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4018static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 4020static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4019{ 4021{
4020 I915_WRITE_NOTRACE(FORCEWAKE, 0); 4022 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4021 /* The below doubles as a POSTING_READ */ 4023 POSTING_READ(FORCEWAKE);
4022 gen6_gt_check_fifodbg(dev_priv); 4024 gen6_gt_check_fifodbg(dev_priv);
4023} 4025}
4024 4026
4025static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) 4027static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4026{ 4028{
4027 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1)); 4029 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(1));
4028 /* The below doubles as a POSTING_READ */ 4030 POSTING_READ(FORCEWAKE_MT);
4029 gen6_gt_check_fifodbg(dev_priv); 4031 gen6_gt_check_fifodbg(dev_priv);
4030} 4032}
4031 4033
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index bf0195a96d53..e2a73b38abe9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -227,31 +227,36 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
227 * number of bits based on the write domains has little performance 227 * number of bits based on the write domains has little performance
228 * impact. 228 * impact.
229 */ 229 */
230 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; 230 if (flush_domains) {
231 flags |= PIPE_CONTROL_TLB_INVALIDATE; 231 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
232 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; 232 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
233 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; 233 /*
234 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; 234 * Ensure that any following seqno writes only happen
235 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; 235 * when the render cache is indeed flushed.
236 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; 236 */
237 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
238 /*
239 * Ensure that any following seqno writes only happen when the render
240 * cache is indeed flushed (but only if the caller actually wants that).
241 */
242 if (flush_domains)
243 flags |= PIPE_CONTROL_CS_STALL; 237 flags |= PIPE_CONTROL_CS_STALL;
238 }
239 if (invalidate_domains) {
240 flags |= PIPE_CONTROL_TLB_INVALIDATE;
241 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
244 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
245 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
246 /*
247 * TLB invalidate requires a post-sync write.
248 */
249 flags |= PIPE_CONTROL_QW_WRITE;
250 }
244 251
245 ret = intel_ring_begin(ring, 6); 252 ret = intel_ring_begin(ring, 4);
246 if (ret) 253 if (ret)
247 return ret; 254 return ret;
248 255
249 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); 256 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
250 intel_ring_emit(ring, flags); 257 intel_ring_emit(ring, flags);
251 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); 258 intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
252 intel_ring_emit(ring, 0); /* lower dword */ 259 intel_ring_emit(ring, 0);
253 intel_ring_emit(ring, 0); /* uppwer dword */
254 intel_ring_emit(ring, MI_NOOP);
255 intel_ring_advance(ring); 260 intel_ring_advance(ring);
256 261
257 return 0; 262 return 0;
@@ -289,8 +294,6 @@ static int init_ring_common(struct intel_ring_buffer *ring)
289 I915_WRITE_HEAD(ring, 0); 294 I915_WRITE_HEAD(ring, 0);
290 ring->write_tail(ring, 0); 295 ring->write_tail(ring, 0);
291 296
292 /* Initialize the ring. */
293 I915_WRITE_START(ring, obj->gtt_offset);
294 head = I915_READ_HEAD(ring) & HEAD_ADDR; 297 head = I915_READ_HEAD(ring) & HEAD_ADDR;
295 298
296 /* G45 ring initialization fails to reset head to zero */ 299 /* G45 ring initialization fails to reset head to zero */
@@ -316,6 +319,11 @@ static int init_ring_common(struct intel_ring_buffer *ring)
316 } 319 }
317 } 320 }
318 321
322 /* Initialize the ring. This must happen _after_ we've cleared the ring
323 * registers with the above sequence (the readback of the HEAD registers
324 * also enforces ordering), otherwise the hw might lose the new ring
325 * register values. */
326 I915_WRITE_START(ring, obj->gtt_offset);
319 I915_WRITE_CTL(ring, 327 I915_WRITE_CTL(ring,
320 ((ring->size - PAGE_SIZE) & RING_NR_PAGES) 328 ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
321 | RING_VALID); 329 | RING_VALID);
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 26a6a4d0d078..d172e9873131 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -444,13 +444,16 @@ static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
444 struct i2c_msg *msgs; 444 struct i2c_msg *msgs;
445 int i, ret = true; 445 int i, ret = true;
446 446
447 /* Would be simpler to allocate both in one go ? */
447 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL); 448 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
448 if (!buf) 449 if (!buf)
449 return false; 450 return false;
450 451
451 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL); 452 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
452 if (!msgs) 453 if (!msgs) {
454 kfree(buf);
453 return false; 455 return false;
456 }
454 457
455 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len); 458 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
456 459